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GET /api/patches/64176/?format=api
{ "id": 64176, "url": "https://patches.dpdk.org/api/patches/64176/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200102175903.9556-2-shshaikh@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200102175903.9556-2-shshaikh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200102175903.9556-2-shshaikh@marvell.com", "date": "2020-01-02T17:59:03", "name": "[2/2] net/qede: enhance transmit data path CPU utilization", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c6956dd91bab32f3d9077cb6650be66ead539765", "submitter": { "id": 1210, "url": "https://patches.dpdk.org/api/people/1210/?format=api", "name": "Shahed Shaikh", "email": "shshaikh@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200102175903.9556-2-shshaikh@marvell.com/mbox/", "series": [ { "id": 7967, "url": "https://patches.dpdk.org/api/series/7967/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=7967", "date": "2020-01-02T17:59:02", "name": "[1/2] net/qede: enhance receive data path CPU utilization", "version": 1, "mbox": "https://patches.dpdk.org/series/7967/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/64176/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/64176/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AB366A04F3;\n\tThu, 2 Jan 2020 18:59:35 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 106B51C1B0;\n\tThu, 2 Jan 2020 18:59:29 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 3C45F1C1A3\n for <dev@dpdk.org>; Thu, 2 Jan 2020 18:59:27 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 002Ht9b1019119 for <dev@dpdk.org>; Thu, 2 Jan 2020 09:59:26 -0800", "from sc-exch04.marvell.com ([199.233.58.184])\n by mx0b-0016f401.pphosted.com with ESMTP id 2x67etnw0n-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 02 Jan 2020 09:59:26 -0800", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com\n (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 2 Jan\n 2020 09:59:24 -0800", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 2 Jan 2020 09:59:23 -0800", "from dut1171.mv.qlogic.com (unknown [10.112.88.18])\n by maili.marvell.com (Postfix) with ESMTP id E1E003F703F;\n Thu, 2 Jan 2020 09:59:23 -0800 (PST)", "from dut1171.mv.qlogic.com (localhost [127.0.0.1])\n by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 002HxNM9009605;\n Thu, 2 Jan 2020 09:59:23 -0800", "(from root@localhost)\n by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 002HxNIA009604;\n Thu, 2 Jan 2020 09:59:23 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=FVS7E4kHXckWf2H2I0SqGq7Mxaap1N5MJfTDHg7xFDU=;\n b=lu0I3uxB1Cc7ZJAsmg+6EVCotHjXQ7qsZfB533+Z+UTVfbtCdm9Xut482fUwJKbz2sjh\n CdKifMMM2lVv6TWrghBaEQTDaQqPjZ8P8I3A6v8j2tZsuz6sIKYcbAI5GzFVwiqbYy8D\n zcIOj11DgnetucGnNiPbDCwbFWd33e/i/S7dhl+ayePdK8KwdhokRNnPd20bNZe+gKLT\n dP9mgyp6dIV/5vZ4yVkGbos5tSc0s/EVmp/eraKmzvAlrtQj3st+k148MFhys/XHxGKs\n B12/DrzlJkXxxnacn1zp1lzec+A+DaW6oErDNeUdmLa6uRJkzaNqkj0DKtV8lW7U6oDo Rw==", "From": "Shahed Shaikh <shshaikh@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<rmody@marvell.com>, <jerinj@marvell.com>,\n <GR-Everest-DPDK-Dev@marvell.com>", "Date": "Thu, 2 Jan 2020 09:59:03 -0800", "Message-ID": "<20200102175903.9556-2-shshaikh@marvell.com>", "X-Mailer": "git-send-email 2.12.0", "In-Reply-To": "<20200102175903.9556-1-shshaikh@marvell.com>", "References": "<20200102175903.9556-1-shshaikh@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,18.0.572\n definitions=2020-01-02_05:2020-01-02,2020-01-02 signatures=0", "Subject": "[dpdk-dev] [PATCH 2/2] net/qede: enhance transmit data path CPU\n\tutilization", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Use lightweight transmit handler which handles non-offloaded Tx data path.\nWe get CPU utilization improvement of ~8%.\n\nSigned-off-by: Shahed Shaikh <shshaikh@marvell.com>\n---\n drivers/net/qede/qede_ethdev.c | 15 +++-\n drivers/net/qede/qede_rxtx.c | 125 +++++++++++++++++++++++++++++++++\n drivers/net/qede/qede_rxtx.h | 2 +\n 3 files changed, 141 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c\nindex 47e90096a..055f046e2 100644\n--- a/drivers/net/qede/qede_ethdev.c\n+++ b/drivers/net/qede/qede_ethdev.c\n@@ -270,8 +270,10 @@ qede_interrupt_handler(void *param)\n static void\n qede_assign_rxtx_handlers(struct rte_eth_dev *dev)\n {\n+\tuint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;\n \tstruct qede_dev *qdev = dev->data->dev_private;\n \tstruct ecore_dev *edev = &qdev->edev;\n+\tbool use_tx_offload = false;\n \n \tif (ECORE_IS_CMT(edev)) {\n \t\tdev->rx_pkt_burst = qede_recv_pkts_cmt;\n@@ -287,7 +289,18 @@ qede_assign_rxtx_handlers(struct rte_eth_dev *dev)\n \t\tdev->rx_pkt_burst = qede_recv_pkts_regular;\n \t}\n \n-\tdev->tx_pkt_burst = qede_xmit_pkts;\n+\tuse_tx_offload = !!(tx_offloads &\n+\t\t\t (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | /* tunnel */\n+\t\t\t DEV_TX_OFFLOAD_TCP_TSO | /* tso */\n+\t\t\t DEV_TX_OFFLOAD_VLAN_INSERT)); /* vlan insert */\n+\n+\tif (use_tx_offload) {\n+\t\tDP_INFO(edev, \"Assigning qede_xmit_pkts\\n\");\n+\t\tdev->tx_pkt_burst = qede_xmit_pkts;\n+\t} else {\n+\t\tDP_INFO(edev, \"Assigning qede_xmit_pkts_regular\\n\");\n+\t\tdev->tx_pkt_burst = qede_xmit_pkts_regular;\n+\t}\n }\n \n static void\ndiff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c\nindex 3b486a0a4..985e49f1c 100644\n--- a/drivers/net/qede/qede_rxtx.c\n+++ b/drivers/net/qede/qede_rxtx.c\n@@ -2234,6 +2234,131 @@ qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,\n }\n #endif\n \n+uint16_t\n+qede_xmit_pkts_regular(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct qede_tx_queue *txq = p_txq;\n+\tstruct qede_dev *qdev = txq->qdev;\n+\tstruct ecore_dev *edev = &qdev->edev;\n+\tstruct eth_tx_1st_bd *bd1;\n+\tstruct eth_tx_2nd_bd *bd2;\n+\tstruct eth_tx_3rd_bd *bd3;\n+\tstruct rte_mbuf *m_seg = NULL;\n+\tstruct rte_mbuf *mbuf;\n+\tstruct qede_tx_entry *sw_tx_ring;\n+\tuint16_t nb_tx_pkts;\n+\tuint16_t bd_prod;\n+\tuint16_t idx;\n+\tuint16_t nb_frags = 0;\n+\tuint16_t nb_pkt_sent = 0;\n+\tuint8_t nbds;\n+\tuint64_t tx_ol_flags;\n+\t/* BD1 */\n+\tuint16_t bd1_bf;\n+\tuint8_t bd1_bd_flags_bf;\n+\n+\tif (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {\n+\t\tPMD_TX_LOG(DEBUG, txq, \"send=%u avail=%u free_thresh=%u\",\n+\t\t\t nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);\n+\t\tqede_process_tx_compl(edev, txq);\n+\t}\n+\n+\tnb_tx_pkts = nb_pkts;\n+\tbd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));\n+\tsw_tx_ring = txq->sw_tx_ring;\n+\n+\twhile (nb_tx_pkts--) {\n+\t\t/* Init flags/values */\n+\t\tnbds = 0;\n+\t\tbd1 = NULL;\n+\t\tbd2 = NULL;\n+\t\tbd3 = NULL;\n+\t\tbd1_bf = 0;\n+\t\tbd1_bd_flags_bf = 0;\n+\t\tnb_frags = 0;\n+\n+\t\tmbuf = *tx_pkts++;\n+\t\tassert(mbuf);\n+\n+\n+\t\t/* Check minimum TX BDS availability against available BDs */\n+\t\tif (unlikely(txq->nb_tx_avail < mbuf->nb_segs))\n+\t\t\tbreak;\n+\n+\t\ttx_ol_flags = mbuf->ol_flags;\n+\t\tbd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;\n+\n+\t\tif (unlikely(txq->nb_tx_avail <\n+\t\t\t\tETH_TX_MIN_BDS_PER_NON_LSO_PKT))\n+\t\t\tbreak;\n+\t\tbd1_bf |=\n+\t\t (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)\n+\t\t\t<< ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;\n+\n+\t\t/* Offload the IP checksum in the hardware */\n+\t\tif (tx_ol_flags & PKT_TX_IP_CKSUM)\n+\t\t\tbd1_bd_flags_bf |=\n+\t\t\t\t1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;\n+\n+\t\t/* L4 checksum offload (tcp or udp) */\n+\t\tif ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&\n+\t\t (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM)))\n+\t\t\tbd1_bd_flags_bf |=\n+\t\t\t\t1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;\n+\n+\t\t/* Fill the entry in the SW ring and the BDs in the FW ring */\n+\t\tidx = TX_PROD(txq);\n+\t\tsw_tx_ring[idx].mbuf = mbuf;\n+\n+\t\t/* BD1 */\n+\t\tbd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);\n+\t\tmemset(bd1, 0, sizeof(struct eth_tx_1st_bd));\n+\t\tnbds++;\n+\n+\t\t/* Map MBUF linear data for DMA and set in the BD1 */\n+\t\tQEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),\n+\t\t\t\t mbuf->data_len);\n+\t\tbd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);\n+\t\tbd1->data.bd_flags.bitfields = bd1_bd_flags_bf;\n+\n+\t\t/* Handle fragmented MBUF */\n+\t\tif (unlikely(mbuf->nb_segs > 1)) {\n+\t\t\tm_seg = mbuf->next;\n+\n+\t\t\t/* Encode scatter gather buffer descriptors */\n+\t\t\tnb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3,\n+\t\t\t\t\t\t nbds - 1);\n+\t\t}\n+\n+\t\tbd1->data.nbds = nbds + nb_frags;\n+\n+\t\ttxq->nb_tx_avail -= bd1->data.nbds;\n+\t\ttxq->sw_tx_prod++;\n+\t\tbd_prod =\n+\t\t rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));\n+#ifdef RTE_LIBRTE_QEDE_DEBUG_TX\n+\t\tprint_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);\n+#endif\n+\t\tnb_pkt_sent++;\n+\t\ttxq->xmit_pkts++;\n+\t}\n+\n+\t/* Write value of prod idx into bd_prod */\n+\ttxq->tx_db.data.bd_prod = bd_prod;\n+\trte_wmb();\n+\trte_compiler_barrier();\n+\tDIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);\n+\trte_wmb();\n+\n+\t/* Check again for Tx completions */\n+\tqede_process_tx_compl(edev, txq);\n+\n+\tPMD_TX_LOG(DEBUG, txq, \"to_send=%u sent=%u bd_prod=%u core=%d\",\n+\t\t nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());\n+\n+\treturn nb_pkt_sent;\n+}\n+\n uint16_t\n qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n {\ndiff --git a/drivers/net/qede/qede_rxtx.h b/drivers/net/qede/qede_rxtx.h\nindex a4c634e88..d7ff870b2 100644\n--- a/drivers/net/qede/qede_rxtx.h\n+++ b/drivers/net/qede/qede_rxtx.h\n@@ -275,6 +275,8 @@ uint16_t qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts,\n \t\t\tuint16_t nb_pkts);\n uint16_t qede_xmit_pkts_cmt(void *p_txq, struct rte_mbuf **tx_pkts,\n \t\t\t uint16_t nb_pkts);\n+uint16_t qede_xmit_pkts_regular(void *p_txq, struct rte_mbuf **tx_pkts,\n+\t\t\t\tuint16_t nb_pkts);\n \n uint16_t qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,\n \t\t\t uint16_t nb_pkts);\n", "prefixes": [ "2/2" ] }