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GET /api/patches/64175/?format=api
{ "id": 64175, "url": "https://patches.dpdk.org/api/patches/64175/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200102175903.9556-1-shshaikh@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200102175903.9556-1-shshaikh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200102175903.9556-1-shshaikh@marvell.com", "date": "2020-01-02T17:59:02", "name": "[1/2] net/qede: enhance receive data path CPU utilization", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "260cee4b2e14978711a5807141fef77fa31ac32c", "submitter": { "id": 1210, "url": "https://patches.dpdk.org/api/people/1210/?format=api", "name": "Shahed Shaikh", "email": "shshaikh@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200102175903.9556-1-shshaikh@marvell.com/mbox/", "series": [ { "id": 7967, "url": "https://patches.dpdk.org/api/series/7967/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=7967", "date": "2020-01-02T17:59:02", "name": "[1/2] net/qede: enhance receive data path CPU utilization", "version": 1, "mbox": "https://patches.dpdk.org/series/7967/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/64175/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/64175/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 00953A04F3;\n\tThu, 2 Jan 2020 18:59:27 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 56CE81C1A6;\n\tThu, 2 Jan 2020 18:59:27 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 1152D1C1A3\n for <dev@dpdk.org>; Thu, 2 Jan 2020 18:59:25 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 002HurIW028769 for <dev@dpdk.org>; Thu, 2 Jan 2020 09:59:25 -0800", "from sc-exch01.marvell.com ([199.233.58.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 2x659vpbvc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 02 Jan 2020 09:59:25 -0800", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 2 Jan\n 2020 09:59:21 -0800", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 2 Jan 2020 09:59:20 -0800", "from dut1171.mv.qlogic.com (unknown [10.112.88.18])\n by maili.marvell.com (Postfix) with ESMTP id B8E6A3F703F;\n Thu, 2 Jan 2020 09:59:20 -0800 (PST)", "from dut1171.mv.qlogic.com (localhost [127.0.0.1])\n by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 002HxK9l009601;\n Thu, 2 Jan 2020 09:59:20 -0800", "(from root@localhost)\n by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 002HxKeY009600;\n Thu, 2 Jan 2020 09:59:20 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-type; s=pfpt0818;\n bh=mVjPPi0Tj/4aT6QXaE0tZxx2oK/l/zb20IVrO8Y6cUo=;\n b=xXrs7KR5/rxYl5IgYSY/orE1KZTW8yU2MR2G6ECy3VrmKjy7s3hlTLOEuVUK0d+GFojq\n T98YMQIJ4+UMJ0raHwCkofRHaV0AMprhiSDIlVUR38EqfMgx6vVyMQ0C3KNVBFfzw+BN\n X+BJq5EwrEdCaxoNVfyg0bbE8KsMl/rkiAplMa/P1JkYcKSBxG3loQ7wWhgKdXz8QE9T\n mLcWueisfDmomkYDJpZKn33Gxhjuh1Ba4ODls5UYBMuBBNfawauNYD//+vgyqQpXszHD\n 64StvgfUXMyZ1FE2eJxIunQHGZWP+bQQBRLK5+5IlmnlVBnGL4tSEUbjQj6hWLThTv7p Rg==", "From": "Shahed Shaikh <shshaikh@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<rmody@marvell.com>, <jerinj@marvell.com>,\n <GR-Everest-DPDK-Dev@marvell.com>", "Date": "Thu, 2 Jan 2020 09:59:02 -0800", "Message-ID": "<20200102175903.9556-1-shshaikh@marvell.com>", "X-Mailer": "git-send-email 2.12.0", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,18.0.572\n definitions=2020-01-02_05:2020-01-02,2020-01-02 signatures=0", "Subject": "[dpdk-dev] [PATCH 1/2] net/qede: enhance receive data path CPU\n\tutilization", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Use light weight receive packet handler for non-LRO and\nnon-scatter packets to improve CPU utilization in receive data path.\nWe achieved ~18% CPU cycles improvement using this handler.\n\nSigned-off-by: Shahed Shaikh <shshaikh@marvell.com>\n---\n drivers/net/qede/qede_ethdev.c | 36 ++++--\n drivers/net/qede/qede_rxtx.c | 222 +++++++++++++++++++++++++++++++++\n drivers/net/qede/qede_rxtx.h | 4 +-\n 3 files changed, 253 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c\nindex 8064735db..47e90096a 100644\n--- a/drivers/net/qede/qede_ethdev.c\n+++ b/drivers/net/qede/qede_ethdev.c\n@@ -267,6 +267,29 @@ qede_interrupt_handler(void *param)\n \t\tDP_ERR(edev, \"rte_intr_ack failed\\n\");\n }\n \n+static void\n+qede_assign_rxtx_handlers(struct rte_eth_dev *dev)\n+{\n+\tstruct qede_dev *qdev = dev->data->dev_private;\n+\tstruct ecore_dev *edev = &qdev->edev;\n+\n+\tif (ECORE_IS_CMT(edev)) {\n+\t\tdev->rx_pkt_burst = qede_recv_pkts_cmt;\n+\t\tdev->tx_pkt_burst = qede_xmit_pkts_cmt;\n+\t\treturn;\n+\t}\n+\n+\tif (dev->data->lro || dev->data->scattered_rx) {\n+\t\tDP_INFO(edev, \"Assigning qede_recv_pkts\\n\");\n+\t\tdev->rx_pkt_burst = qede_recv_pkts;\n+\t} else {\n+\t\tDP_INFO(edev, \"Assigning qede_recv_pkts_regular\\n\");\n+\t\tdev->rx_pkt_burst = qede_recv_pkts_regular;\n+\t}\n+\n+\tdev->tx_pkt_burst = qede_xmit_pkts;\n+}\n+\n static void\n qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)\n {\n@@ -1064,6 +1087,7 @@ static int qede_dev_start(struct rte_eth_dev *eth_dev)\n \t/* Start/resume traffic */\n \tqede_fastpath_start(edev);\n \n+\tqede_assign_rxtx_handlers(eth_dev);\n \tDP_INFO(edev, \"Device started\\n\");\n \n \treturn 0;\n@@ -1951,6 +1975,7 @@ qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)\n \t};\n \n \tif (eth_dev->rx_pkt_burst == qede_recv_pkts ||\n+\t eth_dev->rx_pkt_burst == qede_recv_pkts_regular ||\n \t eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)\n \t\treturn ptypes;\n \n@@ -2242,7 +2267,9 @@ static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)\n \n \t/* update max frame size */\n \tdev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;\n+\n \t/* Reassign back */\n+\tqede_assign_rxtx_handlers(dev);\n \tif (ECORE_IS_CMT(edev)) {\n \t\tdev->rx_pkt_burst = qede_recv_pkts_cmt;\n \t\tdev->tx_pkt_burst = qede_xmit_pkts_cmt;\n@@ -2447,14 +2474,7 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)\n \tstrncpy((char *)params.name, QEDE_PMD_VER_PREFIX,\n \t\tQEDE_PMD_DRV_VER_STR_SIZE);\n \n-\tif (ECORE_IS_CMT(edev)) {\n-\t\teth_dev->rx_pkt_burst = qede_recv_pkts_cmt;\n-\t\teth_dev->tx_pkt_burst = qede_xmit_pkts_cmt;\n-\t} else {\n-\t\teth_dev->rx_pkt_burst = qede_recv_pkts;\n-\t\teth_dev->tx_pkt_burst = qede_xmit_pkts;\n-\t}\n-\n+\tqede_assign_rxtx_handlers(eth_dev);\n \teth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;\n \n \t/* For CMT mode device do periodic polling for slowpath events.\ndiff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c\nindex dbb74fc64..3b486a0a4 100644\n--- a/drivers/net/qede/qede_rxtx.c\n+++ b/drivers/net/qede/qede_rxtx.c\n@@ -1518,6 +1518,228 @@ print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,\n }\n #endif\n \n+uint16_t\n+qede_recv_pkts_regular(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;\n+\tregister struct rte_mbuf *rx_mb = NULL;\n+\tstruct qede_rx_queue *rxq = p_rxq;\n+\tstruct qede_dev *qdev = rxq->qdev;\n+\tstruct ecore_dev *edev = &qdev->edev;\n+\tunion eth_rx_cqe *cqe;\n+\tuint64_t ol_flags;\n+\tenum eth_rx_cqe_type cqe_type;\n+\tint rss_enable = qdev->rss_enable;\n+\tint rx_alloc_count = 0;\n+\tuint32_t packet_type;\n+\tuint32_t rss_hash;\n+\tuint16_t vlan_tci, port_id;\n+\tuint16_t hw_comp_cons, sw_comp_cons, sw_rx_index, num_rx_bds;\n+\tuint16_t rx_pkt = 0;\n+\tuint16_t pkt_len = 0;\n+\tuint16_t len; /* Length of first BD */\n+\tuint16_t preload_idx;\n+\tuint16_t parse_flag;\n+#ifdef RTE_LIBRTE_QEDE_DEBUG_RX\n+\tuint8_t bitfield_val;\n+#endif\n+\tuint8_t offset, flags, bd_num;\n+\n+\n+\t/* Allocate buffers that we used in previous loop */\n+\tif (rxq->rx_alloc_count) {\n+\t\tif (unlikely(qede_alloc_rx_bulk_mbufs(rxq,\n+\t\t\t rxq->rx_alloc_count))) {\n+\t\t\tstruct rte_eth_dev *dev;\n+\n+\t\t\tPMD_RX_LOG(ERR, rxq,\n+\t\t\t\t \"New buffer allocation failed,\"\n+\t\t\t\t \"dropping incoming packetn\");\n+\t\t\tdev = &rte_eth_devices[rxq->port_id];\n+\t\t\tdev->data->rx_mbuf_alloc_failed +=\n+\t\t\t\t\t\t\trxq->rx_alloc_count;\n+\t\t\trxq->rx_alloc_errors += rxq->rx_alloc_count;\n+\t\t\treturn 0;\n+\t\t}\n+\t\tqede_update_rx_prod(qdev, rxq);\n+\t\trxq->rx_alloc_count = 0;\n+\t}\n+\n+\thw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);\n+\tsw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);\n+\n+\trte_rmb();\n+\n+\tif (hw_comp_cons == sw_comp_cons)\n+\t\treturn 0;\n+\n+\tnum_rx_bds = NUM_RX_BDS(rxq);\n+\tport_id = rxq->port_id;\n+\n+\twhile (sw_comp_cons != hw_comp_cons) {\n+\t\tol_flags = 0;\n+\t\tpacket_type = RTE_PTYPE_UNKNOWN;\n+\t\tvlan_tci = 0;\n+\t\trss_hash = 0;\n+\n+\t\t/* Get the CQE from the completion ring */\n+\t\tcqe =\n+\t\t (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);\n+\t\tcqe_type = cqe->fast_path_regular.type;\n+\t\tPMD_RX_LOG(INFO, rxq, \"Rx CQE type %d\\n\", cqe_type);\n+\n+\t\tif (likely(cqe_type == ETH_RX_CQE_TYPE_REGULAR)) {\n+\t\t\tfp_cqe = &cqe->fast_path_regular;\n+\t\t} else {\n+\t\t\tif (cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH) {\n+\t\t\t\tPMD_RX_LOG(INFO, rxq, \"Got unexpected slowpath CQE\\n\");\n+\t\t\t\tecore_eth_cqe_completion\n+\t\t\t\t\t(&edev->hwfns[rxq->queue_id %\n+\t\t\t\t\t\t edev->num_hwfns],\n+\t\t\t\t\t (struct eth_slow_path_rx_cqe *)cqe);\n+\t\t\t}\n+\t\t\tgoto next_cqe;\n+\t\t}\n+\n+\t\t/* Get the data from the SW ring */\n+\t\tsw_rx_index = rxq->sw_rx_cons & num_rx_bds;\n+\t\trx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;\n+\t\tassert(rx_mb != NULL);\n+\n+\t\tparse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);\n+\t\toffset = fp_cqe->placement_offset;\n+\t\tlen = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);\n+\t\tpkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);\n+\t\tvlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);\n+\t\trss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);\n+\t\tbd_num = fp_cqe->bd_num;\n+#ifdef RTE_LIBRTE_QEDE_DEBUG_RX\n+\t\tbitfield_val = fp_cqe->bitfields;\n+#endif\n+\n+\t\tif (unlikely(qede_tunn_exist(parse_flag))) {\n+\t\t\tPMD_RX_LOG(INFO, rxq, \"Rx tunneled packet\\n\");\n+\t\t\tif (unlikely(qede_check_tunn_csum_l4(parse_flag))) {\n+\t\t\t\tPMD_RX_LOG(ERR, rxq,\n+\t\t\t\t\t \"L4 csum failed, flags = 0x%x\\n\",\n+\t\t\t\t\t parse_flag);\n+\t\t\t\trxq->rx_hw_errors++;\n+\t\t\t\tol_flags |= PKT_RX_L4_CKSUM_BAD;\n+\t\t\t} else {\n+\t\t\t\tol_flags |= PKT_RX_L4_CKSUM_GOOD;\n+\t\t\t}\n+\n+\t\t\tif (unlikely(qede_check_tunn_csum_l3(parse_flag))) {\n+\t\t\t\tPMD_RX_LOG(ERR, rxq,\n+\t\t\t\t\t\"Outer L3 csum failed, flags = 0x%x\\n\",\n+\t\t\t\t\tparse_flag);\n+\t\t\t\trxq->rx_hw_errors++;\n+\t\t\t\tol_flags |= PKT_RX_EIP_CKSUM_BAD;\n+\t\t\t} else {\n+\t\t\t\tol_flags |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\t}\n+\n+\t\t\tflags = fp_cqe->tunnel_pars_flags.flags;\n+\n+\t\t\t/* Tunnel_type */\n+\t\t\tpacket_type =\n+\t\t\t\tqede_rx_cqe_to_tunn_pkt_type(flags);\n+\n+\t\t\t/* Inner header */\n+\t\t\tpacket_type |=\n+\t\t\t qede_rx_cqe_to_pkt_type_inner(parse_flag);\n+\n+\t\t\t/* Outer L3/L4 types is not available in CQE */\n+\t\t\tpacket_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);\n+\n+\t\t\t/* Outer L3/L4 types is not available in CQE.\n+\t\t\t * Need to add offset to parse correctly,\n+\t\t\t */\n+\t\t\trx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;\n+\t\t\tpacket_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);\n+\t\t} else {\n+\t\t\tpacket_type |= qede_rx_cqe_to_pkt_type(parse_flag);\n+\t\t}\n+\n+\t\t/* Common handling for non-tunnel packets and for inner\n+\t\t * headers in the case of tunnel.\n+\t\t */\n+\t\tif (unlikely(qede_check_notunn_csum_l4(parse_flag))) {\n+\t\t\tPMD_RX_LOG(ERR, rxq,\n+\t\t\t\t \"L4 csum failed, flags = 0x%x\\n\",\n+\t\t\t\t parse_flag);\n+\t\t\trxq->rx_hw_errors++;\n+\t\t\tol_flags |= PKT_RX_L4_CKSUM_BAD;\n+\t\t} else {\n+\t\t\tol_flags |= PKT_RX_L4_CKSUM_GOOD;\n+\t\t}\n+\t\tif (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {\n+\t\t\tPMD_RX_LOG(ERR, rxq, \"IP csum failed, flags = 0x%x\\n\",\n+\t\t\t\t parse_flag);\n+\t\t\trxq->rx_hw_errors++;\n+\t\t\tol_flags |= PKT_RX_IP_CKSUM_BAD;\n+\t\t} else {\n+\t\t\tol_flags |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t}\n+\n+\t\tif (unlikely(CQE_HAS_VLAN(parse_flag) ||\n+\t\t\t CQE_HAS_OUTER_VLAN(parse_flag))) {\n+\t\t\t/* Note: FW doesn't indicate Q-in-Q packet */\n+\t\t\tol_flags |= PKT_RX_VLAN;\n+\t\t\tif (qdev->vlan_strip_flg) {\n+\t\t\t\tol_flags |= PKT_RX_VLAN_STRIPPED;\n+\t\t\t\trx_mb->vlan_tci = vlan_tci;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (rss_enable) {\n+\t\t\tol_flags |= PKT_RX_RSS_HASH;\n+\t\t\trx_mb->hash.rss = rss_hash;\n+\t\t}\n+\n+\t\trx_alloc_count++;\n+\t\tqede_rx_bd_ring_consume(rxq);\n+\n+\t\t/* Prefetch next mbuf while processing current one. */\n+\t\tpreload_idx = rxq->sw_rx_cons & num_rx_bds;\n+\t\trte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);\n+\n+\t\t/* Update rest of the MBUF fields */\n+\t\trx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;\n+\t\trx_mb->port = port_id;\n+\t\trx_mb->ol_flags = ol_flags;\n+\t\trx_mb->data_len = len;\n+\t\trx_mb->packet_type = packet_type;\n+#ifdef RTE_LIBRTE_QEDE_DEBUG_RX\n+\t\tprint_rx_bd_info(rx_mb, rxq, bitfield_val);\n+#endif\n+\t\trx_mb->nb_segs = bd_num;\n+\t\trx_mb->pkt_len = pkt_len;\n+\n+\t\trx_pkts[rx_pkt] = rx_mb;\n+\t\trx_pkt++;\n+\n+next_cqe:\n+\t\tecore_chain_recycle_consumed(&rxq->rx_comp_ring);\n+\t\tsw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);\n+\t\tif (rx_pkt == nb_pkts) {\n+\t\t\tPMD_RX_LOG(DEBUG, rxq,\n+\t\t\t\t \"Budget reached nb_pkts=%u received=%u\",\n+\t\t\t\t rx_pkt, nb_pkts);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* Request number of bufferes to be allocated in next loop */\n+\trxq->rx_alloc_count = rx_alloc_count;\n+\n+\trxq->rcv_pkts += rx_pkt;\n+\trxq->rx_segs += rx_pkt;\n+\tPMD_RX_LOG(DEBUG, rxq, \"rx_pkts=%u core=%d\", rx_pkt, rte_lcore_id());\n+\n+\treturn rx_pkt;\n+}\n+\n uint16_t\n qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n {\ndiff --git a/drivers/net/qede/qede_rxtx.h b/drivers/net/qede/qede_rxtx.h\nindex 75cc930fd..a4c634e88 100644\n--- a/drivers/net/qede/qede_rxtx.h\n+++ b/drivers/net/qede/qede_rxtx.h\n@@ -283,7 +283,9 @@ uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts,\n \t\t\tuint16_t nb_pkts);\n uint16_t qede_recv_pkts_cmt(void *p_rxq, struct rte_mbuf **rx_pkts,\n \t\t\t uint16_t nb_pkts);\n-\n+uint16_t\n+qede_recv_pkts_regular(void *p_rxq, struct rte_mbuf **rx_pkts,\n+\t\t uint16_t nb_pkts);\n uint16_t qede_rxtx_pkts_dummy(void *p_rxq,\n \t\t\t struct rte_mbuf **pkts,\n \t\t\t uint16_t nb_pkts);\n", "prefixes": [ "1/2" ] }