Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/635/?format=api
{ "id": 635, "url": "https://patches.dpdk.org/api/patches/635/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1411974986-28137-17-git-send-email-changchun.ouyang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1411974986-28137-17-git-send-email-changchun.ouyang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1411974986-28137-17-git-send-email-changchun.ouyang@intel.com", "date": "2014-09-29T07:16:24", "name": "[dpdk-dev,v2,16/18] ixgbe: New functionalities in IXGBE base code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "56d4488effb7383abd5fceb57b39e167d03a9924", "submitter": { "id": 31, "url": "https://patches.dpdk.org/api/people/31/?format=api", "name": "Ouyang Changchun", "email": "changchun.ouyang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1411974986-28137-17-git-send-email-changchun.ouyang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/635/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/635/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 713807E27;\n\tMon, 29 Sep 2014 09:10:57 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id 83B257E48\n\tfor <dev@dpdk.org>; Mon, 29 Sep 2014 09:10:51 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga103.fm.intel.com with ESMTP; 29 Sep 2014 00:08:05 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 29 Sep 2014 00:17:24 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8T7HMaF014408;\n\tMon, 29 Sep 2014 15:17:22 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8T7HJRR028447; Mon, 29 Sep 2014 15:17:22 +0800", "(from couyang@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8T7HJQZ028443; \n\tMon, 29 Sep 2014 15:17:19 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,618,1406617200\"; d=\"scan'208\";a=\"598147329\"", "From": "Ouyang Changchun <changchun.ouyang@intel.com>", "To": "dev@dpdk.org", "Date": "Mon, 29 Sep 2014 15:16:24 +0800", "Message-Id": "<1411974986-28137-17-git-send-email-changchun.ouyang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>", "References": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 16/18] ixgbe: New functionalities in IXGBE\n\tbase code", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch supports these functionalities in IXGBE base code:\nThermal sensor, DMA coalescing, EEE support, Source address pruning,\nAnti-spoofing, Iosf buffer reading and writing, Malicious driver detection.\n\nSigned-off-by: Changchun Ouyang <changchun.ouyang@intel.com>\n---\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c | 4 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c | 181 ++++++++++++++++++++++++++++++\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h | 18 +++\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c | 169 ++++++++++++++++++++++++++++\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h | 12 ++\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h | 152 ++++++++++++++++++++++++-\n 6 files changed, 531 insertions(+), 5 deletions(-)", "diff": "diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\nindex 3e442f7..2b74374 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n@@ -388,6 +388,10 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)\n \t/* Manageability interface */\n \tmac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;\n \n+\tmac->ops.get_thermal_sensor_data =\n+\t\t\t\t\t &ixgbe_get_thermal_sensor_data_generic;\n+\tmac->ops.init_thermal_sensor_thresh =\n+\t\t\t\t &ixgbe_init_thermal_sensor_thresh_generic;\n \n \tmac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;\n \ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\nindex 8ed4b75..b3e89c5 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\n@@ -1018,7 +1018,188 @@ s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n }\n \n \n+/**\n+ * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n+ * @hw: pointer to hardware structure\n+ *\n+ * Updates the temperatures in mac.thermal_sensor_data\n+ **/\n+s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw),\n+\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n+}\n+\n+/**\n+ * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds\n+ * @hw: pointer to hardware structure\n+ *\n+ * Inits the thermal sensor thresholds according to the NVM map\n+ **/\n+s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw),\n+\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n+}\n+\n+/**\n+ * ixgbe_dmac_config - Configure DMA Coalescing registers.\n+ * @hw: pointer to hardware structure\n+ *\n+ * Configure DMA coalescing. If enabling dmac, dmac is activated.\n+ * When disabling dmac, dmac enable dmac bit is cleared.\n+ **/\n+s32 ixgbe_dmac_config(struct ixgbe_hw *hw)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw),\n+\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n+}\n+\n+/**\n+ * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.\n+ * @hw: pointer to hardware structure\n+ *\n+ * Disables dmac, updates per TC settings, and then enable dmac.\n+ **/\n+s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw),\n+\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n+}\n+\n+/**\n+ * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.\n+ * @hw: pointer to hardware structure\n+ *\n+ * Configure DMA coalescing threshold per TC and set high priority bit for\n+ * FCOE TC. The dmac enable bit must be cleared before configuring.\n+ **/\n+s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw),\n+\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n+}\n+\n+/**\n+ * ixgbe_setup_eee - Enable/disable EEE support\n+ * @hw: pointer to the HW structure\n+ * @enable_eee: boolean flag to enable EEE\n+ *\n+ * Enable/disable EEE based on enable_ee flag.\n+ * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C\n+ * are modified.\n+ *\n+ **/\n+s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee),\n+\t\t\tIXGBE_NOT_IMPLEMENTED);\n+}\n+\n+/**\n+ * ixgbe_set_source_address_pruning - Enable/Disable source address pruning\n+ * @hw: pointer to hardware structure\n+ * @enbale: enable or disable source address pruning\n+ * @pool: Rx pool - Rx pool to toggle source address pruning\n+ **/\n+void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,\n+\t\t\t\t unsigned int pool)\n+{\n+\tif (hw->mac.ops.set_source_address_pruning)\n+\t\thw->mac.ops.set_source_address_pruning(hw, enable, pool);\n+}\n+\n+/**\n+ * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing\n+ * @hw: pointer to hardware structure\n+ * @enable: enable or disable switch for Ethertype anti-spoofing\n+ * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing\n+ *\n+ **/\n+void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\n+{\n+\tif (hw->mac.ops.set_ethertype_anti_spoofing)\n+\t\thw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf);\n+}\n+\n+/**\n+ * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit address of PHY register to read\n+ * @device_type: type of device you want to communicate with\n+ * @phy_data: Pointer to read data from PHY register\n+ *\n+ * Reads a value from a specified PHY register\n+ **/\n+s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n+\t\t\t u32 device_type, u32 *phy_data)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr,\n+\t\t\t device_type, phy_data), IXGBE_NOT_IMPLEMENTED);\n+}\n+\n+/**\n+ * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband\n+ * @hw: pointer to hardware structure\n+ * @reg_addr: 32 bit PHY register to write\n+ * @device_type: type of device you want to communicate with\n+ * @phy_data: Data to write to the PHY register\n+ *\n+ * Writes a value to specified PHY register\n+ **/\n+s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n+\t\t\t u32 device_type, u32 phy_data)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr,\n+\t\t\t device_type, phy_data), IXGBE_NOT_IMPLEMENTED);\n+}\n+\n+/**\n+ * ixgbe_disable_mdd - Disable malicious driver detection\n+ * @hw: pointer to hardware structure\n+ *\n+ **/\n+void ixgbe_disable_mdd(struct ixgbe_hw *hw)\n+{\n+\tif (hw->mac.ops.disable_mdd)\n+\t\thw->mac.ops.disable_mdd(hw);\n+}\n+\n+/**\n+ * ixgbe_enable_mdd - Enable malicious driver detection\n+ * @hw: pointer to hardware structure\n+ *\n+ **/\n+void ixgbe_enable_mdd(struct ixgbe_hw *hw)\n+{\n+\tif (hw->mac.ops.enable_mdd)\n+\t\thw->mac.ops.enable_mdd(hw);\n+}\n \n+/**\n+ * ixgbe_mdd_event - Handle malicious driver detection event\n+ * @hw: pointer to hardware structure\n+ * @vf_bitmap: vf bitmap of malicious vfs\n+ *\n+ **/\n+void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap)\n+{\n+\tif (hw->mac.ops.mdd_event)\n+\t\thw->mac.ops.mdd_event(hw, vf_bitmap);\n+}\n+\n+/**\n+ * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver\n+ * detection event\n+ * @hw: pointer to hardware structure\n+ * @vf: vf index\n+ *\n+ **/\n+void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf)\n+{\n+\tif (hw->mac.ops.restore_mdd_vf)\n+\t\thw->mac.ops.restore_mdd_vf(hw, vf);\n+}\n \n /**\n * ixgbe_read_analog_reg8 - Reads 8 bit analog register\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h\nindex 88a31e8..c63664a 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h\n@@ -125,6 +125,8 @@ s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n s32 ixgbe_fc_enable(struct ixgbe_hw *hw);\n s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n \t\t\t u8 ver);\n+s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw);\n+s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw);\n void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);\n s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,\n \t\t\t\t u16 *firmware_version);\n@@ -177,6 +179,22 @@ void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);\n s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n \t\t\t u16 *wwpn_prefix);\n s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);\n+s32 ixgbe_dmac_config(struct ixgbe_hw *hw);\n+s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw);\n+s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw);\n+s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee);\n+void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,\n+\t\t\t\t unsigned int vf);\n+void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable,\n+\t\t\t\t int vf);\n+s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n+\t\t\tu32 device_type, u32 *phy_data);\n+s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n+\t\t\tu32 device_type, u32 phy_data);\n+void ixgbe_disable_mdd(struct ixgbe_hw *hw);\n+void ixgbe_enable_mdd(struct ixgbe_hw *hw);\n+void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap);\n+void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf);\n void ixgbe_disable_rx(struct ixgbe_hw *hw);\n void ixgbe_enable_rx(struct ixgbe_hw *hw);\n \ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\nindex 833aae9..a799b40 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n@@ -4605,6 +4605,175 @@ void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)\n \tIXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);\n }\n \n+STATIC const u8 ixgbe_emc_temp_data[4] = {\n+\tIXGBE_EMC_INTERNAL_DATA,\n+\tIXGBE_EMC_DIODE1_DATA,\n+\tIXGBE_EMC_DIODE2_DATA,\n+\tIXGBE_EMC_DIODE3_DATA\n+};\n+STATIC const u8 ixgbe_emc_therm_limit[4] = {\n+\tIXGBE_EMC_INTERNAL_THERM_LIMIT,\n+\tIXGBE_EMC_DIODE1_THERM_LIMIT,\n+\tIXGBE_EMC_DIODE2_THERM_LIMIT,\n+\tIXGBE_EMC_DIODE3_THERM_LIMIT\n+};\n+\n+/**\n+ * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n+ * @hw: pointer to hardware structure\n+ * @data: pointer to the thermal sensor data structure\n+ *\n+ * Returns the thermal sensor data structure\n+ **/\n+s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)\n+{\n+\ts32 status = IXGBE_SUCCESS;\n+\tu16 ets_offset;\n+\tu16 ets_cfg;\n+\tu16 ets_sensor;\n+\tu8 num_sensors;\n+\tu8 sensor_index;\n+\tu8 sensor_location;\n+\tu8 i;\n+\tstruct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;\n+\n+\tDEBUGFUNC(\"ixgbe_get_thermal_sensor_data_generic\");\n+\n+\t/* Only support thermal sensors attached to 82599 physical port 0 */\n+\tif ((hw->mac.type != ixgbe_mac_82599EB) ||\n+\t (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {\n+\t\tstatus = IXGBE_NOT_IMPLEMENTED;\n+\t\tgoto out;\n+\t}\n+\n+\tstatus = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);\n+\tif (status)\n+\t\tgoto out;\n+\n+\tif ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {\n+\t\tstatus = IXGBE_NOT_IMPLEMENTED;\n+\t\tgoto out;\n+\t}\n+\n+\tstatus = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);\n+\tif (status)\n+\t\tgoto out;\n+\n+\tif (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)\n+\t\t!= IXGBE_ETS_TYPE_EMC) {\n+\t\tstatus = IXGBE_NOT_IMPLEMENTED;\n+\t\tgoto out;\n+\t}\n+\n+\tnum_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);\n+\tif (num_sensors > IXGBE_MAX_SENSORS)\n+\t\tnum_sensors = IXGBE_MAX_SENSORS;\n+\n+\tfor (i = 0; i < num_sensors; i++) {\n+\t\tstatus = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),\n+\t\t\t\t\t &ets_sensor);\n+\t\tif (status)\n+\t\t\tgoto out;\n+\n+\t\tsensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>\n+\t\t\t\tIXGBE_ETS_DATA_INDEX_SHIFT);\n+\t\tsensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>\n+\t\t\t\t IXGBE_ETS_DATA_LOC_SHIFT);\n+\n+\t\tif (sensor_location != 0) {\n+\t\t\tstatus = hw->phy.ops.read_i2c_byte(hw,\n+\t\t\t\t\tixgbe_emc_temp_data[sensor_index],\n+\t\t\t\t\tIXGBE_I2C_THERMAL_SENSOR_ADDR,\n+\t\t\t\t\t&data->sensor[i].temp);\n+\t\t\tif (status)\n+\t\t\t\tgoto out;\n+\t\t}\n+\t}\n+out:\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds\n+ * @hw: pointer to hardware structure\n+ *\n+ * Inits the thermal sensor thresholds according to the NVM map\n+ * and save off the threshold and location values into mac.thermal_sensor_data\n+ **/\n+s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)\n+{\n+\ts32 status = IXGBE_SUCCESS;\n+\tu16 offset;\n+\tu16 ets_offset;\n+\tu16 ets_cfg;\n+\tu16 ets_sensor;\n+\tu8 low_thresh_delta;\n+\tu8 num_sensors;\n+\tu8 sensor_index;\n+\tu8 sensor_location;\n+\tu8 therm_limit;\n+\tu8 i;\n+\tstruct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;\n+\n+\tDEBUGFUNC(\"ixgbe_init_thermal_sensor_thresh_generic\");\n+\n+\tmemset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));\n+\n+\t/* Only support thermal sensors attached to 82599 physical port 0 */\n+\tif ((hw->mac.type != ixgbe_mac_82599EB) ||\n+\t (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))\n+\t\treturn IXGBE_NOT_IMPLEMENTED;\n+\n+\toffset = IXGBE_ETS_CFG;\n+\tif (hw->eeprom.ops.read(hw, offset, &ets_offset))\n+\t\tgoto eeprom_err;\n+\tif ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))\n+\t\treturn IXGBE_NOT_IMPLEMENTED;\n+\n+\toffset = ets_offset;\n+\tif (hw->eeprom.ops.read(hw, offset, &ets_cfg))\n+\t\tgoto eeprom_err;\n+\tif (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)\n+\t\t!= IXGBE_ETS_TYPE_EMC)\n+\t\treturn IXGBE_NOT_IMPLEMENTED;\n+\n+\tlow_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>\n+\t\t\t IXGBE_ETS_LTHRES_DELTA_SHIFT);\n+\tnum_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);\n+\n+\tfor (i = 0; i < num_sensors; i++) {\n+\t\toffset = ets_offset + 1 + i;\n+\t\tif (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {\n+\t\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n+\t\t\t\t \"eeprom read at offset %d failed\",\n+\t\t\t\t offset);\n+\t\t\tcontinue;\n+\t\t}\n+\t\tsensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>\n+\t\t\t\tIXGBE_ETS_DATA_INDEX_SHIFT);\n+\t\tsensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>\n+\t\t\t\t IXGBE_ETS_DATA_LOC_SHIFT);\n+\t\ttherm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;\n+\n+\t\thw->phy.ops.write_i2c_byte(hw,\n+\t\t\tixgbe_emc_therm_limit[sensor_index],\n+\t\t\tIXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);\n+\n+\t\tif ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {\n+\t\t\tdata->sensor[i].location = sensor_location;\n+\t\t\tdata->sensor[i].caution_thresh = therm_limit;\n+\t\t\tdata->sensor[i].max_op_thresh = therm_limit -\n+\t\t\t\t\t\t\tlow_thresh_delta;\n+\t\t}\n+\t}\n+\treturn status;\n+\n+eeprom_err:\n+\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n+\t\t \"eeprom read at offset %d failed\", offset);\n+\treturn IXGBE_NOT_IMPLEMENTED;\n+}\n+\n \n /**\n * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h\nindex 14f1fec..bfd41aa 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h\n@@ -165,6 +165,18 @@ extern s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);\n extern void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);\n bool ixgbe_mng_enabled(struct ixgbe_hw *hw);\n \n+#define IXGBE_I2C_THERMAL_SENSOR_ADDR\t0xF8\n+#define IXGBE_EMC_INTERNAL_DATA\t\t0x00\n+#define IXGBE_EMC_INTERNAL_THERM_LIMIT\t0x20\n+#define IXGBE_EMC_DIODE1_DATA\t\t0x01\n+#define IXGBE_EMC_DIODE1_THERM_LIMIT\t0x19\n+#define IXGBE_EMC_DIODE2_DATA\t\t0x23\n+#define IXGBE_EMC_DIODE2_THERM_LIMIT\t0x1A\n+#define IXGBE_EMC_DIODE3_DATA\t\t0x2A\n+#define IXGBE_EMC_DIODE3_THERM_LIMIT\t0x30\n+\n+s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);\n+s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);\n void ixgbe_disable_rx_generic(struct ixgbe_hw *hw);\n void ixgbe_enable_rx_generic(struct ixgbe_hw *hw);\n #endif /* IXGBE_COMMON */\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\nindex 48f25d1..40ebed9 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n@@ -181,6 +181,26 @@ POSSIBILITY OF SUCH DAMAGE.\n \t\t\t\t\t0x00000400 : 0x00000008)\n #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT\t500\n \n+#define IXGBE_I2C_THERMAL_SENSOR_ADDR\t0xF8\n+#define IXGBE_EMC_INTERNAL_DATA\t\t0x00\n+#define IXGBE_EMC_INTERNAL_THERM_LIMIT\t0x20\n+#define IXGBE_EMC_DIODE1_DATA\t\t0x01\n+#define IXGBE_EMC_DIODE1_THERM_LIMIT\t0x19\n+#define IXGBE_EMC_DIODE2_DATA\t\t0x23\n+#define IXGBE_EMC_DIODE2_THERM_LIMIT\t0x1A\n+\n+#define IXGBE_MAX_SENSORS\t\t3\n+\n+struct ixgbe_thermal_diode_data {\n+\tu8 location;\n+\tu8 temp;\n+\tu8 caution_thresh;\n+\tu8 max_op_thresh;\n+};\n+\n+struct ixgbe_thermal_sensor_data {\n+\tstruct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];\n+};\n \n /* Interrupt Registers */\n #define IXGBE_EICR\t\t0x00800\n@@ -400,6 +420,8 @@ POSSIBILITY OF SUCH DAMAGE.\n #define IXGBE_SPOOF_MACAS_MASK\t\t0xFF\n #define IXGBE_SPOOF_VLANAS_MASK\t\t0xFF00\n #define IXGBE_SPOOF_VLANAS_SHIFT\t8\n+#define IXGBE_SPOOF_ETHERTYPEAS\t\t0xFF000000\n+#define IXGBE_SPOOF_ETHERTYPEAS_SHIFT\t16\n #define IXGBE_PFVFSPOOF_REG_COUNT\t8\n /* 16 of these (0-15) */\n #define IXGBE_DCA_TXCTRL(_i)\t\t(0x07200 + ((_i) * 4))\n@@ -502,6 +524,56 @@ POSSIBILITY OF SUCH DAMAGE.\n #define IXGBE_TDPT2TCCR(_i)\t(0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */\n #define IXGBE_TDPT2TCSR(_i)\t(0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */\n \n+/* Power Management */\n+/* DMA Coalescing configuration */\n+struct ixgbe_dmac_config {\n+\tu16\twatchdog_timer; /* usec units */\n+\tbool\tfcoe_en;\n+\tu32\tlink_speed;\n+\tu8\tfcoe_tc;\n+\tu8\tnum_tcs;\n+};\n+\n+/*\n+ * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed.\n+ * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 ==\n+ * 87500 bytes [85KB]\n+ */\n+#define IXGBE_DMACRXT_10G\t\t0x55\n+#define IXGBE_DMACRXT_1G\t\t0x09\n+#define IXGBE_DMACRXT_100M\t\t0x01\n+\n+/* DMA Coalescing registers */\n+#define IXGBE_DMCMNGTH\t\t\t0x15F20 /* Management Threshold */\n+#define IXGBE_DMACR\t\t\t0x02400 /* Control register */\n+#define IXGBE_DMCTH(_i)\t\t\t(0x03300 + ((_i) * 4)) /* 8 of these */\n+#define IXGBE_DMCTLX\t\t\t0x02404 /* Time to Lx request */\n+/* DMA Coalescing register fields */\n+#define IXGBE_DMCMNGTH_DMCMNGTH_MASK\t0x000FFFF0 /* Mng Threshold mask */\n+#define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT\t4 /* Management Threshold shift */\n+#define IXGBE_DMACR_DMACWT_MASK\t\t0x0000FFFF /* Watchdog Timer mask */\n+#define IXGBE_DMACR_HIGH_PRI_TC_MASK\t0x00FF0000\n+#define IXGBE_DMACR_HIGH_PRI_TC_SHIFT\t16\n+#define IXGBE_DMACR_EN_MNG_IND\t\t0x10000000 /* Enable Mng Indications */\n+#define IXGBE_DMACR_LX_COAL_IND\t\t0x40000000 /* Lx Coalescing indicate */\n+#define IXGBE_DMACR_DMAC_EN\t\t0x80000000 /* DMA Coalescing Enable */\n+#define IXGBE_DMCTH_DMACRXT_MASK\t0x000001FF /* Receive Threshold mask */\n+#define IXGBE_DMCTLX_TTLX_MASK\t\t0x00000FFF /* Time to Lx request mask */\n+\n+/* EEE registers */\n+#define IXGBE_EEER\t\t\t0x043A0 /* EEE register */\n+#define IXGBE_EEE_STAT\t\t\t0x04398 /* EEE Status */\n+#define IXGBE_EEE_SU\t\t\t0x04380 /* EEE Set up */\n+#define IXGBE_TLPIC\t\t\t0x041F4 /* EEE Tx LPI count */\n+#define IXGBE_RLPIC\t\t\t0x041F8 /* EEE Rx LPI count */\n+\n+/* EEE register fields */\n+#define IXGBE_EEER_TX_LPI_EN\t\t0x00010000 /* Enable EEE LPI TX path */\n+#define IXGBE_EEER_RX_LPI_EN\t\t0x00020000 /* Enable EEE LPI RX path */\n+#define IXGBE_EEE_STAT_NEG\t\t0x20000000 /* EEE support neg on link */\n+#define IXGBE_EEE_RX_LPI_STATUS\t\t0x40000000 /* RX Link in LPI status */\n+#define IXGBE_EEE_TX_LPI_STATUS\t\t0x80000000 /* TX Link in LPI status */\n+\n \n \n /* Security Control Registers */\n@@ -1605,6 +1677,7 @@ enum {\n #define IXGBE_MAX_ETQF_FILTERS\t\t8\n #define IXGBE_ETQF_FCOE\t\t\t0x08000000 /* bit 27 */\n #define IXGBE_ETQF_BCN\t\t\t0x10000000 /* bit 28 */\n+#define IXGBE_ETQF_TX_ANTISPOOF\t\t0x20000000 /* bit 29 */\n #define IXGBE_ETQF_1588\t\t\t0x40000000 /* bit 30 */\n #define IXGBE_ETQF_FILTER_EN\t\t0x80000000 /* bit 31 */\n #define IXGBE_ETQF_POOL_ENABLE\t\t(1 << 26) /* bit 26 */\n@@ -1824,6 +1897,9 @@ enum {\n #define IXGBE_GSSR_MAC_CSR_SM\t0x0008\n #define IXGBE_GSSR_FLASH_SM\t0x0010\n #define IXGBE_GSSR_SW_MNG_SM\t0x0400\n+#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */\n+#define IXGBE_GSSR_I2C_MASK\t0x1800\n+#define IXGBE_GSSR_NVM_PHY_MASK\t0xF\n \n /* FW Status register bitmask */\n #define IXGBE_FWSTS_FWRI\t0x00000200 /* Firmware Reset Indication */\n@@ -3160,15 +3236,24 @@ struct ixgbe_mac_operations {\n \n \t/* Manageability interface */\n \ts32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);\n+\ts32 (*get_thermal_sensor_data)(struct ixgbe_hw *);\n+\ts32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);\n \ts32 (*dmac_config)(struct ixgbe_hw *hw);\n \ts32 (*dmac_update_tcs)(struct ixgbe_hw *hw);\n \ts32 (*dmac_config_tcs)(struct ixgbe_hw *hw);\n \tvoid (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);\n-\ts32 (*set_eee)(struct ixgbe_hw *hw, bool enable_eee);\n-\ts32 (*eee_linkup)(struct ixgbe_hw *hw, bool eee_enabled);\n+\ts32 (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee);\n \tvoid (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);\n+\tvoid (*set_source_address_pruning)(struct ixgbe_hw *, bool,\n+\t\t\t\t\t unsigned int);\n \tvoid (*disable_rx)(struct ixgbe_hw *hw);\n \tvoid (*enable_rx)(struct ixgbe_hw *hw);\n+\ts32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);\n+\ts32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);\n+\tvoid (*disable_mdd)(struct ixgbe_hw *hw);\n+\tvoid (*enable_mdd)(struct ixgbe_hw *hw);\n+\tvoid (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap);\n+\tvoid (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf);\n };\n \n struct ixgbe_phy_operations {\n@@ -3234,6 +3319,9 @@ struct ixgbe_mac_info {\n \tbool orig_link_settings_stored;\n \tbool autotry_restart;\n \tu8 flags;\n+\tstruct ixgbe_thermal_sensor_data thermal_sensor_data;\n+\tbool thermal_sensor_enabled;\n+\tstruct ixgbe_dmac_config dmac_config;\n \tbool set_lben;\n };\n \n@@ -3351,12 +3439,66 @@ struct ixgbe_hw {\n #define IXGBE_ERR_OUT_OF_MEM\t\t\t-34\n #define IXGBE_ERR_FEATURE_NOT_SUPPORTED\t\t-36\n #define IXGBE_ERR_EEPROM_PROTECTED_REGION\t-37\n+#define IXGBE_ERR_FDIR_CMD_INCOMPLETE\t\t-38\n \n #define IXGBE_NOT_IMPLEMENTED\t\t\t0x7FFFFFFF\n \n \n-#ifdef IXGBE_OSDEP2\n-#include \"ixgbe_osdep2.h\"\n+#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P)\t((P == 0) ? (0x4010) : (0x8010))\n+#define IXGBE_KRM_LINK_CTRL_1(P)\t((P == 0) ? (0x420C) : (0x820C))\n+#define IXGBE_KRM_DSP_TXFFE_STATE_4(P)\t((P == 0) ? (0x4634) : (0x8634))\n+#define IXGBE_KRM_DSP_TXFFE_STATE_5(P)\t((P == 0) ? (0x4638) : (0x8638))\n+#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P)\t((P == 0) ? (0x4B00) : (0x8B00))\n+#define IXGBE_KRM_PMD_DFX_BURNIN(P)\t((P == 0) ? (0x4E00) : (0x8E00))\n+#define IXGBE_KRM_TX_COEFF_CTRL_1(P)\t((P == 0) ? (0x5520) : (0x9520))\n+#define IXGBE_KRM_RX_ANA_CTL(P)\t\t((P == 0) ? (0x5A00) : (0x9A00))\n+\n+#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B\t\t(1 << 9)\n+#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS\t\t(1 << 11)\n+\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK\t(0x7 << 8)\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G\t(2 << 8)\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G\t(4 << 8)\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ\t\t(1 << 14)\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC\t\t(1 << 15)\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX\t\t(1 << 16)\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR\t\t(1 << 18)\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX\t\t(1 << 24)\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR\t\t(1 << 26)\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE\t\t(1 << 29)\n+#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART\t\t(1 << 31)\n+\n+#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN\t\t\t(1 << 6)\n+#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN\t\t(1 << 15)\n+#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN\t\t(1 << 16)\n+\n+#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL\t(1 << 4)\n+#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS\t(1 << 2)\n+\n+#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK\t(0x3 << 16)\n+\n+#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN\t(1 << 1)\n+#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN\t(1 << 2)\n+#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN\t\t(1 << 3)\n+#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN\t\t(1 << 31)\n+\n+#define IXGBE_SB_IOSF_INDIRECT_CTRL\t0x00011144\n+#define IXGBE_SB_IOSF_INDIRECT_DATA\t0x00011148\n+\n+#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT\t\t0\n+#define IXGBE_SB_IOSF_CTRL_ADDR_MASK\t\t0xFF\n+#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT\t18\n+#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK\t\\\n+\t\t\t\t(0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)\n+#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT\t20\n+#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK\t\\\n+\t\t\t\t(0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)\n+#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT\t28\n+#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK\t0x7\n+#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT\t\t31\n+#define IXGBE_SB_IOSF_CTRL_BUSY\t\t(1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)\n+#define IXGBE_SB_IOSF_TARGET_KR_PHY\t0\n+#define IXGBE_SB_IOSF_TARGET_KX4_PHY\t1\n+#define IXGBE_SB_IOSF_TARGET_KX4_PCS\t2\n \n-#endif /* IXGBE_OSDEP2 */\n #endif /* _IXGBE_TYPE_H_ */\n", "prefixes": [ "dpdk-dev", "v2", "16/18" ] }