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GET /api/patches/63130/?format=api
{ "id": 63130, "url": "https://patches.dpdk.org/api/patches/63130/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20191120034808.2760-3-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191120034808.2760-3-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191120034808.2760-3-pbhagavatula@marvell.com", "date": "2019-11-20T03:48:03", "name": "[v2,2/6] net/octeontx: add application domain validation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3a1c1e6d5f3d9f1945c5b1c1e029b6352c65f74f", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20191120034808.2760-3-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 7533, "url": "https://patches.dpdk.org/api/series/7533/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=7533", "date": "2019-11-20T03:48:01", "name": "octeontx: sync with latest SDK", "version": 2, "mbox": "https://patches.dpdk.org/series/7533/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/63130/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/63130/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 65748A04C1;\n\tWed, 20 Nov 2019 04:48:34 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B0A451B93E;\n\tWed, 20 Nov 2019 04:48:20 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 38B251B103\n for <dev@dpdk.org>; Wed, 20 Nov 2019 04:48:19 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n xAK3jMsC022947 for <dev@dpdk.org>; Tue, 19 Nov 2019 19:48:18 -0800", "from sc-exch02.marvell.com ([199.233.58.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 2wc82vnp2q-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 19 Nov 2019 19:48:18 -0800", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 19 Nov\n 2019 19:48:17 -0800", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n Transport; Tue, 19 Nov 2019 19:48:16 -0800", "from BG-LT7430.marvell.com (unknown [10.28.17.72])\n by maili.marvell.com (Postfix) with ESMTP id 6AA6A3F703F;\n Tue, 19 Nov 2019 19:48:15 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0818;\n bh=4PcrhdBcRAPMty5G7XjDnsDF06Hf6SVecoF2yDKaLj4=;\n b=DB43ZN55poqIq6ir6baV2h+MypchomWsWY/dEeLw4eGrpJXyMYZlvQAiHQxlmA+2/0uI\n PNrtqj2OSA/4hWIv0peAX/XLhLhQiAIZcY2j5KXwGrnOAp4gyCtPudfZM5NOfDD3kx2m\n zezZ44J2DGlHgzTLhMG6ADhrdYNmtIk3tqLZS+tVjdEnygLU/0uleOYjrpW7FKmHzBCp\n h2VqrfrhowFN1OAlALAtfI0M/sapFUCV6rjSYMMJAlRisoWJnhBbve55WZvakRfhOe8k\n sXNSfZI7UTsDy0RaXBTOD6qmSBOTEOBHHep+fQbzeDHmwzndzCtf1rnDDYCdIp88XYtv ow==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Wed, 20 Nov 2019 09:18:03 +0530", "Message-ID": "<20191120034808.2760-3-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20191120034808.2760-1-pbhagavatula@marvell.com>", "References": "<20191120034808.2760-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,18.0.572\n definitions=2019-11-19_08:2019-11-15,2019-11-19 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 2/6] net/octeontx: add application domain\n\tvalidation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd domain validation for PKI and PKO vfs\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/octeontx/octeontx_mbox.c | 15 ++++-\n drivers/common/octeontx/octeontx_mbox.h | 6 +-\n .../octeontx/rte_common_octeontx_version.map | 1 +\n drivers/event/octeontx/ssovf_probe.c | 5 +-\n drivers/net/octeontx/base/octeontx_pkivf.c | 66 +++++++++++++++++--\n drivers/net/octeontx/base/octeontx_pkivf.h | 8 +--\n drivers/net/octeontx/base/octeontx_pkovf.c | 37 +++++++++--\n drivers/net/octeontx/base/octeontx_pkovf.h | 3 +\n drivers/net/octeontx/octeontx_ethdev.c | 13 +++-\n drivers/net/octeontx/octeontx_ethdev.h | 1 +\n 10 files changed, 135 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/common/octeontx/octeontx_mbox.c b/drivers/common/octeontx/octeontx_mbox.c\nindex 68cb0351f..2fd253107 100644\n--- a/drivers/common/octeontx/octeontx_mbox.c\n+++ b/drivers/common/octeontx/octeontx_mbox.c\n@@ -35,6 +35,7 @@ struct mbox {\n \tuint8_t *ram_mbox_base; /* Base address of mbox message stored in ram */\n \tuint8_t *reg; /* Store to this register triggers PF mbox interrupt */\n \tuint16_t tag_own; /* Last tag which was written to own channel */\n+\tuint16_t domain; /* Domain */\n \trte_spinlock_t lock;\n };\n \n@@ -198,7 +199,7 @@ mbox_send(struct mbox *m, struct octeontx_mbox_hdr *hdr, const void *txmsg,\n }\n \n int\n-octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base)\n+octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base, uint16_t domain)\n {\n \tstruct mbox *m = &octeontx_mbox;\n \n@@ -215,13 +216,14 @@ octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base)\n \tif (m->reg != NULL) {\n \t\trte_spinlock_init(&m->lock);\n \t\tm->init_once = 1;\n+\t\tm->domain = domain;\n \t}\n \n \treturn 0;\n }\n \n int\n-octeontx_mbox_set_reg(uint8_t *reg)\n+octeontx_mbox_set_reg(uint8_t *reg, uint16_t domain)\n {\n \tstruct mbox *m = &octeontx_mbox;\n \n@@ -238,6 +240,7 @@ octeontx_mbox_set_reg(uint8_t *reg)\n \tif (m->ram_mbox_base != NULL) {\n \t\trte_spinlock_init(&m->lock);\n \t\tm->init_once = 1;\n+\t\tm->domain = domain;\n \t}\n \n \treturn 0;\n@@ -344,3 +347,11 @@ octeontx_mbox_init(void)\n \n \treturn 0;\n }\n+\n+uint16_t\n+octeontx_get_global_domain(void)\n+{\n+\tstruct mbox *m = &octeontx_mbox;\n+\n+\treturn m->domain;\n+}\ndiff --git a/drivers/common/octeontx/octeontx_mbox.h b/drivers/common/octeontx/octeontx_mbox.h\nindex 1f794c7f7..e56719cb8 100644\n--- a/drivers/common/octeontx/octeontx_mbox.h\n+++ b/drivers/common/octeontx/octeontx_mbox.h\n@@ -36,8 +36,10 @@ struct octeontx_mbox_hdr {\n };\n \n int octeontx_mbox_init(void);\n-int octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base);\n-int octeontx_mbox_set_reg(uint8_t *reg);\n+void octeontx_set_global_domain(uint16_t global_domain);\n+uint16_t octeontx_get_global_domain(void);\n+int octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base, uint16_t domain);\n+int octeontx_mbox_set_reg(uint8_t *reg, uint16_t domain);\n int octeontx_mbox_send(struct octeontx_mbox_hdr *hdr,\n \t\tvoid *txdata, uint16_t txlen, void *rxdata, uint16_t rxlen);\n \ndiff --git a/drivers/common/octeontx/rte_common_octeontx_version.map b/drivers/common/octeontx/rte_common_octeontx_version.map\nindex fdc036a62..2bba7cc93 100644\n--- a/drivers/common/octeontx/rte_common_octeontx_version.map\n+++ b/drivers/common/octeontx/rte_common_octeontx_version.map\n@@ -10,4 +10,5 @@ DPDK_19.08 {\n \tglobal:\n \n \tocteontx_mbox_init;\n+\tocteontx_get_global_domain;\n };\ndiff --git a/drivers/event/octeontx/ssovf_probe.c b/drivers/event/octeontx/ssovf_probe.c\nindex 9252998c1..4da7d1ae4 100644\n--- a/drivers/event/octeontx/ssovf_probe.c\n+++ b/drivers/event/octeontx/ssovf_probe.c\n@@ -181,7 +181,8 @@ ssowvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \tsdev.total_ssowvfs++;\n \tif (vfid == 0) {\n \t\tram_mbox_base = ssovf_bar(OCTEONTX_SSO_HWS, 0, 4);\n-\t\tif (octeontx_mbox_set_ram_mbox_base(ram_mbox_base)) {\n+\t\tif (octeontx_mbox_set_ram_mbox_base(ram_mbox_base,\n+\t\t\t\t\t\t res->domain)) {\n \t\t\tmbox_log_err(\"Invalid Failed to set ram mbox base\");\n \t\t\treturn -EINVAL;\n \t\t}\n@@ -257,7 +258,7 @@ ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \tif (vfid == 0) {\n \t\treg = ssovf_bar(OCTEONTX_SSO_GROUP, 0, 0);\n \t\treg += SSO_VHGRP_PF_MBOX(1);\n-\t\tif (octeontx_mbox_set_reg(reg)) {\n+\t\tif (octeontx_mbox_set_reg(reg, res->domain)) {\n \t\t\tmbox_log_err(\"Invalid Failed to set mbox_reg\");\n \t\t\treturn -EINVAL;\n \t\t}\ndiff --git a/drivers/net/octeontx/base/octeontx_pkivf.c b/drivers/net/octeontx/base/octeontx_pkivf.c\nindex 1babea0e8..783b2a2e5 100644\n--- a/drivers/net/octeontx/base/octeontx_pkivf.c\n+++ b/drivers/net/octeontx/base/octeontx_pkivf.c\n@@ -7,19 +7,50 @@\n #include <rte_eal.h>\n #include <rte_bus_pci.h>\n \n+#include \"../octeontx_logs.h\"\n+#include \"octeontx_io.h\"\n #include \"octeontx_pkivf.h\"\n \n+\n+struct octeontx_pkivf {\n+\tuint8_t\t\t*bar0;\n+\tuint8_t\t\tstatus;\n+\tuint16_t\tdomain;\n+\tuint16_t\tvfid;\n+};\n+\n+struct octeontx_pki_vf_ctl_s {\n+\tstruct octeontx_pkivf pki[PKI_VF_MAX];\n+};\n+\n+static struct octeontx_pki_vf_ctl_s pki_vf_ctl;\n+\n int\n octeontx_pki_port_open(int port)\n {\n+\tuint16_t global_domain = octeontx_get_global_domain();\n \tstruct octeontx_mbox_hdr hdr;\n-\tint res;\n+\tmbox_pki_port_t port_type = {\n+\t\t.port_type = OCTTX_PORT_TYPE_NET,\n+\t};\n+\tint i, res;\n+\n+\t/* Check if atleast one PKI vf is in application domain. */\n+\tfor (i = 0; i < PKI_VF_MAX; i++) {\n+\t\tif (pki_vf_ctl.pki[i].domain != global_domain)\n+\t\t\tcontinue;\n+\t\tbreak;\n+\t}\n+\n+\tif (i == PKI_VF_MAX)\n+\t\treturn -ENODEV;\n \n \thdr.coproc = OCTEONTX_PKI_COPROC;\n \thdr.msg = MBOX_PKI_PORT_OPEN;\n \thdr.vfid = port;\n \n-\tres = octeontx_mbox_send(&hdr, NULL, 0, NULL, 0);\n+\tres = octeontx_mbox_send(&hdr, &port_type, sizeof(mbox_pki_port_t),\n+\t\t\t\t NULL, 0);\n \tif (res < 0)\n \t\treturn -EACCES;\n \treturn res;\n@@ -113,13 +144,40 @@ octeontx_pki_port_errchk_config(int port, pki_errchk_cfg_t *cfg)\n static int\n pkivf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n {\n-\tRTE_SET_USED(pci_drv);\n-\tRTE_SET_USED(pci_dev);\n+\tstruct octeontx_pkivf *res;\n+\tstatic uint8_t vf_cnt;\n+\tuint16_t domain;\n+\tuint16_t vfid;\n+\tuint8_t *bar0;\n+\tuint64_t val;\n \n+\tRTE_SET_USED(pci_drv);\n \t/* For secondary processes, the primary has done all the work */\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\tif (pci_dev->mem_resource[0].addr == NULL) {\n+\t\tocteontx_log_err(\"PKI Empty bar[0] %p\",\n+\t\t\t\t pci_dev->mem_resource[0].addr);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tbar0 = pci_dev->mem_resource[0].addr;\n+\tval = octeontx_read64(bar0);\n+\tdomain = val & 0xffff;\n+\tvfid = (val >> 16) & 0xffff;\n+\n+\tif (unlikely(vfid >= PKI_VF_MAX)) {\n+\t\tocteontx_log_err(\"pki: Invalid vfid %d\", vfid);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tres = &pki_vf_ctl.pki[vf_cnt++];\n+\tres->vfid = vfid;\n+\tres->domain = domain;\n+\tres->bar0 = bar0;\n+\n+\tocteontx_log_dbg(\"PKI Domain=%d vfid=%d\", res->domain, res->vfid);\n \treturn 0;\n }\n \ndiff --git a/drivers/net/octeontx/base/octeontx_pkivf.h b/drivers/net/octeontx/base/octeontx_pkivf.h\nindex 7f19a4bb8..c2a944404 100644\n--- a/drivers/net/octeontx/base/octeontx_pkivf.h\n+++ b/drivers/net/octeontx/base/octeontx_pkivf.h\n@@ -48,6 +48,10 @@ enum {\n \tMBOX_PKI_PARSE_NOTHING = 0x7f\n };\n \n+/* PKI maximum constants */\n+#define PKI_VF_MAX\t\t\t(32)\n+#define PKI_MAX_PKTLEN\t\t\t(32768)\n+\n /* Interface types: */\n enum {\n \tOCTTX_PORT_TYPE_NET, /* Network interface ports */\n@@ -231,10 +235,6 @@ typedef struct mbox_pki_port_delete_qos_entry {\n \tuint16_t index;\n } mbox_pki_del_qos_t;\n \n-/* PKI maximum constants */\n-#define PKI_VF_MAX\t\t\t(1)\n-#define PKI_MAX_PKTLEN\t\t\t(32768)\n-\n /* pki pkind parse mode */\n enum {\n \tPKI_PARSE_LA_TO_LG = 0,\ndiff --git a/drivers/net/octeontx/base/octeontx_pkovf.c b/drivers/net/octeontx/base/octeontx_pkovf.c\nindex 0a6d64b8e..dacbdd0b4 100644\n--- a/drivers/net/octeontx/base/octeontx_pkovf.c\n+++ b/drivers/net/octeontx/base/octeontx_pkovf.c\n@@ -24,6 +24,8 @@ struct octeontx_pko_iomem {\n };\n \n #define PKO_IOMEM_NULL (struct octeontx_pko_iomem){0, 0, 0}\n+#define PKO_VALID\t0x1\n+#define PKO_INUSE\t0x2\n \n struct octeontx_pko_fc_ctl_s {\n \tint64_t buf_cnt;\n@@ -33,13 +35,14 @@ struct octeontx_pko_fc_ctl_s {\n struct octeontx_pkovf {\n \tuint8_t\t\t*bar0;\n \tuint8_t\t\t*bar2;\n+\tuint8_t\t\tstatus;\n \tuint16_t\tdomain;\n \tuint16_t\tvfid;\n };\n \n struct octeontx_pko_vf_ctl_s {\n \trte_spinlock_t lock;\n-\n+\tuint16_t global_domain;\n \tstruct octeontx_pko_iomem fc_iomem;\n \tstruct octeontx_pko_fc_ctl_s *fc_ctl;\n \tstruct octeontx_pkovf pko[PKO_VF_MAX];\n@@ -403,7 +406,7 @@ octeontx_pko_channel_query(struct octeontx_pko_vf_ctl_s *ctl, uint64_t chanid,\n \tcurr.lmtline_va = ctl->pko[dq_vf].bar2;\n \tcurr.ioreg_va = (void *)((uintptr_t)ctl->pko[dq_vf].bar0\n \t\t+ PKO_VF_DQ_OP_SEND((dq), 0));\n-\tcurr.fc_status_va = ctl->fc_ctl + dq;\n+\tcurr.fc_status_va = ctl->fc_ctl + dq_num;\n \n \tocteontx_log_dbg(\"lmtline=%p ioreg_va=%p fc_status_va=%p\",\n \t\t\t curr.lmtline_va, curr.ioreg_va,\n@@ -431,8 +434,10 @@ octeontx_pko_channel_query_dqs(int chanid, void *out, size_t out_elem_size,\n int\n octeontx_pko_vf_count(void)\n {\n+\tuint16_t global_domain = octeontx_get_global_domain();\n \tint vf_cnt;\n \n+\tpko_vf_ctl.global_domain = global_domain;\n \tvf_cnt = 0;\n \twhile (pko_vf_ctl.pko[vf_cnt].bar0)\n \t\tvf_cnt++;\n@@ -440,6 +445,26 @@ octeontx_pko_vf_count(void)\n \treturn vf_cnt;\n }\n \n+size_t\n+octeontx_pko_get_vfid(void)\n+{\n+\tsize_t vf_cnt = octeontx_pko_vf_count();\n+\tsize_t vf_idx;\n+\n+\n+\tfor (vf_idx = 0; vf_idx < vf_cnt; vf_idx++) {\n+\t\tif (!(pko_vf_ctl.pko[vf_idx].status & PKO_VALID))\n+\t\t\tcontinue;\n+\t\tif (pko_vf_ctl.pko[vf_idx].status & PKO_INUSE)\n+\t\t\tcontinue;\n+\n+\t\tpko_vf_ctl.pko[vf_idx].status |= PKO_INUSE;\n+\t\treturn pko_vf_ctl.pko[vf_idx].vfid;\n+\t}\n+\n+\treturn SIZE_MAX;\n+}\n+\n int\n octeontx_pko_init_fc(const size_t pko_vf_count)\n {\n@@ -467,8 +492,10 @@ octeontx_pko_init_fc(const size_t pko_vf_count)\n \n \t/* Configure Flow-Control feature for all DQs of open VFs */\n \tfor (vf_idx = 0; vf_idx < pko_vf_count; vf_idx++) {\n-\t\tdq_ix = vf_idx * PKO_VF_NUM_DQ;\n+\t\tif (pko_vf_ctl.pko[vf_idx].domain != pko_vf_ctl.global_domain)\n+\t\t\tcontinue;\n \n+\t\tdq_ix = pko_vf_ctl.pko[vf_idx].vfid * PKO_VF_NUM_DQ;\n \t\tvf_bar0 = pko_vf_ctl.pko[vf_idx].bar0;\n \n \t\treg = (pko_vf_ctl.fc_iomem.iova +\n@@ -479,6 +506,7 @@ octeontx_pko_init_fc(const size_t pko_vf_count)\n \t\t (0x1 << 0);\t\t/* ENABLE */\n \n \t\tocteontx_write64(reg, vf_bar0 + PKO_VF_DQ_FC_CONFIG);\n+\t\tpko_vf_ctl.pko[vf_idx].status = PKO_VALID;\n \n \t\tocteontx_log_dbg(\"PKO: bar0 %p VF_idx %d DQ_FC_CFG=%\" PRIx64 \"\",\n \t\t\t\t vf_bar0, (int)vf_idx, reg);\n@@ -528,6 +556,7 @@ pkovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \tuint16_t domain;\n \tuint8_t *bar0;\n \tuint8_t *bar2;\n+\tstatic uint8_t vf_cnt;\n \tstruct octeontx_pkovf *res;\n \n \tRTE_SET_USED(pci_drv);\n@@ -558,7 +587,7 @@ pkovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\treturn -EINVAL;\n \t}\n \n-\tres = &pko_vf_ctl.pko[vfid];\n+\tres = &pko_vf_ctl.pko[vf_cnt++];\n \tres->vfid = vfid;\n \tres->domain = domain;\n \tres->bar0 = bar0;\ndiff --git a/drivers/net/octeontx/base/octeontx_pkovf.h b/drivers/net/octeontx/base/octeontx_pkovf.h\nindex cbd28249f..4208ef880 100644\n--- a/drivers/net/octeontx/base/octeontx_pkovf.h\n+++ b/drivers/net/octeontx/base/octeontx_pkovf.h\n@@ -5,6 +5,8 @@\n #ifndef\t__OCTEONTX_PKO_H__\n #define\t__OCTEONTX_PKO_H__\n \n+#include <octeontx_mbox.h>\n+\n /* PKO maximum constants */\n #define\tPKO_VF_MAX\t\t\t(32)\n #define\tPKO_VF_NUM_DQ\t\t\t(8)\n@@ -63,6 +65,7 @@ int octeontx_pko_channel_close(int chanid);\n int octeontx_pko_channel_start(int chanid);\n int octeontx_pko_channel_stop(int chanid);\n int octeontx_pko_vf_count(void);\n+size_t octeontx_pko_get_vfid(void);\n int octeontx_pko_init_fc(const size_t pko_vf_count);\n void octeontx_pko_fc_free(void);\n \ndiff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c\nindex 00686ea26..c2258d136 100644\n--- a/drivers/net/octeontx/octeontx_ethdev.c\n+++ b/drivers/net/octeontx/octeontx_ethdev.c\n@@ -308,7 +308,7 @@ octeontx_dev_configure(struct rte_eth_dev *dev)\n \n \tnic->num_tx_queues = dev->data->nb_tx_queues;\n \n-\tret = octeontx_pko_channel_open(nic->port_id * PKO_VF_NUM_DQ,\n+\tret = octeontx_pko_channel_open(nic->pko_vfid * PKO_VF_NUM_DQ,\n \t\t\t\t\tnic->num_tx_queues,\n \t\t\t\t\tnic->base_ochan);\n \tif (ret) {\n@@ -719,7 +719,7 @@ octeontx_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,\n \tRTE_SET_USED(nb_desc);\n \tRTE_SET_USED(socket_id);\n \n-\tdq_num = (nic->port_id * PKO_VF_NUM_DQ) + qidx;\n+\tdq_num = (nic->pko_vfid * PKO_VF_NUM_DQ) + qidx;\n \n \t/* Socket id check */\n \tif (socket_id != (unsigned int)SOCKET_ID_ANY &&\n@@ -1001,6 +1001,7 @@ octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev,\n \t\t\tint socket_id)\n {\n \tint res;\n+\tsize_t pko_vfid;\n \tchar octtx_name[OCTEONTX_MAX_NAME_LEN];\n \tstruct octeontx_nic *nic = NULL;\n \tstruct rte_eth_dev *eth_dev = NULL;\n@@ -1039,7 +1040,15 @@ octeontx_create(struct rte_vdev_device *dev, int port, uint8_t evdev,\n \t\tgoto err;\n \t}\n \tdata->dev_private = nic;\n+\tpko_vfid = octeontx_pko_get_vfid();\n \n+\tif (pko_vfid == SIZE_MAX) {\n+\t\tocteontx_log_err(\"failed to get pko vfid\");\n+\t\tres = -ENODEV;\n+\t\tgoto err;\n+\t}\n+\n+\tnic->pko_vfid = pko_vfid;\n \tnic->port_id = port;\n \tnic->evdev = evdev;\n \ndiff --git a/drivers/net/octeontx/octeontx_ethdev.h b/drivers/net/octeontx/octeontx_ethdev.h\nindex fd2e99edf..50fae35d9 100644\n--- a/drivers/net/octeontx/octeontx_ethdev.h\n+++ b/drivers/net/octeontx/octeontx_ethdev.h\n@@ -58,6 +58,7 @@ struct octeontx_nic {\n \tuint8_t mcast_mode;\n \tuint16_t num_tx_queues;\n \tuint64_t hwcap;\n+\tuint8_t pko_vfid;\n \tuint8_t link_up;\n \tuint8_t\tduplex;\n \tuint8_t speed;\n", "prefixes": [ "v2", "2/6" ] }