Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 62024,
    "url": "https://patches.dpdk.org/api/patches/62024/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/8a96def4d6a17155821efd4ea8bf3c69bb08143a.1571928488.git.Pavel.Belous@aquantia.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<8a96def4d6a17155821efd4ea8bf3c69bb08143a.1571928488.git.Pavel.Belous@aquantia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/8a96def4d6a17155821efd4ea8bf3c69bb08143a.1571928488.git.Pavel.Belous@aquantia.com",
    "date": "2019-10-25T17:54:02",
    "name": "[RFC,v2,4/7] net/atlantic: add MACSEC internal HW data declaration and functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "rfc",
    "archived": true,
    "hash": "0a004686c49668ef4136b1c9a9056ea307b41f5b",
    "submitter": {
        "id": 1426,
        "url": "https://patches.dpdk.org/api/people/1426/?format=api",
        "name": "Pavel Belous",
        "email": "Pavel.Belous@aquantia.com"
    },
    "delegate": {
        "id": 6690,
        "url": "https://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/8a96def4d6a17155821efd4ea8bf3c69bb08143a.1571928488.git.Pavel.Belous@aquantia.com/mbox/",
    "series": [
        {
            "id": 7081,
            "url": "https://patches.dpdk.org/api/series/7081/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=7081",
            "date": "2019-10-25T17:53:49",
            "name": "RFC: Support MACSEC offload in the RTE_SECURITY infrastructure.",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/7081/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/62024/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/62024/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5FF3B1E544;\n\tFri, 25 Oct 2019 19:54:10 +0200 (CEST)",
            "from NAM05-DM3-obe.outbound.protection.outlook.com\n\t(mail-eopbgr730040.outbound.protection.outlook.com [40.107.73.40])\n\tby dpdk.org (Postfix) with ESMTP id D757A1E53F\n\tfor <dev@dpdk.org>; Fri, 25 Oct 2019 19:54:07 +0200 (CEST)",
            "from CY4PR1101MB2183.namprd11.prod.outlook.com (10.172.76.20) by\n\tCY4PR1101MB2311.namprd11.prod.outlook.com (10.174.53.140) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.2387.22; Fri, 25 Oct 2019 17:54:02 +0000",
            "from CY4PR1101MB2183.namprd11.prod.outlook.com\n\t([fe80::55e:4921:90d1:670a]) by\n\tCY4PR1101MB2183.namprd11.prod.outlook.com\n\t([fe80::55e:4921:90d1:670a%12]) with mapi id 15.20.2387.023;\n\tFri, 25 Oct 2019 17:54:02 +0000"
        ],
        "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n\tb=ZsmfsVDhCElVJtt7259UvEFyLGD1nUZYiRdomP2POleT9MICNjmXFWkI3FA/c7UvcxxlFHPHMPQcegYEvDCXOtjpsaL3ws4ItF7R6vhWsTXzSfXqK5ojN/oLDa7MyWqdnr3KnYQuXk0x4NxhZG4ne2YdyPGnmyUdjwn/Y5B4ntohi4u07ei0WIbm9fUV9YR5Rw2andE1WJtJVobbBjfY7FqViCDHJvNfoiDueUdWwEPclOLKpBG/Re+VjVI2ZroNJLZeIXGLO3KA2851CG6lTzvHj64mtIhkz/35HepRtQ8kOyV5nSkIDAM8ALavGV9Pa/6KUE7SmxklvPJdxDxbHw==",
        "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n\ts=arcselector9901;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=GIuVUkP66JZ6MLknlelkZJznFu/+r7t/pzaGRmkvcTA=;\n\tb=eAVqwJgxoIPXFtnKgMfDDnj5hPjOVLm0VNcVxh7dvMJPHzIe5YkEeS38MFZSJ0ePuJm8MD8TTecrPQJ+BVUl2+CcLb9MG0nsCNPUYFrKxW8gqyTmDTlxNjZxkE4jPUmsn+bkeWDmTaQcNFgih+pjG/Osm4L0KHM2m2JU3/8Mk4c9qeYeFqbOQTQo66+h7rCS9tqMVab2D/Z4cKXh5s5eJdY60i9bR1dwV8eP4Q6Qq3ASuN5FeeT+vyxEnd2HqSn1M1CTLyWsUtOeXdOAS+PPfz9mAu6YQjjk7rHc1q5E0+ZZdks7EQxTq6msBwecLwzaurVcPO3fpiisL8Z8IzFWGg==",
        "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n\tsmtp.mailfrom=aquantia.com;\n\tdmarc=pass action=none header.from=aquantia.com; \n\tdkim=pass header.d=aquantia.com; arc=none",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=AQUANTIA1COM.onmicrosoft.com;\n\ts=selector2-AQUANTIA1COM-onmicrosoft-com; \n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=GIuVUkP66JZ6MLknlelkZJznFu/+r7t/pzaGRmkvcTA=;\n\tb=RKJGzaX2ZPJtQbuyaxZe8j39gFf6tYMn+4lCNGVBeyYkm9zyK8pg/hB26qtZx4Ual64iH8y+ZP44aYxV+w1/nHjh8pBTx3hc0+1J0HQJB0cBuvseYEXyf4ius35Zla0DsHjZFlL9AbalQLVKLaAOq8NvUCdJUY6K7jZxve9Tw+k=",
        "From": "Pavel Belous <Pavel.Belous@aquantia.com>",
        "To": "\"dev@dpdk.org\" <dev@dpdk.org>",
        "CC": "Ferruh Yigit <ferruh.yigit@intel.com>, Akhil Goyal <akhil.goyal@nxp.com>,\n\tJohn McNamara <john.mcnamara@intel.com>, Declan Doherty\n\t<declan.doherty@intel.com>, Konstantin Ananyev\n\t<konstantin.ananyev@intel.com>, Thomas Monjalon <thomas@monjalon.net>,\n\tIgor Russkikh <Igor.Russkikh@aquantia.com>,\n\tFenilkumar Patel <fenpatel@cisco.com>, \n\tHitesh K Maisheri <hmaisher@cisco.com>, Pavel Belous\n\t<Pavel.Belous@aquantia.com>, Pavel Belous <Pavel.Belous@aquantia.com>",
        "Thread-Topic": "[RFC v2 4/7] net/atlantic: add MACSEC internal HW data\n\tdeclaration and functions",
        "Thread-Index": "AQHVi10vZ5oHVBWGfkSXHhlJ6Ih/LQ==",
        "Date": "Fri, 25 Oct 2019 17:54:02 +0000",
        "Message-ID": "<8a96def4d6a17155821efd4ea8bf3c69bb08143a.1571928488.git.Pavel.Belous@aquantia.com>",
        "References": "<cover.1571928488.git.Pavel.Belous@aquantia.com>",
        "In-Reply-To": "<cover.1571928488.git.Pavel.Belous@aquantia.com>",
        "Accept-Language": "en-US",
        "Content-Language": "en-US",
        "X-MS-Has-Attach": "",
        "X-MS-TNEF-Correlator": "",
        "x-clientproxiedby": "PR1PR01CA0020.eurprd01.prod.exchangelabs.com\n\t(2603:10a6:102::33) To CY4PR1101MB2183.namprd11.prod.outlook.com\n\t(2603:10b6:910:18::20)",
        "authentication-results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Pavel.Belous@aquantia.com; ",
        "x-ms-exchange-messagesentrepresentingtype": "1",
        "x-mailer": "git-send-email 2.7.4",
        "x-originating-ip": "[95.79.108.179]",
        "x-ms-publictraffictype": "Email",
        "x-ms-office365-filtering-correlation-id": "c37ead66-c1d5-4bc5-c229-08d75974519b",
        "x-ms-traffictypediagnostic": "CY4PR1101MB2311:",
        "x-ld-processed": "83e2e134-991c-4ede-8ced-34d47e38e6b1,ExtFwd",
        "x-ms-exchange-transport-forked": "True",
        "x-microsoft-antispam-prvs": "<CY4PR1101MB231148B8E28E4BACBB850C99E1650@CY4PR1101MB2311.namprd11.prod.outlook.com>",
        "x-ms-oob-tlc-oobclassifiers": "OLM:3276;",
        "x-forefront-prvs": "02015246A9",
        "x-forefront-antispam-report": "SFV:NSPM;\n\tSFS:(10009020)(39850400004)(366004)(396003)(376002)(136003)(346002)(199004)(189003)(66476007)(66556008)(486006)(66446008)(64756008)(7736002)(476003)(36756003)(86362001)(2616005)(6486002)(446003)(71200400001)(118296001)(6512007)(5640700003)(71190400001)(44832011)(2906002)(6436002)(2351001)(11346002)(305945005)(66946007)(30864003)(14454004)(5660300002)(508600001)(25786009)(4326008)(50226002)(66066001)(6116002)(2501003)(107886003)(3846002)(256004)(14444005)(19627235002)(54906003)(99286004)(6916009)(26005)(186003)(102836004)(76176011)(52116002)(386003)(6506007)(316002)(8676002)(1730700003)(81156014)(81166006)(8936002)(579004)(559001)(569006);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR1101MB2311;\n\tH:CY4PR1101MB2183.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; \n\tPTR:InfoNoRecords; A:1; MX:1; ",
        "received-spf": "None (protection.outlook.com: aquantia.com does not designate\n\tpermitted sender hosts)",
        "x-ms-exchange-senderadcheck": "1",
        "x-microsoft-antispam": "BCL:0;",
        "x-microsoft-antispam-message-info": "O7OC0eUgEd8TMHj4rx9+1sL8JEQZoY9u/EZD9D6HXq3xJ1Sdf0+8sd0PFsyaqwP7VoR4QtqcGN/U4u3W1OC5DWTZTSWccS8M1WaK2xhyiNY2cNs9bGnkI4+J2M+yKY9AwZG4U+lbjSC161TBFhOxnzoryCYUaCRH4jXbVehSMNhzdVRZ8sxyXpwchBg8Oai2ZDQgSPCKsfouh8Hl8BgCXNREIhUlgHhYPiFb7fbLFad3AG6BmCQtuz5Z/ymXCo/wv4J91m37OC/Qt1PmM2XN6W/ryOdQ1KGiXKPWuhKZoiJ4yncLJWgmoCqJtzFHhBYBrANXUakGT9AQfB9sL2pU2+mQSLy91h2VG7ZRDy4lBfJG4nXt9TzERkRfGXW+PYVD0dnGv6feK3NmY1xe8bhLFR4YiOWxDbiCNuYi08AOfOKzGBvCvZ9BXXrYLyz14Vcw",
        "Content-Type": "text/plain; charset=\"iso-8859-1\"",
        "Content-Transfer-Encoding": "quoted-printable",
        "MIME-Version": "1.0",
        "X-OriginatorOrg": "aquantia.com",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "c37ead66-c1d5-4bc5-c229-08d75974519b",
        "X-MS-Exchange-CrossTenant-originalarrivaltime": "25 Oct 2019 17:54:02.2082\n\t(UTC)",
        "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted",
        "X-MS-Exchange-CrossTenant-id": "83e2e134-991c-4ede-8ced-34d47e38e6b1",
        "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED",
        "X-MS-Exchange-CrossTenant-userprincipalname": "utIR3afYg0cy/z32rS37QE0zdurtb8dM7c7UL0aE0L/1eoWgfrD5PJ9yt/QLIJtvMCVvhmO8mQTzWkpFUtrarw==",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR1101MB2311",
        "Subject": "[dpdk-dev] [RFC v2 4/7] net/atlantic: add MACSEC internal HW data\n\tdeclaration and functions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Pavel Belous <Pavel.Belous@aquantia.com>\n\nMACSEC configuration is done by configuring multiple tables of MACSEC block:\n\n- Ingress Pre-Security Classification table\n- Ingress SC/SA/SAK lookup tables\n- Ingress Post-Security Classification table\n- Egress Packet Classifier table\n- Egress Control Filter table\n- Egress SC/SA/SAK lookup tables\n- Ingress/Egress SC/SA/Common counters tables\n- Some additional tables and spare registers\n\nEach entry of the tables is distributed across a set of PHY registers.\n\nThis patch adds declarations for internal MACSEC HW structures\nand helper functions (HAL) for accessing these tables inside MACSEC block.\n\nThis HAL was automatically generated based on the RTL design of the MACSEC\nblock.\n\nSigned-off-by: Pavel Belous <pavel.belous@aquantia.com>\nSigned-off-by: Igor Russkikh <igor.russkikh@aquantia.com>\n---\n drivers/net/atlantic/Makefile                      |    1 +\n drivers/net/atlantic/macsec/MSS_Egress_registers.h | 1498 ++++++++++++++++++\n .../net/atlantic/macsec/MSS_Ingress_registers.h    | 1135 ++++++++++++++\n drivers/net/atlantic/macsec/macsec_api.c           | 1612 ++++++++++++++++++++\n drivers/net/atlantic/macsec/macsec_api.h           |  111 ++\n drivers/net/atlantic/macsec/macsec_struct.h        |  269 ++++\n drivers/net/atlantic/meson.build                   |    1 +\n 7 files changed, 4627 insertions(+)\n create mode 100644 drivers/net/atlantic/macsec/MSS_Egress_registers.h\n create mode 100644 drivers/net/atlantic/macsec/MSS_Ingress_registers.h\n create mode 100644 drivers/net/atlantic/macsec/macsec_api.c\n create mode 100644 drivers/net/atlantic/macsec/macsec_api.h\n create mode 100644 drivers/net/atlantic/macsec/macsec_struct.h",
    "diff": "diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile\nindex 6340588..966676b 100644\n--- a/drivers/net/atlantic/Makefile\n+++ b/drivers/net/atlantic/Makefile\n@@ -35,5 +35,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils_fw2x.c\n SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_b0.c\n SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += rte_pmd_atlantic.c\n SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += mdio.c\n+SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += macsec_api.c\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/net/atlantic/macsec/MSS_Egress_registers.h b/drivers/net/atlantic/macsec/MSS_Egress_registers.h\nnew file mode 100644\nindex 0000000..ccbb20f\n--- /dev/null\n+++ b/drivers/net/atlantic/macsec/MSS_Egress_registers.h\n@@ -0,0 +1,1498 @@\n+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */\n+/* Copyright (C) 2014-2019 aQuantia Corporation. */\n+\n+#ifndef MSS_EGRESS_REGS_HEADER\n+#define MSS_EGRESS_REGS_HEADER\n+\n+\n+#define mssEgressVersionStatusRegister_ADDR 0x00005000\n+#define mssEgressControlRegister_ADDR 0x00005002\n+#define mssEgressPrescaleControlRegister_ADDR 0x00005004\n+#define mssEgressVlanTpid_0Register_ADDR 0x00005008\n+#define mssEgressVlanTpid_1Register_ADDR 0x0000500A\n+#define mssEgressVlanControlRegister_ADDR 0x0000500C\n+#define mssEgressPnControlRegister_ADDR 0x0000500E\n+#define mssEgressMtuSizeControlRegister_ADDR 0x00005010\n+#define mssEgressGcmDataInput_0ControlRegister_ADDR 0x00005012\n+#define mssEgressGcmDataInput_1ControlRegister_ADDR 0x00005014\n+#define mssEgressGcmDataInput_2ControlRegister_ADDR 0x00005016\n+#define mssEgressGcmDataInput_3ControlRegister_ADDR 0x00005018\n+#define mssEgressGcmKey_0ControlRegister_ADDR 0x0000501A\n+#define mssEgressGcmKey_0ControlRegister_word_REF(word) (0x0000501A\n+#define mssEgressGcmKey_1ControlRegister_ADDR 0x0000501C\n+#define mssEgressGcmKey_2ControlRegister_ADDR 0x0000501E\n+#define mssEgressGcmKey_3ControlRegister_ADDR 0x00005020\n+#define mssEgressGcmInitialVector_0ControlRegister_ADDR 0x00005022\n+#define mssEgressGcmInitialVector_1ControlRegister_ADDR 0x00005024\n+#define mssEgressGcmInitialVector_2ControlRegister_ADDR 0x00005026\n+#define mssEgressGcmInitialVector_3ControlRegister_ADDR 0x00005028\n+#define mssEgressGcmHashInput_0ControlRegister_ADDR 0x0000502A\n+#define mssEgressGcmHashInput_1ControlRegister_ADDR 0x0000502C\n+#define mssEgressGcmHashInput_2ControlRegister_ADDR 0x0000502E\n+#define mssEgressGcmHashInput_3ControlRegister_ADDR 0x00005030\n+#define mssEgressGcmDataOut_0StatusRegister_ADDR 0x00005032\n+#define mssEgressGcmDataOut_1StatusRegister_ADDR 0x00005034\n+#define mssEgressGcmDataOut_2StatusRegister_ADDR 0x00005036\n+#define mssEgressGcmDataOut_3StatusRegister_ADDR 0x00005038\n+#define mssEgressGcmHashOut_0StatusRegister_ADDR 0x0000503A\n+#define mssEgressGcmHashOut_1StatusRegister_ADDR 0x0000503C\n+#define mssEgressGcmHashOut_2StatusRegister_ADDR 0x0000503E\n+#define mssEgressGcmHashOut_3StatusRegister_ADDR 0x00005040\n+#define mssEgressBufferDebugStatusRegister_ADDR 0x00005042\n+#define mssEgressPacketFormatDebugStatusRegister_ADDR 0x00005044\n+#define mssEgressGcmMultLengthADebugStatusRegister_ADDR 0x00005046\n+#define mssEgressGcmMultLengthCDebugStatusRegister_ADDR 0x0000504A\n+#define mssEgressGcmMultDataCountDebugStatusRegister_ADDR 0x0000504E\n+#define mssEgressGcmCounterIncrmentDebugStatusRegister_ADDR 0x00005050\n+#define mssEgressGcmBusyDebugStatusRegister_ADDR 0x00005052\n+#define mssEgressSpareControlRegister_ADDR 0x00005054\n+#define mssEgressInterruptStatusRegister_ADDR 0x0000505C\n+#define mssEgressInterruptMaskRegister_ADDR 0x0000505E\n+#define mssEgressSaExpiredStatusRegister_ADDR 0x00005060\n+#define mssEgressSaThresholdExpiredStatusRegister_ADDR 0x00005062\n+#define mssEgressEccInterruptStatusRegister_ADDR 0x00005064\n+#define mssEgressEgprcLutEccError_1AddressStatusRegister_ADDR 0x00005066\n+#define mssEgressEgprcLutEccError_2AddressStatusRegister_ADDR 0x00005068\n+#define mssEgressEgprctlfLutEccErrorAddressStatusRegister_ADDR 0x0000506A\n+#define mssEgressEgpfmtLutEccErrorAddressStatusRegister_ADDR 0x0000506C\n+#define mssEgressEgmibEccErrorAddressStatusRegister_ADDR 0x0000506E\n+#define mssEgressEccControlRegister_ADDR 0x00005070\n+#define mssEgressDebugControlRegister_ADDR 0x00005072\n+#define mssEgressDebugStatusRegister_ADDR 0x00005074\n+#define mssEgressLutAddressControlRegister_ADDR 0x00005080\n+#define mssEgressLutControlRegister_ADDR 0x00005081\n+#define mssEgressLutDataControlRegister_ADDR 0x000050A0\n+\n+struct mssEgressVersionStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressID:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressVersion:8;\n+\t\t\tunsigned int mssEgressRevision:8;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSoftReset:1;\n+\t\t\tunsigned int mssEgressDropKayPacket:1;\n+\t\t\tunsigned int mssEgressDropEgprcLutMiss:1;\n+\t\t\tunsigned int mssEgressGcmStart:1;\n+\t\t\tunsigned int mssEgresssGcmTestMode:1;\n+\t\t\tunsigned int mssEgressUnmatchedUseSc_0:1;\n+\t\t\tunsigned int mssEgressDropInvalidSa_scPackets:1;\n+\t\t\tunsigned int mssEgressExplicitSectagReportShortLength:1;\n+\t\t\tunsigned int mssEgressExternalClassificationEnable:1;\n+\t\t\tunsigned int mssEgressIcvLsb_8BytesEnable:1;\n+\t\t\tunsigned int mssEgressHighPriority:1;\n+\t\t\tunsigned int mssEgressClearCounter:1;\n+\t\t\tunsigned int mssEgressClearGlobalTime:1;\n+\t\t\tunsigned int mssEgressEthertypeExplicitSectagLsb:3;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEthertypeExplicitSectagMsb:13;\n+\t\t\tunsigned int reserved0:3;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressPrescaleControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressPrescaleConfigurationLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressPrescaleConfigurationMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressVlanTpid_0Register_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressVlanStagTpid:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressVlanTpid_1Register_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressVlanQtagTpid:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressVlanControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressVlanUpMapTable:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressVlanUpMapTableMSW:8;\n+\t\t\tunsigned int mssEgressVlanUpDefault:3;\n+\t\t\tunsigned int mssEgressVlanStagUpParseEnable:1;\n+\t\t\tunsigned int mssEgressVlanQtagUpParseEnable:1;\n+\t\t\tunsigned int mssEgressVlanQinqParseEnable:1;\n+\t\t\tunsigned int mssEgressVlanStagParseEnable:1;\n+\t\t\tunsigned int mssEgressVlanQtagParseEnable:1;\n+\t\t} bits_1;\n+\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressPnControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSaPnThresholdLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSaPnThresholdMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressMtuSizeControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressControlledPacketMtuSize:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressUncontrolledPacketMtuSize:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmDataInput_0ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataInput_0LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataInput_0MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmDataInput_1ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataInput_1LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataInput_1MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmDataInput_2ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataInput_2LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataInput_2MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmDataInput_3ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataInput_3LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataInput_3MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmKey_0ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmKey_0LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmKey_0MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmKey_1ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmKey_1LSW:16;\n+\t\t} bits_0;\n+\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmKey_1MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmKey_2ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmKey_2LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmKey_2MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmKey_3ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmKey_3LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmKey_3MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmInitialVector_0ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmInitialVector_0LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmInitialVector_0MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmInitialVector_1ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmInitialVector_1LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmInitialVector_1MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmInitialVector_2ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmInitialVector_2LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmInitialVector_2MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmInitialVector_3ControlRegister_t\n+{\n+\t union\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmInitialVector_3LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmInitialVector_3MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmHashInput_0ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashInput_0LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashInput_0MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmHashInput_1ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashInput_1LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashInput_1MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmHashInput_2ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashInput_2LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashInput_2MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmHashInput_3ControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashInput_3LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashInput_3MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmDataOut_0StatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataOut_0LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataOut_0MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmDataOut_1StatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataOut_1LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataOut_1MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmDataOut_2StatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataOut_2LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataOut_2MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmDataOut_3StatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataOut_3LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmDataOut_3MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmHashOut_0StatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashOut_0LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashOut_0MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmHashOut_1StatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashOut_1LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashOut_1MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmHashOut_2StatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashOut_2LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashOut_2MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmHashOut_3StatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashOut_3LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmHashOut_3MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressBufferDebugStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEofInsertionDebug:4;\n+\t\t\tunsigned int mssEgressRemovalDebug:4;\n+\t\t\tunsigned int mssEgressRemovalS_wDebug:6;\n+\t\t\tunsigned int reserved0:2;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssEgressPacketFormatDebugStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressPacketFormatDebug:8;\n+\t\t\tunsigned int mssEgressSectagInsertionDebug:6;\n+\t\t\tunsigned int mssEgressPadInsertionDebugLsb:2;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressPadInsertionDebugMsb:4;\n+\t\t\tunsigned int mssEgressSectagRemovalDebug:6;\n+\t\t\tunsigned int reserved0:6;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmMultLengthADebugStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmMultLengthADebug_0:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmMultLengthADebug_1:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmMultLengthADebug_2:16;\n+\t\t} bits_2;\n+\t\tunsigned int word_2;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmMultLengthADebug_3:16;\n+\t\t} bits_3;\n+\t\tunsigned int word_3;\n+\t};\n+};\n+\n+struct mssEgressGcmMultLengthCDebugStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmMultLengthCDebug_0:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmMultLengthCDebug_1:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmMultLengthCDebug_2:16;\n+\t\t} bits_2;\n+\t\tunsigned int word_2;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmMultLengthCDebug_3:16;\n+\t\t} bits_3;\n+\t\tunsigned int word_3;\n+\t};\n+};\n+\n+struct mssEgressGcmMultDataCountDebugStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmMultDataCountDebug:2;\n+\t\t\tunsigned int reserved0:14;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssEgressGcmCounterIncrmentDebugStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmCounterIncrementDebugLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressGcmCounterIncrementDebugMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressGcmBusyDebugStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressDatapathBusy:1;\n+\t\t\tunsigned int mssEgressPacketFormatBusy:1;\n+\t\t\tunsigned int mssEgressAesCounterBusy:1;\n+\t\t\tunsigned int mssEgressPostGcmBufferBusy:1;\n+\t\t\tunsigned int mssEgressGcmBufferBusy:1;\n+\t\t\tunsigned int mssEgressLookupBusy:1;\n+\t\t\tunsigned int reserved0:10;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssEgressSpareControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSpareConfiguration_1LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSpareConfiguration_1MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSpareConfiguration_2LSW:16;\n+\t\t} bits_2;\n+\t\tunsigned int word_2;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSpareConfiguration_2MSW:16;\n+\t\t} bits_3;\n+\t\tunsigned int word_3;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSpareConfiguration_3LSW:16;\n+\t\t} bits_4;\n+\t\tunsigned int word_4;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSpareConfiguration_3MSW:16;\n+\t\t} bits_5;\n+\t\tunsigned int word_5;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSpareConfiguration_4LSW:16;\n+\t\t} bits_6;\n+\t\tunsigned int word_6;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSpareConfiguration_4MSW:16;\n+\t\t} bits_7;\n+\t\tunsigned int word_7;\n+\t};\n+};\n+\n+struct mssEgressInterruptStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressMasterInterrupt:1;\n+\t\t\tunsigned int mssEgressSaExpiredInterrupt:1;\n+\t\t\tunsigned int mssEgressSaThresholdExpiredInterrupt:1;\n+\t\t\tunsigned int mssEgressMibSaturationInterrupt:1;\n+\t\t\tunsigned int mssEgressEccErrorInterrupt:1;\n+\t\t\tunsigned int reserved0:11;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressInterruptMaskRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressMasterInterruptEnable:1;\n+\t\t\tunsigned int mssEgressSaExpiredInterruptEnable:1;\n+\t\t\tunsigned int mssEgressSaExpiredThresholdInterruptEnable:1;\n+\t\t\tunsigned int mssEgressMibSaturationInterruptEnable:1;\n+\t\t\tunsigned int mssEgressEccErrorInterruptEnable:1;\n+\t\t\tunsigned int reserved0:11;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressSaExpiredStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSaExpiredLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSaExpiredMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressSaThresholdExpiredStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSaThresholdExpiredLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSaThresholdExpiredMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressEccInterruptStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSaEccErrorInterruptLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressSaEccErrorInterruptMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressEgprcLutEccError_1AddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEgprcLutEccError_1AddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEgprcLutEccError_1AddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressEgprcLutEccError_2AddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEgprcLutEccError_2AddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEgprcLutEccError_2AddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressEgprctlfLutEccErrorAddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEgprctlfLutEccErrorAddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEgprctlfLutEccErrorAddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressEgpfmtLutEccErrorAddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEgpfmtLutEccErrorAddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEgpfmtLutEccErrorAddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressEgmibEccErrorAddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEgmibEccErrorAddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEgmibEccErrorAddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssEgressEccControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressEccEnable:1;\n+\t\t\tunsigned int mssEgressFastPnNumberEnable:1;\n+\t\t\tunsigned int reserved0:14;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssEgressDebugControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressDebugBusSelect:2;\n+\t\t\tunsigned int reserved0:14;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssEgressDebugStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressClassificationLutDebug:12;\n+\t\t\tunsigned int mssEgressMacControlFilterDebugLsb:4;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressMacControlFilterDebugMsb:7;\n+\t\t\tunsigned int mssEgressSectagProcessingLutDebug:8;\n+\t\t\tunsigned int reserved0:1;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLookupDebugLSW:16;\n+\t\t} bits_2;\n+\t\tunsigned int word_2;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLookupDebugMSW:16;\n+\t\t} bits_3;\n+\t\tunsigned int word_3;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressDatapathDebug:6;\n+\t\t\tunsigned int reserved0:10;\n+\t\t} bits_4;\n+\t\tunsigned int word_4;\n+\t};\n+};\n+\n+struct mssEgressLutAddressControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutAddress:9;\n+\t\t\tunsigned int reserved0:3;\n+\t\t\tunsigned int mssEgressLutSelect:4;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssEgressLutControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:14;\n+\t\t\tunsigned int mssEgressLutRead:1;\n+\t\t\tunsigned int mssEgressLutWrite:1;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssEgressLutDataControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_0:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_1:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_2:16;\n+\t\t} bits_2;\n+\t\tunsigned int word_2;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_3:16;\n+\t\t} bits_3;\n+\t\tunsigned int word_3;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_4:16;\n+\t\t} bits_4;\n+\t\tunsigned int word_4;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_5:16;\n+\t\t} bits_5;\n+\t\tunsigned int word_5;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_6:16;\n+\t\t} bits_6;\n+\t\tunsigned int word_6;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_7:16;\n+\t\t} bits_7;\n+\t\tunsigned int word_7;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_8:16;\n+\t\t} bits_8;\n+\t\tunsigned int word_8;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_9:16;\n+\t\t} bits_9;\n+\t\tunsigned int word_9;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_10:16;\n+\t\t} bits_10;\n+\t\tunsigned short word_10;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_11:16;\n+\t\t} bits_11;\n+\t\tunsigned short word_11;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_12:16;\n+\t\t} bits_12;\n+\t\tunsigned short word_12;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_13:16;\n+\t\t} bits_13;\n+\t\tunsigned short word_13;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_14:16;\n+\t\t} bits_14;\n+\t\tunsigned short word_14;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_15:16;\n+\t\t} bits_15;\n+\t\tunsigned short word_15;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_16:16;\n+\t\t} bits_16;\n+\t\tunsigned short word_16;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_17:16;\n+\t\t} bits_17;\n+\t\tunsigned short word_17;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_18:16;\n+\t\t} bits_18;\n+\t\tunsigned short word_18;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_19:16;\n+\t\t} bits_19;\n+\t\tunsigned short word_19;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_20:16;\n+\t\t} bits_20;\n+\t\tunsigned int word_20;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_21:16;\n+\t\t} bits_21;\n+\t\tunsigned int word_21;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_22:16;\n+\t\t} bits_22;\n+\t\tunsigned int word_22;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_23:16;\n+\t\t} bits_23;\n+\t\tunsigned int word_23;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_24:16;\n+\t\t} bits_24;\n+\t\tunsigned int word_24;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_25:16;\n+\t\t} bits_25;\n+\t\tunsigned int word_25;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_26:16;\n+\t\t} bits_26;\n+\t\tunsigned int word_26;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssEgressLutData_27:16;\n+\t\t} bits_27;\n+\t\tunsigned int word_27;\n+\t};\n+};\n+\n+#endif /* MSS_EGRESS_REGS_HEADER */\ndiff --git a/drivers/net/atlantic/macsec/MSS_Ingress_registers.h b/drivers/net/atlantic/macsec/MSS_Ingress_registers.h\nnew file mode 100644\nindex 0000000..ec5adb3\n--- /dev/null\n+++ b/drivers/net/atlantic/macsec/MSS_Ingress_registers.h\n@@ -0,0 +1,1135 @@\n+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */\n+/* Copyright (C) 2014-2019 aQuantia Corporation. */\n+\n+#ifndef MSS_INGRESS_REGS_HEADER\n+#define MSS_INGRESS_REGS_HEADER\n+\n+#define mssIngressVersionStatusRegister_ADDR 0x00008000\n+#define mssIngressPrescaleControlRegister_ADDR 0x00008004\n+#define mssIngressVlanTpid_0Register_ADDR 0x00008006\n+#define mssIngressVlanTpid_1Register_ADDR 0x00008008\n+#define mssIngressVlanControlRegister_ADDR 0x0000800A\n+#define mssIngressMtuSizeControlRegister_ADDR 0x0000800C\n+#define mssIngressControlRegister_ADDR 0x0000800E\n+#define mssIngressSaControlRegister_ADDR 0x00008010\n+#define mssIngressDebugStatusRegister_ADDR 0x00008012\n+#define mssIngressBusyStatusRegister_ADDR 0x00008022\n+#define mssIngressSpareControlRegister_ADDR 0x00008024\n+#define mssIngressSciDefaultControlRegister_ADDR 0x0000802A\n+#define mssIngressInterruptStatusRegister_ADDR 0x0000802E\n+#define mssIngressInterruptMaskRegister_ADDR 0x00008030\n+#define mssIngressSaIcvErrorStatusRegister_ADDR 0x00008032\n+#define mssIngressSaReplayErrorStatusRegister_ADDR 0x00008034\n+#define mssIngressSaExpiredStatusRegister_ADDR 0x00008036\n+#define mssIngressSaThresholdExpiredStatusRegister_ADDR 0x00008038\n+#define mssIngressEccInterruptStatusRegister_ADDR 0x0000803A\n+#define mssIngressIgprcLutEccError_1AddressStatusRegister_ADDR 0x0000803C\n+#define mssIngressIgprcLutEccError_2AddressStatusRegister_ADDR 0x0000803E\n+#define mssIngressIgctlfLutEccErrorAddressStatusRegister_ADDR 0x00008040\n+#define mssIngressIgpfmtLutEccErrorAddressStatusRegister_ADDR 0x00008042\n+#define mssIngressIgpopLutEccErrorAddressStatusRegister_ADDR 0x00008044\n+#define mssIngressIgpoctlfLutEccErrorAddressStatusRegister_ADDR 0x00008046\n+#define mssIngressIgpocLutEccError_1AddressStatusRegister_ADDR 0x00008048\n+#define mssIngressIgpocLutEccError_2AddressStatusRegister_ADDR 0x0000804A\n+#define mssIngressIgmibEccErrorAddressStatusRegister_ADDR 0x0000804C\n+#define mssIngressEccControlRegister_ADDR 0x0000804E\n+#define mssIngressDebugControlRegister_ADDR 0x00008050\n+#define mssIngressAdditionalDebugStatusRegister_ADDR 0x00008052\n+#define mssIngressLutAddressControlRegister_ADDR 0x00008080\n+#define mssIngressLutControlRegister_ADDR 0x00008081\n+#define mssIngressLutDataControlRegister_ADDR 0x000080A0\n+\n+struct mssIngressVersionStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressID:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressVersion:8;\n+\t\t\tunsigned int mssIngressRevision:8;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressPrescaleControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressPrescaleConfigurationLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressPrescaleConfigurationMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressVlanTpid_0Register_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressVlanStag:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressVlanTpid_1Register_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressVlanQtag:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressVlanControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressVlanUpMapTableLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressVlanUpMapTableMSW:8;\n+\t\t\tunsigned int mssIngressVlanUpDefault:3;\n+\t\t\tunsigned int mssIngressVlanStagUpParseEnable:1;\n+\t\t\tunsigned int mssIngressVlanQtagUpParseEnable:1;\n+\t\t\tunsigned int mssIngressVlanQinqParseEnable:1;\n+\t\t\tunsigned int mssIngressVlanStagParseEnable:1;\n+\t\t\tunsigned int mssIngressVlanQtagParseEnable:1;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressMtuSizeControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressControlledPacketMtuSize:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressUncontrolledPacketMtuSize:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSoftReset:1;\n+\t\t\tunsigned int mssIngressOperationPointToPoint:1;\n+\t\t\tunsigned int mssIngressCreateSci:1;\n+\t\t\tunsigned int mssIngressMaskShortLengthError:1;\n+\t\t\tunsigned int mssIngressDropKayPacket:1;\n+\t\t\tunsigned int mssIngressDropIgprcMiss:1;\n+\t\t\tunsigned int mssIngressCheckIcv:1;\n+\t\t\tunsigned int mssIngressClearGlobalTime:1;\n+\t\t\tunsigned int mssIngressClearCount:1;\n+\t\t\tunsigned int mssIngressHighPriority:1;\n+\t\t\tunsigned int mssIngressRemoveSectag:1;\n+\t\t\tunsigned int mssIngressGlobalValidateFrames:2;\n+\t\t\tunsigned int mssIngressIcvLsb_8BytesEnable:1;\n+\t\t\tunsigned int reserved0:2;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressSaControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaThresholdLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaThresholdMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressDebugStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpfmtStateMachine:4;\n+\t\t\tunsigned int mssIngressIgpfmtBufferDepth:4;\n+\t\t\tunsigned int mssIngressIgpfmtPadInsertionStateMachine:4;\n+\t\t\tunsigned int mssIngressIgpfmtPadInsertionBufferDepth:2;\n+\t\t\tunsigned int reserved0:2;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpopStateMachine:4;\n+\t\t\tunsigned int mssIngressIgpopBufferDepth:5;\n+\t\t\tunsigned int mssIngressIgpfmtSectagRemovalStateMachine:2;\n+\t\t\tunsigned int mssIngressIgpfmtSectagRemovalBufferDepth:3;\n+\t\t\tunsigned int mssIngressIgpfmtLastBytesRemovalStateMachine:2;\n+\t\t} bits_2;\n+\t\tunsigned int word_2;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpfmtLastBytesRemovalBufferDepth:2;\n+\t\t\tunsigned int reserved0:14;\n+\t\t} bits_3;\n+\t\tunsigned int word_3;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGcmCounterLSW:16;\n+\t\t} bits_4;\n+\t\tunsigned int word_4;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGcmCounterMSW:16;\n+\t\t} bits_5;\n+\t\tunsigned int word_5;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGmcMultBufferDepth:2;\n+\t\t\tunsigned int reserved0:14;\n+\t\t} bits_6;\n+\t\tunsigned int word_6;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_7;\n+\t\tunsigned int word_7;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGcmMultLengthA_0:16;\n+\t\t} bits_8;\n+\t\tunsigned int word_8;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGcmMultLengthA_1:16;\n+\t\t} bits_9;\n+\t\tunsigned int word_9;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGcmMultLengthA_2:16;\n+\t\t} bits_10;\n+\t\tunsigned short word_10;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGcmMultLengthA_3:16;\n+\t\t} bits_11;\n+\t\tunsigned short word_11;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGcmMultLengthC_0:16;\n+\t\t} bits_12;\n+\t\tunsigned short word_12;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGcmMultLengthC_1:16;\n+\t\t} bits_13;\n+\t\tunsigned short word_13;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGcmMultLengthC_2:16;\n+\t\t} bits_14;\n+\t\tunsigned short word_14;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressGcmMultLengthC_3:16;\n+\t\t} bits_15;\n+\t\tunsigned short word_15;\n+\t};\n+};\n+\n+struct mssIngressBusyStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressDataPathBusy:1;\n+\t\t\tunsigned int mssIngressIgpfmtBusy:1;\n+\t\t\tunsigned int mssIngressAesCounterBusy:1;\n+\t\t\tunsigned int mssIngressIgpopBusy:1;\n+\t\t\tunsigned int mssIngressGcmBufferBusy:1;\n+\t\t\tunsigned int mssIngressIgprcBusy:1;\n+\t\t\tunsigned int mssIngressIgpocBusy:1;\n+\t\t\tunsigned int reserved0:9;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssIngressSpareControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSpareControl_1LSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSpareControl_1MSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSpareControl_2LSW:16;\n+\t\t} bits_2;\n+\t\tunsigned int word_2;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSpareControl_2MSW:16;\n+\t\t} bits_3;\n+\t\tunsigned int word_3;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSpareControl_3LSW:16;\n+\t\t} bits_4;\n+\t\tunsigned int word_4;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSpareControl_3MSW:16;\n+\t\t} bits_5;\n+\t\tunsigned int word_5;\n+\t};\n+};\n+\n+struct mssIngressSciDefaultControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSciDefault_0:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSciDefault_1:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSciDefault_2:16;\n+\t\t} bits_2;\n+\t\tunsigned int word_2;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSciDefault_3:16;\n+\t\t} bits_3;\n+\t\tunsigned int word_3;\n+\t};\n+};\n+\n+struct mssIngressInterruptStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssMasterIngressInterrupt:1;\n+\t\t\tunsigned int mssIngressSaExpiredInterrupt:1;\n+\t\t\tunsigned int mssIngressSaThresholdExpiredInterrupt:1;\n+\t\t\tunsigned int mssIngressIcvErrorInterrupt:1;\n+\t\t\tunsigned int mssIngressReplayErrorInterrupt:1;\n+\t\t\tunsigned int mssIngressMibSaturationInterrupt:1;\n+\t\t\tunsigned int mssIngressEccErrorInterrupt:1;\n+\t\t\tunsigned int mssIngressTciE_cErrorInterrupt:1;\n+\t\t\tunsigned int mssIngressIgpocMissInterrupt:1;\n+\t\t\tunsigned int reserved0:7;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressInterruptMaskRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressMasterInterruptEnable:1;\n+\t\t\tunsigned int mssIngressSaExpiredInterruptEnable:1;\n+\t\t\tunsigned int mssIngressSaThresholdExpiredInterruptEnable:1;\n+\t\t\tunsigned int mssIngressIcvErrorInterruptEnable:1;\n+\t\t\tunsigned int mssIngressReplayErrorInterruptEnable:1;\n+\t\t\tunsigned int mssIngressMibSaturationInterruptEnable:1;\n+\t\t\tunsigned int mssIngressEccErrorInterruptEnable:1;\n+\t\t\tunsigned int mssIngressTciE_cErrorInterruptEnable:1;\n+\t\t\tunsigned int mssIngressIgpocMissInterruptEnable:1;\n+\t\t\tunsigned int reserved0:7;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressSaIcvErrorStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaIcvErrorLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaIcvErrorMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressSaReplayErrorStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaReplayErrorLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaReplayErrorMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressSaExpiredStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaExpiredLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaExpiredMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressSaThresholdExpiredStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaThresholdExpiredLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaThresholdExpiredMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressEccInterruptStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaEccErrorInterruptLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressSaEccErrorInterruptMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressIgprcLutEccError_1AddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgprcLutEccError_1AddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgprcLutEccError_1AddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressIgprcLutEccError_2AddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgprcLutEccError_2AddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgprcLutEccError_2AddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressIgctlfLutEccErrorAddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgctlfLutEccErrorAddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgctlfLutEccErrorAddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressIgpfmtLutEccErrorAddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpfmtLutEccErrorAddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpfmtLutEccErrorAddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressIgpopLutEccErrorAddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpopLutEccErrorAddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpopLutEccErrorAddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressIgpoctlfLutEccErrorAddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpoctlfLutEccErrorAddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpoctlfLutEccErrorAddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressIgpocLutEccError_1AddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpocLutEccError_1AddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpocLutEccError_1AddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressIgpocLutEccError_2AddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpocLutEccError_2AddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpocLutEccError_2AddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressIgmibEccErrorAddressStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgmibEccErrorAddressLSW:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgmibEccErrorAddressMSW:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+};\n+\n+struct mssIngressEccControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressEccEnable:1;\n+\t\t\tunsigned int reserved0:15;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssIngressDebugControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressDebugBusSelect:2;\n+\t\t\tunsigned int reserved0:14;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssIngressAdditionalDebugStatusRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpoctlfLutDebug:11;\n+\t\t\tunsigned int mssIngressIgpocDebugLsb:5;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpocDebugMsb:15;\n+\t\t\tunsigned int reserved0:1;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpocLutDebug:14;\n+\t\t\tunsigned int mssIngressIgpopDebugLsb:2;\n+\t\t} bits_2;\n+\t\tunsigned int word_2;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgpopDebugMsb:6;\n+\t\t\tunsigned int mssIngressDataPathDebug:10;\n+\t\t} bits_3;\n+\t\tunsigned int word_3;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgprctlfLutDebug:11;\n+\t\t\tunsigned int mssIngressIgprcLutDebugLsb:5;\n+\t\t} bits_4;\n+\t\tunsigned int word_4;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressIgprcLutDebugMsb:8;\n+\t\t\tunsigned int reserved0:8;\n+\t\t} bits_5;\n+\t\tunsigned int word_5;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLookupDebug:12;\n+\t\t\tunsigned int mssIngressProcessingDebugLsb:4;\n+\t\t} bits_6;\n+\t\tunsigned int word_6;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressProcessingDebugMsb:7;\n+\t\t\tunsigned int reserved0:9;\n+\t\t} bits_7;\n+\t\tunsigned int word_7;\n+\t};\n+};\n+\n+struct mssIngressLutAddressControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutAddress:9;\n+\t\t\tunsigned int reserved0:3;\n+\t\t\tunsigned int mssIngressLutSelect:4;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssIngressLutControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int reserved0:14;\n+\t\t\tunsigned int mssIngressLutRead:1;\n+\t\t\tunsigned int mssIngressLutWrite:1;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+};\n+\n+struct mssIngressLutDataControlRegister_t\n+{\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_0:16;\n+\t\t} bits_0;\n+\t\tunsigned short word_0;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_1:16;\n+\t\t} bits_1;\n+\t\tunsigned short word_1;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_2:16;\n+\t\t} bits_2;\n+\t\tunsigned int word_2;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_3:16;\n+\t\t} bits_3;\n+\t\tunsigned int word_3;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_4:16;\n+\t\t} bits_4;\n+\t\tunsigned int word_4;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_5:16;\n+\t\t} bits_5;\n+\t\tunsigned int word_5;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_6:16;\n+\t\t} bits_6;\n+\t\tunsigned int word_6;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_7:16;\n+\t\t} bits_7;\n+\t\tunsigned int word_7;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_8:16;\n+\t\t} bits_8;\n+\t\tunsigned int word_8;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_9:16;\n+\t\t} bits_9;\n+\t\tunsigned int word_9;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_10:16;\n+\t\t} bits_10;\n+\t\tunsigned short word_10;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_11:16;\n+\t\t} bits_11;\n+\t\tunsigned short word_11;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_12:16;\n+\t\t} bits_12;\n+\t\tunsigned short word_12;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_13:16;\n+\t\t} bits_13;\n+\t\tunsigned short word_13;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_14:16;\n+\t\t} bits_14;\n+\t\tunsigned short word_14;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_15:16;\n+\t\t} bits_15;\n+\t\tunsigned short word_15;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_16:16;\n+\t\t} bits_16;\n+\t\tunsigned short word_16;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_17:16;\n+\t\t} bits_17;\n+\t\tunsigned short word_17;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_18:16;\n+\t\t} bits_18;\n+\t\tunsigned short word_18;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_19:16;\n+\t\t} bits_19;\n+\t\tunsigned short word_19;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_20:16;\n+\t\t} bits_20;\n+\t\tunsigned int word_20;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_21:16;\n+\t\t} bits_21;\n+\t\tunsigned int word_21;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_22:16;\n+\t\t} bits_22;\n+\t\tunsigned int word_22;\n+\t};\n+\tunion\n+\t{\n+\t\tstruct\n+\t\t{\n+\t\t\tunsigned int mssIngressLutData_23:16;\n+\t\t} bits_23;\n+\t\tunsigned int word_23;\n+\t};\n+};\n+\n+#endif /* MSS_INGRESS_REGS_HEADER */\ndiff --git a/drivers/net/atlantic/macsec/macsec_api.c b/drivers/net/atlantic/macsec/macsec_api.c\nnew file mode 100644\nindex 0000000..2003821\n--- /dev/null\n+++ b/drivers/net/atlantic/macsec/macsec_api.c\n@@ -0,0 +1,1612 @@\n+// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n+/* Copyright (C) 2014-2019 aQuantia Corporation. */\n+\n+#include \"macsec_api.h\"\n+#include \"MSS_Ingress_registers.h\"\n+#include \"MSS_Egress_registers.h\"\n+#include \"mdio.h\"\n+\n+#include \"errno.h\"\n+\n+static\n+int SetRawSECIngressRecordVal(struct aq_hw_s *hw, uint16_t* packedRecVal, uint8_t numWords, uint8_t tableID, uint16_t tableIndex)\n+{\n+    struct mssIngressLutAddressControlRegister_t tableSelReg;\n+    struct mssIngressLutControlRegister_t readWriteReg;\n+\n+    unsigned int i;\n+\n+    for (i = 0; i < numWords; i += 2)\n+    {\n+        mdioWrite(hw, MMD_GLOBAL, mssIngressLutDataControlRegister_ADDR + i, packedRecVal[i]);\n+        mdioWrite(hw, MMD_GLOBAL, mssIngressLutDataControlRegister_ADDR + i + 1, packedRecVal[i + 1]);\n+    }\n+\n+    for (i = numWords; i < 24; i += 2)\n+    {\n+        mdioWrite(hw, MMD_GLOBAL, mssIngressLutDataControlRegister_ADDR + i, 0);\n+        mdioWrite(hw, MMD_GLOBAL, mssIngressLutDataControlRegister_ADDR + i + 1, 0);\n+    }\n+\n+    tableSelReg.bits_0.mssIngressLutSelect = tableID;\n+    tableSelReg.bits_0.mssIngressLutAddress = tableIndex;\n+\n+    readWriteReg.bits_0.mssIngressLutRead = 0;\n+    readWriteReg.bits_0.mssIngressLutWrite = 1;\n+\n+    mdioWrite(hw, MMD_GLOBAL, mssIngressLutAddressControlRegister_ADDR, tableSelReg.word_0);\n+    mdioWrite(hw, MMD_GLOBAL, mssIngressLutControlRegister_ADDR, readWriteReg.word_0);\n+\n+    return 0;\n+}\n+\n+static\n+int GetRawSECIngressRecordVal(struct aq_hw_s *hw, uint16_t* packedRecVal, uint8_t numWords, uint8_t tableID, uint16_t tableIndex)\n+{\n+    struct mssIngressLutAddressControlRegister_t tableSelReg;\n+    struct mssIngressLutControlRegister_t readWriteReg;\n+\n+    unsigned int i;\n+\n+    tableSelReg.bits_0.mssIngressLutSelect = tableID;\n+    tableSelReg.bits_0.mssIngressLutAddress = tableIndex;\n+\n+    readWriteReg.bits_0.mssIngressLutRead = 1;\n+    readWriteReg.bits_0.mssIngressLutWrite = 0;\n+\n+    mdioWrite(hw, MMD_GLOBAL, mssIngressLutAddressControlRegister_ADDR, tableSelReg.word_0);\n+    mdioWrite(hw, MMD_GLOBAL, mssIngressLutControlRegister_ADDR, readWriteReg.word_0);\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * numWords);\n+\n+    for (i = 0; i < numWords; i += 2)\n+    {\n+        mdioRead(hw, MMD_GLOBAL, mssIngressLutDataControlRegister_ADDR + i, &packedRecVal[i]);\n+        mdioRead(hw, MMD_GLOBAL, mssIngressLutDataControlRegister_ADDR + i + 1, &packedRecVal[i + 1]);\n+    }\n+\n+    return 0;\n+}\n+\n+static\n+int SetRawSECEgressRecordVal(struct aq_hw_s *hw, uint16_t* packedRecVal, uint8_t numWords, uint8_t tableID, uint16_t tableIndex)\n+{\n+    struct mssEgressLutAddressControlRegister_t tableSelReg;\n+    struct mssEgressLutControlRegister_t readWriteReg;\n+\n+    unsigned int i;\n+\n+    for (i = 0; i < numWords; i += 2)\n+    {\n+        mdioWrite(hw, MMD_GLOBAL, mssEgressLutDataControlRegister_ADDR + i, packedRecVal[i]);\n+        mdioWrite(hw, MMD_GLOBAL, mssEgressLutDataControlRegister_ADDR + i + 1, packedRecVal[i + 1]);\n+    }\n+\n+    for (i = numWords; i < 28; i += 2)\n+    {\n+        mdioWrite(hw, MMD_GLOBAL, mssEgressLutDataControlRegister_ADDR + i, 0);\n+        mdioWrite(hw, MMD_GLOBAL, mssEgressLutDataControlRegister_ADDR + i + 1, 0);\n+    }\n+\n+    tableSelReg.bits_0.mssEgressLutSelect = tableID;\n+    tableSelReg.bits_0.mssEgressLutAddress = tableIndex;\n+\n+    readWriteReg.bits_0.mssEgressLutRead = 0;\n+    readWriteReg.bits_0.mssEgressLutWrite = 1;\n+\n+    mdioWrite(hw, MMD_GLOBAL, mssEgressLutAddressControlRegister_ADDR, tableSelReg.word_0);\n+    mdioWrite(hw, MMD_GLOBAL, mssEgressLutControlRegister_ADDR, readWriteReg.word_0);\n+\n+    return 0;\n+}\n+\n+static\n+int GetRawSECEgressRecordVal(struct aq_hw_s *hw, uint16_t* packedRecVal, uint8_t numWords, uint8_t tableID, uint16_t tableIndex)\n+{\n+    struct mssEgressLutAddressControlRegister_t tableSelReg;\n+    struct mssEgressLutControlRegister_t readWriteReg;\n+\n+    unsigned int i;\n+\n+    tableSelReg.bits_0.mssEgressLutSelect = tableID;\n+    tableSelReg.bits_0.mssEgressLutAddress = tableIndex;\n+\n+    readWriteReg.bits_0.mssEgressLutRead = 1;\n+    readWriteReg.bits_0.mssEgressLutWrite = 0;\n+\n+    mdioWrite(hw, MMD_GLOBAL, mssEgressLutAddressControlRegister_ADDR, tableSelReg.word_0);\n+    mdioWrite(hw, MMD_GLOBAL, mssEgressLutControlRegister_ADDR, readWriteReg.word_0);\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * numWords);\n+\n+    for (i = 0; i < numWords; i += 2)\n+    {\n+        mdioRead(hw, MMD_GLOBAL, mssEgressLutDataControlRegister_ADDR + i, &packedRecVal[i]);\n+        mdioRead(hw, MMD_GLOBAL, mssEgressLutDataControlRegister_ADDR + i + 1, &packedRecVal[i + 1]);\n+    }\n+\n+    return 0;\n+}\n+\n+int AQ_API_SetIngressPreCTLFRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressPreCTLFRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[6];\n+\n+    if (tableIndex >= NUMROWS_INGRESSPRECTLFRECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 6);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x0000) | (((rec->sa_da[0] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[1] = (packedRecVal[1] & 0x0000) | (((rec->sa_da[0] >> 16) & 0xFFFF) << 0);\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->sa_da[1] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[3] = (packedRecVal[3] & 0x0000) | (((rec->eth_type >> 0) & 0xFFFF) << 0);\n+    packedRecVal[4] = (packedRecVal[4] & 0x0000) | (((rec->match_mask >> 0) & 0xFFFF) << 0);\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFF0) | (((rec->match_type >> 0) & 0xF) << 0);\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFEF) | (((rec->action >> 0) & 0x1) << 4);\n+\n+    SetRawSECIngressRecordVal(hw, packedRecVal, 6, 0, ROWOFFSET_INGRESSPRECTLFRECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetIngressPreCTLFRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressPreCTLFRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[6];\n+\n+    if (tableIndex >= NUMROWS_INGRESSPRECTLFRECORD)\n+        return -EINVAL;\n+\n+    if ((tableIndex % 2) > 0)\n+    {\n+        GetRawSECIngressRecordVal(hw, packedRecVal, 6, 0, ROWOFFSET_INGRESSPRECTLFRECORD + tableIndex - 1);\n+    }\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_IngressPreCTLFRecord));\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 6, 0, ROWOFFSET_INGRESSPRECTLFRECORD + tableIndex);\n+\n+    rec->sa_da[0] = (rec->sa_da[0] & 0xFFFF0000) | (((packedRecVal[0] >> 0) & 0xFFFF) << 0);\n+    rec->sa_da[0] = (rec->sa_da[0] & 0x0000FFFF) | (((packedRecVal[1] >> 0) & 0xFFFF) << 16);\n+\n+    rec->sa_da[1] = (rec->sa_da[1] & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+\n+    rec->eth_type = (rec->eth_type & 0xFFFF0000) | (((packedRecVal[3] >> 0) & 0xFFFF) << 0);\n+\n+    rec->match_mask = (rec->match_mask & 0xFFFF0000) | (((packedRecVal[4] >> 0) & 0xFFFF) << 0);\n+\n+    rec->match_type = (rec->match_type & 0xFFFFFFF0) | (((packedRecVal[5] >> 0) & 0xF) << 0);\n+\n+    rec->action = (rec->action & 0xFFFFFFFE) | (((packedRecVal[5] >> 4) & 0x1) << 0);\n+\n+    return 0;\n+}\n+\n+int AQ_API_SetIngressPreClassRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressPreClassRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[20];\n+\n+    if (tableIndex >= NUMROWS_INGRESSPRECLASSRECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 20);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x0000) | (((rec->sci[0] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[1] = (packedRecVal[1] & 0x0000) | (((rec->sci[0] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->sci[1] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[3] = (packedRecVal[3] & 0x0000) | (((rec->sci[1] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0xFF00) | (((rec->tci >> 0) & 0xFF) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0x00FF) | (((rec->encr_offset >> 0) & 0xFF) << 8);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0x0000) | (((rec->eth_type >> 0) & 0xFFFF) << 0);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0x0000) | (((rec->snap[0] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[7] = (packedRecVal[7] & 0x0000) | (((rec->snap[0] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[8] = (packedRecVal[8] & 0xFF00) | (((rec->snap[1] >> 0) & 0xFF) << 0);\n+\n+    packedRecVal[8] = (packedRecVal[8] & 0x00FF) | (((rec->llc >> 0) & 0xFF) << 8);\n+    packedRecVal[9] = (packedRecVal[9] & 0x0000) | (((rec->llc >> 8) & 0xFFFF) << 0);\n+\n+    packedRecVal[10] = (packedRecVal[10] & 0x0000) | (((rec->mac_sa[0] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[11] = (packedRecVal[11] & 0x0000) | (((rec->mac_sa[0] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[12] = (packedRecVal[12] & 0x0000) | (((rec->mac_sa[1] >> 0) & 0xFFFF) << 0);\n+\n+    packedRecVal[13] = (packedRecVal[13] & 0x0000) | (((rec->mac_da[0] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[14] = (packedRecVal[14] & 0x0000) | (((rec->mac_da[0] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[15] = (packedRecVal[15] & 0x0000) | (((rec->mac_da[1] >> 0) & 0xFFFF) << 0);\n+\n+    packedRecVal[16] = (packedRecVal[16] & 0xFFFE) | (((rec->lpbk_packet >> 0) & 0x1) << 0);\n+\n+    packedRecVal[16] = (packedRecVal[16] & 0xFFF9) | (((rec->an_mask >> 0) & 0x3) << 1);\n+\n+    packedRecVal[16] = (packedRecVal[16] & 0xFE07) | (((rec->tci_mask >> 0) & 0x3F) << 3);\n+\n+    packedRecVal[16] = (packedRecVal[16] & 0x01FF) | (((rec->sci_mask >> 0) & 0x7F) << 9);\n+    packedRecVal[17] = (packedRecVal[17] & 0xFFFE) | (((rec->sci_mask >> 7) & 0x1) << 0);\n+\n+    packedRecVal[17] = (packedRecVal[17] & 0xFFF9) | (((rec->eth_type_mask >> 0) & 0x3) << 1);\n+\n+    packedRecVal[17] = (packedRecVal[17] & 0xFF07) | (((rec->snap_mask >> 0) & 0x1F) << 3);\n+\n+    packedRecVal[17] = (packedRecVal[17] & 0xF8FF) | (((rec->llc_mask >> 0) & 0x7) << 8);\n+\n+    packedRecVal[17] = (packedRecVal[17] & 0xF7FF) | (((rec->_802_2_encapsulate >> 0) & 0x1) << 11);\n+\n+    packedRecVal[17] = (packedRecVal[17] & 0x0FFF) | (((rec->sa_mask >> 0) & 0xF) << 12);\n+    packedRecVal[18] = (packedRecVal[18] & 0xFFFC) | (((rec->sa_mask >> 4) & 0x3) << 0);\n+\n+    packedRecVal[18] = (packedRecVal[18] & 0xFF03) | (((rec->da_mask >> 0) & 0x3F) << 2);\n+\n+    packedRecVal[18] = (packedRecVal[18] & 0xFEFF) | (((rec->lpbk_mask >> 0) & 0x1) << 8);\n+\n+    packedRecVal[18] = (packedRecVal[18] & 0xC1FF) | (((rec->sc_idx >> 0) & 0x1F) << 9);\n+\n+    packedRecVal[18] = (packedRecVal[18] & 0xBFFF) | (((rec->proc_dest >> 0) & 0x1) << 14);\n+\n+    packedRecVal[18] = (packedRecVal[18] & 0x7FFF) | (((rec->action >> 0) & 0x1) << 15);\n+    packedRecVal[19] = (packedRecVal[19] & 0xFFFE) | (((rec->action >> 1) & 0x1) << 0);\n+\n+    packedRecVal[19] = (packedRecVal[19] & 0xFFFD) | (((rec->ctrl_unctrl >> 0) & 0x1) << 1);\n+\n+    packedRecVal[19] = (packedRecVal[19] & 0xFFFB) | (((rec->sci_from_table >> 0) & 0x1) << 2);\n+\n+    packedRecVal[19] = (packedRecVal[19] & 0xFF87) | (((rec->reserved >> 0) & 0xF) << 3);\n+\n+    packedRecVal[19] = (packedRecVal[19] & 0xFF7F) | (((rec->valid >> 0) & 0x1) << 7);\n+\n+    SetRawSECIngressRecordVal(hw, packedRecVal, 20, 1, ROWOFFSET_INGRESSPRECLASSRECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetIngressPreClassRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressPreClassRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[20];\n+\n+    if (tableIndex >= NUMROWS_INGRESSPRECLASSRECORD)\n+        return -EINVAL;\n+\n+    if ((tableIndex % 2) > 0)\n+    {\n+        GetRawSECIngressRecordVal(hw, packedRecVal, 20, 1, \n+            ROWOFFSET_INGRESSPRECLASSRECORD + tableIndex - 1);\n+    }\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_IngressPreClassRecord));\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 20, 1, ROWOFFSET_INGRESSPRECLASSRECORD + tableIndex);\n+\n+    rec->sci[0] = (rec->sci[0] & 0xFFFF0000) | (((packedRecVal[0] >> 0) & 0xFFFF) << 0);\n+    rec->sci[0] = (rec->sci[0] & 0x0000FFFF) | (((packedRecVal[1] >> 0) & 0xFFFF) << 16);\n+\n+    rec->sci[1] = (rec->sci[1] & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+    rec->sci[1] = (rec->sci[1] & 0x0000FFFF) | (((packedRecVal[3] >> 0) & 0xFFFF) << 16);\n+\n+    rec->tci = (rec->tci & 0xFFFFFF00) | (((packedRecVal[4] >> 0) & 0xFF) << 0);\n+\n+    rec->encr_offset = (rec->encr_offset & 0xFFFFFF00) | (((packedRecVal[4] >> 8) & 0xFF) << 0);\n+\n+    rec->eth_type = (rec->eth_type & 0xFFFF0000) | (((packedRecVal[5] >> 0) & 0xFFFF) << 0);\n+\n+    rec->snap[0] = (rec->snap[0] & 0xFFFF0000) | (((packedRecVal[6] >> 0) & 0xFFFF) << 0);\n+    rec->snap[0] = (rec->snap[0] & 0x0000FFFF) | (((packedRecVal[7] >> 0) & 0xFFFF) << 16);\n+\n+    rec->snap[1] = (rec->snap[1] & 0xFFFFFF00) | (((packedRecVal[8] >> 0) & 0xFF) << 0);\n+\n+    rec->llc = (rec->llc & 0xFFFFFF00) | (((packedRecVal[8] >> 8) & 0xFF) << 0);\n+    rec->llc = (rec->llc & 0xFF0000FF) | (((packedRecVal[9] >> 0) & 0xFFFF) << 8);\n+\n+    rec->mac_sa[0] = (rec->mac_sa[0] & 0xFFFF0000) | (((packedRecVal[10] >> 0) & 0xFFFF) << 0);\n+    rec->mac_sa[0] = (rec->mac_sa[0] & 0x0000FFFF) | (((packedRecVal[11] >> 0) & 0xFFFF) << 16);\n+\n+    rec->mac_sa[1] = (rec->mac_sa[1] & 0xFFFF0000) | (((packedRecVal[12] >> 0) & 0xFFFF) << 0);\n+\n+    rec->mac_da[0] = (rec->mac_da[0] & 0xFFFF0000) | (((packedRecVal[13] >> 0) & 0xFFFF) << 0);\n+    rec->mac_da[0] = (rec->mac_da[0] & 0x0000FFFF) | (((packedRecVal[14] >> 0) & 0xFFFF) << 16);\n+\n+    rec->mac_da[1] = (rec->mac_da[1] & 0xFFFF0000) | (((packedRecVal[15] >> 0) & 0xFFFF) << 0);\n+\n+    rec->lpbk_packet = (rec->lpbk_packet & 0xFFFFFFFE) | (((packedRecVal[16] >> 0) & 0x1) << 0);\n+\n+    rec->an_mask = (rec->an_mask & 0xFFFFFFFC) | (((packedRecVal[16] >> 1) & 0x3) << 0);\n+\n+    rec->tci_mask = (rec->tci_mask & 0xFFFFFFC0) | (((packedRecVal[16] >> 3) & 0x3F) << 0);\n+\n+    rec->sci_mask = (rec->sci_mask & 0xFFFFFF80) | (((packedRecVal[16] >> 9) & 0x7F) << 0);\n+    rec->sci_mask = (rec->sci_mask & 0xFFFFFF7F) | (((packedRecVal[17] >> 0) & 0x1) << 7);\n+\n+    rec->eth_type_mask = (rec->eth_type_mask & 0xFFFFFFFC) | (((packedRecVal[17] >> 1) & 0x3) << 0);\n+\n+    rec->snap_mask = (rec->snap_mask & 0xFFFFFFE0) | (((packedRecVal[17] >> 3) & 0x1F) << 0);\n+\n+    rec->llc_mask = (rec->llc_mask & 0xFFFFFFF8) | (((packedRecVal[17] >> 8) & 0x7) << 0);\n+\n+    rec->_802_2_encapsulate = (rec->_802_2_encapsulate & 0xFFFFFFFE) | (((packedRecVal[17] >> 11) & 0x1) << 0);\n+\n+    rec->sa_mask = (rec->sa_mask & 0xFFFFFFF0) | (((packedRecVal[17] >> 12) & 0xF) << 0);\n+    rec->sa_mask = (rec->sa_mask & 0xFFFFFFCF) | (((packedRecVal[18] >> 0) & 0x3) << 4);\n+\n+    rec->da_mask = (rec->da_mask & 0xFFFFFFC0) | (((packedRecVal[18] >> 2) & 0x3F) << 0);\n+\n+    rec->lpbk_mask = (rec->lpbk_mask & 0xFFFFFFFE) | (((packedRecVal[18] >> 8) & 0x1) << 0);\n+\n+    rec->sc_idx = (rec->sc_idx & 0xFFFFFFE0) | (((packedRecVal[18] >> 9) & 0x1F) << 0);\n+\n+    rec->proc_dest = (rec->proc_dest & 0xFFFFFFFE) | (((packedRecVal[18] >> 14) & 0x1) << 0);\n+\n+    rec->action = (rec->action & 0xFFFFFFFE) | (((packedRecVal[18] >> 15) & 0x1) << 0);\n+    rec->action = (rec->action & 0xFFFFFFFD) | (((packedRecVal[19] >> 0) & 0x1) << 1);\n+\n+    rec->ctrl_unctrl = (rec->ctrl_unctrl & 0xFFFFFFFE) | (((packedRecVal[19] >> 1) & 0x1) << 0);\n+\n+    rec->sci_from_table = (rec->sci_from_table & 0xFFFFFFFE) | (((packedRecVal[19] >> 2) & 0x1) << 0);\n+\n+    rec->reserved = (rec->reserved & 0xFFFFFFF0) | (((packedRecVal[19] >> 3) & 0xF) << 0);\n+\n+    rec->valid = (rec->valid & 0xFFFFFFFE) | (((packedRecVal[19] >> 7) & 0x1) << 0);\n+\n+    return 0;\n+}\n+\n+\n+int AQ_API_SetIngressSCRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressSCRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[8];\n+\n+    if (tableIndex >= NUMROWS_INGRESSSCRECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 8);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x0000) | (((rec->stop_time >> 0) & 0xFFFF) << 0);\n+    packedRecVal[1] = (packedRecVal[1] & 0x0000) | (((rec->stop_time >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->start_time >> 0) & 0xFFFF) << 0);\n+    packedRecVal[3] = (packedRecVal[3] & 0x0000) | (((rec->start_time >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0xFFFC) | (((rec->validate_frames >> 0) & 0x3) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0xFFFB) | (((rec->replay_protect >> 0) & 0x1) << 2);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0x0007) | (((rec->anti_replay_window >> 0) & 0x1FFF) << 3);\n+    packedRecVal[5] = (packedRecVal[5] & 0x0000) | (((rec->anti_replay_window >> 13) & 0xFFFF) << 0);\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFF8) | (((rec->anti_replay_window >> 29) & 0x7) << 0);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFF7) | (((rec->receiving >> 0) & 0x1) << 3);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFEF) | (((rec->fresh >> 0) & 0x1) << 4);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFDF) | (((rec->an_rol >> 0) & 0x1) << 5);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0x003F) | (((rec->reserved >> 0) & 0x3FF) << 6);\n+    packedRecVal[7] = (packedRecVal[7] & 0x8000) | (((rec->reserved >> 10) & 0x7FFF) << 0);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0x7FFF) | (((rec->valid >> 0) & 0x1) << 15);\n+\n+    SetRawSECIngressRecordVal(hw, packedRecVal, 8, 3, ROWOFFSET_INGRESSSCRECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetIngressSCRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressSCRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[8];\n+\n+    if (tableIndex >= NUMROWS_INGRESSSCRECORD)\n+        return -EINVAL;\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_IngressSCRecord));\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 8, 3, ROWOFFSET_INGRESSSCRECORD + tableIndex);\n+\n+    rec->stop_time = (rec->stop_time & 0xFFFF0000) | (((packedRecVal[0] >> 0) & 0xFFFF) << 0);\n+    rec->stop_time = (rec->stop_time & 0x0000FFFF) | (((packedRecVal[1] >> 0) & 0xFFFF) << 16);\n+\n+    rec->start_time = (rec->start_time & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+    rec->start_time = (rec->start_time & 0x0000FFFF) | (((packedRecVal[3] >> 0) & 0xFFFF) << 16);\n+\n+    rec->validate_frames = (rec->validate_frames & 0xFFFFFFFC) | (((packedRecVal[4] >> 0) & 0x3) << 0);\n+\n+    rec->replay_protect = (rec->replay_protect & 0xFFFFFFFE) | (((packedRecVal[4] >> 2) & 0x1) << 0);\n+\n+    rec->anti_replay_window = (rec->anti_replay_window & 0xFFFFE000) | (((packedRecVal[4] >> 3) & 0x1FFF) << 0);\n+    rec->anti_replay_window = (rec->anti_replay_window & 0xE0001FFF) | (((packedRecVal[5] >> 0) & 0xFFFF) << 13);\n+    rec->anti_replay_window = (rec->anti_replay_window & 0x1FFFFFFF) | (((packedRecVal[6] >> 0) & 0x7) << 29);\n+\n+    rec->receiving = (rec->receiving & 0xFFFFFFFE) | (((packedRecVal[6] >> 3) & 0x1) << 0);\n+\n+    rec->fresh = (rec->fresh & 0xFFFFFFFE) | (((packedRecVal[6] >> 4) & 0x1) << 0);\n+\n+    rec->an_rol = (rec->an_rol & 0xFFFFFFFE) | (((packedRecVal[6] >> 5) & 0x1) << 0);\n+\n+    rec->reserved = (rec->reserved & 0xFFFFFC00) | (((packedRecVal[6] >> 6) & 0x3FF) << 0);\n+    rec->reserved = (rec->reserved & 0xFE0003FF) | (((packedRecVal[7] >> 0) & 0x7FFF) << 10);\n+\n+    rec->valid = (rec->valid & 0xFFFFFFFE) | (((packedRecVal[7] >> 15) & 0x1) << 0);\n+\n+    return 0;\n+}\n+\n+int AQ_API_SetIngressSARecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressSARecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[8];\n+\n+    if (tableIndex >= NUMROWS_INGRESSSARECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 8);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x0000) | (((rec->stop_time >> 0) & 0xFFFF) << 0);\n+    packedRecVal[1] = (packedRecVal[1] & 0x0000) | (((rec->stop_time >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->start_time >> 0) & 0xFFFF) << 0);\n+    packedRecVal[3] = (packedRecVal[3] & 0x0000) | (((rec->start_time >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0x0000) | (((rec->next_pn >> 0) & 0xFFFF) << 0);\n+    packedRecVal[5] = (packedRecVal[5] & 0x0000) | (((rec->next_pn >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFFE) | (((rec->sat_nextpn >> 0) & 0x1) << 0);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFFD) | (((rec->in_use >> 0) & 0x1) << 1);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFFB) | (((rec->fresh >> 0) & 0x1) << 2);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0x0007) | (((rec->reserved >> 0) & 0x1FFF) << 3);\n+    packedRecVal[7] = (packedRecVal[7] & 0x8000) | (((rec->reserved >> 13) & 0x7FFF) << 0);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0x7FFF) | (((rec->valid >> 0) & 0x1) << 15);\n+\n+    SetRawSECIngressRecordVal(hw, packedRecVal, 8, 3, ROWOFFSET_INGRESSSARECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetIngressSARecord(struct aq_hw_s *hw, AQ_API_SEC_IngressSARecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[8];\n+\n+    if (tableIndex >= NUMROWS_INGRESSSARECORD)\n+        return -EINVAL;\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_IngressSARecord));\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 8, 3, ROWOFFSET_INGRESSSARECORD + tableIndex);\n+\n+    rec->stop_time = (rec->stop_time & 0xFFFF0000) | (((packedRecVal[0] >> 0) & 0xFFFF) << 0);\n+    rec->stop_time = (rec->stop_time & 0x0000FFFF) | (((packedRecVal[1] >> 0) & 0xFFFF) << 16);\n+\n+    rec->start_time = (rec->start_time & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+    rec->start_time = (rec->start_time & 0x0000FFFF) | (((packedRecVal[3] >> 0) & 0xFFFF) << 16);\n+\n+    rec->next_pn = (rec->next_pn & 0xFFFF0000) | (((packedRecVal[4] >> 0) & 0xFFFF) << 0);\n+    rec->next_pn = (rec->next_pn & 0x0000FFFF) | (((packedRecVal[5] >> 0) & 0xFFFF) << 16);\n+\n+    rec->sat_nextpn = (rec->sat_nextpn & 0xFFFFFFFE) | (((packedRecVal[6] >> 0) & 0x1) << 0);\n+\n+    rec->in_use = (rec->in_use & 0xFFFFFFFE) | (((packedRecVal[6] >> 1) & 0x1) << 0);\n+\n+    rec->fresh = (rec->fresh & 0xFFFFFFFE) | (((packedRecVal[6] >> 2) & 0x1) << 0);\n+\n+    rec->reserved = (rec->reserved & 0xFFFFE000) | (((packedRecVal[6] >> 3) & 0x1FFF) << 0);\n+    rec->reserved = (rec->reserved & 0xF0001FFF) | (((packedRecVal[7] >> 0) & 0x7FFF) << 13);\n+\n+    rec->valid = (rec->valid & 0xFFFFFFFE) | (((packedRecVal[7] >> 15) & 0x1) << 0);\n+\n+    return 0;\n+}\n+\n+int AQ_API_SetIngressSAKeyRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressSAKeyRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[18];\n+\n+    if (tableIndex >= NUMROWS_INGRESSSAKEYRECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 18);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x0000) | (((rec->key[0] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[1] = (packedRecVal[1] & 0x0000) | (((rec->key[0] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->key[1] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[3] = (packedRecVal[3] & 0x0000) | (((rec->key[1] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0x0000) | (((rec->key[2] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[5] = (packedRecVal[5] & 0x0000) | (((rec->key[2] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0x0000) | (((rec->key[3] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[7] = (packedRecVal[7] & 0x0000) | (((rec->key[3] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[8] = (packedRecVal[8] & 0x0000) | (((rec->key[4] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[9] = (packedRecVal[9] & 0x0000) | (((rec->key[4] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[10] = (packedRecVal[10] & 0x0000) | (((rec->key[5] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[11] = (packedRecVal[11] & 0x0000) | (((rec->key[5] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[12] = (packedRecVal[12] & 0x0000) | (((rec->key[6] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[13] = (packedRecVal[13] & 0x0000) | (((rec->key[6] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[14] = (packedRecVal[14] & 0x0000) | (((rec->key[7] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[15] = (packedRecVal[15] & 0x0000) | (((rec->key[7] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[16] = (packedRecVal[16] & 0xFFFC) | (((rec->key_len >> 0) & 0x3) << 0);\n+\n+    SetRawSECIngressRecordVal(hw, packedRecVal, 18, 2, ROWOFFSET_INGRESSSAKEYRECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetIngressSAKeyRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressSAKeyRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[18];\n+\n+    if (tableIndex >= NUMROWS_INGRESSSAKEYRECORD)\n+        return -EINVAL;\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_IngressSAKeyRecord));\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 18, 2, ROWOFFSET_INGRESSSAKEYRECORD + tableIndex);\n+\n+    rec->key[0] = (rec->key[0] & 0xFFFF0000) | (((packedRecVal[0] >> 0) & 0xFFFF) << 0);\n+    rec->key[0] = (rec->key[0] & 0x0000FFFF) | (((packedRecVal[1] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[1] = (rec->key[1] & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+    rec->key[1] = (rec->key[1] & 0x0000FFFF) | (((packedRecVal[3] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[2] = (rec->key[2] & 0xFFFF0000) | (((packedRecVal[4] >> 0) & 0xFFFF) << 0);\n+    rec->key[2] = (rec->key[2] & 0x0000FFFF) | (((packedRecVal[5] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[3] = (rec->key[3] & 0xFFFF0000) | (((packedRecVal[6] >> 0) & 0xFFFF) << 0);\n+    rec->key[3] = (rec->key[3] & 0x0000FFFF) | (((packedRecVal[7] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[4] = (rec->key[4] & 0xFFFF0000) | (((packedRecVal[8] >> 0) & 0xFFFF) << 0);\n+    rec->key[4] = (rec->key[4] & 0x0000FFFF) | (((packedRecVal[9] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[5] = (rec->key[5] & 0xFFFF0000) | (((packedRecVal[10] >> 0) & 0xFFFF) << 0);\n+    rec->key[5] = (rec->key[5] & 0x0000FFFF) | (((packedRecVal[11] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[6] = (rec->key[6] & 0xFFFF0000) | (((packedRecVal[12] >> 0) & 0xFFFF) << 0);\n+    rec->key[6] = (rec->key[6] & 0x0000FFFF) | (((packedRecVal[13] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[7] = (rec->key[7] & 0xFFFF0000) | (((packedRecVal[14] >> 0) & 0xFFFF) << 0);\n+    rec->key[7] = (rec->key[7] & 0x0000FFFF) | (((packedRecVal[15] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key_len = (rec->key_len & 0xFFFFFFFC) | (((packedRecVal[16] >> 0) & 0x3) << 0);\n+\n+    return 0;\n+}\n+\n+int AQ_API_SetIngressPostClassRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressPostClassRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[8];\n+\n+    if (tableIndex >= NUMROWS_INGRESSPOSTCLASSRECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 8);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0xFF00) | (((rec->byte0 >> 0) & 0xFF) << 0);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x00FF) | (((rec->byte1 >> 0) & 0xFF) << 8);\n+\n+    packedRecVal[1] = (packedRecVal[1] & 0xFF00) | (((rec->byte2 >> 0) & 0xFF) << 0);\n+\n+    packedRecVal[1] = (packedRecVal[1] & 0x00FF) | (((rec->byte3 >> 0) & 0xFF) << 8);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->eth_type >> 0) & 0xFFFF) << 0);\n+\n+    packedRecVal[3] = (packedRecVal[3] & 0xFFFE) | (((rec->eth_type_valid >> 0) & 0x1) << 0);\n+\n+    packedRecVal[3] = (packedRecVal[3] & 0xE001) | (((rec->vlan_id >> 0) & 0xFFF) << 1);\n+\n+    packedRecVal[3] = (packedRecVal[3] & 0x1FFF) | (((rec->vlan_up >> 0) & 0x7) << 13);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0xFFFE) | (((rec->vlan_valid >> 0) & 0x1) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0xFFC1) | (((rec->sai >> 0) & 0x1F) << 1);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0xFFBF) | (((rec->sai_hit >> 0) & 0x1) << 6);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0xF87F) | (((rec->eth_type_mask >> 0) & 0xF) << 7);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0x07FF) | (((rec->byte3_location >> 0) & 0x1F) << 11);\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFFE) | (((rec->byte3_location >> 5) & 0x1) << 0);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFF9) | (((rec->byte3_mask >> 0) & 0x3) << 1);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xFE07) | (((rec->byte2_location >> 0) & 0x3F) << 3);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xF9FF) | (((rec->byte2_mask >> 0) & 0x3) << 9);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0x07FF) | (((rec->byte1_location >> 0) & 0x1F) << 11);\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFFE) | (((rec->byte1_location >> 5) & 0x1) << 0);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFF9) | (((rec->byte1_mask >> 0) & 0x3) << 1);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xFE07) | (((rec->byte0_location >> 0) & 0x3F) << 3);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xF9FF) | (((rec->byte0_mask >> 0) & 0x3) << 9);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xE7FF) | (((rec->eth_type_valid_mask >> 0) & 0x3) << 11);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0x1FFF) | (((rec->vlan_id_mask >> 0) & 0x7) << 13);\n+    packedRecVal[7] = (packedRecVal[7] & 0xFFFE) | (((rec->vlan_id_mask >> 3) & 0x1) << 0);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0xFFF9) | (((rec->vlan_up_mask >> 0) & 0x3) << 1);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0xFFE7) | (((rec->vlan_valid_mask >> 0) & 0x3) << 3);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0xFF9F) | (((rec->sai_mask >> 0) & 0x3) << 5);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0xFE7F) | (((rec->sai_hit_mask >> 0) & 0x3) << 7);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0xFDFF) | (((rec->firstlevel_actions >> 0) & 0x1) << 9);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0xFBFF) | (((rec->secondlevel_actions >> 0) & 0x1) << 10);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0x87FF) | (((rec->reserved >> 0) & 0xF) << 11);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0x7FFF) | (((rec->valid >> 0) & 0x1) << 15);\n+\n+    SetRawSECIngressRecordVal(hw, packedRecVal, 8, 4, ROWOFFSET_INGRESSPOSTCLASSRECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetIngressPostClassRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressPostClassRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[8];\n+\n+    if (tableIndex >= NUMROWS_INGRESSPOSTCLASSRECORD)\n+        return -EINVAL;\n+\n+    if ((tableIndex % 2) > 0)\n+    {\n+        GetRawSECIngressRecordVal(hw, packedRecVal, 8, 4, ROWOFFSET_INGRESSPOSTCLASSRECORD + tableIndex - 1);\n+    }\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_IngressPostClassRecord));\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 8, 4, ROWOFFSET_INGRESSPOSTCLASSRECORD + tableIndex);\n+\n+    rec->byte0 = (rec->byte0 & 0xFFFFFF00) | (((packedRecVal[0] >> 0) & 0xFF) << 0);\n+\n+    rec->byte1 = (rec->byte1 & 0xFFFFFF00) | (((packedRecVal[0] >> 8) & 0xFF) << 0);\n+\n+    rec->byte2 = (rec->byte2 & 0xFFFFFF00) | (((packedRecVal[1] >> 0) & 0xFF) << 0);\n+\n+    rec->byte3 = (rec->byte3 & 0xFFFFFF00) | (((packedRecVal[1] >> 8) & 0xFF) << 0);\n+\n+    rec->eth_type = (rec->eth_type & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+\n+    rec->eth_type_valid = (rec->eth_type_valid & 0xFFFFFFFE) | (((packedRecVal[3] >> 0) & 0x1) << 0);\n+\n+    rec->vlan_id = (rec->vlan_id & 0xFFFFF000) | (((packedRecVal[3] >> 1) & 0xFFF) << 0);\n+\n+    rec->vlan_up = (rec->vlan_up & 0xFFFFFFF8) | (((packedRecVal[3] >> 13) & 0x7) << 0);\n+\n+    rec->vlan_valid = (rec->vlan_valid & 0xFFFFFFFE) | (((packedRecVal[4] >> 0) & 0x1) << 0);\n+\n+    rec->sai = (rec->sai & 0xFFFFFFE0) | (((packedRecVal[4] >> 1) & 0x1F) << 0);\n+\n+    rec->sai_hit = (rec->sai_hit & 0xFFFFFFFE) | (((packedRecVal[4] >> 6) & 0x1) << 0);\n+\n+    rec->eth_type_mask = (rec->eth_type_mask & 0xFFFFFFF0) | (((packedRecVal[4] >> 7) & 0xF) << 0);\n+\n+    rec->byte3_location = (rec->byte3_location & 0xFFFFFFE0) | (((packedRecVal[4] >> 11) & 0x1F) << 0);\n+    rec->byte3_location = (rec->byte3_location & 0xFFFFFFDF) | (((packedRecVal[5] >> 0) & 0x1) << 5);\n+\n+    rec->byte3_mask = (rec->byte3_mask & 0xFFFFFFFC) | (((packedRecVal[5] >> 1) & 0x3) << 0);\n+\n+    rec->byte2_location = (rec->byte2_location & 0xFFFFFFC0) | (((packedRecVal[5] >> 3) & 0x3F) << 0);\n+\n+    rec->byte2_mask = (rec->byte2_mask & 0xFFFFFFFC) | (((packedRecVal[5] >> 9) & 0x3) << 0);\n+\n+    rec->byte1_location = (rec->byte1_location & 0xFFFFFFE0) | (((packedRecVal[5] >> 11) & 0x1F) << 0);\n+    rec->byte1_location = (rec->byte1_location & 0xFFFFFFDF) | (((packedRecVal[6] >> 0) & 0x1) << 5);\n+\n+    rec->byte1_mask = (rec->byte1_mask & 0xFFFFFFFC) | (((packedRecVal[6] >> 1) & 0x3) << 0);\n+\n+    rec->byte0_location = (rec->byte0_location & 0xFFFFFFC0) | (((packedRecVal[6] >> 3) & 0x3F) << 0);\n+\n+    rec->byte0_mask = (rec->byte0_mask & 0xFFFFFFFC) | (((packedRecVal[6] >> 9) & 0x3) << 0);\n+\n+    rec->eth_type_valid_mask = (rec->eth_type_valid_mask & 0xFFFFFFFC) | (((packedRecVal[6] >> 11) & 0x3) << 0);\n+\n+    rec->vlan_id_mask = (rec->vlan_id_mask & 0xFFFFFFF8) | (((packedRecVal[6] >> 13) & 0x7) << 0);\n+    rec->vlan_id_mask = (rec->vlan_id_mask & 0xFFFFFFF7) | (((packedRecVal[7] >> 0) & 0x1) << 3);\n+\n+    rec->vlan_up_mask = (rec->vlan_up_mask & 0xFFFFFFFC) | (((packedRecVal[7] >> 1) & 0x3) << 0);\n+\n+    rec->vlan_valid_mask = (rec->vlan_valid_mask & 0xFFFFFFFC) | (((packedRecVal[7] >> 3) & 0x3) << 0);\n+\n+    rec->sai_mask = (rec->sai_mask & 0xFFFFFFFC) | (((packedRecVal[7] >> 5) & 0x3) << 0);\n+\n+    rec->sai_hit_mask = (rec->sai_hit_mask & 0xFFFFFFFC) | (((packedRecVal[7] >> 7) & 0x3) << 0);\n+\n+    rec->firstlevel_actions = (rec->firstlevel_actions & 0xFFFFFFFE) | (((packedRecVal[7] >> 9) & 0x1) << 0);\n+\n+    rec->secondlevel_actions = (rec->secondlevel_actions & 0xFFFFFFFE) | (((packedRecVal[7] >> 10) & 0x1) << 0);\n+\n+    rec->reserved = (rec->reserved & 0xFFFFFFF0) | (((packedRecVal[7] >> 11) & 0xF) << 0);\n+\n+    rec->valid = (rec->valid & 0xFFFFFFFE) | (((packedRecVal[7] >> 15) & 0x1) << 0);\n+\n+    return 0;\n+}\n+\n+\n+int AQ_API_SetIngressPostCTLFRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressPostCTLFRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[6];\n+\n+    if (tableIndex >= NUMROWS_INGRESSPOSTCTLFRECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 6);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x0000) | (((rec->sa_da[0] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[1] = (packedRecVal[1] & 0x0000) | (((rec->sa_da[0] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->sa_da[1] >> 0) & 0xFFFF) << 0);\n+\n+    packedRecVal[3] = (packedRecVal[3] & 0x0000) | (((rec->eth_type >> 0) & 0xFFFF) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0x0000) | (((rec->match_mask >> 0) & 0xFFFF) << 0);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFF0) | (((rec->match_type >> 0) & 0xF) << 0);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFEF) | (((rec->action >> 0) & 0x1) << 4);\n+\n+    SetRawSECIngressRecordVal(hw, packedRecVal, 6, 5, ROWOFFSET_INGRESSPOSTCTLFRECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetIngressPostCTLFRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressPostCTLFRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[6];\n+\n+    if (tableIndex >= NUMROWS_INGRESSPOSTCTLFRECORD)\n+        return -EINVAL;\n+\n+    if ((tableIndex % 2) > 0)\n+    {\n+        GetRawSECIngressRecordVal(hw, packedRecVal, 6, 5, ROWOFFSET_INGRESSPOSTCTLFRECORD + tableIndex - 1);\n+    }\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_IngressPostCTLFRecord));\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 6, 5, ROWOFFSET_INGRESSPOSTCTLFRECORD + tableIndex);\n+\n+    rec->sa_da[0] = (rec->sa_da[0] & 0xFFFF0000) | (((packedRecVal[0] >> 0) & 0xFFFF) << 0);\n+    rec->sa_da[0] = (rec->sa_da[0] & 0x0000FFFF) | (((packedRecVal[1] >> 0) & 0xFFFF) << 16);\n+\n+    rec->sa_da[1] = (rec->sa_da[1] & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+\n+    rec->eth_type = (rec->eth_type & 0xFFFF0000) | (((packedRecVal[3] >> 0) & 0xFFFF) << 0);\n+\n+    rec->match_mask = (rec->match_mask & 0xFFFF0000) | (((packedRecVal[4] >> 0) & 0xFFFF) << 0);\n+\n+    rec->match_type = (rec->match_type & 0xFFFFFFF0) | (((packedRecVal[5] >> 0) & 0xF) << 0);\n+\n+    rec->action = (rec->action & 0xFFFFFFFE) | (((packedRecVal[5] >> 4) & 0x1) << 0);\n+\n+    return 0;\n+}\n+\n+int AQ_API_SetEgressCTLFRecord(struct aq_hw_s *hw, const AQ_API_SEC_EgressCTLFRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[6];\n+\n+    if (tableIndex >= NUMROWS_EGRESSCTLFRECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 6);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x0000) | (((rec->sa_da[0] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[1] = (packedRecVal[1] & 0x0000) | (((rec->sa_da[0] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->sa_da[1] >> 0) & 0xFFFF) << 0);\n+\n+    packedRecVal[3] = (packedRecVal[3] & 0x0000) | (((rec->eth_type >> 0) & 0xFFFF) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0x0000) | (((rec->match_mask >> 0) & 0xFFFF) << 0);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFF0) | (((rec->match_type >> 0) & 0xF) << 0);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFEF) | (((rec->action >> 0) & 0x1) << 4);\n+\n+    SetRawSECEgressRecordVal(hw, packedRecVal, 6, 0, ROWOFFSET_EGRESSCTLFRECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetEgressCTLFRecord(struct aq_hw_s *hw, AQ_API_SEC_EgressCTLFRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[6];\n+\n+    if (tableIndex >= NUMROWS_EGRESSCTLFRECORD)\n+        return -EINVAL;\n+\n+    if ((tableIndex % 2) > 0)\n+    {\n+        GetRawSECEgressRecordVal(hw, packedRecVal, 6, 0, ROWOFFSET_EGRESSCTLFRECORD + tableIndex - 1);\n+    }\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_EgressCTLFRecord));\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 6, 0, ROWOFFSET_EGRESSCTLFRECORD + tableIndex);\n+\n+    rec->sa_da[0] = (rec->sa_da[0] & 0xFFFF0000) | (((packedRecVal[0] >> 0) & 0xFFFF) << 0);\n+    rec->sa_da[0] = (rec->sa_da[0] & 0x0000FFFF) | (((packedRecVal[1] >> 0) & 0xFFFF) << 16);\n+\n+    rec->sa_da[1] = (rec->sa_da[1] & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+\n+    rec->eth_type = (rec->eth_type & 0xFFFF0000) | (((packedRecVal[3] >> 0) & 0xFFFF) << 0);\n+\n+    rec->match_mask = (rec->match_mask & 0xFFFF0000) | (((packedRecVal[4] >> 0) & 0xFFFF) << 0);\n+\n+    rec->match_type = (rec->match_type & 0xFFFFFFF0) | (((packedRecVal[5] >> 0) & 0xF) << 0);\n+\n+    rec->action = (rec->action & 0xFFFFFFFE) | (((packedRecVal[5] >> 4) & 0x1) << 0);\n+\n+    return 0;\n+}\n+\n+int AQ_API_SetEgressClassRecord(struct aq_hw_s *hw, const AQ_API_SEC_EgressClassRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[28];\n+\n+    if (tableIndex >= NUMROWS_EGRESSCLASSRECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 28);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0xF000) | (((rec->vlan_id >> 0) & 0xFFF) << 0);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x8FFF) | (((rec->vlan_up >> 0) & 0x7) << 12);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x7FFF) | (((rec->vlan_valid >> 0) & 0x1) << 15);\n+\n+    packedRecVal[1] = (packedRecVal[1] & 0xFF00) | (((rec->byte3 >> 0) & 0xFF) << 0);\n+\n+    packedRecVal[1] = (packedRecVal[1] & 0x00FF) | (((rec->byte2 >> 0) & 0xFF) << 8);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0xFF00) | (((rec->byte1 >> 0) & 0xFF) << 0);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x00FF) | (((rec->byte0 >> 0) & 0xFF) << 8);\n+\n+    packedRecVal[3] = (packedRecVal[3] & 0xFF00) | (((rec->tci >> 0) & 0xFF) << 0);\n+\n+    packedRecVal[3] = (packedRecVal[3] & 0x00FF) | (((rec->sci[0] >> 0) & 0xFF) << 8);\n+    packedRecVal[4] = (packedRecVal[4] & 0x0000) | (((rec->sci[0] >> 8) & 0xFFFF) << 0);\n+    packedRecVal[5] = (packedRecVal[5] & 0xFF00) | (((rec->sci[0] >> 24) & 0xFF) << 0);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0x00FF) | (((rec->sci[1] >> 0) & 0xFF) << 8);\n+    packedRecVal[6] = (packedRecVal[6] & 0x0000) | (((rec->sci[1] >> 8) & 0xFFFF) << 0);\n+    packedRecVal[7] = (packedRecVal[7] & 0xFF00) | (((rec->sci[1] >> 24) & 0xFF) << 0);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0x00FF) | (((rec->eth_type >> 0) & 0xFF) << 8);\n+    packedRecVal[8] = (packedRecVal[8] & 0xFF00) | (((rec->eth_type >> 8) & 0xFF) << 0);\n+\n+    packedRecVal[8] = (packedRecVal[8] & 0x00FF) | (((rec->snap[0] >> 0) & 0xFF) << 8);\n+    packedRecVal[9] = (packedRecVal[9] & 0x0000) | (((rec->snap[0] >> 8) & 0xFFFF) << 0);\n+    packedRecVal[10] = (packedRecVal[10] & 0xFF00) | (((rec->snap[0] >> 24) & 0xFF) << 0);\n+\n+    packedRecVal[10] = (packedRecVal[10] & 0x00FF) | (((rec->snap[1] >> 0) & 0xFF) << 8);\n+\n+    packedRecVal[11] = (packedRecVal[11] & 0x0000) | (((rec->llc >> 0) & 0xFFFF) << 0);\n+    packedRecVal[12] = (packedRecVal[12] & 0xFF00) | (((rec->llc >> 16) & 0xFF) << 0);\n+\n+    packedRecVal[12] = (packedRecVal[12] & 0x00FF) | (((rec->mac_sa[0] >> 0) & 0xFF) << 8);\n+    packedRecVal[13] = (packedRecVal[13] & 0x0000) | (((rec->mac_sa[0] >> 8) & 0xFFFF) << 0);\n+    packedRecVal[14] = (packedRecVal[14] & 0xFF00) | (((rec->mac_sa[0] >> 24) & 0xFF) << 0);\n+\n+    packedRecVal[14] = (packedRecVal[14] & 0x00FF) | (((rec->mac_sa[1] >> 0) & 0xFF) << 8);\n+    packedRecVal[15] = (packedRecVal[15] & 0xFF00) | (((rec->mac_sa[1] >> 8) & 0xFF) << 0);\n+\n+    packedRecVal[15] = (packedRecVal[15] & 0x00FF) | (((rec->mac_da[0] >> 0) & 0xFF) << 8);\n+    packedRecVal[16] = (packedRecVal[16] & 0x0000) | (((rec->mac_da[0] >> 8) & 0xFFFF) << 0);\n+    packedRecVal[17] = (packedRecVal[17] & 0xFF00) | (((rec->mac_da[0] >> 24) & 0xFF) << 0);\n+\n+    packedRecVal[17] = (packedRecVal[17] & 0x00FF) | (((rec->mac_da[1] >> 0) & 0xFF) << 8);\n+    packedRecVal[18] = (packedRecVal[18] & 0xFF00) | (((rec->mac_da[1] >> 8) & 0xFF) << 0);\n+\n+    packedRecVal[18] = (packedRecVal[18] & 0x00FF) | (((rec->pn >> 0) & 0xFF) << 8);\n+    packedRecVal[19] = (packedRecVal[19] & 0x0000) | (((rec->pn >> 8) & 0xFFFF) << 0);\n+    packedRecVal[20] = (packedRecVal[20] & 0xFF00) | (((rec->pn >> 24) & 0xFF) << 0);\n+\n+    packedRecVal[20] = (packedRecVal[20] & 0xC0FF) | (((rec->byte3_location >> 0) & 0x3F) << 8);\n+\n+    packedRecVal[20] = (packedRecVal[20] & 0xBFFF) | (((rec->byte3_mask >> 0) & 0x1) << 14);\n+\n+    packedRecVal[20] = (packedRecVal[20] & 0x7FFF) | (((rec->byte2_location >> 0) & 0x1) << 15);\n+    packedRecVal[21] = (packedRecVal[21] & 0xFFE0) | (((rec->byte2_location >> 1) & 0x1F) << 0);\n+\n+    packedRecVal[21] = (packedRecVal[21] & 0xFFDF) | (((rec->byte2_mask >> 0) & 0x1) << 5);\n+\n+    packedRecVal[21] = (packedRecVal[21] & 0xF03F) | (((rec->byte1_location >> 0) & 0x3F) << 6);\n+\n+    packedRecVal[21] = (packedRecVal[21] & 0xEFFF) | (((rec->byte1_mask >> 0) & 0x1) << 12);\n+\n+    packedRecVal[21] = (packedRecVal[21] & 0x1FFF) | (((rec->byte0_location >> 0) & 0x7) << 13);\n+    packedRecVal[22] = (packedRecVal[22] & 0xFFF8) | (((rec->byte0_location >> 3) & 0x7) << 0);\n+\n+    packedRecVal[22] = (packedRecVal[22] & 0xFFF7) | (((rec->byte0_mask >> 0) & 0x1) << 3);\n+\n+    packedRecVal[22] = (packedRecVal[22] & 0xFFCF) | (((rec->vlan_id_mask >> 0) & 0x3) << 4);\n+\n+    packedRecVal[22] = (packedRecVal[22] & 0xFFBF) | (((rec->vlan_up_mask >> 0) & 0x1) << 6);\n+\n+    packedRecVal[22] = (packedRecVal[22] & 0xFF7F) | (((rec->vlan_valid_mask >> 0) & 0x1) << 7);\n+\n+    packedRecVal[22] = (packedRecVal[22] & 0x00FF) | (((rec->tci_mask >> 0) & 0xFF) << 8);\n+\n+    packedRecVal[23] = (packedRecVal[23] & 0xFF00) | (((rec->sci_mask >> 0) & 0xFF) << 0);\n+\n+    packedRecVal[23] = (packedRecVal[23] & 0xFCFF) | (((rec->eth_type_mask >> 0) & 0x3) << 8);\n+\n+    packedRecVal[23] = (packedRecVal[23] & 0x83FF) | (((rec->snap_mask >> 0) & 0x1F) << 10);\n+\n+    packedRecVal[23] = (packedRecVal[23] & 0x7FFF) | (((rec->llc_mask >> 0) & 0x1) << 15);\n+    packedRecVal[24] = (packedRecVal[24] & 0xFFFC) | (((rec->llc_mask >> 1) & 0x3) << 0);\n+\n+    packedRecVal[24] = (packedRecVal[24] & 0xFF03) | (((rec->sa_mask >> 0) & 0x3F) << 2);\n+\n+    packedRecVal[24] = (packedRecVal[24] & 0xC0FF) | (((rec->da_mask >> 0) & 0x3F) << 8);\n+\n+    packedRecVal[24] = (packedRecVal[24] & 0x3FFF) | (((rec->pn_mask >> 0) & 0x3) << 14);\n+    packedRecVal[25] = (packedRecVal[25] & 0xFFFC) | (((rec->pn_mask >> 2) & 0x3) << 0);\n+\n+    packedRecVal[25] = (packedRecVal[25] & 0xFFFB) | (((rec->eight02dot2 >> 0) & 0x1) << 2);\n+\n+    packedRecVal[25] = (packedRecVal[25] & 0xFFF7) | (((rec->tci_sc >> 0) & 0x1) << 3);\n+\n+    packedRecVal[25] = (packedRecVal[25] & 0xFFEF) | (((rec->tci_87543 >> 0) & 0x1) << 4);\n+\n+    packedRecVal[25] = (packedRecVal[25] & 0xFFDF) | (((rec->exp_sectag_en >> 0) & 0x1) << 5);\n+\n+    packedRecVal[25] = (packedRecVal[25] & 0xF83F) | (((rec->sc_idx >> 0) & 0x1F) << 6);\n+\n+    packedRecVal[25] = (packedRecVal[25] & 0xE7FF) | (((rec->sc_sa >> 0) & 0x3) << 11);\n+\n+    packedRecVal[25] = (packedRecVal[25] & 0xDFFF) | (((rec->debug >> 0) & 0x1) << 13);\n+\n+    packedRecVal[25] = (packedRecVal[25] & 0x3FFF) | (((rec->action >> 0) & 0x3) << 14);\n+\n+    packedRecVal[26] = (packedRecVal[26] & 0xFFF7) | (((rec->valid >> 0) & 0x1) << 3);\n+\n+    SetRawSECEgressRecordVal(hw, packedRecVal, 28, 1, ROWOFFSET_EGRESSCLASSRECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetEgressClassRecord(struct aq_hw_s *hw, AQ_API_SEC_EgressClassRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[28];\n+\n+    if (tableIndex >= NUMROWS_EGRESSCLASSRECORD)\n+        return -EINVAL;\n+\n+    if ((tableIndex % 2) > 0) {\n+        GetRawSECEgressRecordVal(hw, packedRecVal, 28, 1, ROWOFFSET_EGRESSCLASSRECORD + tableIndex - 1);\n+    }\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_EgressClassRecord));\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 28, 1, ROWOFFSET_EGRESSCLASSRECORD + tableIndex);\n+\n+    rec->vlan_id = (rec->vlan_id & 0xFFFFF000) | (((packedRecVal[0] >> 0) & 0xFFF) << 0);\n+\n+    rec->vlan_up = (rec->vlan_up & 0xFFFFFFF8) | (((packedRecVal[0] >> 12) & 0x7) << 0);\n+\n+    rec->vlan_valid = (rec->vlan_valid & 0xFFFFFFFE) | (((packedRecVal[0] >> 15) & 0x1) << 0);\n+\n+    rec->byte3 = (rec->byte3 & 0xFFFFFF00) | (((packedRecVal[1] >> 0) & 0xFF) << 0);\n+\n+    rec->byte2 = (rec->byte2 & 0xFFFFFF00) | (((packedRecVal[1] >> 8) & 0xFF) << 0);\n+\n+    rec->byte1 = (rec->byte1 & 0xFFFFFF00) | (((packedRecVal[2] >> 0) & 0xFF) << 0);\n+\n+    rec->byte0 = (rec->byte0 & 0xFFFFFF00) | (((packedRecVal[2] >> 8) & 0xFF) << 0);\n+\n+    rec->tci = (rec->tci & 0xFFFFFF00) | (((packedRecVal[3] >> 0) & 0xFF) << 0);\n+\n+    rec->sci[0] = (rec->sci[0] & 0xFFFFFF00) | (((packedRecVal[3] >> 8) & 0xFF) << 0);\n+    rec->sci[0] = (rec->sci[0] & 0xFF0000FF) | (((packedRecVal[4] >> 0) & 0xFFFF) << 8);\n+    rec->sci[0] = (rec->sci[0] & 0x00FFFFFF) | (((packedRecVal[5] >> 0) & 0xFF) << 24);\n+\n+    rec->sci[1] = (rec->sci[1] & 0xFFFFFF00) | (((packedRecVal[5] >> 8) & 0xFF) << 0);\n+    rec->sci[1] = (rec->sci[1] & 0xFF0000FF) | (((packedRecVal[6] >> 0) & 0xFFFF) << 8);\n+    rec->sci[1] = (rec->sci[1] & 0x00FFFFFF) | (((packedRecVal[7] >> 0) & 0xFF) << 24);\n+\n+    rec->eth_type = (rec->eth_type & 0xFFFFFF00) | (((packedRecVal[7] >> 8) & 0xFF) << 0);\n+    rec->eth_type = (rec->eth_type & 0xFFFF00FF) | (((packedRecVal[8] >> 0) & 0xFF) << 8);\n+\n+    rec->snap[0] = (rec->snap[0] & 0xFFFFFF00) | (((packedRecVal[8] >> 8) & 0xFF) << 0);\n+    rec->snap[0] = (rec->snap[0] & 0xFF0000FF) | (((packedRecVal[9] >> 0) & 0xFFFF) << 8);\n+    rec->snap[0] = (rec->snap[0] & 0x00FFFFFF) | (((packedRecVal[10] >> 0) & 0xFF) << 24);\n+\n+    rec->snap[1] = (rec->snap[1] & 0xFFFFFF00) | (((packedRecVal[10] >> 8) & 0xFF) << 0);\n+\n+    rec->llc = (rec->llc & 0xFFFF0000) | (((packedRecVal[11] >> 0) & 0xFFFF) << 0);\n+    rec->llc = (rec->llc & 0xFF00FFFF) | (((packedRecVal[12] >> 0) & 0xFF) << 16);\n+\n+    rec->mac_sa[0] = (rec->mac_sa[0] & 0xFFFFFF00) | (((packedRecVal[12] >> 8) & 0xFF) << 0);\n+    rec->mac_sa[0] = (rec->mac_sa[0] & 0xFF0000FF) | (((packedRecVal[13] >> 0) & 0xFFFF) << 8);\n+    rec->mac_sa[0] = (rec->mac_sa[0] & 0x00FFFFFF) | (((packedRecVal[14] >> 0) & 0xFF) << 24);\n+\n+    rec->mac_sa[1] = (rec->mac_sa[1] & 0xFFFFFF00) | (((packedRecVal[14] >> 8) & 0xFF) << 0);\n+    rec->mac_sa[1] = (rec->mac_sa[1] & 0xFFFF00FF) | (((packedRecVal[15] >> 0) & 0xFF) << 8);\n+\n+    rec->mac_da[0] = (rec->mac_da[0] & 0xFFFFFF00) | (((packedRecVal[15] >> 8) & 0xFF) << 0);\n+    rec->mac_da[0] = (rec->mac_da[0] & 0xFF0000FF) | (((packedRecVal[16] >> 0) & 0xFFFF) << 8);\n+    rec->mac_da[0] = (rec->mac_da[0] & 0x00FFFFFF) | (((packedRecVal[17] >> 0) & 0xFF) << 24);\n+\n+    rec->mac_da[1] = (rec->mac_da[1] & 0xFFFFFF00) | (((packedRecVal[17] >> 8) & 0xFF) << 0);\n+    rec->mac_da[1] = (rec->mac_da[1] & 0xFFFF00FF) | (((packedRecVal[18] >> 0) & 0xFF) << 8);\n+\n+    rec->pn = (rec->pn & 0xFFFFFF00) | (((packedRecVal[18] >> 8) & 0xFF) << 0);\n+    rec->pn = (rec->pn & 0xFF0000FF) | (((packedRecVal[19] >> 0) & 0xFFFF) << 8);\n+    rec->pn = (rec->pn & 0x00FFFFFF) | (((packedRecVal[20] >> 0) & 0xFF) << 24);\n+\n+    rec->byte3_location = (rec->byte3_location & 0xFFFFFFC0) | (((packedRecVal[20] >> 8) & 0x3F) << 0);\n+\n+    rec->byte3_mask = (rec->byte3_mask & 0xFFFFFFFE) | (((packedRecVal[20] >> 14) & 0x1) << 0);\n+\n+    rec->byte2_location = (rec->byte2_location & 0xFFFFFFFE) | (((packedRecVal[20] >> 15) & 0x1) << 0);\n+    rec->byte2_location = (rec->byte2_location & 0xFFFFFFC1) | (((packedRecVal[21] >> 0) & 0x1F) << 1);\n+\n+    rec->byte2_mask = (rec->byte2_mask & 0xFFFFFFFE) | (((packedRecVal[21] >> 5) & 0x1) << 0);\n+\n+    rec->byte1_location = (rec->byte1_location & 0xFFFFFFC0) | (((packedRecVal[21] >> 6) & 0x3F) << 0);\n+\n+    rec->byte1_mask = (rec->byte1_mask & 0xFFFFFFFE) | (((packedRecVal[21] >> 12) & 0x1) << 0);\n+\n+    rec->byte0_location = (rec->byte0_location & 0xFFFFFFF8) | (((packedRecVal[21] >> 13) & 0x7) << 0);\n+    rec->byte0_location = (rec->byte0_location & 0xFFFFFFC7) | (((packedRecVal[22] >> 0) & 0x7) << 3);\n+\n+    rec->byte0_mask = (rec->byte0_mask & 0xFFFFFFFE) | (((packedRecVal[22] >> 3) & 0x1) << 0);\n+\n+    rec->vlan_id_mask = (rec->vlan_id_mask & 0xFFFFFFFC) | (((packedRecVal[22] >> 4) & 0x3) << 0);\n+\n+    rec->vlan_up_mask = (rec->vlan_up_mask & 0xFFFFFFFE) | (((packedRecVal[22] >> 6) & 0x1) << 0);\n+\n+    rec->vlan_valid_mask = (rec->vlan_valid_mask & 0xFFFFFFFE) | (((packedRecVal[22] >> 7) & 0x1) << 0);\n+\n+    rec->tci_mask = (rec->tci_mask & 0xFFFFFF00) | (((packedRecVal[22] >> 8) & 0xFF) << 0);\n+\n+    rec->sci_mask = (rec->sci_mask & 0xFFFFFF00) | (((packedRecVal[23] >> 0) & 0xFF) << 0);\n+\n+    rec->eth_type_mask = (rec->eth_type_mask & 0xFFFFFFFC) | (((packedRecVal[23] >> 8) & 0x3) << 0);\n+\n+    rec->snap_mask = (rec->snap_mask & 0xFFFFFFE0) | (((packedRecVal[23] >> 10) & 0x1F) << 0);\n+\n+    rec->llc_mask = (rec->llc_mask & 0xFFFFFFFE) | (((packedRecVal[23] >> 15) & 0x1) << 0);\n+    rec->llc_mask = (rec->llc_mask & 0xFFFFFFF9) | (((packedRecVal[24] >> 0) & 0x3) << 1);\n+\n+    rec->sa_mask = (rec->sa_mask & 0xFFFFFFC0) | (((packedRecVal[24] >> 2) & 0x3F) << 0);\n+\n+    rec->da_mask = (rec->da_mask & 0xFFFFFFC0) | (((packedRecVal[24] >> 8) & 0x3F) << 0);\n+\n+    rec->pn_mask = (rec->pn_mask & 0xFFFFFFFC) | (((packedRecVal[24] >> 14) & 0x3) << 0);\n+    rec->pn_mask = (rec->pn_mask & 0xFFFFFFF3) | (((packedRecVal[25] >> 0) & 0x3) << 2);\n+\n+    rec->eight02dot2 = (rec->eight02dot2 & 0xFFFFFFFE) | (((packedRecVal[25] >> 2) & 0x1) << 0);\n+\n+    rec->tci_sc = (rec->tci_sc & 0xFFFFFFFE) | (((packedRecVal[25] >> 3) & 0x1) << 0);\n+\n+    rec->tci_87543 = (rec->tci_87543 & 0xFFFFFFFE) | (((packedRecVal[25] >> 4) & 0x1) << 0);\n+\n+    rec->exp_sectag_en = (rec->exp_sectag_en & 0xFFFFFFFE) | (((packedRecVal[25] >> 5) & 0x1) << 0);\n+\n+    rec->sc_idx = (rec->sc_idx & 0xFFFFFFE0) | (((packedRecVal[25] >> 6) & 0x1F) << 0);\n+\n+    rec->sc_sa = (rec->sc_sa & 0xFFFFFFFC) | (((packedRecVal[25] >> 11) & 0x3) << 0);\n+\n+    rec->debug = (rec->debug & 0xFFFFFFFE) | (((packedRecVal[25] >> 13) & 0x1) << 0);\n+\n+    rec->action = (rec->action & 0xFFFFFFFC) | (((packedRecVal[25] >> 14) & 0x3) << 0);\n+\n+    rec->valid = (rec->valid & 0xFFFFFFFE) | (((packedRecVal[26] >> 3) & 0x1) << 0);\n+\n+    return 0;\n+}\n+\n+int AQ_API_SetEgressSCRecord(struct aq_hw_s *hw, const AQ_API_SEC_EgressSCRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[8];\n+\n+    if (tableIndex >= NUMROWS_EGRESSSCRECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 8);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x0000) | (((rec->start_time >> 0) & 0xFFFF) << 0);\n+    packedRecVal[1] = (packedRecVal[1] & 0x0000) | (((rec->start_time >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->stop_time >> 0) & 0xFFFF) << 0);\n+    packedRecVal[3] = (packedRecVal[3] & 0x0000) | (((rec->stop_time >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0xFFFC) | (((rec->curr_an >> 0) & 0x3) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0xFFFB) | (((rec->an_roll >> 0) & 0x1) << 2);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0xFE07) | (((rec->tci >> 0) & 0x3F) << 3);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0x01FF) | (((rec->enc_off >> 0) & 0x7F) << 9);\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFFE) | (((rec->enc_off >> 7) & 0x1) << 0);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFFD) | (((rec->protect >> 0) & 0x1) << 1);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFFB) | (((rec->recv >> 0) & 0x1) << 2);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFF7) | (((rec->fresh >> 0) & 0x1) << 3);\n+\n+    packedRecVal[5] = (packedRecVal[5] & 0xFFCF) | (((rec->sak_len >> 0) & 0x3) << 4);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0x7FFF) | (((rec->valid >> 0) & 0x1) << 15);\n+\n+    SetRawSECEgressRecordVal(hw, packedRecVal, 8, 2, ROWOFFSET_EGRESSSCRECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetEgressSCRecord(struct aq_hw_s *hw, AQ_API_SEC_EgressSCRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[8];\n+\n+    if (tableIndex >= NUMROWS_EGRESSSCRECORD)\n+        return -EINVAL;\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_EgressSCRecord));\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 8, 2, ROWOFFSET_EGRESSSCRECORD + tableIndex);\n+\n+    rec->start_time = (rec->start_time & 0xFFFF0000) | (((packedRecVal[0] >> 0) & 0xFFFF) << 0);\n+    rec->start_time = (rec->start_time & 0x0000FFFF) | (((packedRecVal[1] >> 0) & 0xFFFF) << 16);\n+\n+    rec->stop_time = (rec->stop_time & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+    rec->stop_time = (rec->stop_time & 0x0000FFFF) | (((packedRecVal[3] >> 0) & 0xFFFF) << 16);\n+\n+    rec->curr_an = (rec->curr_an & 0xFFFFFFFC) | (((packedRecVal[4] >> 0) & 0x3) << 0);\n+\n+    rec->an_roll = (rec->an_roll & 0xFFFFFFFE) | (((packedRecVal[4] >> 2) & 0x1) << 0);\n+\n+    rec->tci = (rec->tci & 0xFFFFFFC0) | (((packedRecVal[4] >> 3) & 0x3F) << 0);\n+\n+    rec->enc_off = (rec->enc_off & 0xFFFFFF80) | (((packedRecVal[4] >> 9) & 0x7F) << 0);\n+    rec->enc_off = (rec->enc_off & 0xFFFFFF7F) | (((packedRecVal[5] >> 0) & 0x1) << 7);\n+\n+    rec->protect = (rec->protect & 0xFFFFFFFE) | (((packedRecVal[5] >> 1) & 0x1) << 0);\n+\n+    rec->recv = (rec->recv & 0xFFFFFFFE) | (((packedRecVal[5] >> 2) & 0x1) << 0);\n+\n+    rec->fresh = (rec->fresh & 0xFFFFFFFE) | (((packedRecVal[5] >> 3) & 0x1) << 0);\n+\n+    rec->sak_len = (rec->sak_len & 0xFFFFFFFC) | (((packedRecVal[5] >> 4) & 0x3) << 0);\n+\n+    rec->valid = (rec->valid & 0xFFFFFFFE) | (((packedRecVal[7] >> 15) & 0x1) << 0);\n+\n+    return 0;\n+}\n+\n+int AQ_API_SetEgressSARecord(struct aq_hw_s *hw, const AQ_API_SEC_EgressSARecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[8];\n+\n+    if (tableIndex >= NUMROWS_EGRESSSARECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 8);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x0000) | (((rec->start_time >> 0) & 0xFFFF) << 0);\n+    packedRecVal[1] = (packedRecVal[1] & 0x0000) | (((rec->start_time >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->stop_time >> 0) & 0xFFFF) << 0);\n+    packedRecVal[3] = (packedRecVal[3] & 0x0000) | (((rec->stop_time >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0x0000) | (((rec->next_pn >> 0) & 0xFFFF) << 0);\n+    packedRecVal[5] = (packedRecVal[5] & 0x0000) | (((rec->next_pn >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFFE) | (((rec->sat_pn >> 0) & 0x1) << 0);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0xFFFD) | (((rec->fresh >> 0) & 0x1) << 1);\n+\n+    packedRecVal[7] = (packedRecVal[7] & 0x7FFF) | (((rec->valid >> 0) & 0x1) << 15);\n+\n+    SetRawSECEgressRecordVal(hw, packedRecVal, 8, 2, ROWOFFSET_EGRESSSARECORD + tableIndex);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetEgressSARecord(struct aq_hw_s *hw, AQ_API_SEC_EgressSARecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[8];\n+\n+    if (tableIndex >= NUMROWS_EGRESSSARECORD)\n+        return -EINVAL;\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_EgressSARecord));\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 8, 2, ROWOFFSET_EGRESSSARECORD + tableIndex);\n+\n+    rec->start_time = (rec->start_time & 0xFFFF0000) | (((packedRecVal[0] >> 0) & 0xFFFF) << 0);\n+    rec->start_time = (rec->start_time & 0x0000FFFF) | (((packedRecVal[1] >> 0) & 0xFFFF) << 16);\n+\n+    rec->stop_time = (rec->stop_time & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+    rec->stop_time = (rec->stop_time & 0x0000FFFF) | (((packedRecVal[3] >> 0) & 0xFFFF) << 16);\n+\n+    rec->next_pn = (rec->next_pn & 0xFFFF0000) | (((packedRecVal[4] >> 0) & 0xFFFF) << 0);\n+    rec->next_pn = (rec->next_pn & 0x0000FFFF) | (((packedRecVal[5] >> 0) & 0xFFFF) << 16);\n+\n+    rec->sat_pn = (rec->sat_pn & 0xFFFFFFFE) | (((packedRecVal[6] >> 0) & 0x1) << 0);\n+\n+    rec->fresh = (rec->fresh & 0xFFFFFFFE) | (((packedRecVal[6] >> 1) & 0x1) << 0);\n+\n+    rec->valid = (rec->valid & 0xFFFFFFFE) | (((packedRecVal[7] >> 15) & 0x1) << 0);\n+\n+    return 0;\n+}\n+\n+int AQ_API_SetEgressSAKeyRecord(struct aq_hw_s *hw, const AQ_API_SEC_EgressSAKeyRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[16];\n+\n+    if (tableIndex >= NUMROWS_EGRESSSAKEYRECORD)\n+        return -EINVAL;\n+\n+    memset(packedRecVal, 0, sizeof(uint16_t) * 16);\n+\n+    packedRecVal[0] = (packedRecVal[0] & 0x0000) | (((rec->key[0] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[1] = (packedRecVal[1] & 0x0000) | (((rec->key[0] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[2] = (packedRecVal[2] & 0x0000) | (((rec->key[1] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[3] = (packedRecVal[3] & 0x0000) | (((rec->key[1] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[4] = (packedRecVal[4] & 0x0000) | (((rec->key[2] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[5] = (packedRecVal[5] & 0x0000) | (((rec->key[2] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[6] = (packedRecVal[6] & 0x0000) | (((rec->key[3] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[7] = (packedRecVal[7] & 0x0000) | (((rec->key[3] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[8] = (packedRecVal[8] & 0x0000) | (((rec->key[4] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[9] = (packedRecVal[9] & 0x0000) | (((rec->key[4] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[10] = (packedRecVal[10] & 0x0000) | (((rec->key[5] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[11] = (packedRecVal[11] & 0x0000) | (((rec->key[5] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[12] = (packedRecVal[12] & 0x0000) | (((rec->key[6] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[13] = (packedRecVal[13] & 0x0000) | (((rec->key[6] >> 16) & 0xFFFF) << 0);\n+\n+    packedRecVal[14] = (packedRecVal[14] & 0x0000) | (((rec->key[7] >> 0) & 0xFFFF) << 0);\n+    packedRecVal[15] = (packedRecVal[15] & 0x0000) | (((rec->key[7] >> 16) & 0xFFFF) << 0);\n+\n+    SetRawSECEgressRecordVal(hw, packedRecVal, 8, 2, ROWOFFSET_EGRESSSAKEYRECORD + tableIndex);\n+    SetRawSECEgressRecordVal(hw, packedRecVal + 8, 8, 2, ROWOFFSET_EGRESSSAKEYRECORD + tableIndex - 32);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetEgressSAKeyRecord(struct aq_hw_s *hw, AQ_API_SEC_EgressSAKeyRecord* rec, uint16_t tableIndex)\n+{\n+    uint16_t packedRecVal[16];\n+\n+    if (tableIndex >= NUMROWS_EGRESSSAKEYRECORD)\n+        return -EINVAL;\n+\n+    memset(rec, 0, sizeof(AQ_API_SEC_EgressSAKeyRecord));\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 8, 2, ROWOFFSET_EGRESSSAKEYRECORD + tableIndex);\n+    GetRawSECEgressRecordVal(hw, packedRecVal + 8, 8, 2, ROWOFFSET_EGRESSSAKEYRECORD + tableIndex - 32);\n+\n+    rec->key[0] = (rec->key[0] & 0xFFFF0000) | (((packedRecVal[0] >> 0) & 0xFFFF) << 0);\n+    rec->key[0] = (rec->key[0] & 0x0000FFFF) | (((packedRecVal[1] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[1] = (rec->key[1] & 0xFFFF0000) | (((packedRecVal[2] >> 0) & 0xFFFF) << 0);\n+    rec->key[1] = (rec->key[1] & 0x0000FFFF) | (((packedRecVal[3] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[2] = (rec->key[2] & 0xFFFF0000) | (((packedRecVal[4] >> 0) & 0xFFFF) << 0);\n+    rec->key[2] = (rec->key[2] & 0x0000FFFF) | (((packedRecVal[5] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[3] = (rec->key[3] & 0xFFFF0000) | (((packedRecVal[6] >> 0) & 0xFFFF) << 0);\n+    rec->key[3] = (rec->key[3] & 0x0000FFFF) | (((packedRecVal[7] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[4] = (rec->key[4] & 0xFFFF0000) | (((packedRecVal[8] >> 0) & 0xFFFF) << 0);\n+    rec->key[4] = (rec->key[4] & 0x0000FFFF) | (((packedRecVal[9] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[5] = (rec->key[5] & 0xFFFF0000) | (((packedRecVal[10] >> 0) & 0xFFFF) << 0);\n+    rec->key[5] = (rec->key[5] & 0x0000FFFF) | (((packedRecVal[11] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[6] = (rec->key[6] & 0xFFFF0000) | (((packedRecVal[12] >> 0) & 0xFFFF) << 0);\n+    rec->key[6] = (rec->key[6] & 0x0000FFFF) | (((packedRecVal[13] >> 0) & 0xFFFF) << 16);\n+\n+    rec->key[7] = (rec->key[7] & 0xFFFF0000) | (((packedRecVal[14] >> 0) & 0xFFFF) << 0);\n+    rec->key[7] = (rec->key[7] & 0x0000FFFF) | (((packedRecVal[15] >> 0) & 0xFFFF) << 16);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetEgressSCCounters(struct aq_hw_s *hw, AQ_API_SEC_EgressSCCounters* counters, uint16_t SCIndex)\n+{\n+    uint16_t packedRecVal[4];\n+\n+    if (SCIndex >= NUMROWS_EGRESSSCRECORD)\n+        return -EINVAL;\n+\n+    memset(counters, 0, sizeof(AQ_API_SEC_EgressSCCounters));\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, SCIndex * 8 + 4);\n+    counters->sc_protected_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->sc_protected_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, SCIndex * 8 + 5);\n+    counters->sc_encrypted_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->sc_encrypted_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, SCIndex * 8 + 6);\n+    counters->sc_protected_octets[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->sc_protected_octets[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, SCIndex * 8 + 7);\n+    counters->sc_encrypted_octets[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->sc_encrypted_octets[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetEgressSACounters(struct aq_hw_s *hw, AQ_API_SEC_EgressSACounters* counters, uint16_t SAIndex)\n+{\n+    uint16_t packedRecVal[4];\n+\n+    if (SAIndex >= NUMROWS_EGRESSSARECORD)\n+        return -EINVAL;\n+\n+    memset(counters, 0, sizeof(AQ_API_SEC_EgressSACounters));\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, SAIndex * 8 + 0);\n+    counters->sa_hit_drop_redirect[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->sa_hit_drop_redirect[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, SAIndex * 8 + 1);\n+    counters->sa_protected2_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->sa_protected2_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, SAIndex * 8 + 2);\n+    counters->sa_protected_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->sa_protected_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, SAIndex * 8 + 3);\n+    counters->sa_encrypted_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->sa_encrypted_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetEgressCommonCounters(struct aq_hw_s *hw, AQ_API_SEC_EgressCommonCounters* counters)\n+{\n+    uint16_t packedRecVal[4];\n+\n+    memset(counters, 0, sizeof(AQ_API_SEC_EgressCommonCounters));\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, 256 + 0);\n+    counters->ctl_pkt[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->ctl_pkt[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, 256 + 1);\n+    counters->unknown_sa_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->unknown_sa_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, 256 + 2);\n+    counters->untagged_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->untagged_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, 256 + 3);\n+    counters->too_long[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->too_long[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, 256 + 4);\n+    counters->ecc_error_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->ecc_error_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECEgressRecordVal(hw, packedRecVal, 4, 3, 256 + 5);\n+    counters->unctrl_hit_drop_redir[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->unctrl_hit_drop_redir[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    return 0;\n+}\n+\n+int AQ_API_ClearEgressCounters(struct aq_hw_s *hw)\n+{\n+    struct mssEgressControlRegister_t controlReg;\n+\n+    memset(&controlReg, 0, sizeof(struct mssEgressControlRegister_t));\n+\n+    mdioRead(hw, MMD_GLOBAL, mssEgressControlRegister_ADDR, &controlReg.word_0);\n+    mdioRead(hw, MMD_GLOBAL, mssEgressControlRegister_ADDR + 4, &controlReg.word_1);\n+\n+    controlReg.bits_0.mssEgressClearCounter = 0;\n+\n+    mdioWrite(hw, MMD_GLOBAL, mssEgressControlRegister_ADDR, controlReg.word_0);\n+    mdioWrite(hw, MMD_GLOBAL, mssEgressControlRegister_ADDR + 4, controlReg.word_1);\n+\n+    controlReg.bits_0.mssEgressClearCounter = 1;\n+\n+    mdioWrite(hw, MMD_GLOBAL, mssEgressControlRegister_ADDR, controlReg.word_0);\n+    mdioWrite(hw, MMD_GLOBAL, mssEgressControlRegister_ADDR + 4, controlReg.word_1);\n+\n+    controlReg.bits_0.mssEgressClearCounter = 0;\n+\n+    mdioWrite(hw, MMD_GLOBAL, mssEgressControlRegister_ADDR, controlReg.word_0);\n+    mdioWrite(hw, MMD_GLOBAL, mssEgressControlRegister_ADDR + 4,  controlReg.word_1);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetIngressSACounters(struct aq_hw_s *hw, AQ_API_SEC_IngressSACounters* counters, uint16_t SAIndex)\n+{\n+    uint16_t packedRecVal[4];\n+\n+    if (SAIndex >= NUMROWS_INGRESSSARECORD)\n+        return -EINVAL;\n+\n+    memset(counters, 0, sizeof(AQ_API_SEC_IngressSACounters));\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 0);\n+    counters->untagged_hit_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->untagged_hit_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 1);\n+    counters->ctrl_hit_drop_redir_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->ctrl_hit_drop_redir_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 2);\n+    counters->not_using_sa[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->not_using_sa[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 3);\n+    counters->unused_sa[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->unused_sa[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 4);\n+    counters->not_valid_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->not_valid_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 5);\n+    counters->invalid_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->invalid_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 6);\n+    counters->ok_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->ok_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 7);\n+    counters->late_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->late_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 8);\n+    counters->delayed_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->delayed_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 9);\n+    counters->unchecked_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->unchecked_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 10);\n+    counters->validated_octets[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->validated_octets[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, SAIndex * 12 + 11);\n+    counters->decrypted_octets[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->decrypted_octets[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    return 0;\n+}\n+\n+int AQ_API_GetIngressCommonCounters(struct aq_hw_s *hw, AQ_API_SEC_IngressCommonCounters* counters)\n+{\n+    uint16_t packedRecVal[4];\n+\n+    memset(counters, 0, sizeof(AQ_API_SEC_IngressCommonCounters));\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 0);\n+    counters->ctl_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->ctl_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 1);\n+    counters->tagged_miss_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->tagged_miss_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 2);\n+    counters->untagged_miss_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->untagged_miss_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 3);\n+    counters->notag_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->notag_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 4);\n+    counters->untagged_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->untagged_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 5);\n+    counters->bad_tag_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->bad_tag_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 6);\n+    counters->no_sci_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->no_sci_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 7);\n+    counters->unknown_sci_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->unknown_sci_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 8);\n+    counters->ctrl_prt_pass_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->ctrl_prt_pass_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 9);\n+    counters->unctrl_prt_pass_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->unctrl_prt_pass_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 10);\n+    counters->ctrl_prt_fail_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->ctrl_prt_fail_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 11);\n+    counters->unctrl_prt_fail_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->unctrl_prt_fail_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 12);\n+    counters->too_long_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->too_long_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 13);\n+    counters->igpoc_ctl_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->igpoc_ctl_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 14);\n+    counters->ecc_error_pkts[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->ecc_error_pkts[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    GetRawSECIngressRecordVal(hw, packedRecVal, 4, 6, 385 + 15);\n+    counters->unctrl_hit_drop_redir[0] = packedRecVal[0] | (packedRecVal[1] << 16);\n+    counters->unctrl_hit_drop_redir[1] = packedRecVal[2] | (packedRecVal[3] << 16);\n+\n+    return 0;\n+}\n+\n+int AQ_API_ClearIngressCounters(struct aq_hw_s *hw)\n+{\n+    struct mssIngressControlRegister_t controlReg;\n+\n+    memset(&controlReg, 0, sizeof(struct mssIngressControlRegister_t));\n+\n+    mdioRead(hw, MMD_GLOBAL, mssIngressControlRegister_ADDR, &controlReg.word_0);\n+    mdioRead(hw, MMD_GLOBAL, mssIngressControlRegister_ADDR +4, &controlReg.word_1);\n+\n+    controlReg.bits_0.mssIngressClearCount = 0;\n+\n+    mdioWrite(hw, MMD_GLOBAL, mssIngressControlRegister_ADDR, controlReg.word_0);\n+    mdioWrite(hw, MMD_GLOBAL, mssIngressControlRegister_ADDR + 4, controlReg.word_1);\n+\n+    controlReg.bits_0.mssIngressClearCount = 1;\n+\n+    mdioWrite(hw, MMD_GLOBAL, mssIngressControlRegister_ADDR, controlReg.word_0);\n+    mdioWrite(hw, MMD_GLOBAL, mssIngressControlRegister_ADDR + 4, controlReg.word_1);\n+\n+    controlReg.bits_0.mssIngressClearCount = 0;\n+\n+    mdioWrite(hw, MMD_GLOBAL, mssIngressControlRegister_ADDR, controlReg.word_0);\n+    mdioWrite(hw, MMD_GLOBAL, mssIngressControlRegister_ADDR + 4, controlReg.word_1);\n+\n+    return 0;\n+}\n+\n+\ndiff --git a/drivers/net/atlantic/macsec/macsec_api.h b/drivers/net/atlantic/macsec/macsec_api.h\nnew file mode 100644\nindex 0000000..653c29c\n--- /dev/null\n+++ b/drivers/net/atlantic/macsec/macsec_api.h\n@@ -0,0 +1,111 @@\n+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */\n+/* Copyright (C) 2014-2019 aQuantia Corporation. */\n+\n+#ifndef __MACSEC_API_H__\n+#define __MACSEC_API_H__\n+\n+#include \"../atl_types.h\"\n+#include \"macsec_struct.h\"\n+\n+\n+#define NUMROWS_INGRESSPRECTLFRECORD 24\n+#define ROWOFFSET_INGRESSPRECTLFRECORD 0\n+\n+#define NUMROWS_INGRESSPRECLASSRECORD 48\n+#define ROWOFFSET_INGRESSPRECLASSRECORD 0\n+\n+#define NUMROWS_INGRESSPOSTCLASSRECORD 48\n+#define ROWOFFSET_INGRESSPOSTCLASSRECORD 0\n+\n+#define NUMROWS_INGRESSSCRECORD 32\n+#define ROWOFFSET_INGRESSSCRECORD 0\n+ \n+#define NUMROWS_INGRESSSARECORD 32\n+#define ROWOFFSET_INGRESSSARECORD 32\n+\n+#define NUMROWS_INGRESSSAKEYRECORD 32\n+#define ROWOFFSET_INGRESSSAKEYRECORD 0\n+\n+#define NUMROWS_INGRESSPOSTCTLFRECORD 24\n+#define ROWOFFSET_INGRESSPOSTCTLFRECORD 0\n+\n+#define NUMROWS_EGRESSCTLFRECORD 24\n+#define ROWOFFSET_EGRESSCTLFRECORD 0\n+\n+#define NUMROWS_EGRESSCLASSRECORD 48\n+#define ROWOFFSET_EGRESSCLASSRECORD 0\n+\n+#define NUMROWS_EGRESSSCRECORD 32\n+#define ROWOFFSET_EGRESSSCRECORD 0\n+\n+#define NUMROWS_EGRESSSARECORD 32\n+#define ROWOFFSET_EGRESSSARECORD 32\n+\n+#define NUMROWS_EGRESSSAKEYRECORD 32\n+#define ROWOFFSET_EGRESSSAKEYRECORD 96\n+\n+int AQ_API_GetEgressCTLFRecord(struct aq_hw_s *hw, AQ_API_SEC_EgressCTLFRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_SetEgressCTLFRecord(struct aq_hw_s *hw, const AQ_API_SEC_EgressCTLFRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetEgressClassRecord(struct aq_hw_s *hw, AQ_API_SEC_EgressClassRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_SetEgressClassRecord(struct aq_hw_s *hw, const AQ_API_SEC_EgressClassRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetEgressSCRecord(struct aq_hw_s *hw, AQ_API_SEC_EgressSCRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_SetEgressSCRecord(struct aq_hw_s *hw, const AQ_API_SEC_EgressSCRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetEgressSARecord(struct aq_hw_s *hw, AQ_API_SEC_EgressSARecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_SetEgressSARecord(struct aq_hw_s *hw, const AQ_API_SEC_EgressSARecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetEgressSAKeyRecord(struct aq_hw_s *hw, AQ_API_SEC_EgressSAKeyRecord* rec, uint16_t tableIndex); \n+\n+int AQ_API_SetEgressSAKeyRecord(struct aq_hw_s *hw, const AQ_API_SEC_EgressSAKeyRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetIngressPreCTLFRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressPreCTLFRecord* rec, uint16_t);\n+\n+int AQ_API_SetIngressPreCTLFRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressPreCTLFRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetIngressPreClassRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressPreClassRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_SetIngressPreClassRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressPreClassRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetIngressSCRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressSCRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_SetIngressSCRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressSCRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetIngressSARecord(struct aq_hw_s *hw, AQ_API_SEC_IngressSARecord* rec, uint16_t);\n+\n+int AQ_API_SetIngressSARecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressSARecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetIngressSAKeyRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressSAKeyRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_SetIngressSAKeyRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressSAKeyRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetIngressPostClassRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressPostClassRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_SetIngressPostClassRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressPostClassRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetIngressPostCTLFRecord(struct aq_hw_s *hw, AQ_API_SEC_IngressPostCTLFRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_SetIngressPostCTLFRecord(struct aq_hw_s *hw, const AQ_API_SEC_IngressPostCTLFRecord* rec, uint16_t tableIndex);\n+\n+int AQ_API_GetEgressSCCounters(struct aq_hw_s *hw, AQ_API_SEC_EgressSCCounters* counters, uint16_t SCIndex);\n+\n+int AQ_API_GetEgressSACounters(struct aq_hw_s *hw, AQ_API_SEC_EgressSACounters* counters, uint16_t SAindex);\n+\n+int AQ_API_GetEgressCommonCounters(struct aq_hw_s *hw, AQ_API_SEC_EgressCommonCounters* counters);\n+\n+int AQ_API_ClearEgressCounters(struct aq_hw_s *hw);\n+\n+int AQ_API_GetIngressSACounters(struct aq_hw_s *hw, AQ_API_SEC_IngressSACounters* counters, uint16_t SAindex);\n+\n+int AQ_API_GetIngressCommonCounters(struct aq_hw_s *hw, AQ_API_SEC_IngressCommonCounters* counters);\n+int AQ_API_ClearIngressCounters(struct aq_hw_s *hw);\n+\n+\n+\n+\n+#endif /* __MACSEC_API_H__ */\ndiff --git a/drivers/net/atlantic/macsec/macsec_struct.h b/drivers/net/atlantic/macsec/macsec_struct.h\nnew file mode 100644\nindex 0000000..b408fdf\n--- /dev/null\n+++ b/drivers/net/atlantic/macsec/macsec_struct.h\n@@ -0,0 +1,269 @@\n+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */\n+/* Copyright (C) 2014-2019 aQuantia Corporation. */\n+\n+#ifndef _MACSEC_STRUCT_H_\n+#define _MACSEC_STRUCT_H_\n+\n+typedef struct\n+{\n+\tuint32_t sa_da[2];\n+\tuint32_t eth_type;\n+\tuint32_t match_mask;\n+\tuint32_t match_type;\n+\tuint32_t action;\n+} AQ_API_SEC_EgressCTLFRecord;\n+\n+typedef struct\n+{\n+\tuint32_t vlan_id;\n+\tuint32_t vlan_up;\n+\tuint32_t vlan_valid;\n+\tuint32_t byte3;\n+\tuint32_t byte2;\n+\tuint32_t byte1;\n+\tuint32_t byte0;\n+\tuint32_t tci;\n+\tuint32_t sci[2];\n+\tuint32_t eth_type;\n+\tuint32_t snap[2];\n+\tuint32_t llc;\n+\tuint32_t mac_sa[2];\n+\tuint32_t mac_da[2];\n+\tuint32_t pn;\n+\tuint32_t byte3_location;\n+\tuint32_t byte3_mask;\n+\tuint32_t byte2_location;\n+\tuint32_t byte2_mask;\n+\tuint32_t byte1_location;\n+\tuint32_t byte1_mask;\n+\tuint32_t byte0_location;\n+\tuint32_t byte0_mask;\n+\tuint32_t vlan_id_mask;\n+\tuint32_t vlan_up_mask;\n+\tuint32_t vlan_valid_mask;\n+\tuint32_t tci_mask;\n+\tuint32_t sci_mask;\n+\tuint32_t eth_type_mask;\n+\tuint32_t snap_mask;\n+\tuint32_t llc_mask;\n+\tuint32_t sa_mask;\n+\tuint32_t da_mask;\n+\tuint32_t pn_mask;\n+\tuint32_t eight02dot2;\n+\tuint32_t tci_sc;\n+\tuint32_t tci_87543;\n+\tuint32_t exp_sectag_en;\n+\tuint32_t sc_idx;\n+\tuint32_t sc_sa;\n+\tuint32_t debug;\n+\tuint32_t action;\n+\tuint32_t valid;\n+} AQ_API_SEC_EgressClassRecord;\n+\n+typedef struct\n+{\n+\tuint32_t start_time;\n+\tuint32_t stop_time;\n+\tuint32_t curr_an;\n+\tuint32_t an_roll;\n+\tuint32_t tci;\n+\tuint32_t enc_off;\n+\tuint32_t protect;\n+\tuint32_t recv;\n+\tuint32_t fresh;\n+\tuint32_t sak_len;\n+\tuint32_t valid;\n+} AQ_API_SEC_EgressSCRecord;\n+\n+typedef struct\n+{\n+\tuint32_t start_time;\n+\tuint32_t stop_time;\n+\tuint32_t next_pn;\n+\tuint32_t sat_pn;\n+\tuint32_t fresh;\n+\tuint32_t valid;\n+} AQ_API_SEC_EgressSARecord;\n+\n+typedef struct\n+{\n+\tuint32_t key[8];\n+} AQ_API_SEC_EgressSAKeyRecord;\n+\n+typedef struct\n+{\n+\tuint32_t sa_da[2];\n+\tuint32_t eth_type;\n+\tuint32_t match_mask;\n+\tuint32_t match_type;\n+\tuint32_t action;\n+} AQ_API_SEC_IngressPreCTLFRecord;\n+\n+typedef struct\n+{\n+\tuint32_t sci[2];\n+\tuint32_t tci;\n+\tuint32_t encr_offset;\n+\tuint32_t eth_type;\n+\tuint32_t snap[2];\n+\tuint32_t llc;\n+\tuint32_t mac_sa[2];\n+\tuint32_t mac_da[2];\n+\tuint32_t lpbk_packet;\n+\tuint32_t an_mask;\n+\tuint32_t tci_mask;\n+\tuint32_t sci_mask;\n+\tuint32_t eth_type_mask;\n+\tuint32_t snap_mask;\n+\tuint32_t llc_mask;\n+\tuint32_t _802_2_encapsulate;\n+\tuint32_t sa_mask;\n+\tuint32_t da_mask;\n+\tuint32_t lpbk_mask;\n+\tuint32_t sc_idx;\n+\tuint32_t proc_dest;\n+\tuint32_t action;\n+\tuint32_t ctrl_unctrl;\n+\tuint32_t sci_from_table;\n+\tuint32_t reserved;\n+\tuint32_t valid;\n+} AQ_API_SEC_IngressPreClassRecord;\n+\n+typedef struct\n+{\n+\tuint32_t stop_time;\n+\tuint32_t start_time;\n+\tuint32_t validate_frames;\n+\tuint32_t replay_protect;\n+\tuint32_t anti_replay_window;\n+\tuint32_t receiving;\n+\tuint32_t fresh;\n+\tuint32_t an_rol;\n+\tuint32_t reserved;\n+\tuint32_t valid;\n+} AQ_API_SEC_IngressSCRecord;\n+\n+typedef struct\n+{\n+\tuint32_t stop_time;\n+\tuint32_t start_time;\n+\tuint32_t next_pn;\n+\tuint32_t sat_nextpn;\n+\tuint32_t in_use;\n+\tuint32_t fresh;\n+\tuint32_t reserved;\n+\tuint32_t valid;\n+} AQ_API_SEC_IngressSARecord;\n+\n+typedef struct\n+{\n+\tuint32_t key[8];\n+\tuint32_t key_len;\n+} AQ_API_SEC_IngressSAKeyRecord;\n+\n+typedef struct\n+{\n+\tuint32_t byte0;\n+\tuint32_t byte1;\n+\tuint32_t byte2;\n+\tuint32_t byte3;\n+\tuint32_t eth_type;\n+\tuint32_t eth_type_valid;\n+\tuint32_t vlan_id;\n+\tuint32_t vlan_up;\n+\tuint32_t vlan_valid;\n+\tuint32_t sai;\n+\tuint32_t sai_hit;\n+\tuint32_t eth_type_mask;\n+\tuint32_t byte3_location;\n+\tuint32_t byte3_mask;\n+\tuint32_t byte2_location;\n+\tuint32_t byte2_mask;\n+\tuint32_t byte1_location;\n+\tuint32_t byte1_mask;\n+\tuint32_t byte0_location;\n+\tuint32_t byte0_mask;\n+\tuint32_t eth_type_valid_mask;\n+\tuint32_t vlan_id_mask;\n+\tuint32_t vlan_up_mask;\n+\tuint32_t vlan_valid_mask;\n+\tuint32_t sai_mask;\n+\tuint32_t sai_hit_mask;\n+\tuint32_t firstlevel_actions;\n+\tuint32_t secondlevel_actions;\n+\tuint32_t reserved;\n+\tuint32_t valid;\n+} AQ_API_SEC_IngressPostClassRecord;\n+\n+typedef struct\n+{\n+\tuint32_t sa_da[2];\n+\tuint32_t eth_type;\n+\tuint32_t match_mask;\n+\tuint32_t match_type;\n+\tuint32_t action;\n+} AQ_API_SEC_IngressPostCTLFRecord;\n+\n+typedef struct\n+{\n+\tuint32_t sc_protected_pkts[2];\n+\tuint32_t sc_encrypted_pkts[2];\n+\tuint32_t sc_protected_octets[2];\n+\tuint32_t sc_encrypted_octets[2];\n+} AQ_API_SEC_EgressSCCounters;\n+\n+typedef struct\n+{\n+\tuint32_t sa_hit_drop_redirect[2];\n+\tuint32_t sa_protected2_pkts[2];\n+\tuint32_t sa_protected_pkts[2];\n+\tuint32_t sa_encrypted_pkts[2];\n+} AQ_API_SEC_EgressSACounters;\n+\n+typedef struct\n+{\n+\tuint32_t ctl_pkt[2];\n+\tuint32_t unknown_sa_pkts[2];\n+\tuint32_t untagged_pkts[2];\n+\tuint32_t too_long[2];\n+\tuint32_t ecc_error_pkts[2];\n+\tuint32_t unctrl_hit_drop_redir[2];\n+} AQ_API_SEC_EgressCommonCounters;\n+\n+typedef struct\n+{\n+\tuint32_t untagged_hit_pkts[2];\n+\tuint32_t ctrl_hit_drop_redir_pkts[2];\n+\tuint32_t not_using_sa[2];\n+\tuint32_t unused_sa[2];\n+\tuint32_t not_valid_pkts[2];\n+\tuint32_t invalid_pkts[2];\n+\tuint32_t ok_pkts[2];\n+\tuint32_t late_pkts[2];\n+\tuint32_t delayed_pkts[2];\n+\tuint32_t unchecked_pkts[2];\n+\tuint32_t validated_octets[2];\n+\tuint32_t decrypted_octets[2];\n+} AQ_API_SEC_IngressSACounters;\n+\n+typedef struct\n+{\n+\tuint32_t ctl_pkts[2];\n+\tuint32_t tagged_miss_pkts[2];\n+\tuint32_t untagged_miss_pkts[2];\n+\tuint32_t notag_pkts[2];\n+\tuint32_t untagged_pkts[2];\n+\tuint32_t bad_tag_pkts[2];\n+\tuint32_t no_sci_pkts[2];\n+\tuint32_t unknown_sci_pkts[2];\n+\tuint32_t ctrl_prt_pass_pkts[2];\n+\tuint32_t unctrl_prt_pass_pkts[2];\n+\tuint32_t ctrl_prt_fail_pkts[2];\n+\tuint32_t unctrl_prt_fail_pkts[2];\n+\tuint32_t too_long_pkts[2];\n+\tuint32_t igpoc_ctl_pkts[2];\n+\tuint32_t ecc_error_pkts[2];\n+\tuint32_t unctrl_hit_drop_redir[2];\n+} AQ_API_SEC_IngressCommonCounters;\n+\n+#endif\ndiff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build\nindex d1c66f4..139cdec 100644\n--- a/drivers/net/atlantic/meson.build\n+++ b/drivers/net/atlantic/meson.build\n@@ -13,4 +13,5 @@ sources = files(\n \t'hw_atl/hw_atl_utils.c',\n \t'rte_pmd_atlantic.c',\n \t'macsec/mdio.c',\n+\t'macsec/macsec_api.c',\n )\n",
    "prefixes": [
        "RFC",
        "v2",
        "4/7"
    ]
}