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{
    "id": 60855,
    "url": "https://patches.dpdk.org/api/patches/60855/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20191010063234.32568-7-g.singh@nxp.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20191010063234.32568-7-g.singh@nxp.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20191010063234.32568-7-g.singh@nxp.com",
    "date": "2019-10-10T06:32:26",
    "name": "[v4,06/14] net/pfe: add MAC and host interface initialisation",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "40879ffd5f0fd722c8afbb3948b76a5b4f96b171",
    "submitter": {
        "id": 1068,
        "url": "https://patches.dpdk.org/api/people/1068/?format=api",
        "name": "Gagandeep Singh",
        "email": "g.singh@nxp.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20191010063234.32568-7-g.singh@nxp.com/mbox/",
    "series": [
        {
            "id": 6777,
            "url": "https://patches.dpdk.org/api/series/6777/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6777",
            "date": "2019-10-10T06:32:20",
            "name": "introduces pfe network PMD",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/6777/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/60855/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/60855/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8BB741E946;\n\tThu, 10 Oct 2019 08:48:29 +0200 (CEST)",
            "from inva021.nxp.com (inva021.nxp.com [92.121.34.21])\n\tby dpdk.org (Postfix) with ESMTP id 6DDAE1E91D\n\tfor <dev@dpdk.org>; Thu, 10 Oct 2019 08:48:16 +0200 (CEST)",
            "from inva021.nxp.com (localhost [127.0.0.1])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 4EE8B200445;\n\tThu, 10 Oct 2019 08:48:16 +0200 (CEST)",
            "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id DAC4C200440;\n\tThu, 10 Oct 2019 08:48:12 +0200 (CEST)",
            "from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 6F1D2402CB;\n\tThu, 10 Oct 2019 14:48:08 +0800 (SGT)"
        ],
        "From": "Gagandeep Singh <g.singh@nxp.com>",
        "To": "dev@dpdk.org,\n\tferruh.yigit@intel.com",
        "Cc": "thomas@monjalon.net, Gagandeep Singh <g.singh@nxp.com>,\n\tAkhil Goyal <akhil.goyal@nxp.com>",
        "Date": "Thu, 10 Oct 2019 12:02:26 +0530",
        "Message-Id": "<20191010063234.32568-7-g.singh@nxp.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20191010063234.32568-1-g.singh@nxp.com>",
        "References": "<20191001110209.6047-1-g.singh@nxp.com>\n\t<20191010063234.32568-1-g.singh@nxp.com>",
        "X-Virus-Scanned": "ClamAV using ClamSMTP",
        "Subject": "[dpdk-dev] [PATCH v4 06/14] net/pfe: add MAC and host interface\n\tinitialisation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "HIF or host interface is responsible for transmit\nand receive packets between physical ethernet\ninterfaces and HIF library defined logical interfaces.\n\nThis patch initialise that host interface and MAC.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\nSigned-off-by: Akhil Goyal <akhil.goyal@nxp.com>\nAcked-by: Nipun Gupta <nipun.gupta@nxp.com>\n---\n drivers/net/pfe/Makefile      |  10 +\n drivers/net/pfe/base/pfe.h    |  83 +++++\n drivers/net/pfe/meson.build   |  12 +-\n drivers/net/pfe/pfe_eth.h     |   2 +\n drivers/net/pfe/pfe_ethdev.c  | 153 ++++++++-\n drivers/net/pfe/pfe_hal.c     | 629 ++++++++++++++++++++++++++++++++++\n drivers/net/pfe/pfe_hif.c     | 256 ++++++++++++++\n drivers/net/pfe/pfe_hif.h     | 106 ++++++\n drivers/net/pfe/pfe_hif_lib.c |  20 ++\n drivers/net/pfe/pfe_hif_lib.h | 162 +++++++++\n drivers/net/pfe/pfe_mod.h     |   5 +\n 11 files changed, 1436 insertions(+), 2 deletions(-)\n create mode 100644 drivers/net/pfe/pfe_hal.c\n create mode 100644 drivers/net/pfe/pfe_hif.c\n create mode 100644 drivers/net/pfe/pfe_hif.h\n create mode 100644 drivers/net/pfe/pfe_hif_lib.c\n create mode 100644 drivers/net/pfe/pfe_hif_lib.h",
    "diff": "diff --git a/drivers/net/pfe/Makefile b/drivers/net/pfe/Makefile\nindex ea9da0e30..5c317e10b 100644\n--- a/drivers/net/pfe/Makefile\n+++ b/drivers/net/pfe/Makefile\n@@ -10,13 +10,23 @@ include $(RTE_SDK)/mk/rte.vars.mk\n LIB = librte_pmd_pfe.a\n \n CFLAGS += -O3 $(WERROR_FLAGS)\n+CFLAGS += -Wno-pointer-arith\n+CFLAGS += -I$(RTE_SDK)/drivers/net/pfe/base/\n CFLAGS += -I$(RTE_SDK)/drivers/common/dpaax\n \n EXPORT_MAP := rte_pmd_pfe_version.map\n LIBABIVER := 1\n \n+# Driver uses below experimental APIs\n+# rte_mem_iova2virt\n+# rte_mem_virt2memseg\n+CFLAGS += -DALLOW_EXPERIMENTAL_API\n+\n # Interfaces with DPDK\n SRCS-$(CONFIG_RTE_LIBRTE_PFE_PMD) += pfe_ethdev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PFE_PMD) += pfe_hal.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PFE_PMD) += pfe_hif_lib.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PFE_PMD) += pfe_hif.c\n \n LDLIBS += -lrte_bus_vdev\n LDLIBS += -lrte_bus_dpaa\ndiff --git a/drivers/net/pfe/base/pfe.h b/drivers/net/pfe/base/pfe.h\nindex 15b17802c..92e81914a 100644\n--- a/drivers/net/pfe/base/pfe.h\n+++ b/drivers/net/pfe/base/pfe.h\n@@ -311,6 +311,70 @@ void bmu_set_config(void *base, struct BMU_CFG *cfg);\n enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL};\n #endif\n \n+void gemac_init(void *base, void *config);\n+void gemac_disable_rx_checksum_offload(void *base);\n+void gemac_enable_rx_checksum_offload(void *base);\n+void gemac_set_mdc_div(void *base, int mdc_div);\n+void gemac_set_speed(void *base, enum mac_speed gem_speed);\n+void gemac_set_duplex(void *base, int duplex);\n+void gemac_set_mode(void *base, int mode);\n+void gemac_enable(void *base);\n+void gemac_tx_disable(void *base);\n+void gemac_tx_enable(void *base);\n+void gemac_disable(void *base);\n+void gemac_reset(void *base);\n+void gemac_set_address(void *base, struct spec_addr *addr);\n+struct spec_addr gemac_get_address(void *base);\n+void gemac_set_loop(void *base, enum mac_loop gem_loop);\n+void gemac_set_laddr1(void *base, struct pfe_mac_addr *address);\n+void gemac_set_laddr2(void *base, struct pfe_mac_addr *address);\n+void gemac_set_laddr3(void *base, struct pfe_mac_addr *address);\n+void gemac_set_laddr4(void *base, struct pfe_mac_addr *address);\n+void gemac_set_laddrN(void *base, struct pfe_mac_addr *address,\n+\t\t      unsigned int entry_index);\n+void gemac_clear_laddr1(void *base);\n+void gemac_clear_laddr2(void *base);\n+void gemac_clear_laddr3(void *base);\n+void gemac_clear_laddr4(void *base);\n+void gemac_clear_laddrN(void *base, unsigned int entry_index);\n+struct pfe_mac_addr gemac_get_hash(void *base);\n+void gemac_set_hash(void *base, struct pfe_mac_addr *hash);\n+struct pfe_mac_addr gem_get_laddr1(void *base);\n+struct pfe_mac_addr gem_get_laddr2(void *base);\n+struct pfe_mac_addr gem_get_laddr3(void *base);\n+struct pfe_mac_addr gem_get_laddr4(void *base);\n+struct pfe_mac_addr gem_get_laddrN(void *base, unsigned int entry_index);\n+void gemac_set_config(void *base, struct gemac_cfg *cfg);\n+void gemac_allow_broadcast(void *base);\n+void gemac_no_broadcast(void *base);\n+void gemac_enable_1536_rx(void *base);\n+void gemac_disable_1536_rx(void *base);\n+int gemac_set_rx(void *base, int mtu);\n+void gemac_enable_rx_jmb(void *base);\n+void gemac_disable_rx_jmb(void *base);\n+void gemac_enable_stacked_vlan(void *base);\n+void gemac_disable_stacked_vlan(void *base);\n+void gemac_enable_pause_rx(void *base);\n+void gemac_disable_pause_rx(void *base);\n+void gemac_enable_pause_tx(void *base);\n+void gemac_disable_pause_tx(void *base);\n+void gemac_enable_copy_all(void *base);\n+void gemac_disable_copy_all(void *base);\n+void gemac_set_bus_width(void *base, int width);\n+void gemac_set_wol(void *base, u32 wol_conf);\n+\n+void gpi_init(void *base, struct gpi_cfg *cfg);\n+void gpi_reset(void *base);\n+void gpi_enable(void *base);\n+void gpi_disable(void *base);\n+void gpi_set_config(void *base, struct gpi_cfg *cfg);\n+\n+void hif_init(void);\n+void hif_tx_enable(void);\n+void hif_tx_disable(void);\n+void hif_rx_enable(void);\n+void hif_rx_disable(void);\n+\n /* Get Chip Revision level\n  *\n  */\n@@ -336,4 +400,23 @@ static inline void hif_tx_dma_start(void)\n \twritel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL);\n }\n \n+\n+static inline void *pfe_mem_ptov(phys_addr_t paddr)\n+{\n+\treturn rte_mem_iova2virt(paddr);\n+}\n+\n+static phys_addr_t pfe_mem_vtop(uint64_t vaddr) __attribute__((unused));\n+\n+static inline phys_addr_t pfe_mem_vtop(uint64_t vaddr)\n+{\n+\tconst struct rte_memseg *memseg;\n+\n+\tmemseg = rte_mem_virt2memseg((void *)(uintptr_t)vaddr, NULL);\n+\tif (memseg)\n+\t\treturn memseg->phys_addr + RTE_PTR_DIFF(vaddr, memseg->addr);\n+\n+\treturn (size_t)NULL;\n+}\n+\n #endif /* _PFE_H_ */\ndiff --git a/drivers/net/pfe/meson.build b/drivers/net/pfe/meson.build\nindex fa5dfad69..bb2597668 100644\n--- a/drivers/net/pfe/meson.build\n+++ b/drivers/net/pfe/meson.build\n@@ -6,4 +6,14 @@ if host_machine.system() != 'linux'\n endif\n deps += ['bus_dpaa']\n \n-sources = files('pfe_ethdev.c')\n+sources = files('pfe_ethdev.c',\n+\t\t'pfe_hal.c',\n+\t\t'pfe_hif_lib.c',\n+\t\t'pfe_hif.c')\n+\n+# Driver uses below experimental APIs\n+# rte_mem_iova2virt\n+# rte_mem_virt2memseg\n+allow_experimental_apis = true\n+\n+includes += include_directories('base')\ndiff --git a/drivers/net/pfe/pfe_eth.h b/drivers/net/pfe/pfe_eth.h\nindex 5811b54eb..ab739f03c 100644\n--- a/drivers/net/pfe/pfe_eth.h\n+++ b/drivers/net/pfe/pfe_eth.h\n@@ -17,6 +17,8 @@ extern unsigned int pfe_svr;\n #define SVR_LS1012A_REV2\t0x87040020\n #define SVR_LS1012A_REV1\t0x87040010\n \n+#define PFE_ETH_OVERHEAD        (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN)\n+#define MAX_MTU_ON_REV1         1878\n struct ls1012a_eth_platform_data {\n \t/* device specific information */\n \tu32 device_flags;\ndiff --git a/drivers/net/pfe/pfe_ethdev.c b/drivers/net/pfe/pfe_ethdev.c\nindex 26a1fed10..ac1e608c8 100644\n--- a/drivers/net/pfe/pfe_ethdev.c\n+++ b/drivers/net/pfe/pfe_ethdev.c\n@@ -23,9 +23,32 @@ static struct pfe *g_pfe;\n  * information from HW.\n  */\n unsigned int pfe_svr = SVR_LS1012A_REV1;\n+static void *cbus_emac_base[3];\n+static void *cbus_gpi_base[3];\n \n int pfe_logtype_pmd;\n \n+/* pfe_gemac_init\n+ */\n+static int\n+pfe_gemac_init(struct pfe_eth_priv_s *priv)\n+{\n+\tstruct gemac_cfg cfg;\n+\n+\tcfg.speed = SPEED_1000M;\n+\tcfg.duplex = DUPLEX_FULL;\n+\n+\tgemac_set_config(priv->EMAC_baseaddr, &cfg);\n+\tgemac_allow_broadcast(priv->EMAC_baseaddr);\n+\tgemac_enable_1536_rx(priv->EMAC_baseaddr);\n+\tgemac_enable_stacked_vlan(priv->EMAC_baseaddr);\n+\tgemac_enable_pause_rx(priv->EMAC_baseaddr);\n+\tgemac_set_bus_width(priv->EMAC_baseaddr, 64);\n+\tgemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);\n+\n+\treturn 0;\n+}\n+\n static void\n pfe_soc_version_get(void)\n {\n@@ -100,18 +123,44 @@ pfe_eth_init(struct rte_vdev_device *vdev, struct pfe *pfe, int id)\n {\n \tstruct rte_eth_dev *eth_dev = NULL;\n \tstruct pfe_eth_priv_s *priv = NULL;\n+\tstruct ls1012a_eth_platform_data *einfo;\n+\tstruct ls1012a_pfe_platform_data *pfe_info;\n \tint err;\n \n \teth_dev = rte_eth_vdev_allocate(vdev, sizeof(*priv));\n \tif (eth_dev == NULL)\n \t\treturn -ENOMEM;\n \n+\t/* Extract pltform data */\n+\tpfe_info = (struct ls1012a_pfe_platform_data *)&pfe->platform_data;\n+\tif (!pfe_info) {\n+\t\tPFE_PMD_ERR(\"pfe missing additional platform data\");\n+\t\terr = -ENODEV;\n+\t\tgoto err0;\n+\t}\n+\n+\teinfo = (struct ls1012a_eth_platform_data *)pfe_info->ls1012a_eth_pdata;\n+\n+\t/* einfo never be NULL, but no harm in having this check */\n+\tif (!einfo) {\n+\t\tPFE_PMD_ERR(\"pfe missing additional gemacs platform data\");\n+\t\terr = -ENODEV;\n+\t\tgoto err0;\n+\t}\n+\n \tpriv = eth_dev->data->dev_private;\n \tpriv->ndev = eth_dev;\n+\tpriv->id = einfo[id].gem_id;\n \tpriv->pfe = pfe;\n \n \tpfe->eth.eth_priv[id] = priv;\n \n+\t/* Set the info in the priv to the current info */\n+\tpriv->einfo = &einfo[id];\n+\tpriv->EMAC_baseaddr = cbus_emac_base[id];\n+\tpriv->PHY_baseaddr = cbus_emac_base[id];\n+\tpriv->GPI_baseaddr = cbus_gpi_base[id];\n+\n #define HIF_GEMAC_TMUQ_BASE\t6\n \tpriv->low_tmu_q = HIF_GEMAC_TMUQ_BASE + (id * 2);\n \tpriv->high_tmu_q = priv->low_tmu_q + 1;\n@@ -129,6 +178,7 @@ pfe_eth_init(struct rte_vdev_device *vdev, struct pfe *pfe, int id)\n \t}\n \n \teth_dev->data->mtu = 1500;\n+\tpfe_gemac_init(priv);\n \n \teth_dev->data->nb_rx_queues = 1;\n \teth_dev->data->nb_tx_queues = 1;\n@@ -146,6 +196,58 @@ pfe_eth_init(struct rte_vdev_device *vdev, struct pfe *pfe, int id)\n \treturn err;\n }\n \n+static int\n+pfe_get_gemac_if_proprties(struct pfe *pfe,\n+\t\t__rte_unused const struct device_node *parent,\n+\t\tunsigned int port, unsigned int if_cnt,\n+\t\tstruct ls1012a_pfe_platform_data *pdata)\n+{\n+\tconst struct device_node *gem = NULL;\n+\tsize_t size;\n+\tunsigned int ii = 0, phy_id = 0;\n+\tconst u32 *addr;\n+\tconst void *mac_addr;\n+\n+\tfor (ii = 0; ii < if_cnt; ii++) {\n+\t\tgem = of_get_next_child(parent, gem);\n+\t\tif (!gem)\n+\t\t\tgoto err;\n+\t\taddr = of_get_property(gem, \"reg\", &size);\n+\t\tif (addr && (rte_be_to_cpu_32((unsigned int)*addr) == port))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (ii >= if_cnt) {\n+\t\tPFE_PMD_ERR(\"Failed to find interface = %d\", if_cnt);\n+\t\tgoto err;\n+\t}\n+\n+\tpdata->ls1012a_eth_pdata[port].gem_id = port;\n+\n+\tmac_addr = of_get_mac_address(gem);\n+\n+\tif (mac_addr) {\n+\t\tmemcpy(pdata->ls1012a_eth_pdata[port].mac_addr, mac_addr,\n+\t\t       ETH_ALEN);\n+\t}\n+\n+\taddr = of_get_property(gem, \"fsl,mdio-mux-val\", &size);\n+\tif (!addr) {\n+\t\tPFE_PMD_ERR(\"Invalid mdio-mux-val....\");\n+\t} else {\n+\t\tphy_id = rte_be_to_cpu_32((unsigned int)*addr);\n+\t\tpdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id;\n+\t}\n+\tif (pdata->ls1012a_eth_pdata[port].phy_id < 32)\n+\t\tpfe->mdio_muxval[pdata->ls1012a_eth_pdata[port].phy_id] =\n+\t\t\t pdata->ls1012a_eth_pdata[port].mdio_muxval;\n+\n+\treturn 0;\n+\n+err:\n+\treturn -1;\n+}\n+\n /* Parse integer from integer argument */\n static int\n parse_integer_arg(const char *key __rte_unused,\n@@ -204,7 +306,7 @@ pmd_pfe_probe(struct rte_vdev_device *vdev)\n \tconst uint32_t *addr;\n \tuint64_t cbus_addr, ddr_size, cbus_size;\n \tint rc = -1, fd = -1, gem_id;\n-\tunsigned int interface_count = 0;\n+\tunsigned int ii, interface_count = 0;\n \tsize_t size = 0;\n \tstruct pfe_vdev_init_params init_params = {\n \t\t.gem_id = -1\n@@ -268,6 +370,7 @@ pmd_pfe_probe(struct rte_vdev_device *vdev)\n \t\tgoto err;\n \t}\n \n+\tg_pfe->ddr_baseaddr = pfe_mem_ptov(g_pfe->ddr_phys_baseaddr);\n \tg_pfe->ddr_size = ddr_size;\n \tg_pfe->cbus_size = cbus_size;\n \n@@ -299,6 +402,42 @@ pmd_pfe_probe(struct rte_vdev_device *vdev)\n \tPFE_PMD_INFO(\"num interfaces = %d \", interface_count);\n \n \tg_pfe->max_intf  = interface_count;\n+\tg_pfe->platform_data.ls1012a_mdio_pdata[0].phy_mask = 0xffffffff;\n+\n+\tfor (ii = 0; ii < interface_count; ii++) {\n+\t\tpfe_get_gemac_if_proprties(g_pfe, np, ii, interface_count,\n+\t\t\t\t\t   &g_pfe->platform_data);\n+\t}\n+\n+\tpfe_lib_init(g_pfe->cbus_baseaddr, g_pfe->ddr_baseaddr,\n+\t\t     g_pfe->ddr_phys_baseaddr, g_pfe->ddr_size);\n+\n+\tPFE_PMD_INFO(\"CLASS version: %x\", readl(CLASS_VERSION));\n+\tPFE_PMD_INFO(\"TMU version: %x\", readl(TMU_VERSION));\n+\n+\tPFE_PMD_INFO(\"BMU1 version: %x\", readl(BMU1_BASE_ADDR + BMU_VERSION));\n+\tPFE_PMD_INFO(\"BMU2 version: %x\", readl(BMU2_BASE_ADDR + BMU_VERSION));\n+\n+\tPFE_PMD_INFO(\"EGPI1 version: %x\", readl(EGPI1_BASE_ADDR + GPI_VERSION));\n+\tPFE_PMD_INFO(\"EGPI2 version: %x\", readl(EGPI2_BASE_ADDR + GPI_VERSION));\n+\tPFE_PMD_INFO(\"HGPI version: %x\", readl(HGPI_BASE_ADDR + GPI_VERSION));\n+\n+\tPFE_PMD_INFO(\"HIF version: %x\", readl(HIF_VERSION));\n+\tPFE_PMD_INFO(\"HIF NOPCY version: %x\", readl(HIF_NOCPY_VERSION));\n+\n+\tcbus_emac_base[0] = EMAC1_BASE_ADDR;\n+\tcbus_emac_base[1] = EMAC2_BASE_ADDR;\n+\n+\tcbus_gpi_base[0] = EGPI1_BASE_ADDR;\n+\tcbus_gpi_base[1] = EGPI2_BASE_ADDR;\n+\n+\trc = pfe_hif_lib_init(g_pfe);\n+\tif (rc < 0)\n+\t\tgoto err_hif_lib;\n+\n+\trc = pfe_hif_init(g_pfe);\n+\tif (rc < 0)\n+\t\tgoto err_hif;\n \tpfe_soc_version_get();\n eth_init:\n \tif (init_params.gem_id < 0)\n@@ -318,6 +457,12 @@ pmd_pfe_probe(struct rte_vdev_device *vdev)\n \treturn 0;\n \n err_eth:\n+\tpfe_hif_exit(g_pfe);\n+\n+err_hif:\n+\tpfe_hif_lib_exit(g_pfe);\n+\n+err_hif_lib:\n err_prop:\n \tmunmap(g_pfe->cbus_baseaddr, cbus_size);\n err:\n@@ -347,6 +492,12 @@ pmd_pfe_remove(struct rte_vdev_device *vdev)\n \tpfe_eth_exit(eth_dev, g_pfe);\n \tmunmap(g_pfe->cbus_baseaddr, g_pfe->cbus_size);\n \n+\tif (g_pfe->nb_devs == 0) {\n+\t\tpfe_hif_exit(g_pfe);\n+\t\tpfe_hif_lib_exit(g_pfe);\n+\t\trte_free(g_pfe);\n+\t\tg_pfe = NULL;\n+\t}\n \treturn 0;\n }\n \ndiff --git a/drivers/net/pfe/pfe_hal.c b/drivers/net/pfe/pfe_hal.c\nnew file mode 100644\nindex 000000000..be3b0d01b\n--- /dev/null\n+++ b/drivers/net/pfe/pfe_hal.c\n@@ -0,0 +1,629 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#include \"pfe_logs.h\"\n+#include \"pfe_mod.h\"\n+\n+#define PFE_MTU_RESET_MASK\t0xC000FFFF\n+\n+void *cbus_base_addr;\n+void *ddr_base_addr;\n+unsigned long ddr_phys_base_addr;\n+unsigned int ddr_size;\n+static struct pe_info pe[MAX_PE];\n+\n+/* Initializes the PFE library.\n+ * Must be called before using any of the library functions.\n+ *\n+ * @param[in] cbus_base\t\tCBUS virtual base address (as mapped in\n+ * the host CPU address space)\n+ * @param[in] ddr_base\t\tPFE DDR range virtual base address (as\n+ * mapped in the host CPU address space)\n+ * @param[in] ddr_phys_base\tPFE DDR range physical base address (as\n+ * mapped in platform)\n+ * @param[in] size\t\tPFE DDR range size (as defined by the host\n+ * software)\n+ */\n+void\n+pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,\n+\t\t  unsigned int size)\n+{\n+\tcbus_base_addr = cbus_base;\n+\tddr_base_addr = ddr_base;\n+\tddr_phys_base_addr = ddr_phys_base;\n+\tddr_size = size;\n+\n+\tpe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0);\n+\tpe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0);\n+\tpe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1);\n+\tpe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1);\n+\tpe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2);\n+\tpe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2);\n+\tpe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3);\n+\tpe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3);\n+\tpe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4);\n+\tpe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4);\n+\tpe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5);\n+\tpe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5);\n+\tpe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0);\n+\tpe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0);\n+\tpe[TMU0_ID].pmem_size = TMU_IMEM_SIZE;\n+\tpe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;\n+\tpe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;\n+\tpe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;\n+\n+\tpe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1);\n+\tpe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1);\n+\tpe[TMU1_ID].pmem_size = TMU_IMEM_SIZE;\n+\tpe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;\n+\tpe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;\n+\tpe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;\n+\n+\tpe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3);\n+\tpe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3);\n+\tpe[TMU3_ID].pmem_size = TMU_IMEM_SIZE;\n+\tpe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;\n+\tpe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;\n+\tpe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;\n+\n+#if !defined(CONFIG_FSL_PFE_UTIL_DISABLED)\n+\tpe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR;\n+\tpe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA;\n+\tpe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR;\n+\tpe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA;\n+#endif\n+}\n+\n+/**************************** MTIP GEMAC ***************************/\n+\n+/* Enable Rx Checksum Engine. With this enabled, Frame with bad IP,\n+ *   TCP or UDP checksums are discarded\n+ *\n+ * @param[in] base\tGEMAC base address.\n+ */\n+void\n+gemac_enable_rx_checksum_offload(__rte_unused void *base)\n+{\n+\t/*Do not find configuration to do this */\n+}\n+\n+/* Disable Rx Checksum Engine.\n+ *\n+ * @param[in] base\tGEMAC base address.\n+ */\n+void\n+gemac_disable_rx_checksum_offload(__rte_unused void *base)\n+{\n+\t/*Do not find configuration to do this */\n+}\n+\n+/* GEMAC set speed.\n+ * @param[in] base\tGEMAC base address\n+ * @param[in] speed\tGEMAC speed (10, 100 or 1000 Mbps)\n+ */\n+void\n+gemac_set_speed(void *base, enum mac_speed gem_speed)\n+{\n+\tu32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;\n+\tu32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;\n+\n+\tswitch (gem_speed) {\n+\tcase SPEED_10M:\n+\t\t\trcr |= EMAC_RCNTRL_RMII_10T;\n+\t\t\tbreak;\n+\n+\tcase SPEED_1000M:\n+\t\t\tecr |= EMAC_ECNTRL_SPEED;\n+\t\t\tbreak;\n+\n+\tcase SPEED_100M:\n+\tdefault:\n+\t\t\t/*It is in 100M mode */\n+\t\t\tbreak;\n+\t}\n+\twritel(ecr, (base + EMAC_ECNTRL_REG));\n+\twritel(rcr, (base + EMAC_RCNTRL_REG));\n+}\n+\n+/* GEMAC set duplex.\n+ * @param[in] base\tGEMAC base address\n+ * @param[in] duplex\tGEMAC duplex mode (Full, Half)\n+ */\n+void\n+gemac_set_duplex(void *base, int duplex)\n+{\n+\tif (duplex == DUPLEX_HALF) {\n+\t\twritel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base\n+\t\t\t+ EMAC_TCNTRL_REG);\n+\t\twritel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base\n+\t\t\t+ EMAC_RCNTRL_REG));\n+\t} else {\n+\t\twritel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base\n+\t\t\t+ EMAC_TCNTRL_REG);\n+\t\twritel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base\n+\t\t\t+ EMAC_RCNTRL_REG));\n+\t}\n+}\n+\n+/* GEMAC set mode.\n+ * @param[in] base\tGEMAC base address\n+ * @param[in] mode\tGEMAC operation mode (MII, RMII, RGMII, SGMII)\n+ */\n+void\n+gemac_set_mode(void *base, __rte_unused int mode)\n+{\n+\tu32 val = readl(base + EMAC_RCNTRL_REG);\n+\n+\t/*Remove loopbank*/\n+\tval &= ~EMAC_RCNTRL_LOOP;\n+\n+\t/*Enable flow control and MII mode*/\n+\tval |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE | EMAC_RCNTRL_CRC_FWD);\n+\n+\twritel(val, base + EMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC enable function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void\n+gemac_enable(void *base)\n+{\n+\twritel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base +\n+\t\tEMAC_ECNTRL_REG);\n+}\n+\n+/* GEMAC disable function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void\n+gemac_disable(void *base)\n+{\n+\twritel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base +\n+\t\tEMAC_ECNTRL_REG);\n+}\n+\n+/* GEMAC TX disable function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void\n+gemac_tx_disable(void *base)\n+{\n+\twritel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base +\n+\t\tEMAC_TCNTRL_REG);\n+}\n+\n+void\n+gemac_tx_enable(void *base)\n+{\n+\twritel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base +\n+\t\t\tEMAC_TCNTRL_REG);\n+}\n+\n+/* Sets the hash register of the MAC.\n+ * This register is used for matching unicast and multicast frames.\n+ *\n+ * @param[in] base\tGEMAC base address.\n+ * @param[in] hash\t64-bit hash to be configured.\n+ */\n+void\n+gemac_set_hash(void *base, struct pfe_mac_addr *hash)\n+{\n+\twritel(hash->bottom,  base + EMAC_GALR);\n+\twritel(hash->top, base + EMAC_GAUR);\n+}\n+\n+void\n+gemac_set_laddrN(void *base, struct pfe_mac_addr *address,\n+\t\t      unsigned int entry_index)\n+{\n+\tif (entry_index < 1 || entry_index > EMAC_SPEC_ADDR_MAX)\n+\t\treturn;\n+\n+\tentry_index = entry_index - 1;\n+\tif (entry_index < 1) {\n+\t\twritel(htonl(address->bottom),  base + EMAC_PHY_ADDR_LOW);\n+\t\twritel((htonl(address->top) | 0x8808), base +\n+\t\t\tEMAC_PHY_ADDR_HIGH);\n+\t} else {\n+\t\twritel(htonl(address->bottom),  base + ((entry_index - 1) * 8)\n+\t\t\t+ EMAC_SMAC_0_0);\n+\t\twritel((htonl(address->top) | 0x8808), base + ((entry_index -\n+\t\t\t1) * 8) + EMAC_SMAC_0_1);\n+\t}\n+}\n+\n+void\n+gemac_clear_laddrN(void *base, unsigned int entry_index)\n+{\n+\tif (entry_index < 1 || entry_index > EMAC_SPEC_ADDR_MAX)\n+\t\treturn;\n+\n+\tentry_index = entry_index - 1;\n+\tif (entry_index < 1) {\n+\t\twritel(0, base + EMAC_PHY_ADDR_LOW);\n+\t\twritel(0, base + EMAC_PHY_ADDR_HIGH);\n+\t} else {\n+\t\twritel(0,  base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0);\n+\t\twritel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1);\n+\t}\n+}\n+\n+/* Set the loopback mode of the MAC.  This can be either no loopback for\n+ * normal operation, local loopback through MAC internal loopback module or PHY\n+ *   loopback for external loopback through a PHY.  This asserts the external\n+ * loop pin.\n+ *\n+ * @param[in] base\tGEMAC base address.\n+ * @param[in] gem_loop\tLoopback mode to be enabled. LB_LOCAL - MAC\n+ * Loopback,\n+ *\t\t\tLB_EXT - PHY Loopback.\n+ */\n+void\n+gemac_set_loop(void *base, __rte_unused enum mac_loop gem_loop)\n+{\n+\tpr_info(\"%s()\\n\", __func__);\n+\twritel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base +\n+\t\tEMAC_RCNTRL_REG));\n+}\n+\n+/* GEMAC allow frames\n+ * @param[in] base\tGEMAC base address\n+ */\n+void\n+gemac_enable_copy_all(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base +\n+\t\tEMAC_RCNTRL_REG));\n+}\n+\n+/* GEMAC do not allow frames\n+ * @param[in] base\tGEMAC base address\n+ */\n+void\n+gemac_disable_copy_all(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base +\n+\t\tEMAC_RCNTRL_REG));\n+}\n+\n+/* GEMAC allow broadcast function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void\n+gemac_allow_broadcast(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base +\n+\t\tEMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC no broadcast function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void\n+gemac_no_broadcast(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base +\n+\t\tEMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC enable 1536 rx function.\n+ * @param[in]\tbase\tGEMAC base address\n+ */\n+void\n+gemac_enable_1536_rx(void *base)\n+{\n+\t/* Set 1536 as Maximum frame length */\n+\twritel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK)\n+\t\t\t| (1536 << 16),\n+\t\t\tbase + EMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC set Max rx function.\n+ * @param[in]\tbase\tGEMAC base address\n+ */\n+int\n+gemac_set_rx(void *base, int mtu)\n+{\n+\tif (mtu < HIF_RX_PKT_MIN_SIZE || mtu > JUMBO_FRAME_SIZE) {\n+\t\tPFE_PMD_ERR(\"Invalid or not support MTU size\");\n+\t\treturn -1;\n+\t}\n+\n+\tif (pfe_svr == SVR_LS1012A_REV1 &&\n+\t    mtu > (MAX_MTU_ON_REV1 + PFE_ETH_OVERHEAD)) {\n+\t\tPFE_PMD_ERR(\"Max supported MTU on Rev1 is %d\", MAX_MTU_ON_REV1);\n+\t\treturn -1;\n+\t}\n+\n+\twritel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK)\n+\t\t\t| (mtu << 16),\n+\t\t\tbase + EMAC_RCNTRL_REG);\n+\treturn 0;\n+}\n+\n+/* GEMAC enable jumbo function.\n+ * @param[in]\tbase\tGEMAC base address\n+ */\n+void\n+gemac_enable_rx_jmb(void *base)\n+{\n+\tif (pfe_svr == SVR_LS1012A_REV1) {\n+\t\tPFE_PMD_ERR(\"Jumbo not supported on Rev1\");\n+\t\treturn;\n+\t}\n+\n+\twritel((readl(base + EMAC_RCNTRL_REG) & PFE_MTU_RESET_MASK) |\n+\t\t\t(JUMBO_FRAME_SIZE << 16), base + EMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC enable stacked vlan function.\n+ * @param[in]\tbase\tGEMAC base address\n+ */\n+void\n+gemac_enable_stacked_vlan(__rte_unused void *base)\n+{\n+\t/* MTIP doesn't support stacked vlan */\n+}\n+\n+/* GEMAC enable pause rx function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void\n+gemac_enable_pause_rx(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE,\n+\t       base + EMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC disable pause rx function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void\n+gemac_disable_pause_rx(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE,\n+\t       base + EMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC enable pause tx function.\n+ * @param[in] base GEMAC base address\n+ */\n+void\n+gemac_enable_pause_tx(void *base)\n+{\n+\twritel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY);\n+}\n+\n+/* GEMAC disable pause tx function.\n+ * @param[in] base GEMAC base address\n+ */\n+void\n+gemac_disable_pause_tx(void *base)\n+{\n+\twritel(0x0, base + EMAC_RX_SECTION_EMPTY);\n+}\n+\n+/* GEMAC wol configuration\n+ * @param[in] base\tGEMAC base address\n+ * @param[in] wol_conf\tWoL register configuration\n+ */\n+void\n+gemac_set_wol(void *base, u32 wol_conf)\n+{\n+\tu32  val = readl(base + EMAC_ECNTRL_REG);\n+\n+\tif (wol_conf)\n+\t\tval |= (EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);\n+\telse\n+\t\tval &= ~(EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);\n+\twritel(val, base + EMAC_ECNTRL_REG);\n+}\n+\n+/* Sets Gemac bus width to 64bit\n+ * @param[in] base       GEMAC base address\n+ * @param[in] width     gemac bus width to be set possible values are 32/64/128\n+ */\n+void\n+gemac_set_bus_width(__rte_unused void *base, __rte_unused int width)\n+{\n+}\n+\n+/* Sets Gemac configuration.\n+ * @param[in] base\tGEMAC base address\n+ * @param[in] cfg\tGEMAC configuration\n+ */\n+void\n+gemac_set_config(void *base, struct gemac_cfg *cfg)\n+{\n+\t/*GEMAC config taken from VLSI */\n+\twritel(0x00000004, base + EMAC_TFWR_STR_FWD);\n+\twritel(0x00000005, base + EMAC_RX_SECTION_FULL);\n+\n+\tif (pfe_svr == SVR_LS1012A_REV1)\n+\t\twritel(0x00000768, base + EMAC_TRUNC_FL);\n+\telse\n+\t\twritel(0x00003fff, base + EMAC_TRUNC_FL);\n+\n+\twritel(0x00000030, base + EMAC_TX_SECTION_EMPTY);\n+\twritel(0x00000000, base + EMAC_MIB_CTRL_STS_REG);\n+\n+\tgemac_set_mode(base, cfg->mode);\n+\n+\tgemac_set_speed(base, cfg->speed);\n+\n+\tgemac_set_duplex(base, cfg->duplex);\n+}\n+\n+/**************************** GPI ***************************/\n+\n+/* Initializes a GPI block.\n+ * @param[in] base\tGPI base address\n+ * @param[in] cfg\tGPI configuration\n+ */\n+void\n+gpi_init(void *base, struct gpi_cfg *cfg)\n+{\n+\tgpi_reset(base);\n+\n+\tgpi_disable(base);\n+\n+\tgpi_set_config(base, cfg);\n+}\n+\n+/* Resets a GPI block.\n+ * @param[in] base\tGPI base address\n+ */\n+void\n+gpi_reset(void *base)\n+{\n+\twritel(CORE_SW_RESET, base + GPI_CTRL);\n+}\n+\n+/* Enables a GPI block.\n+ * @param[in] base\tGPI base address\n+ */\n+void\n+gpi_enable(void *base)\n+{\n+\twritel(CORE_ENABLE, base + GPI_CTRL);\n+}\n+\n+/* Disables a GPI block.\n+ * @param[in] base\tGPI base address\n+ */\n+void\n+gpi_disable(void *base)\n+{\n+\twritel(CORE_DISABLE, base + GPI_CTRL);\n+}\n+\n+/* Sets the configuration of a GPI block.\n+ * @param[in] base\tGPI base address\n+ * @param[in] cfg\tGPI configuration\n+ */\n+void\n+gpi_set_config(void *base, struct gpi_cfg *cfg)\n+{\n+\twritel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL),\tbase\n+\t\t+ GPI_LMEM_ALLOC_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL),\tbase\n+\t\t+ GPI_LMEM_FREE_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL),\tbase\n+\t\t+ GPI_DDR_ALLOC_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),\tbase\n+\t\t+ GPI_DDR_FREE_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);\n+\twritel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);\n+\twritel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);\n+\twritel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);\n+\twritel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);\n+\twritel((DDR_HDR_SIZE << 16) |\tLMEM_HDR_SIZE,\tbase + GPI_HDR_SIZE);\n+\twritel((DDR_BUF_SIZE << 16) |\tLMEM_BUF_SIZE,\tbase + GPI_BUF_SIZE);\n+\n+\twritel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |\n+\t\tGPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);\n+\twritel(cfg->tmlf_txthres, base + GPI_TMLF_TX);\n+\twritel(cfg->aseq_len,\tbase + GPI_DTX_ASEQ);\n+\twritel(1, base + GPI_TOE_CHKSUM_EN);\n+\n+\tif (cfg->mtip_pause_reg) {\n+\t\twritel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG);\n+\t\twritel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME);\n+\t}\n+}\n+\n+/**************************** HIF ***************************/\n+/* Initializes HIF copy block.\n+ *\n+ */\n+void\n+hif_init(void)\n+{\n+\t/*Initialize HIF registers*/\n+\twritel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE,\n+\t       HIF_POLL_CTRL);\n+}\n+\n+/* Enable hif tx DMA and interrupt\n+ *\n+ */\n+void\n+hif_tx_enable(void)\n+{\n+\twritel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);\n+\twritel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN),\n+\t       HIF_INT_ENABLE);\n+}\n+\n+/* Disable hif tx DMA and interrupt\n+ *\n+ */\n+void\n+hif_tx_disable(void)\n+{\n+\tu32\thif_int;\n+\n+\twritel(0, HIF_TX_CTRL);\n+\n+\thif_int = readl(HIF_INT_ENABLE);\n+\thif_int &= HIF_TXPKT_INT_EN;\n+\twritel(hif_int, HIF_INT_ENABLE);\n+}\n+\n+/* Enable hif rx DMA and interrupt\n+ *\n+ */\n+void\n+hif_rx_enable(void)\n+{\n+\thif_rx_dma_start();\n+\twritel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN),\n+\t       HIF_INT_ENABLE);\n+}\n+\n+/* Disable hif rx DMA and interrupt\n+ *\n+ */\n+void\n+hif_rx_disable(void)\n+{\n+\tu32\thif_int;\n+\n+\twritel(0, HIF_RX_CTRL);\n+\n+\thif_int = readl(HIF_INT_ENABLE);\n+\thif_int &= HIF_RXPKT_INT_EN;\n+\twritel(hif_int, HIF_INT_ENABLE);\n+}\ndiff --git a/drivers/net/pfe/pfe_hif.c b/drivers/net/pfe/pfe_hif.c\nnew file mode 100644\nindex 000000000..28530d12c\n--- /dev/null\n+++ b/drivers/net/pfe/pfe_hif.c\n@@ -0,0 +1,256 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#include \"pfe_logs.h\"\n+#include \"pfe_mod.h\"\n+#include <sys/ioctl.h>\n+#include <sys/epoll.h>\n+#include <sys/eventfd.h>\n+\n+static int\n+pfe_hif_alloc_descr(struct pfe_hif *hif)\n+{\n+\tvoid *addr;\n+\tint err = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\taddr = rte_zmalloc(NULL, HIF_RX_DESC_NT * sizeof(struct hif_desc) +\n+\t\tHIF_TX_DESC_NT * sizeof(struct hif_desc), RTE_CACHE_LINE_SIZE);\n+\tif (!addr) {\n+\t\tPFE_PMD_ERR(\"Could not allocate buffer descriptors!\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err0;\n+\t}\n+\n+\thif->descr_baseaddr_p = pfe_mem_vtop((uintptr_t)addr);\n+\thif->descr_baseaddr_v = addr;\n+\thif->rx_ring_size = HIF_RX_DESC_NT;\n+\thif->tx_ring_size = HIF_TX_DESC_NT;\n+\n+\treturn 0;\n+\n+err0:\n+\treturn err;\n+}\n+\n+static void\n+pfe_hif_free_descr(struct pfe_hif *hif)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\trte_free(hif->descr_baseaddr_v);\n+}\n+\n+#if defined(LS1012A_PFE_RESET_WA)\n+static void\n+pfe_hif_disable_rx_desc(struct pfe_hif *hif)\n+{\n+\tu32 ii;\n+\tstruct hif_desc\t*desc = hif->rx_base;\n+\n+\t/*Mark all descriptors as LAST_BD */\n+\tfor (ii = 0; ii < hif->rx_ring_size; ii++) {\n+\t\tdesc->ctrl |= BD_CTRL_LAST_BD;\n+\t\tdesc++;\n+\t}\n+}\n+\n+struct class_rx_hdr_t {\n+\tu32     next_ptr;       /* ptr to the start of the first DDR buffer */\n+\tu16     length;         /* total packet length */\n+\tu16     phyno;          /* input physical port number */\n+\tu32     status;         /* gemac status bits */\n+\tu32     status2;            /* reserved for software usage */\n+};\n+\n+/* STATUS_BAD_FRAME_ERR is set for all errors (including checksums if enabled)\n+ * except overflow\n+ */\n+#define STATUS_BAD_FRAME_ERR            BIT(16)\n+#define STATUS_LENGTH_ERR               BIT(17)\n+#define STATUS_CRC_ERR                  BIT(18)\n+#define STATUS_TOO_SHORT_ERR            BIT(19)\n+#define STATUS_TOO_LONG_ERR             BIT(20)\n+#define STATUS_CODE_ERR                 BIT(21)\n+#define STATUS_MC_HASH_MATCH            BIT(22)\n+#define STATUS_CUMULATIVE_ARC_HIT       BIT(23)\n+#define STATUS_UNICAST_HASH_MATCH       BIT(24)\n+#define STATUS_IP_CHECKSUM_CORRECT      BIT(25)\n+#define STATUS_TCP_CHECKSUM_CORRECT     BIT(26)\n+#define STATUS_UDP_CHECKSUM_CORRECT     BIT(27)\n+#define STATUS_OVERFLOW_ERR             BIT(28) /* GPI error */\n+#define MIN_PKT_SIZE\t\t\t64\n+#define DUMMY_PKT_COUNT\t\t\t128\n+\n+static inline void\n+copy_to_lmem(u32 *dst, u32 *src, int len)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < len; i += sizeof(u32))\t{\n+\t\t*dst = htonl(*src);\n+\t\tdst++; src++;\n+\t}\n+}\n+#if defined(RTE_TOOLCHAIN_GCC)\n+__attribute__ ((optimize(1)))\n+#endif\n+static void\n+send_dummy_pkt_to_hif(void)\n+{\n+\tvoid *lmem_ptr, *ddr_ptr, *lmem_virt_addr;\n+\tu64 physaddr;\n+\tstruct class_rx_hdr_t local_hdr;\n+\tstatic u32 dummy_pkt[] =  {\n+\t\t0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,\n+\t\t0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,\n+\t\t0x33221100, 0xa8c05544, 0x00000301, 0x00000000,\n+\t\t0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };\n+\n+\tddr_ptr = (void *)(size_t)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);\n+\tif (!ddr_ptr)\n+\t\treturn;\n+\n+\tlmem_ptr = (void *)(size_t)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL);\n+\tif (!lmem_ptr)\n+\t\treturn;\n+\n+\tPFE_PMD_INFO(\"Sending a dummy pkt to HIF %p %p\", ddr_ptr, lmem_ptr);\n+\tphysaddr = DDR_VIRT_TO_PFE(ddr_ptr);\n+\n+\tlmem_virt_addr = (void *)CBUS_PFE_TO_VIRT((unsigned long)lmem_ptr);\n+\n+\tlocal_hdr.phyno = htons(0); /* RX_PHY_0 */\n+\tlocal_hdr.length = htons(MIN_PKT_SIZE);\n+\n+\tlocal_hdr.next_ptr = htonl((u32)physaddr);\n+\t/*Mark checksum is correct */\n+\tlocal_hdr.status = htonl((STATUS_IP_CHECKSUM_CORRECT |\n+\t\t\t\tSTATUS_UDP_CHECKSUM_CORRECT |\n+\t\t\t\tSTATUS_TCP_CHECKSUM_CORRECT |\n+\t\t\t\tSTATUS_UNICAST_HASH_MATCH |\n+\t\t\t\tSTATUS_CUMULATIVE_ARC_HIT));\n+\tcopy_to_lmem((u32 *)lmem_virt_addr, (u32 *)&local_hdr,\n+\t\t     sizeof(local_hdr));\n+\n+\tcopy_to_lmem((u32 *)(lmem_virt_addr + LMEM_HDR_SIZE), (u32 *)dummy_pkt,\n+\t\t     0x40);\n+\n+\twritel((unsigned long)lmem_ptr, CLASS_INQ_PKTPTR);\n+}\n+\n+void\n+pfe_hif_rx_idle(struct pfe_hif *hif)\n+{\n+\tint hif_stop_loop = DUMMY_PKT_COUNT;\n+\tu32 rx_status;\n+\n+\tpfe_hif_disable_rx_desc(hif);\n+\tPFE_PMD_INFO(\"Bringing hif to idle state...\");\n+\twritel(0, HIF_INT_ENABLE);\n+\t/*If HIF Rx BDP is busy send a dummy packet */\n+\tdo {\n+\t\trx_status = readl(HIF_RX_STATUS);\n+\t\tif (rx_status & BDP_CSR_RX_DMA_ACTV)\n+\t\t\tsend_dummy_pkt_to_hif();\n+\n+\t\tsleep(1);\n+\t} while (--hif_stop_loop);\n+\n+\tif (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)\n+\t\tPFE_PMD_ERR(\"Failed\\n\");\n+\telse\n+\t\tPFE_PMD_INFO(\"Done\\n\");\n+}\n+#endif\n+\n+/*\n+ * pfe_hif_init\n+ * This function initializes the baseaddresses and irq, etc.\n+ */\n+int\n+pfe_hif_init(struct pfe *pfe)\n+{\n+\tstruct pfe_hif *hif = &pfe->hif;\n+\tint err;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+#if defined(LS1012A_PFE_RESET_WA)\n+\tpfe_hif_rx_idle(hif);\n+#endif\n+\n+\terr = pfe_hif_alloc_descr(hif);\n+\tif (err)\n+\t\tgoto err0;\n+\n+\trte_spinlock_init(&hif->tx_lock);\n+\trte_spinlock_init(&hif->lock);\n+\n+\tgpi_enable(HGPI_BASE_ADDR);\n+\tif (getenv(\"PFE_INTR_SUPPORT\")) {\n+\t\tstruct epoll_event epoll_ev;\n+\t\tint event_fd = -1, epoll_fd, pfe_cdev_fd;\n+\n+\t\tpfe_cdev_fd = open(PFE_CDEV_PATH, O_RDWR);\n+\t\tif (pfe_cdev_fd < 0) {\n+\t\t\tPFE_PMD_WARN(\"Unable to open PFE device file (%s).\\n\",\n+\t\t\t\t     PFE_CDEV_PATH);\n+\t\t\tpfe->cdev_fd = PFE_CDEV_INVALID_FD;\n+\t\t\treturn -1;\n+\t\t}\n+\t\tpfe->cdev_fd = pfe_cdev_fd;\n+\n+\t\tevent_fd = eventfd(0, EFD_NONBLOCK);\n+\t\t/* hif interrupt enable */\n+\t\terr = ioctl(pfe->cdev_fd, PFE_CDEV_HIF_INTR_EN, &event_fd);\n+\t\tif (err) {\n+\t\t\tPFE_PMD_ERR(\"\\nioctl failed for intr enable err: %d\\n\",\n+\t\t\t\t\terrno);\n+\t\t\tgoto err0;\n+\t\t}\n+\t\tepoll_fd = epoll_create(1);\n+\t\tepoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;\n+\t\tepoll_ev.data.fd = event_fd;\n+\t\terr = epoll_ctl(epoll_fd, EPOLL_CTL_ADD, event_fd, &epoll_ev);\n+\t\tif (err < 0) {\n+\t\t\tPFE_PMD_ERR(\"epoll_ctl failed with err = %d\\n\", errno);\n+\t\t\tgoto err0;\n+\t\t}\n+\t\tpfe->hif.epoll_fd = epoll_fd;\n+\t}\n+\treturn 0;\n+err0:\n+\treturn err;\n+}\n+\n+/* pfe_hif_exit- */\n+void\n+pfe_hif_exit(struct pfe *pfe)\n+{\n+\tstruct pfe_hif *hif = &pfe->hif;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\trte_spinlock_lock(&hif->lock);\n+\thif->shm->g_client_status[0] = 0;\n+\t/* Make sure all clients are disabled*/\n+\thif->shm->g_client_status[1] = 0;\n+\n+\trte_spinlock_unlock(&hif->lock);\n+\n+\tif (hif->setuped) {\n+#if defined(LS1012A_PFE_RESET_WA)\n+\t\tpfe_hif_rx_idle(hif);\n+#endif\n+\t\t/*Disable Rx/Tx */\n+\t\thif_rx_disable();\n+\t\thif_tx_disable();\n+\n+\t\tpfe_hif_free_descr(hif);\n+\t\tpfe->hif.setuped = 0;\n+\t}\n+\tgpi_disable(HGPI_BASE_ADDR);\n+}\ndiff --git a/drivers/net/pfe/pfe_hif.h b/drivers/net/pfe/pfe_hif.h\nnew file mode 100644\nindex 000000000..fa3c08cc7\n--- /dev/null\n+++ b/drivers/net/pfe/pfe_hif.h\n@@ -0,0 +1,106 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _PFE_HIF_H_\n+#define _PFE_HIF_H_\n+\n+#define HIF_CLIENT_QUEUES_MAX\t16\n+#define HIF_RX_PKT_MIN_SIZE RTE_CACHE_LINE_SIZE\n+/*\n+ * HIF_TX_DESC_NT value should be always greter than 4,\n+ * Otherwise HIF_TX_POLL_MARK will become zero.\n+ */\n+#define HIF_RX_DESC_NT\t\t64\n+#define HIF_TX_DESC_NT\t\t2048\n+\n+enum {\n+\tPFE_CL_GEM0 = 0,\n+\tPFE_CL_GEM1,\n+\tHIF_CLIENTS_MAX\n+};\n+\n+/*structure to store client queue info */\n+struct hif_rx_queue {\n+\tstruct rx_queue_desc *base;\n+\tu32\tsize;\n+\tu32\twrite_idx;\n+};\n+\n+struct hif_tx_queue {\n+\tstruct tx_queue_desc *base;\n+\tu32\tsize;\n+\tu32\tack_idx;\n+};\n+\n+/*Structure to store the client info */\n+struct hif_client {\n+\tunsigned int\trx_qn;\n+\tstruct hif_rx_queue\trx_q[HIF_CLIENT_QUEUES_MAX];\n+\tunsigned int\ttx_qn;\n+\tstruct hif_tx_queue\ttx_q[HIF_CLIENT_QUEUES_MAX];\n+};\n+\n+/*HIF hardware buffer descriptor */\n+struct hif_desc {\n+\tu32 ctrl;\n+\tu32 status;\n+\tu32 data;\n+\tu32 next;\n+};\n+\n+struct __hif_desc {\n+\tu32 ctrl;\n+\tu32 status;\n+\tu32 data;\n+};\n+\n+struct hif_desc_sw {\n+\tdma_addr_t data;\n+\tu16 len;\n+\tu8 client_id;\n+\tu8 q_no;\n+\tu16 flags;\n+};\n+\n+struct pfe_hif {\n+\t/* To store registered clients in hif layer */\n+\tstruct hif_client client[HIF_CLIENTS_MAX];\n+\tstruct hif_shm *shm;\n+\n+\tvoid\t*descr_baseaddr_v;\n+\tunsigned long\tdescr_baseaddr_p;\n+\n+\tstruct hif_desc *rx_base;\n+\tu32\trx_ring_size;\n+\tu32\trxtoclean_index;\n+\tvoid\t*rx_buf_addr[HIF_RX_DESC_NT];\n+\tvoid\t*rx_buf_vaddr[HIF_RX_DESC_NT];\n+\tint\trx_buf_len[HIF_RX_DESC_NT];\n+\tunsigned int qno;\n+\tunsigned int client_id;\n+\tunsigned int client_ctrl;\n+\tunsigned int started;\n+\tunsigned int setuped;\n+\n+\tstruct hif_desc *tx_base;\n+\tu32\ttx_ring_size;\n+\tu32\ttxtosend;\n+\tu32\ttxtoclean;\n+\tu32\ttxavail;\n+\tu32\ttxtoflush;\n+\tstruct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT];\n+\tint32_t\tepoll_fd; /**< File descriptor created for interrupt polling */\n+\n+/* tx_lock synchronizes hif packet tx as well as pfe_hif structure access */\n+\trte_spinlock_t tx_lock;\n+/* lock synchronizes hif rx queue processing */\n+\trte_spinlock_t lock;\n+\tstruct rte_device *dev;\n+};\n+\n+int pfe_hif_init(struct pfe *pfe);\n+void pfe_hif_exit(struct pfe *pfe);\n+void pfe_hif_rx_idle(struct pfe_hif *hif);\n+\n+#endif /* _PFE_HIF_H_ */\ndiff --git a/drivers/net/pfe/pfe_hif_lib.c b/drivers/net/pfe/pfe_hif_lib.c\nnew file mode 100644\nindex 000000000..8f8121be1\n--- /dev/null\n+++ b/drivers/net/pfe/pfe_hif_lib.c\n@@ -0,0 +1,20 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#include \"pfe_logs.h\"\n+#include \"pfe_mod.h\"\n+\n+int\n+pfe_hif_lib_init(__rte_unused struct pfe *pfe)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\treturn 0;\n+}\n+\n+void\n+pfe_hif_lib_exit(__rte_unused struct pfe *pfe)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+}\ndiff --git a/drivers/net/pfe/pfe_hif_lib.h b/drivers/net/pfe/pfe_hif_lib.h\nnew file mode 100644\nindex 000000000..45fae7d93\n--- /dev/null\n+++ b/drivers/net/pfe/pfe_hif_lib.h\n@@ -0,0 +1,162 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _PFE_HIF_LIB_H_\n+#define _PFE_HIF_LIB_H_\n+\n+#define HIF_CL_REQ_TIMEOUT\t10\n+#define GFP_DMA_PFE 0\n+\n+enum {\n+\tREQUEST_CL_REGISTER = 0,\n+\tREQUEST_CL_UNREGISTER,\n+\tHIF_REQUEST_MAX\n+};\n+\n+enum {\n+\t/* Event to indicate that client rx queue is reached water mark level */\n+\tEVENT_HIGH_RX_WM = 0,\n+\t/* Event to indicate that, packet received for client */\n+\tEVENT_RX_PKT_IND,\n+\t/* Event to indicate that, packet tx done for client */\n+\tEVENT_TXDONE_IND,\n+\tHIF_EVENT_MAX\n+};\n+\n+/*structure to store client queue info */\n+\n+/*structure to store client queue info */\n+struct hif_client_rx_queue {\n+\tstruct rx_queue_desc *base;\n+\tu32\tsize;\n+\tu32\tread_idx;\n+\tu32\twrite_idx;\n+\tu16\tqueue_id;\n+\tu16\tport_id;\n+\tvoid   *priv;\n+};\n+\n+struct hif_client_tx_queue {\n+\tstruct tx_queue_desc *base;\n+\tu32\tsize;\n+\tu32\tread_idx;\n+\tu32\twrite_idx;\n+\tu32\ttx_pending;\n+\tunsigned long jiffies_last_packet;\n+\tu32\tnocpy_flag;\n+\tu32\tprev_tmu_tx_pkts;\n+\tu32\tdone_tmu_tx_pkts;\n+\tu16\tqueue_id;\n+\tu16\tport_id;\n+\tvoid   *priv;\n+};\n+\n+struct hif_client_s {\n+\tint\tid;\n+\tunsigned int\ttx_qn;\n+\tunsigned int\trx_qn;\n+\tvoid\t*rx_qbase;\n+\tvoid\t*tx_qbase;\n+\tint\ttx_qsize;\n+\tint\trx_qsize;\n+\tint\tcpu_id;\n+\tint\tport_id;\n+\tstruct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];\n+\tstruct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];\n+\tint (*event_handler)(void *data, int event, int qno);\n+\tunsigned long queue_mask[HIF_EVENT_MAX];\n+\tstruct pfe *pfe;\n+\tvoid *priv;\n+};\n+\n+/*\n+ * Client specific shared memory\n+ * It contains number of Rx/Tx queues, base addresses and queue sizes\n+ */\n+struct hif_client_shm {\n+\tu32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */\n+\tunsigned long rx_qbase; /*Rx queue base address */\n+\tu32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */\n+\tunsigned long tx_qbase; /* Tx queue base address */\n+\tu32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */\n+};\n+\n+/*Client shared memory ctrl bit description */\n+#define CLIENT_CTRL_RX_Q_CNT_OFST\t0\n+#define CLIENT_CTRL_TX_Q_CNT_OFST\t8\n+#define CLIENT_CTRL_RX_Q_CNT(ctrl)\t(((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \\\n+\t\t\t\t\t\t& 0xFF)\n+#define CLIENT_CTRL_TX_Q_CNT(ctrl)\t(((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \\\n+\t\t\t\t\t\t& 0xFF)\n+\n+/*\n+ * Shared memory used to communicate between HIF driver and host/client drivers\n+ * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be\n+ * initialized with host buffers and buffers count in the pool.\n+ * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT.\n+ *\n+ */\n+struct hif_shm {\n+\tu32 rx_buf_pool_cnt; /*Number of rx buffers available*/\n+\t/*Rx buffers required to initialize HIF rx descriptors */\n+\tstruct rte_mempool *pool;\n+\tvoid *rx_buf_pool[HIF_RX_DESC_NT];\n+\tunsigned long g_client_status[2]; /*Global client status bit mask */\n+\t/* Client specific shared memory */\n+\tstruct hif_client_shm client[HIF_CLIENTS_MAX];\n+};\n+\n+#define CL_DESC_OWN\tBIT(31)\n+/* This sets owner ship to HIF driver */\n+#define CL_DESC_LAST\tBIT(30)\n+/* This indicates last packet for multi buffers handling */\n+#define CL_DESC_FIRST\tBIT(29)\n+/* This indicates first packet for multi buffers handling */\n+\n+#define CL_DESC_BUF_LEN(x)\t\t((x) & 0xFFFF)\n+#define CL_DESC_FLAGS(x)\t\t(((x) & 0xF) << 16)\n+#define CL_DESC_GET_FLAGS(x)\t\t(((x) >> 16) & 0xF)\n+\n+struct rx_queue_desc {\n+\tvoid *data;\n+\tu32\tctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/\n+\tu32\tclient_ctrl;\n+};\n+\n+struct tx_queue_desc {\n+\tvoid *data;\n+\tu32\tctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/\n+};\n+\n+/* HIF Rx is not working properly for 2-byte aligned buffers and\n+ * ip_header should be 4byte aligned for better iperformance.\n+ * \"ip_header = 64 + 6(hif_header) + 14 (MAC Header)\" will be 4byte aligned.\n+ * In case HW parse support:\n+ * \"ip_header = 64 + 6(hif_header) + 16 (parse) + 14 (MAC Header)\" will be\n+ * 4byte aligned.\n+ */\n+#define PFE_HIF_SIZE\t\tsizeof(struct hif_hdr)\n+\n+#ifdef RTE_LIBRTE_PFE_SW_PARSE\n+#define PFE_PKT_HEADER_SZ\tPFE_HIF_SIZE\n+#else\n+#define PFE_PKT_HEADER_SZ\t(PFE_HIF_SIZE + sizeof(struct pfe_parse))\n+#endif\n+\n+#define MAX_L2_HDR_SIZE\t\t14\t/* Not correct for VLAN/PPPoE */\n+#define MAX_L3_HDR_SIZE\t\t20\t/* Not correct for IPv6 */\n+#define MAX_L4_HDR_SIZE\t\t60\t/* TCP with maximum options */\n+#define MAX_HDR_SIZE\t\t(MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE \\\n+\t\t\t\t + MAX_L4_HDR_SIZE)\n+/* Used in page mode to clamp packet size to the maximum supported by the hif\n+ *hw interface (<16KiB)\n+ */\n+#define MAX_PFE_PKT_SIZE\t16380UL\n+\n+extern unsigned int emac_txq_cnt;\n+\n+int pfe_hif_lib_init(struct pfe *pfe);\n+void pfe_hif_lib_exit(struct pfe *pfe);\n+\n+#endif /* _PFE_HIF_LIB_H_ */\ndiff --git a/drivers/net/pfe/pfe_mod.h b/drivers/net/pfe/pfe_mod.h\nindex 8a41370c3..97fbb4891 100644\n--- a/drivers/net/pfe/pfe_mod.h\n+++ b/drivers/net/pfe/pfe_mod.h\n@@ -7,6 +7,9 @@\n \n struct pfe;\n \n+#include \"pfe.h\"\n+#include \"pfe_hif.h\"\n+#include \"pfe_hif_lib.h\"\n #include \"pfe_eth.h\"\n \n #define PHYID_MAX_VAL 32\n@@ -42,6 +45,8 @@ struct pfe {\n \tuint64_t ddr_size;\n \tvoid *cbus_baseaddr;\n \tuint64_t cbus_size;\n+\tstruct ls1012a_pfe_platform_data platform_data;\n+\tstruct pfe_hif hif;\n \tstruct pfe_eth eth;\n \tint mdio_muxval[PHYID_MAX_VAL];\n \tuint8_t nb_devs;\n",
    "prefixes": [
        "v4",
        "06/14"
    ]
}