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GET /api/patches/59879/?format=api
{ "id": 59879, "url": "https://patches.dpdk.org/api/patches/59879/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190926123609.28417-8-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190926123609.28417-8-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190926123609.28417-8-rnagadheeraj@marvell.com", "date": "2019-09-26T12:36:59", "name": "[v5,7/8] crypto/nitrox: add cipher auth crypto chain processing", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ca3a40accecd59c3eb80c1695b382e762d400e59", "submitter": { "id": 1365, "url": "https://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190926123609.28417-8-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 6550, "url": "https://patches.dpdk.org/api/series/6550/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6550", "date": "2019-09-26T12:36:45", "name": "add Nitrox crypto device support", "version": 5, "mbox": "https://patches.dpdk.org/series/6550/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/59879/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/59879/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost 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mx.microsoft.com 1; spf=pass\n\tsmtp.mailfrom=marvell.com;\n\tdmarc=pass action=none header.from=marvell.com; \n\tdkim=pass header.d=marvell.com; arc=none", "From": "Nagadheeraj Rottela <rnagadheeraj@marvell.com>", "To": "\"akhil.goyal@nxp.com\" <akhil.goyal@nxp.com>,\n\t\"pablo.de.lara.guarch@intel.com\" <pablo.de.lara.guarch@intel.com>", "CC": "Srikanth Jampala <jsrikanth@marvell.com>, \"dev@dpdk.org\" <dev@dpdk.org>, \n\tNagadheeraj Rottela <rnagadheeraj@marvell.com>", "Thread-Topic": "[PATCH v5 7/8] crypto/nitrox: add cipher auth crypto chain\n\tprocessing", "Thread-Index": "AQHVdGcXXely57gln0ulOQs/E03TVQ==", "Date": "Thu, 26 Sep 2019 12:36:59 +0000", "Message-ID": "<20190926123609.28417-8-rnagadheeraj@marvell.com>", "References": "<20190716091016.4788-1-rnagadheeraj@marvell.com>\n\t<20190926123609.28417-1-rnagadheeraj@marvell.com>", "In-Reply-To": "<20190926123609.28417-1-rnagadheeraj@marvell.com>", "Accept-Language": "en-IN, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": 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"+Syr3KeikKq8cbvjR2AJNJqBoQPehypehmy0weQPYpyIZyBqdiX7gUHi5lGHdiqR4mPKzKboAgo/SfdOgr1J4kAPp/s+WoxtVdYoA75wzBDooL4ryw0mqlD4hjmsH006ZucqPqFB+LnLXr6WYelWVD5vh+JvVq3vN+xM4w+vcGXyGzxNfMlJhed2AH7hCjjBVDaMKG02kNueabAItB71bVxMAc90X/iMWJpQKuZp1SpW+dF7p5We62VfbK0bx3MQKpgCklngESbJfb142GX5Jf/XPYOxg6LlsdV8bZ97UT9VmtyRcu1r2FpWZBgUwixcrhsH+SdSXKXUs/NstWBQp2zwEj/1XOvPiz5Sdde+e2XDK7TvhwqyUzskrOt3JwG38mpgNLbOM68feD/GNXiKR5xcfy4UrcJCWRXYy+hWvc/Yih+szF30yJHg0KcbVsxTj5JhLudR+UtJgf8MBRyDqw==", "Content-Type": "text/plain; charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-MS-Exchange-CrossTenant-Network-Message-Id": "d359af75-7eed-4349-bec9-08d7427e3980", "X-MS-Exchange-CrossTenant-originalarrivaltime": "26 Sep 2019 12:36:59.6584\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "70e1fb47-1155-421d-87fc-2e58f638b6e0", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "z7+L5JHT/JA2ugUYWuGPPPeBR+bnfY0YfzEcKZDkSB6PaEENmfFtwf2o6jUQu7W+j9SVQePOHJWzjk3G6ZvKfJNmM9U4i0LcYLPhVvSJedQ=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR18MB2766", "X-OriginatorOrg": "marvell.com", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,1.0.8\n\tdefinitions=2019-09-26_06:2019-09-25,2019-09-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v5 7/8] crypto/nitrox: add cipher auth crypto\n\tchain processing", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add cipher auth crypto chain processing functionality in symmetric\nrequest manager.\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n doc/guides/cryptodevs/features/nitrox.ini | 40 +++\n doc/guides/cryptodevs/nitrox.rst | 20 ++\n drivers/crypto/nitrox/nitrox_sym.c | 7 +-\n drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 412 +++++++++++++++++++++++++++++-\n 4 files changed, 476 insertions(+), 3 deletions(-)\n create mode 100644 doc/guides/cryptodevs/features/nitrox.ini", "diff": "diff --git a/doc/guides/cryptodevs/features/nitrox.ini b/doc/guides/cryptodevs/features/nitrox.ini\nnew file mode 100644\nindex 000000000..ddc3c05f4\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/nitrox.ini\n@@ -0,0 +1,40 @@\n+;\n+; Supported features of the 'nitrox' crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Symmetric crypto = Y\n+Sym operation chaining = Y\n+HW Accelerated = Y\n+In Place SGL = Y\n+OOP SGL In SGL Out = Y\n+OOP SGL In LB Out = Y\n+OOP LB In SGL Out = Y\n+OOP LB In LB Out = Y\n+\n+;\n+; Supported crypto algorithms of the 'nitrox' crypto driver.\n+;\n+[Cipher]\n+AES CBC (128) = Y\n+AES CBC (192) = Y\n+AES CBC (256) = Y\n+\n+;\n+; Supported authentication algorithms of the 'nitrox' crypto driver.\n+;\n+[Auth]\n+SHA1 HMAC = Y\n+SHA224 HMAC = Y\n+SHA256 HMAC = Y\n+\n+;\n+; Supported AEAD algorithms of the 'nitrox' crypto driver.\n+;\n+[AEAD]\n+\n+;\n+; Supported Asymmetric algorithms of the 'nitrox' crypto driver.\n+;\n+[Asymmetric]\ndiff --git a/doc/guides/cryptodevs/nitrox.rst b/doc/guides/cryptodevs/nitrox.rst\nindex 6f6e2675d..ffc1d95ab 100644\n--- a/doc/guides/cryptodevs/nitrox.rst\n+++ b/doc/guides/cryptodevs/nitrox.rst\n@@ -10,6 +10,26 @@ information about the NITROX V security processor can be obtained here:\n \n * https://www.marvell.com/security-solutions/nitrox-security-processors/nitrox-v/\n \n+Features\n+--------\n+\n+Nitrox crypto PMD has support for:\n+\n+Cipher algorithms:\n+\n+* ``RTE_CRYPTO_CIPHER_AES_CBC``\n+\n+Hash algorithms:\n+\n+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``\n+\n+Limitations\n+-----------\n+\n+* AES_CBC Cipher Only combination is not supported.\n+\n Installation\n ------------\n \ndiff --git a/drivers/crypto/nitrox/nitrox_sym.c b/drivers/crypto/nitrox/nitrox_sym.c\nindex 0ca15f847..e25baec2d 100644\n--- a/drivers/crypto/nitrox/nitrox_sym.c\n+++ b/drivers/crypto/nitrox/nitrox_sym.c\n@@ -706,7 +706,12 @@ nitrox_sym_pmd_create(struct nitrox_device *ndev)\n \tcdev->dequeue_burst = nitrox_sym_dev_deq_burst;\n \tcdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n \t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n-\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING;\n+\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n+\t\tRTE_CRYPTODEV_FF_IN_PLACE_SGL |\n+\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |\n+\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n+\t\tRTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT |\n+\t\tRTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT;\n \n \tndev->sym_dev = cdev->data->dev_private;\n \tndev->sym_dev->cdev = cdev;\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\nindex a37b754f2..d96e72718 100644\n--- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n+++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n@@ -10,9 +10,24 @@\n #include \"nitrox_sym_reqmgr.h\"\n #include \"nitrox_logs.h\"\n \n+#define MAX_SGBUF_CNT 16\n+#define MAX_SGCOMP_CNT 5\n+/* SLC_STORE_INFO */\n+#define MIN_UDD_LEN 16\n+/* PKT_IN_HDR + SLC_STORE_INFO */\n+#define FDATA_SIZE 32\n+/* Base destination port for the solicited requests */\n+#define SOLICIT_BASE_DPORT 256\n #define PENDING_SIG 0xFFFFFFFFFFFFFFFFUL\n #define CMD_TIMEOUT 2\n \n+struct gphdr {\n+\tuint16_t param0;\n+\tuint16_t param1;\n+\tuint16_t param2;\n+\tuint16_t param3;\n+};\n+\n union pkt_instr_hdr {\n \tuint64_t value;\n \tstruct {\n@@ -105,12 +120,46 @@ struct resp_hdr {\n \tuint64_t completion;\n };\n \n+struct nitrox_sglist {\n+\tuint16_t len;\n+\tuint16_t raz0;\n+\tuint32_t raz1;\n+\trte_iova_t iova;\n+\tvoid *virt;\n+};\n+\n+struct nitrox_sgcomp {\n+\tuint16_t len[4];\n+\tuint64_t iova[4];\n+};\n+\n+struct nitrox_sgtable {\n+\tuint8_t map_bufs_cnt;\n+\tuint8_t nr_sgcomp;\n+\tuint16_t total_bytes;\n+\n+\tstruct nitrox_sglist sglist[MAX_SGBUF_CNT];\n+\tstruct nitrox_sgcomp sgcomp[MAX_SGCOMP_CNT];\n+};\n+\n+struct iv {\n+\tuint8_t *virt;\n+\trte_iova_t iova;\n+\tuint16_t len;\n+};\n+\n struct nitrox_softreq {\n \tstruct nitrox_crypto_ctx *ctx;\n \tstruct rte_crypto_op *op;\n+\tstruct gphdr gph;\n \tstruct nps_pkt_instr instr;\n \tstruct resp_hdr resp;\n+\tstruct nitrox_sgtable in;\n+\tstruct nitrox_sgtable out;\n+\tstruct iv iv;\n \tuint64_t timeout;\n+\trte_iova_t dptr;\n+\trte_iova_t rptr;\n \trte_iova_t iova;\n };\n \n@@ -121,10 +170,369 @@ softreq_init(struct nitrox_softreq *sr, rte_iova_t iova)\n \tsr->iova = iova;\n }\n \n+/*\n+ * 64-Byte Instruction Format\n+ *\n+ * ----------------------\n+ * | DPTR0 | 8 bytes\n+ * ----------------------\n+ * | PKT_IN_INSTR_HDR | 8 bytes\n+ * ----------------------\n+ * | PKT_IN_HDR | 16 bytes\n+ * ----------------------\n+ * | SLC_INFO | 16 bytes\n+ * ----------------------\n+ * | Front data | 16 bytes\n+ * ----------------------\n+ */\n+static void\n+create_se_instr(struct nitrox_softreq *sr, uint8_t qno)\n+{\n+\tstruct nitrox_crypto_ctx *ctx = sr->ctx;\n+\trte_iova_t ctx_handle;\n+\n+\t/* fill the packet instruction */\n+\t/* word 0 */\n+\tsr->instr.dptr0 = rte_cpu_to_be_64(sr->dptr);\n+\n+\t/* word 1 */\n+\tsr->instr.ih.value = 0;\n+\tsr->instr.ih.s.g = 1;\n+\tsr->instr.ih.s.gsz = sr->in.map_bufs_cnt;\n+\tsr->instr.ih.s.ssz = sr->out.map_bufs_cnt;\n+\tsr->instr.ih.s.fsz = FDATA_SIZE + sizeof(struct gphdr);\n+\tsr->instr.ih.s.tlen = sr->instr.ih.s.fsz + sr->in.total_bytes;\n+\tsr->instr.ih.value = rte_cpu_to_be_64(sr->instr.ih.value);\n+\n+\t/* word 2 */\n+\tsr->instr.irh.value[0] = 0;\n+\tsr->instr.irh.s.uddl = MIN_UDD_LEN;\n+\t/* context length in 64-bit words */\n+\tsr->instr.irh.s.ctxl = RTE_ALIGN_MUL_CEIL(sizeof(ctx->fctx), 8) / 8;\n+\t/* offset from solicit base port 256 */\n+\tsr->instr.irh.s.destport = SOLICIT_BASE_DPORT + qno;\n+\t/* Invalid context cache */\n+\tsr->instr.irh.s.ctxc = 0x3;\n+\tsr->instr.irh.s.arg = ctx->req_op;\n+\tsr->instr.irh.s.opcode = ctx->opcode;\n+\tsr->instr.irh.value[0] = rte_cpu_to_be_64(sr->instr.irh.value[0]);\n+\n+\t/* word 3 */\n+\tctx_handle = ctx->iova + offsetof(struct nitrox_crypto_ctx, fctx);\n+\tsr->instr.irh.s.ctxp = rte_cpu_to_be_64(ctx_handle);\n+\n+\t/* word 4 */\n+\tsr->instr.slc.value[0] = 0;\n+\tsr->instr.slc.s.ssz = sr->out.map_bufs_cnt;\n+\tsr->instr.slc.value[0] = rte_cpu_to_be_64(sr->instr.slc.value[0]);\n+\n+\t/* word 5 */\n+\tsr->instr.slc.s.rptr = rte_cpu_to_be_64(sr->rptr);\n+\t/*\n+\t * No conversion for front data,\n+\t * It goes into payload\n+\t * put GP Header in front data\n+\t */\n+\tmemcpy(&sr->instr.fdata[0], &sr->gph, sizeof(sr->instr.fdata[0]));\n+\tsr->instr.fdata[1] = 0;\n+\t/* flush the soft_req changes before posting the cmd */\n+\trte_wmb();\n+}\n+\n+static void\n+softreq_copy_iv(struct nitrox_softreq *sr)\n+{\n+\tsr->iv.virt = rte_crypto_op_ctod_offset(sr->op, uint8_t *,\n+\t\t\t\t\t\tsr->ctx->iv.offset);\n+\tsr->iv.iova = rte_crypto_op_ctophys_offset(sr->op, sr->ctx->iv.offset);\n+\tsr->iv.len = sr->ctx->iv.length;\n+}\n+\n+static int\n+extract_cipher_auth_digest(struct nitrox_softreq *sr,\n+\t\t\t struct nitrox_sglist *digest)\n+{\n+\tstruct rte_crypto_op *op = sr->op;\n+\tstruct rte_mbuf *mdst = op->sym->m_dst ? op->sym->m_dst :\n+\t\t\t\t\top->sym->m_src;\n+\n+\tif (sr->ctx->auth_op == RTE_CRYPTO_AUTH_OP_VERIFY &&\n+\t unlikely(!op->sym->auth.digest.data))\n+\t\treturn -EINVAL;\n+\n+\tdigest->len = sr->ctx->digest_length;\n+\tif (op->sym->auth.digest.data) {\n+\t\tdigest->iova = op->sym->auth.digest.phys_addr;\n+\t\tdigest->virt = op->sym->auth.digest.data;\n+\t\treturn 0;\n+\t}\n+\n+\tif (unlikely(rte_pktmbuf_data_len(mdst) < op->sym->auth.data.offset +\n+\t op->sym->auth.data.length + digest->len))\n+\t\treturn -EINVAL;\n+\n+\tdigest->iova = rte_pktmbuf_mtophys_offset(mdst,\n+\t\t\t\t\top->sym->auth.data.offset +\n+\t\t\t\t\top->sym->auth.data.length);\n+\tdigest->virt = rte_pktmbuf_mtod_offset(mdst, uint8_t *,\n+\t\t\t\t\top->sym->auth.data.offset +\n+\t\t\t\t\top->sym->auth.data.length);\n+\treturn 0;\n+}\n+\n+static void\n+fill_sglist(struct nitrox_sgtable *sgtbl, uint16_t len, rte_iova_t iova,\n+\t void *virt)\n+{\n+\tstruct nitrox_sglist *sglist = sgtbl->sglist;\n+\tuint8_t cnt = sgtbl->map_bufs_cnt;\n+\n+\tif (unlikely(!len))\n+\t\treturn;\n+\n+\tsglist[cnt].len = len;\n+\tsglist[cnt].iova = iova;\n+\tsglist[cnt].virt = virt;\n+\tsgtbl->total_bytes += len;\n+\tcnt++;\n+\tsgtbl->map_bufs_cnt = cnt;\n+}\n+\n+static int\n+create_sglist_from_mbuf(struct nitrox_sgtable *sgtbl, struct rte_mbuf *mbuf,\n+\t\t\tuint32_t off, int datalen)\n+{\n+\tstruct nitrox_sglist *sglist = sgtbl->sglist;\n+\tuint8_t cnt = sgtbl->map_bufs_cnt;\n+\tstruct rte_mbuf *m;\n+\tint mlen;\n+\n+\tif (unlikely(datalen <= 0))\n+\t\treturn 0;\n+\n+\tfor (m = mbuf; m && off > rte_pktmbuf_data_len(m); m = m->next)\n+\t\toff -= rte_pktmbuf_data_len(m);\n+\n+\tif (unlikely(!m))\n+\t\treturn -EIO;\n+\n+\tmlen = rte_pktmbuf_data_len(m) - off;\n+\tif (datalen <= mlen)\n+\t\tmlen = datalen;\n+\tsglist[cnt].len = mlen;\n+\tsglist[cnt].iova = rte_pktmbuf_mtophys_offset(m, off);\n+\tsglist[cnt].virt = rte_pktmbuf_mtod_offset(m, uint8_t *, off);\n+\tsgtbl->total_bytes += mlen;\n+\tcnt++;\n+\tdatalen -= mlen;\n+\tfor (m = m->next; m && datalen; m = m->next) {\n+\t\tmlen = rte_pktmbuf_data_len(m) < datalen ?\n+\t\t\trte_pktmbuf_data_len(m) : datalen;\n+\t\tsglist[cnt].len = mlen;\n+\t\tsglist[cnt].iova = rte_pktmbuf_mtophys(m);\n+\t\tsglist[cnt].virt = rte_pktmbuf_mtod(m, uint8_t *);\n+\t\tsgtbl->total_bytes += mlen;\n+\t\tcnt++;\n+\t\tdatalen -= mlen;\n+\t}\n+\n+\tRTE_VERIFY(cnt <= MAX_SGBUF_CNT);\n+\tsgtbl->map_bufs_cnt = cnt;\n+\treturn 0;\n+}\n+\n+static int\n+create_cipher_auth_sglist(struct nitrox_softreq *sr,\n+\t\t\t struct nitrox_sgtable *sgtbl, struct rte_mbuf *mbuf)\n+{\n+\tstruct rte_crypto_op *op = sr->op;\n+\tint auth_only_len;\n+\tint err;\n+\n+\tfill_sglist(sgtbl, sr->iv.len, sr->iv.iova, sr->iv.virt);\n+\tauth_only_len = op->sym->auth.data.length - op->sym->cipher.data.length;\n+\tif (unlikely(auth_only_len < 0))\n+\t\treturn -EINVAL;\n+\n+\terr = create_sglist_from_mbuf(sgtbl, mbuf, op->sym->auth.data.offset,\n+\t\t\t\t auth_only_len);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\terr = create_sglist_from_mbuf(sgtbl, mbuf, op->sym->cipher.data.offset,\n+\t\t\t\t op->sym->cipher.data.length);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\treturn 0;\n+}\n+\n+static void\n+create_sgcomp(struct nitrox_sgtable *sgtbl)\n+{\n+\tint i, j, nr_sgcomp;\n+\tstruct nitrox_sgcomp *sgcomp = sgtbl->sgcomp;\n+\tstruct nitrox_sglist *sglist = sgtbl->sglist;\n+\n+\tnr_sgcomp = RTE_ALIGN_MUL_CEIL(sgtbl->map_bufs_cnt, 4) / 4;\n+\tsgtbl->nr_sgcomp = nr_sgcomp;\n+\tfor (i = 0; i < nr_sgcomp; i++, sgcomp++) {\n+\t\tfor (j = 0; j < 4; j++, sglist++) {\n+\t\t\tsgcomp->len[j] = rte_cpu_to_be_16(sglist->len);\n+\t\t\tsgcomp->iova[j] = rte_cpu_to_be_64(sglist->iova);\n+\t\t}\n+\t}\n+}\n+\n+static int\n+create_cipher_auth_inbuf(struct nitrox_softreq *sr,\n+\t\t\t struct nitrox_sglist *digest)\n+{\n+\tint err;\n+\tstruct nitrox_crypto_ctx *ctx = sr->ctx;\n+\n+\terr = create_cipher_auth_sglist(sr, &sr->in, sr->op->sym->m_src);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\tif (ctx->auth_op == RTE_CRYPTO_AUTH_OP_VERIFY)\n+\t\tfill_sglist(&sr->in, digest->len, digest->iova, digest->virt);\n+\n+\tcreate_sgcomp(&sr->in);\n+\tsr->dptr = sr->iova + offsetof(struct nitrox_softreq, in.sgcomp);\n+\treturn 0;\n+}\n+\n+static int\n+create_cipher_auth_oop_outbuf(struct nitrox_softreq *sr,\n+\t\t\t struct nitrox_sglist *digest)\n+{\n+\tint err;\n+\tstruct nitrox_crypto_ctx *ctx = sr->ctx;\n+\n+\terr = create_cipher_auth_sglist(sr, &sr->out, sr->op->sym->m_dst);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\tif (ctx->auth_op == RTE_CRYPTO_AUTH_OP_GENERATE)\n+\t\tfill_sglist(&sr->out, digest->len, digest->iova, digest->virt);\n+\n+\treturn 0;\n+}\n+\n+static void\n+create_cipher_auth_inplace_outbuf(struct nitrox_softreq *sr,\n+\t\t\t\t struct nitrox_sglist *digest)\n+{\n+\tint i, cnt;\n+\tstruct nitrox_crypto_ctx *ctx = sr->ctx;\n+\n+\tcnt = sr->out.map_bufs_cnt;\n+\tfor (i = 0; i < sr->in.map_bufs_cnt; i++, cnt++) {\n+\t\tsr->out.sglist[cnt].len = sr->in.sglist[i].len;\n+\t\tsr->out.sglist[cnt].iova = sr->in.sglist[i].iova;\n+\t\tsr->out.sglist[cnt].virt = sr->in.sglist[i].virt;\n+\t}\n+\n+\tsr->out.map_bufs_cnt = cnt;\n+\tif (ctx->auth_op == RTE_CRYPTO_AUTH_OP_GENERATE) {\n+\t\tfill_sglist(&sr->out, digest->len, digest->iova,\n+\t\t\t digest->virt);\n+\t} else if (ctx->auth_op == RTE_CRYPTO_AUTH_OP_VERIFY) {\n+\t\tsr->out.map_bufs_cnt--;\n+\t}\n+}\n+\n+static int\n+create_cipher_auth_outbuf(struct nitrox_softreq *sr,\n+\t\t\t struct nitrox_sglist *digest)\n+{\n+\tstruct rte_crypto_op *op = sr->op;\n+\tint cnt = 0;\n+\n+\tsr->resp.orh = PENDING_SIG;\n+\tsr->out.sglist[cnt].len = sizeof(sr->resp.orh);\n+\tsr->out.sglist[cnt].iova = sr->iova + offsetof(struct nitrox_softreq,\n+\t\t\t\t\t\t resp.orh);\n+\tsr->out.sglist[cnt].virt = &sr->resp.orh;\n+\tcnt++;\n+\tsr->out.map_bufs_cnt = cnt;\n+\tif (op->sym->m_dst) {\n+\t\tint err;\n+\n+\t\terr = create_cipher_auth_oop_outbuf(sr, digest);\n+\t\tif (unlikely(err))\n+\t\t\treturn err;\n+\t} else {\n+\t\tcreate_cipher_auth_inplace_outbuf(sr, digest);\n+\t}\n+\n+\tcnt = sr->out.map_bufs_cnt;\n+\tsr->resp.completion = PENDING_SIG;\n+\tsr->out.sglist[cnt].len = sizeof(sr->resp.completion);\n+\tsr->out.sglist[cnt].iova = sr->iova + offsetof(struct nitrox_softreq,\n+\t\t\t\t\t\t resp.completion);\n+\tsr->out.sglist[cnt].virt = &sr->resp.completion;\n+\tcnt++;\n+\tRTE_VERIFY(cnt <= MAX_SGBUF_CNT);\n+\tsr->out.map_bufs_cnt = cnt;\n+\n+\tcreate_sgcomp(&sr->out);\n+\tsr->rptr = sr->iova + offsetof(struct nitrox_softreq, out.sgcomp);\n+\treturn 0;\n+}\n+\n+static void\n+create_aead_gph(uint32_t cryptlen, uint16_t ivlen, uint32_t authlen,\n+\t\tstruct gphdr *gph)\n+{\n+\tint auth_only_len;\n+\tunion {\n+\t\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\t\tuint16_t iv_offset : 8;\n+\t\t\tuint16_t auth_offset\t: 8;\n+#else\n+\t\t\tuint16_t auth_offset\t: 8;\n+\t\t\tuint16_t iv_offset : 8;\n+#endif\n+\t\t};\n+\t\tuint16_t value;\n+\t} param3;\n+\n+\tgph->param0 = rte_cpu_to_be_16(cryptlen);\n+\tgph->param1 = rte_cpu_to_be_16(authlen);\n+\n+\tauth_only_len = authlen - cryptlen;\n+\tgph->param2 = rte_cpu_to_be_16(ivlen + auth_only_len);\n+\n+\tparam3.iv_offset = 0;\n+\tparam3.auth_offset = ivlen;\n+\tgph->param3 = rte_cpu_to_be_16(param3.value);\n+}\n+\n static int\n process_cipher_auth_data(struct nitrox_softreq *sr)\n {\n-\tRTE_SET_USED(sr);\n+\tstruct rte_crypto_op *op = sr->op;\n+\tint err;\n+\tstruct nitrox_sglist digest;\n+\n+\tsoftreq_copy_iv(sr);\n+\terr = extract_cipher_auth_digest(sr, &digest);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\terr = create_cipher_auth_inbuf(sr, &digest);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\terr = create_cipher_auth_outbuf(sr, &digest);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\tcreate_aead_gph(op->sym->cipher.data.length, sr->iv.len,\n+\t\t\top->sym->auth.data.length, &sr->gph);\n \treturn 0;\n }\n \n@@ -152,11 +560,11 @@ nitrox_process_se_req(uint16_t qno, struct rte_crypto_op *op,\n \t\t struct nitrox_crypto_ctx *ctx,\n \t\t struct nitrox_softreq *sr)\n {\n-\tRTE_SET_USED(qno);\n \tsoftreq_init(sr, sr->iova);\n \tsr->ctx = ctx;\n \tsr->op = op;\n \tprocess_softreq(sr);\n+\tcreate_se_instr(sr, qno);\n \tsr->timeout = rte_get_timer_cycles() + CMD_TIMEOUT * rte_get_timer_hz();\n \treturn 0;\n }\n", "prefixes": [ "v5", "7/8" ] }