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GET /api/patches/59789/?format=api
{ "id": 59789, "url": "https://patches.dpdk.org/api/patches/59789/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1569479349-36962-10-git-send-email-orika@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1569479349-36962-10-git-send-email-orika@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1569479349-36962-10-git-send-email-orika@mellanox.com", "date": "2019-09-26T06:29:05", "name": "[09/13] net/mlx5: add internal tag item and action", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "42886560bdf393312e506bd8f040512aad4f57e7", "submitter": { "id": 795, "url": "https://patches.dpdk.org/api/people/795/?format=api", "name": "Ori Kam", "email": "orika@mellanox.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1569479349-36962-10-git-send-email-orika@mellanox.com/mbox/", "series": [ { "id": 6536, "url": "https://patches.dpdk.org/api/series/6536/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6536", "date": "2019-09-26T06:28:56", "name": "add hairpin feature", "version": 1, "mbox": "https://patches.dpdk.org/series/6536/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/59789/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/59789/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 14CB21BEBB;\n\tThu, 26 Sep 2019 08:30:22 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id CF1B21B94D\n\tfor <dev@dpdk.org>; Thu, 26 Sep 2019 08:30:05 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n\torika@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 26 Sep 2019 09:30:03 +0300", "from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx\n\t[10.210.16.126])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x8Q6TmlO012493;\n\tThu, 26 Sep 2019 09:30:03 +0300" ], "From": "Ori Kam <orika@mellanox.com>", "To": "Matan Azrad <matan@mellanox.com>, Shahaf Shuler <shahafs@mellanox.com>, \n\tViacheslav Ovsiienko <viacheslavo@mellanox.com>", "Cc": "dev@dpdk.org, orika@mellanox.com, jingjing.wu@intel.com,\n\tstephen@networkplumber.org", "Date": "Thu, 26 Sep 2019 06:29:05 +0000", "Message-Id": "<1569479349-36962-10-git-send-email-orika@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1569479349-36962-1-git-send-email-orika@mellanox.com>", "References": "<1569479349-36962-1-git-send-email-orika@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 09/13] net/mlx5: add internal tag item and action", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit introduce the setting and matching on regiters.\nThis item and and action will be used with number of different\nfeatures like hairpin, metering, metadata.\n\nSigned-off-by: Ori Kam <orika@mellanox.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 52 +++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 54 ++++++++++++--\n drivers/net/mlx5/mlx5_flow_dv.c | 158 +++++++++++++++++++++++++++++++++++++++-\n drivers/net/mlx5/mlx5_prm.h | 3 +-\n 4 files changed, 257 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 482f65b..00afc18 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -316,6 +316,58 @@ struct mlx5_flow_tunnel_info {\n \t},\n };\n \n+enum mlx5_feature_name {\n+\tMLX5_HAIRPIN_RX,\n+\tMLX5_HAIRPIN_TX,\n+\tMLX5_APPLICATION,\n+};\n+\n+/**\n+ * Translate tag ID to register.\n+ *\n+ * @param[in] dev\n+ * Pointer to the Ethernet device structure.\n+ * @param[in] feature\n+ * The feature that request the register.\n+ * @param[in] id\n+ * The request register ID.\n+ * @param[out] error\n+ * Error description in case of any.\n+ *\n+ * @return\n+ * The request register on success, a negative errno\n+ * value otherwise and rte_errno is set.\n+ */\n+__rte_unused\n+static enum modify_reg flow_get_reg_id(struct rte_eth_dev *dev,\n+\t\t\t\t enum mlx5_feature_name feature,\n+\t\t\t\t uint32_t id,\n+\t\t\t\t struct rte_flow_error *error)\n+{\n+\tstatic enum modify_reg id2reg[] = {\n+\t\t[0] = REG_A,\n+\t\t[1] = REG_C_2,\n+\t\t[2] = REG_C_3,\n+\t\t[3] = REG_C_4,\n+\t\t[4] = REG_B,};\n+\n+\tdev = (void *)dev;\n+\tswitch (feature) {\n+\tcase MLX5_HAIRPIN_RX:\n+\t\treturn REG_B;\n+\tcase MLX5_HAIRPIN_TX:\n+\t\treturn REG_A;\n+\tcase MLX5_APPLICATION:\n+\t\tif (id > 4)\n+\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\t NULL, \"invalid tag id\");\n+\t\treturn id2reg[id];\n+\t}\n+\treturn rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t NULL, \"invalid feature name\");\n+}\n+\n /**\n * Discover the maximum number of priority available.\n *\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 235bccd..0148c1b 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -27,6 +27,43 @@\n #include \"mlx5.h\"\n #include \"mlx5_prm.h\"\n \n+enum modify_reg {\n+\tREG_A,\n+\tREG_B,\n+\tREG_C_0,\n+\tREG_C_1,\n+\tREG_C_2,\n+\tREG_C_3,\n+\tREG_C_4,\n+\tREG_C_5,\n+\tREG_C_6,\n+\tREG_C_7,\n+};\n+\n+/* Private rte flow items. */\n+enum mlx5_rte_flow_item_type {\n+\tMLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,\n+\tMLX5_RTE_FLOW_ITEM_TYPE_TAG,\n+};\n+\n+/* Private rte flow actions. */\n+enum mlx5_rte_flow_action_type {\n+\tMLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,\n+\tMLX5_RTE_FLOW_ACTION_TYPE_TAG,\n+};\n+\n+/* Matches on selected register. */\n+struct mlx5_rte_flow_item_tag {\n+\tuint16_t id;\n+\trte_be32_t data;\n+};\n+\n+/* Modify selected register. */\n+struct mlx5_rte_flow_action_set_tag {\n+\tuint16_t id;\n+\trte_be32_t data;\n+};\n+\n /* Pattern outer Layer bits. */\n #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)\n #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)\n@@ -53,16 +90,17 @@\n /* General pattern items bits. */\n #define MLX5_FLOW_ITEM_METADATA (1u << 16)\n #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)\n+#define MLX5_FLOW_ITEM_TAG (1u << 18)\n \n /* Pattern MISC bits. */\n-#define MLX5_FLOW_LAYER_ICMP (1u << 18)\n-#define MLX5_FLOW_LAYER_ICMP6 (1u << 19)\n-#define MLX5_FLOW_LAYER_GRE_KEY (1u << 20)\n+#define MLX5_FLOW_LAYER_ICMP (1u << 19)\n+#define MLX5_FLOW_LAYER_ICMP6 (1u << 20)\n+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)\n \n /* Pattern tunnel Layer bits (continued). */\n-#define MLX5_FLOW_LAYER_IPIP (1u << 21)\n-#define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)\n-#define MLX5_FLOW_LAYER_NVGRE (1u << 23)\n+#define MLX5_FLOW_LAYER_IPIP (1u << 22)\n+#define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 23)\n+#define MLX5_FLOW_LAYER_NVGRE (1u << 24)\n \n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n@@ -139,6 +177,7 @@\n #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)\n #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)\n #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)\n+#define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)\n \n #define MLX5_FLOW_FATE_ACTIONS \\\n \t(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \\\n@@ -172,7 +211,8 @@\n \t\t\t\t MLX5_FLOW_ACTION_DEC_TCP_SEQ | \\\n \t\t\t\t MLX5_FLOW_ACTION_INC_TCP_ACK | \\\n \t\t\t\t MLX5_FLOW_ACTION_DEC_TCP_ACK | \\\n-\t\t\t\t MLX5_FLOW_ACTION_OF_SET_VLAN_VID)\n+\t\t\t\t MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \\\n+\t\t\t\t MLX5_FLOW_ACTION_SET_TAG)\n \n #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \\\n \t\t\t\tMLX5_FLOW_ACTION_OF_PUSH_VLAN)\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 2a7e3ed..dde0831 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -723,6 +723,59 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\t\t MLX5_MODIFICATION_TYPE_ADD, error);\n }\n \n+static enum mlx5_modification_field reg_to_field[] = {\n+\t[REG_A] = MLX5_MODI_META_DATA_REG_A,\n+\t[REG_B] = MLX5_MODI_META_DATA_REG_B,\n+\t[REG_C_0] = MLX5_MODI_META_REG_C_0,\n+\t[REG_C_1] = MLX5_MODI_META_REG_C_1,\n+\t[REG_C_2] = MLX5_MODI_META_REG_C_2,\n+\t[REG_C_3] = MLX5_MODI_META_REG_C_3,\n+\t[REG_C_4] = MLX5_MODI_META_REG_C_4,\n+\t[REG_C_5] = MLX5_MODI_META_REG_C_5,\n+\t[REG_C_6] = MLX5_MODI_META_REG_C_6,\n+\t[REG_C_7] = MLX5_MODI_META_REG_C_7,\n+};\n+\n+/**\n+ * Convert register set to DV specification.\n+ *\n+ * @param[in,out] resource\n+ * Pointer to the modify-header resource.\n+ * @param[in] action\n+ * Pointer to action specification.\n+ * @param[out] error\n+ * Pointer to the error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+flow_dv_convert_action_set_reg\n+\t\t\t(struct mlx5_flow_dv_modify_hdr_resource *resource,\n+\t\t\t const struct rte_flow_action *action,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tconst struct mlx5_rte_flow_action_set_tag *conf = (action->conf);\n+\tstruct mlx5_modification_cmd *actions = resource->actions;\n+\tuint32_t i = resource->actions_num;\n+\n+\tif (i >= MLX5_MODIFY_NUM)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n+\t\t\t\t\t \"too many items to modify\");\n+\tactions[i].action_type = MLX5_MODIFICATION_TYPE_SET;\n+\tactions[i].field = reg_to_field[conf->id];\n+\tactions[i].data0 = rte_cpu_to_be_32(actions[i].data0);\n+\tactions[i].data1 = conf->data;\n+\t++i;\n+\tresource->actions_num = i;\n+\tif (!resource->actions_num)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n+\t\t\t\t\t \"invalid modification flow item\");\n+\treturn 0;\n+}\n+\n /**\n * Validate META item.\n *\n@@ -4640,6 +4693,94 @@ struct field_modify_info modify_tcp[] = {\n }\n \n /**\n+ * Add tag item to matcher\n+ *\n+ * @param[in, out] matcher\n+ * Flow matcher.\n+ * @param[in, out] key\n+ * Flow matcher value.\n+ * @param[in] item\n+ * Flow pattern to translate.\n+ */\n+static void\n+flow_dv_translate_item_tag(void *matcher, void *key,\n+\t\t\t const struct rte_flow_item *item)\n+{\n+\tvoid *misc2_m =\n+\t\tMLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);\n+\tvoid *misc2_v =\n+\t\tMLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);\n+\tconst struct mlx5_rte_flow_item_tag *tag_v = item->spec;\n+\tconst struct mlx5_rte_flow_item_tag *tag_m = item->mask;\n+\tenum modify_reg reg = tag_v->id;\n+\trte_be32_t value = tag_v->data;\n+\trte_be32_t mask = tag_m->data;\n+\n+\tswitch (reg) {\n+\tcase REG_A:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,\n+\t\t\t\trte_be_to_cpu_32(mask));\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,\n+\t\t\t\trte_be_to_cpu_32(value));\n+\t\tbreak;\n+\tcase REG_B:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b,\n+\t\t\t\t rte_be_to_cpu_32(mask));\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b,\n+\t\t\t\trte_be_to_cpu_32(value));\n+\t\tbreak;\n+\tcase REG_C_0:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0,\n+\t\t\t\t rte_be_to_cpu_32(mask));\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0,\n+\t\t\t\trte_be_to_cpu_32(value));\n+\t\tbreak;\n+\tcase REG_C_1:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1,\n+\t\t\t\t rte_be_to_cpu_32(mask));\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1,\n+\t\t\t\trte_be_to_cpu_32(value));\n+\t\tbreak;\n+\tcase REG_C_2:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2,\n+\t\t\t\t rte_be_to_cpu_32(mask));\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2,\n+\t\t\t\trte_be_to_cpu_32(value));\n+\t\tbreak;\n+\tcase REG_C_3:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3,\n+\t\t\t\t rte_be_to_cpu_32(mask));\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3,\n+\t\t\t\trte_be_to_cpu_32(value));\n+\t\tbreak;\n+\tcase REG_C_4:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4,\n+\t\t\t\t rte_be_to_cpu_32(mask));\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4,\n+\t\t\t\trte_be_to_cpu_32(value));\n+\t\tbreak;\n+\tcase REG_C_5:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5,\n+\t\t\t\t rte_be_to_cpu_32(mask));\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5,\n+\t\t\t\trte_be_to_cpu_32(value));\n+\t\tbreak;\n+\tcase REG_C_6:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6,\n+\t\t\t\t rte_be_to_cpu_32(mask));\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6,\n+\t\t\t\trte_be_to_cpu_32(value));\n+\t\tbreak;\n+\tcase REG_C_7:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7,\n+\t\t\t\t rte_be_to_cpu_32(mask));\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7,\n+\t\t\t\trte_be_to_cpu_32(value));\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n * Add source vport match to the specified matcher.\n *\n * @param[in, out] matcher\n@@ -5225,8 +5366,9 @@ struct field_modify_info modify_tcp[] = {\n \t\tstruct mlx5_flow_tbl_resource *tbl;\n \t\tuint32_t port_id = 0;\n \t\tstruct mlx5_flow_dv_port_id_action_resource port_id_resource;\n+\t\tint action_type = actions->type;\n \n-\t\tswitch (actions->type) {\n+\t\tswitch (action_type) {\n \t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_PORT_ID:\n@@ -5541,6 +5683,12 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\t\tMLX5_FLOW_ACTION_INC_TCP_ACK :\n \t\t\t\t\tMLX5_FLOW_ACTION_DEC_TCP_ACK;\n \t\t\tbreak;\n+\t\tcase MLX5_RTE_FLOW_ACTION_TYPE_TAG:\n+\t\t\tif (flow_dv_convert_action_set_reg(&res, actions,\n+\t\t\t\t\t\t\t error))\n+\t\t\t\treturn -rte_errno;\n+\t\t\taction_flags |= MLX5_FLOW_ACTION_SET_TAG;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_END:\n \t\t\tactions_end = true;\n \t\t\tif (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {\n@@ -5565,8 +5713,9 @@ struct field_modify_info modify_tcp[] = {\n \tflow->actions = action_flags;\n \tfor (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {\n \t\tint tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);\n+\t\tint item_type = items->type;\n \n-\t\tswitch (items->type) {\n+\t\tswitch (item_type) {\n \t\tcase RTE_FLOW_ITEM_TYPE_PORT_ID:\n \t\t\tflow_dv_translate_item_port_id(dev, match_mask,\n \t\t\t\t\t\t match_value, items);\n@@ -5712,6 +5861,11 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\t\t\t items, tunnel);\n \t\t\tlast_item = MLX5_FLOW_LAYER_ICMP6;\n \t\t\tbreak;\n+\t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TAG:\n+\t\t\tflow_dv_translate_item_tag(match_mask, match_value,\n+\t\t\t\t\t\t items);\n+\t\t\tlast_item = MLX5_FLOW_ITEM_TAG;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n \t\t}\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex d4084db..695578f 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -623,7 +623,8 @@ struct mlx5_ifc_fte_match_set_misc2_bits {\n \tu8 metadata_reg_c_1[0x20];\n \tu8 metadata_reg_c_0[0x20];\n \tu8 metadata_reg_a[0x20];\n-\tu8 reserved_at_1a0[0x60];\n+\tu8 metadata_reg_b[0x20];\n+\tu8 reserved_at_1c0[0x40];\n };\n \n struct mlx5_ifc_fte_match_set_misc3_bits {\n", "prefixes": [ "09/13" ] }