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GET /api/patches/59541/?format=api
{ "id": 59541, "url": "https://patches.dpdk.org/api/patches/59541/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190923062702.3836-2-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190923062702.3836-2-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190923062702.3836-2-qi.z.zhang@intel.com", "date": "2019-09-23T06:26:32", "name": "[v4,01/30] net/ice/base: remove redundant empty lines", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bc66223247e4bb298c88158229d33f6bb7247800", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "https://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190923062702.3836-2-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6481, "url": "https://patches.dpdk.org/api/series/6481/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6481", "date": "2019-09-23T06:26:31", "name": "net/ice/base: share code update secend batch.", "version": 4, "mbox": "https://patches.dpdk.org/series/6481/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/59541/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/59541/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5061C1BE84;\n\tMon, 23 Sep 2019 08:24:24 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 8C1D51BE85\n\tfor <dev@dpdk.org>; Mon, 23 Sep 2019 08:24:12 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t22 Sep 2019 23:24:12 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga005.jf.intel.com with ESMTP; 22 Sep 2019 23:24:09 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,539,1559545200\"; d=\"scan'208\";a=\"363530391\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 23 Sep 2019 14:26:32 +0800", "Message-Id": "<20190923062702.3836-2-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190923062702.3836-1-qi.z.zhang@intel.com>", "References": "<20190902035551.16852-1-qi.z.zhang@intel.com>\n\t<20190923062702.3836-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 01/30] net/ice/base: remove redundant empty\n\tlines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Remove redundant empty lines\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 111 -------------------------------\n drivers/net/ice/base/ice_bitops.h | 2 -\n drivers/net/ice/base/ice_common.c | 25 -------\n drivers/net/ice/base/ice_common.h | 2 -\n drivers/net/ice/base/ice_controlq.c | 9 ---\n drivers/net/ice/base/ice_controlq.h | 1 -\n drivers/net/ice/base/ice_devids.h | 1 -\n drivers/net/ice/base/ice_flex_pipe.c | 5 --\n drivers/net/ice/base/ice_flex_pipe.h | 1 -\n drivers/net/ice/base/ice_hw_autogen.h | 2 -\n drivers/net/ice/base/ice_lan_tx_rx.h | 9 ---\n drivers/net/ice/base/ice_nvm.c | 4 --\n drivers/net/ice/base/ice_protocol_type.h | 2 -\n drivers/net/ice/base/ice_sched.c | 4 --\n drivers/net/ice/base/ice_switch.c | 8 ---\n drivers/net/ice/base/ice_switch.h | 2 -\n drivers/net/ice/base/ice_type.h | 9 ---\n 17 files changed, 197 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 8e1d6a07d..e6a1350ba 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -9,12 +9,10 @@\n * descriptor format. It is shared between Firmware and Software.\n */\n \n-\n #define ICE_MAX_VSI\t\t\t768\n #define ICE_AQC_TOPO_MAX_LEVEL_NUM\t0x9\n #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX\t9728\n \n-\n struct ice_aqc_generic {\n \t__le32 param0;\n \t__le32 param1;\n@@ -22,7 +20,6 @@ struct ice_aqc_generic {\n \t__le32 addr_low;\n };\n \n-\n /* Get version (direct 0x0001) */\n struct ice_aqc_get_ver {\n \t__le32 rom_ver;\n@@ -37,7 +34,6 @@ struct ice_aqc_get_ver {\n \tu8 api_patch;\n };\n \n-\n /* Send driver version (indirect 0x0002) */\n struct ice_aqc_driver_ver {\n \tu8 major_ver;\n@@ -49,7 +45,6 @@ struct ice_aqc_driver_ver {\n \t__le32 addr_low;\n };\n \n-\n /* Queue Shutdown (direct 0x0003) */\n struct ice_aqc_q_shutdown {\n \tu8 driver_unloading;\n@@ -57,9 +52,6 @@ struct ice_aqc_q_shutdown {\n \tu8 reserved[15];\n };\n \n-\n-\n-\n /* Request resource ownership (direct 0x0008)\n * Release resource ownership (direct 0x0009)\n */\n@@ -92,7 +84,6 @@ struct ice_aqc_req_res {\n \tu8 reserved[2];\n };\n \n-\n /* Get function capabilities (indirect 0x000A)\n * Get device capabilities (indirect 0x000B)\n */\n@@ -105,7 +96,6 @@ struct ice_aqc_list_caps {\n \t__le32 addr_low;\n };\n \n-\n /* Device/Function buffer entry, repeated per reported capability */\n struct ice_aqc_list_caps_elem {\n \t__le16 cap;\n@@ -132,7 +122,6 @@ struct ice_aqc_list_caps_elem {\n \t__le64 rsvd2;\n };\n \n-\n /* Manage MAC address, read command - indirect (0x0107)\n * This struct is also used for the response\n */\n@@ -153,7 +142,6 @@ struct ice_aqc_manage_mac_read {\n \t__le32 addr_low;\n };\n \n-\n /* Response buffer format for manage MAC read command */\n struct ice_aqc_manage_mac_read_resp {\n \tu8 lport_num;\n@@ -163,7 +151,6 @@ struct ice_aqc_manage_mac_read_resp {\n \tu8 mac_addr[ETH_ALEN];\n };\n \n-\n /* Manage MAC address, write command - direct (0x0108) */\n struct ice_aqc_manage_mac_write {\n \tu8 rsvd;\n@@ -182,7 +169,6 @@ struct ice_aqc_manage_mac_write {\n \t__le32 addr_low;\n };\n \n-\n /* Clear PXE Command and response (direct 0x0110) */\n struct ice_aqc_clear_pxe {\n \tu8 rx_cnt;\n@@ -190,7 +176,6 @@ struct ice_aqc_clear_pxe {\n \tu8 reserved[15];\n };\n \n-\n /* Configure No-Drop Policy Command (direct 0x0112) */\n struct ice_aqc_config_no_drop_policy {\n \tu8 opts;\n@@ -215,7 +200,6 @@ struct ice_aqc_get_sw_cfg {\n \t__le32 addr_low;\n };\n \n-\n /* Each entry in the response buffer is of the following type: */\n struct ice_aqc_get_sw_cfg_resp_elem {\n \t/* VSI/Port Number */\n@@ -242,7 +226,6 @@ struct ice_aqc_get_sw_cfg_resp_elem {\n #define ICE_AQC_GET_SW_CONF_RESP_IS_VF\t\tBIT(15)\n };\n \n-\n /* The response buffer is as follows. Note that the length of the\n * elements array varies with the length of the command response.\n */\n@@ -250,8 +233,6 @@ struct ice_aqc_get_sw_cfg_resp {\n \tstruct ice_aqc_get_sw_cfg_resp_elem elements[1];\n };\n \n-\n-\n /* These resource type defines are used for all switch resource\n * commands where a resource type is required, such as:\n * Get Resource Allocation command (indirect 0x0204)\n@@ -324,7 +305,6 @@ struct ice_aqc_get_res_resp {\n \tstruct ice_aqc_get_res_resp_elem elem[1];\n };\n \n-\n /* Allocate Resources command (indirect 0x0208)\n * Free Resources command (indirect 0x0209)\n */\n@@ -335,7 +315,6 @@ struct ice_aqc_alloc_free_res_cmd {\n \t__le32 addr_low;\n };\n \n-\n /* Resource descriptor */\n struct ice_aqc_res_elem {\n \tunion {\n@@ -344,7 +323,6 @@ struct ice_aqc_res_elem {\n \t} e;\n };\n \n-\n /* Buffer for Allocate/Free Resources commands */\n struct ice_aqc_alloc_free_res_elem {\n \t__le16 res_type; /* Types defined above cmd 0x0204 */\n@@ -355,7 +333,6 @@ struct ice_aqc_alloc_free_res_elem {\n \tstruct ice_aqc_res_elem elem[1];\n };\n \n-\n /* Get Allocated Resource Descriptors Command (indirect 0x020A) */\n struct ice_aqc_get_allocd_res_desc {\n \tunion {\n@@ -379,7 +356,6 @@ struct ice_aqc_get_allocd_res_desc_resp {\n \tstruct ice_aqc_res_elem elem[1];\n };\n \n-\n /* Add VSI (indirect 0x0210)\n * Update VSI (indirect 0x0211)\n * Get VSI (indirect 0x0212)\n@@ -405,7 +381,6 @@ struct ice_aqc_add_get_update_free_vsi {\n \t__le32 addr_low;\n };\n \n-\n /* Response descriptor for:\n * Add VSI (indirect 0x0210)\n * Update VSI (indirect 0x0211)\n@@ -420,7 +395,6 @@ struct ice_aqc_add_update_free_vsi_resp {\n \t__le32 addr_low;\n };\n \n-\n struct ice_aqc_get_vsi_resp {\n \t__le16 vsi_num;\n \tu8 vf_id;\n@@ -434,7 +408,6 @@ struct ice_aqc_get_vsi_resp {\n \t__le32 addr_low;\n };\n \n-\n struct ice_aqc_vsi_props {\n \t__le16 valid_sections;\n #define ICE_AQ_VSI_PROP_SW_VALID\t\tBIT(0)\n@@ -589,7 +562,6 @@ struct ice_aqc_vsi_props {\n \tu8 reserved[24];\n };\n \n-\n /* Add/update mirror rule - direct (0x0260) */\n #define ICE_AQC_RULE_ID_VALID_S\t\t7\n #define ICE_AQC_RULE_ID_VALID_M\t\t(0x1 << ICE_AQC_RULE_ID_VALID_S)\n@@ -694,7 +666,6 @@ struct ice_aqc_storm_cfg {\n \t__le32 reserved;\n };\n \n-\n #define ICE_MAX_NUM_RECIPES 64\n \n /* Add/Get Recipe (indirect 0x0290/0x0292)*/\n@@ -779,7 +750,6 @@ struct ice_aqc_sw_rules {\n \t__le32 addr_low;\n };\n \n-\n #pragma pack(1)\n /* Add/Update/Get/Remove lookup Rx/Tx command/response entry\n * This structures describes the lookup rules and associated actions. \"index\"\n@@ -867,7 +837,6 @@ struct ice_sw_rule_lkup_rx_tx {\n };\n #pragma pack()\n \n-\n /* Add/Update/Remove large action command/response entry\n * \"index\" is returned as part of a response to a successful Add command, and\n * can be used to identify the action for Update/Get/Remove commands.\n@@ -928,7 +897,6 @@ struct ice_sw_rule_lg_act {\n #define ICE_LG_ACT_STAT_COUNT_M\t\t(0x7F << ICE_LG_ACT_STAT_COUNT_S)\n };\n \n-\n /* Add/Update/Remove VSI list command/response entry\n * \"index\" is returned as part of a response to a successful Add command, and\n * can be used to identify the VSI list for Update/Get/Remove commands.\n@@ -939,7 +907,6 @@ struct ice_sw_rule_vsi_list {\n \t__le16 vsi[1]; /* Array of number_vsi VSI numbers */\n };\n \n-\n #pragma pack(1)\n /* Query VSI list command/response entry */\n struct ice_sw_rule_vsi_list_query {\n@@ -948,7 +915,6 @@ struct ice_sw_rule_vsi_list_query {\n };\n #pragma pack()\n \n-\n #pragma pack(1)\n /* Add switch rule response:\n * Content of return buffer is same as the input buffer. The status field and\n@@ -974,7 +940,6 @@ struct ice_aqc_sw_rules_elem {\n \n #pragma pack()\n \n-\n /* PFC Ignore (direct 0x0301)\n * The command and response use the same descriptor structure\n */\n@@ -1009,7 +974,6 @@ struct ice_aqc_set_dcb_params {\n \tu8 rsvd[14];\n };\n \n-\n /* Get Default Topology (indirect 0x0400) */\n struct ice_aqc_get_topo {\n \tu8 port_num;\n@@ -1020,7 +984,6 @@ struct ice_aqc_get_topo {\n \t__le32 addr_low;\n };\n \n-\n /* Update TSE (indirect 0x0403)\n * Get TSE (indirect 0x0404)\n * Add TSE (indirect 0x0401)\n@@ -1037,7 +1000,6 @@ struct ice_aqc_sched_elem_cmd {\n \t__le32 addr_low;\n };\n \n-\n /* This is the buffer for:\n * Suspend Nodes (indirect 0x0409)\n * Resume Nodes (indirect 0x040A)\n@@ -1046,7 +1008,6 @@ struct ice_aqc_suspend_resume_elem {\n \t__le32 teid[1];\n };\n \n-\n struct ice_aqc_txsched_move_grp_info_hdr {\n \t__le32 src_parent_teid;\n \t__le32 dest_parent_teid;\n@@ -1054,19 +1015,16 @@ struct ice_aqc_txsched_move_grp_info_hdr {\n \t__le16 reserved;\n };\n \n-\n struct ice_aqc_move_elem {\n \tstruct ice_aqc_txsched_move_grp_info_hdr hdr;\n \t__le32 teid[1];\n };\n \n-\n struct ice_aqc_elem_info_bw {\n \t__le16 bw_profile_idx;\n \t__le16 bw_alloc;\n };\n \n-\n struct ice_aqc_txsched_elem {\n \tu8 elem_type; /* Special field, reserved for some aq calls */\n #define ICE_AQC_ELEM_TYPE_UNDEFINED\t\t0x0\n@@ -1098,50 +1056,42 @@ struct ice_aqc_txsched_elem {\n \t__le16 reserved2;\n };\n \n-\n struct ice_aqc_txsched_elem_data {\n \t__le32 parent_teid;\n \t__le32 node_teid;\n \tstruct ice_aqc_txsched_elem data;\n };\n \n-\n struct ice_aqc_txsched_topo_grp_info_hdr {\n \t__le32 parent_teid;\n \t__le16 num_elems;\n \t__le16 reserved2;\n };\n \n-\n struct ice_aqc_add_elem {\n \tstruct ice_aqc_txsched_topo_grp_info_hdr hdr;\n \tstruct ice_aqc_txsched_elem_data generic[1];\n };\n \n-\n struct ice_aqc_conf_elem {\n \tstruct ice_aqc_txsched_elem_data generic[1];\n };\n \n-\n struct ice_aqc_get_elem {\n \tstruct ice_aqc_txsched_elem_data generic[1];\n };\n \n-\n struct ice_aqc_get_topo_elem {\n \tstruct ice_aqc_txsched_topo_grp_info_hdr hdr;\n \tstruct ice_aqc_txsched_elem_data\n \t\tgeneric[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n };\n \n-\n struct ice_aqc_delete_elem {\n \tstruct ice_aqc_txsched_topo_grp_info_hdr hdr;\n \t__le32 teid[1];\n };\n \n-\n /* Query Port ETS (indirect 0x040E)\n *\n * This indirect command is used to query port TC node configuration.\n@@ -1168,7 +1118,6 @@ struct ice_aqc_port_ets_elem {\n \t__le32 tc_node_teid[8]; /* Used for response, reserved in command */\n };\n \n-\n /* Rate limiting profile for\n * Add RL profile (indirect 0x0410)\n * Query RL profile (indirect 0x0411)\n@@ -1184,7 +1133,6 @@ struct ice_aqc_rl_profile {\n \t__le32 addr_low;\n };\n \n-\n struct ice_aqc_rl_profile_elem {\n \tu8 level;\n \tu8 flags;\n@@ -1204,13 +1152,10 @@ struct ice_aqc_rl_profile_elem {\n \t__le16 rl_encode;\n };\n \n-\n struct ice_aqc_rl_profile_generic_elem {\n \tstruct ice_aqc_rl_profile_elem generic[1];\n };\n \n-\n-\n /* Configure L2 Node CGD (indirect 0x0414)\n * This indirect command allows configuring a congestion domain for given L2\n * node TEIDs in the scheduler topology.\n@@ -1222,19 +1167,16 @@ struct ice_aqc_cfg_l2_node_cgd {\n \t__le32 addr_low;\n };\n \n-\n struct ice_aqc_cfg_l2_node_cgd_elem {\n \t__le32 node_teid;\n \tu8 cgd;\n \tu8 reserved[3];\n };\n \n-\n struct ice_aqc_cfg_l2_node_cgd_data {\n \tstruct ice_aqc_cfg_l2_node_cgd_elem elem[1];\n };\n \n-\n /* Query Scheduler Resource Allocation (indirect 0x0412)\n * This indirect command retrieves the scheduler resources allocated by\n * EMP Firmware to the given PF.\n@@ -1245,7 +1187,6 @@ struct ice_aqc_query_txsched_res {\n \t__le32 addr_low;\n };\n \n-\n struct ice_aqc_generic_sched_props {\n \t__le16 phys_levels;\n \t__le16 logical_levels;\n@@ -1257,7 +1198,6 @@ struct ice_aqc_generic_sched_props {\n \tu8 rsvd1[22];\n };\n \n-\n struct ice_aqc_layer_props {\n \tu8 logical_layer;\n \tu8 chunk_size;\n@@ -1271,13 +1211,11 @@ struct ice_aqc_layer_props {\n \tu8 rsvd1[14];\n };\n \n-\n struct ice_aqc_query_txsched_res_resp {\n \tstruct ice_aqc_generic_sched_props sched_props;\n \tstruct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n };\n \n-\n /* Query Node to Root Topology (indirect 0x0413)\n * This command uses ice_aqc_get_elem as its data buffer.\n */\n@@ -1288,7 +1226,6 @@ struct ice_aqc_query_node_to_root {\n \t__le32 addr_low;\n };\n \n-\n /* Get PHY capabilities (indirect 0x0600) */\n struct ice_aqc_get_phy_caps {\n \tu8 lport_num;\n@@ -1311,7 +1248,6 @@ struct ice_aqc_get_phy_caps {\n \t__le32 addr_low;\n };\n \n-\n /* This is #define of PHY type (Extended):\n * The first set of defines is for phy_type_low.\n */\n@@ -1453,7 +1389,6 @@ struct ice_aqc_get_phy_caps_data {\n \t} qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];\n };\n \n-\n /* Set PHY capabilities (direct 0x0601)\n * NOTE: This command must be followed by setup link and restart auto-neg\n */\n@@ -1464,7 +1399,6 @@ struct ice_aqc_set_phy_cfg {\n \t__le32 addr_low;\n };\n \n-\n /* Set PHY config command data structure */\n struct ice_aqc_set_phy_cfg_data {\n \t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n@@ -1485,7 +1419,6 @@ struct ice_aqc_set_phy_cfg_data {\n \tu8 rsvd1;\n };\n \n-\n /* Set MAC Config command data structure (direct 0x0603) */\n struct ice_aqc_set_mac_cfg {\n \t__le16 max_frame_size;\n@@ -1505,7 +1438,6 @@ struct ice_aqc_set_mac_cfg {\n \tu8 reserved[7];\n };\n \n-\n /* Restart AN command data structure (direct 0x0605)\n * Also used for response, with only the lport_num field present.\n */\n@@ -1518,7 +1450,6 @@ struct ice_aqc_restart_an {\n \tu8 reserved2[13];\n };\n \n-\n /* Get link status (indirect 0x0607), also used for Link Status Event */\n struct ice_aqc_get_link_status {\n \tu8 lport_num;\n@@ -1535,7 +1466,6 @@ struct ice_aqc_get_link_status {\n \t__le32 addr_low;\n };\n \n-\n /* Get link status response data structure, also used for Link Status Event */\n struct ice_aqc_get_link_status_data {\n \tu8 topo_media_conflict;\n@@ -1621,7 +1551,6 @@ struct ice_aqc_get_link_status_data {\n \t__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */\n };\n \n-\n /* Set event mask command (direct 0x0613) */\n struct ice_aqc_set_event_mask {\n \tu8\tlport_num;\n@@ -1641,8 +1570,6 @@ struct ice_aqc_set_event_mask {\n \tu8\treserved1[6];\n };\n \n-\n-\n /* Set MAC Loopback command (direct 0x0620) */\n struct ice_aqc_set_mac_lb {\n \tu8 lb_mode;\n@@ -1651,9 +1578,6 @@ struct ice_aqc_set_mac_lb {\n \tu8 reserved[15];\n };\n \n-\n-\n-\n struct ice_aqc_link_topo_addr {\n \tu8 lport_num;\n \tu8 lport_num_valid;\n@@ -1716,8 +1640,6 @@ struct ice_aqc_set_port_id_led {\n \tu8 rsvd[13];\n };\n \n-\n-\n /* Read/Write SFF EEPROM command (indirect 0x06EE) */\n struct ice_aqc_sff_eeprom {\n \tu8 lport_num;\n@@ -1797,7 +1719,6 @@ struct ice_aqc_nvm {\n #define ICE_AQC_NVM_LLDP_STATUS_M_LEN\t\t4 /* In Bits */\n #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN\t\t4 /* In Bytes */\n \n-\n /* Used for 0x0704 as well as for 0x0705 commands */\n struct ice_aqc_nvm_cfg {\n \tu8\tcmd_flags;\n@@ -1812,14 +1733,12 @@ struct ice_aqc_nvm_cfg {\n \t__le32 addr_low;\n };\n \n-\n struct ice_aqc_nvm_cfg_data {\n \t__le16 field_id;\n \t__le16 field_options;\n \t__le16 field_value;\n };\n \n-\n /* NVM Checksum Command (direct, 0x0706) */\n struct ice_aqc_nvm_checksum {\n \tu8 flags;\n@@ -1831,9 +1750,6 @@ struct ice_aqc_nvm_checksum {\n \tu8 rsvd2[12];\n };\n \n-\n-\n-\n /* Get LLDP MIB (indirect 0x0A00)\n * Note: This is also used by the LLDP MIB Change Event (0x0A01)\n * as the format is the same.\n@@ -1985,7 +1901,6 @@ struct ice_aqc_lldp_stop_start_specific_agent {\n \tu8 reserved[15];\n };\n \n-\n /* Get/Set RSS key (indirect 0x0B04/0x0B02) */\n struct ice_aqc_get_set_rss_key {\n #define ICE_AQC_GSET_RSS_KEY_VSI_VALID\tBIT(15)\n@@ -1997,7 +1912,6 @@ struct ice_aqc_get_set_rss_key {\n \t__le32 addr_low;\n };\n \n-\n #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE\t0x28\n #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE\t0xC\n #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \\\n@@ -2019,7 +1933,6 @@ struct ice_aqc_get_set_rss_keys {\n \tu8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];\n };\n \n-\n /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */\n struct ice_aqc_get_set_rss_lut {\n #define ICE_AQC_GSET_RSS_LUT_VSI_VALID\tBIT(15)\n@@ -2055,7 +1968,6 @@ struct ice_aqc_get_set_rss_lut {\n \t__le32 addr_low;\n };\n \n-\n /* Clear FD Table Command (direct, 0x0B06) */\n struct ice_aqc_clear_fd_table {\n \tu8 clear_type;\n@@ -2066,9 +1978,6 @@ struct ice_aqc_clear_fd_table {\n \tu8 reserved[12];\n };\n \n-\n-\n-\n /* Add Tx LAN Queues (indirect 0x0C30) */\n struct ice_aqc_add_txqs {\n \tu8 num_qgrps;\n@@ -2078,7 +1987,6 @@ struct ice_aqc_add_txqs {\n \t__le32 addr_low;\n };\n \n-\n /* This is the descriptor of each queue entry for the Add Tx LAN Queues\n * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.\n */\n@@ -2091,7 +1999,6 @@ struct ice_aqc_add_txqs_perq {\n \tstruct ice_aqc_txsched_elem info;\n };\n \n-\n /* The format of the command buffer for Add Tx LAN Queues (0x0C30)\n * is an array of the following structs. Please note that the length of\n * each struct ice_aqc_add_tx_qgrp is variable due\n@@ -2104,7 +2011,6 @@ struct ice_aqc_add_tx_qgrp {\n \tstruct ice_aqc_add_txqs_perq txqs[1];\n };\n \n-\n /* Disable Tx LAN Queues (indirect 0x0C31) */\n struct ice_aqc_dis_txqs {\n \tu8 cmd_type;\n@@ -2127,7 +2033,6 @@ struct ice_aqc_dis_txqs {\n \t__le32 addr_low;\n };\n \n-\n /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)\n * contains the following structures, arrayed one after the\n * other.\n@@ -2150,12 +2055,10 @@ struct ice_aqc_dis_txq_item {\n \t\t\t(1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)\n };\n \n-\n struct ice_aqc_dis_txq {\n \tstruct ice_aqc_dis_txq_item qgrps[1];\n };\n \n-\n /* Tx LAN Queues Cleanup Event (0x0C31) */\n struct ice_aqc_txqs_cleanup {\n \t__le16 caller_opc;\n@@ -2163,7 +2066,6 @@ struct ice_aqc_txqs_cleanup {\n \tu8 reserved[12];\n };\n \n-\n /* Move / Reconfigure Tx Queues (indirect 0x0C32) */\n struct ice_aqc_move_txqs {\n \tu8 cmd_type;\n@@ -2184,7 +2086,6 @@ struct ice_aqc_move_txqs {\n \t__le32 addr_low;\n };\n \n-\n /* This is the descriptor of each queue entry for the move Tx LAN Queues\n * command (0x0C32).\n */\n@@ -2195,15 +2096,12 @@ struct ice_aqc_move_txqs_elem {\n \t__le32 q_teid;\n };\n \n-\n struct ice_aqc_move_txqs_data {\n \t__le32 src_teid;\n \t__le32 dest_teid;\n \tstruct ice_aqc_move_txqs_elem txqs[1];\n };\n \n-\n-\n /* Download Package (indirect 0x0C40) */\n /* Also used for Update Package (indirect 0x0C42) */\n struct ice_aqc_download_pkg {\n@@ -2255,9 +2153,6 @@ struct ice_aqc_get_pkg_info_resp {\n \tstruct ice_aqc_get_pkg_info pkg_info[1];\n };\n \n-\n-\n-\n /* Lan Queue Overflow Event (direct, 0x1001) */\n struct ice_aqc_event_lan_overflow {\n \t__le32 prtdcb_ruptq;\n@@ -2265,9 +2160,6 @@ struct ice_aqc_event_lan_overflow {\n \tu8 reserved[8];\n };\n \n-\n-\n-\n /**\n * struct ice_aq_desc - Admin Queue (AQ) descriptor\n * @flags: ICE_AQ_FLAG_* flags\n@@ -2361,7 +2253,6 @@ struct ice_aq_desc {\n \t} params;\n };\n \n-\n /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */\n #define ICE_AQ_LG_BUF\t512\n \n@@ -2572,8 +2463,6 @@ enum ice_adminq_opc {\n \tice_aqc_opc_update_pkg\t\t\t\t= 0x0C42,\n \tice_aqc_opc_get_pkg_info_list\t\t\t= 0x0C43,\n \n-\n-\n \t/* Standalone Commands/Events */\n \tice_aqc_opc_event_lan_overflow\t\t\t= 0x1001,\n };\ndiff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h\nindex f0aa8ce88..32f64cac0 100644\n--- a/drivers/net/ice/base/ice_bitops.h\n+++ b/drivers/net/ice/base/ice_bitops.h\n@@ -8,7 +8,6 @@\n /* Define the size of the bitmap chunk */\n typedef u32 ice_bitmap_t;\n \n-\n /* Number of bits per bitmap chunk */\n #define BITS_PER_CHUNK\t\t(BITS_PER_BYTE * sizeof(ice_bitmap_t))\n /* Determine which chunk a bit belongs in */\n@@ -372,5 +371,4 @@ ice_cmp_bitmap(ice_bitmap_t *bmp1, ice_bitmap_t *bmp2, u16 size)\n \treturn true;\n }\n \n-\n #endif /* _ICE_BITOPS_H_ */\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 11e902ea1..16b91dc12 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -11,7 +11,6 @@\n \n #define ICE_PF_RESET_WAIT_COUNT\t200\n \n-\n /**\n * ice_set_mac_type - Sets MAC type\n * @hw: pointer to the HW structure\n@@ -41,7 +40,6 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw)\n \treturn status;\n }\n \n-\n /**\n * ice_clear_pf_cfg - Clear PF configuration\n * @hw: pointer to the hardware structure\n@@ -113,7 +111,6 @@ ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,\n \t\t\t\t ETH_ALEN, ICE_DMA_TO_NONDMA);\n \t\t\tbreak;\n \t\t}\n-\n \treturn ICE_SUCCESS;\n }\n \n@@ -533,7 +530,6 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)\n \tice_free(hw, sw);\n }\n \n-\n /**\n * ice_get_itr_intrl_gran\n * @hw: pointer to the HW struct\n@@ -598,7 +594,6 @@ void ice_print_rollback_msg(struct ice_hw *hw)\n \t\t\t &ver_lo);\n \tSNPRINTF(nvm_str, sizeof(nvm_str), \"%x.%02x 0x%x %d.%d.%d\", ver_hi,\n \t\t ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);\n-\n \tice_warn(hw,\n \t\t \"Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\",\n \t\t nvm_str, hw->fw_maj_ver, hw->fw_min_ver);\n@@ -617,7 +612,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \n \tice_debug(hw, ICE_DBG_TRACE, \"%s\\n\", __func__);\n \n-\n \t/* Set MAC type based on DeviceID */\n \tstatus = ice_set_mac_type(hw);\n \tif (status)\n@@ -627,14 +621,12 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \t\t\t PF_FUNC_RID_FUNCTION_NUMBER_M) >>\n \t\tPF_FUNC_RID_FUNCTION_NUMBER_S;\n \n-\n \tstatus = ice_reset(hw, ICE_RESET_PFR);\n \tif (status)\n \t\treturn status;\n \n \tice_get_itr_intrl_gran(hw);\n \n-\n \tstatus = ice_create_all_ctrlq(hw);\n \tif (status)\n \t\tgoto err_unroll_cqinit;\n@@ -686,7 +678,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \t\tgoto err_unroll_alloc;\n \t}\n \n-\n \t/* Initialize port_info struct with scheduler data */\n \tstatus = ice_sched_init_port(hw->port_info);\n \tif (status)\n@@ -725,7 +716,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \tif (status)\n \t\tgoto err_unroll_sched;\n \n-\n \t/* Get MAC information */\n \t/* A single port can report up to two (LAN and WoL) addresses */\n \tmac_buf = ice_calloc(hw, 2,\n@@ -926,7 +916,6 @@ enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)\n \twr32(hw, GLGEN_RTRIG, val);\n \tice_flush(hw);\n \n-\n \t/* wait for the FW to be ready */\n \treturn ice_check_reset(hw);\n }\n@@ -997,8 +986,6 @@ ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,\n \treturn ICE_ERR_DOES_NOT_EXIST;\n }\n \n-\n-\n /**\n * ice_copy_rxq_ctx_to_hw\n * @hw: pointer to the hardware structure\n@@ -1321,7 +1308,6 @@ ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)\n }\n #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */\n \n-\n /* FW Admin Queue command wrappers */\n \n /**\n@@ -2142,7 +2128,6 @@ ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,\n \n \tcmd->flags = flags;\n \n-\n \t/* Prep values for flags, sah, sal */\n \tcmd->sah = HTONS(*((const u16 *)mac_addr));\n \tcmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));\n@@ -2179,7 +2164,6 @@ void ice_clear_pxe_mode(struct ice_hw *hw)\n \t\tice_aq_clear_pxe_mode(hw);\n }\n \n-\n /**\n * ice_get_link_speed_based_on_phy_type - returns link speed\n * @phy_type_low: lower part of phy_type\n@@ -2848,7 +2832,6 @@ ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)\n \treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n }\n \n-\n /**\n * ice_aq_set_port_id_led\n * @pi: pointer to the port information\n@@ -2869,7 +2852,6 @@ ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,\n \n \tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);\n \n-\n \tif (is_orig_mode)\n \t\tcmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;\n \telse\n@@ -3357,7 +3339,6 @@ ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,\n \treturn status;\n }\n \n-\n /* End of FW Admin Queue command wrappers */\n \n /**\n@@ -3581,9 +3562,6 @@ ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n \treturn ICE_SUCCESS;\n }\n \n-\n-\n-\n /**\n * ice_read_byte - read context byte into struct\n * @src_ctx: the context structure to read from\n@@ -4047,8 +4025,6 @@ ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n \t\t\t ICE_SCHED_NODE_OWNER_LAN);\n }\n \n-\n-\n /**\n * ice_replay_pre_init - replay pre initialization\n * @hw: pointer to the HW struct\n@@ -4246,7 +4222,6 @@ ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,\n \tcur_stats->rx_errors += error_cnt;\n }\n \n-\n /**\n * ice_sched_query_elem - query element information from HW\n * @hw: pointer to the HW struct\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex c42c58670..bcb0a999d 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -169,7 +169,6 @@ ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,\n enum ice_status\n ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);\n \n-\n enum ice_status\n ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,\n \t\t struct ice_sq_cd *cd);\n@@ -178,7 +177,6 @@ ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,\n \t\t u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,\n \t\t bool write, struct ice_sq_cd *cd);\n \n-\n enum ice_status\n ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);\n enum ice_status\ndiff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c\nindex 1ea8f3a24..8a65fae40 100644\n--- a/drivers/net/ice/base/ice_controlq.c\n+++ b/drivers/net/ice/base/ice_controlq.c\n@@ -4,7 +4,6 @@\n \n #include \"ice_common.h\"\n \n-\n #define ICE_CQ_INIT_REGS(qinfo, prefix)\t\t\t\t\\\n do {\t\t\t\t\t\t\t\t\\\n \t(qinfo)->sq.head = prefix##_ATQH;\t\t\t\\\n@@ -53,7 +52,6 @@ static void ice_mailbox_init_regs(struct ice_hw *hw)\n \tICE_CQ_INIT_REGS(cq, PF_MBX);\n }\n \n-\n /**\n * ice_check_sq_alive\n * @hw: pointer to the HW struct\n@@ -521,7 +519,6 @@ ice_shutdown_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n \treturn ret_code;\n }\n \n-\n /**\n * ice_init_check_adminq - Check version for Admin Queue to know if its alive\n * @hw: pointer to the hardware structure\n@@ -533,12 +530,10 @@ static enum ice_status ice_init_check_adminq(struct ice_hw *hw)\n \n \tice_debug(hw, ICE_DBG_TRACE, \"%s\\n\", __func__);\n \n-\n \tstatus = ice_aq_get_fw_ver(hw, NULL);\n \tif (status)\n \t\tgoto init_ctrlq_free_rq;\n \n-\n \tif (!ice_aq_ver_check(hw)) {\n \t\tstatus = ICE_ERR_FW_API_VER;\n \t\tgoto init_ctrlq_free_rq;\n@@ -633,7 +628,6 @@ enum ice_status ice_init_all_ctrlq(struct ice_hw *hw)\n \n \tice_debug(hw, ICE_DBG_TRACE, \"%s\\n\", __func__);\n \n-\n \t/* Init FW admin queue */\n \tret_code = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN);\n \tif (ret_code)\n@@ -972,7 +966,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \n \tice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);\n \n-\n \t(cq->sq.next_to_use)++;\n \tif (cq->sq.next_to_use == cq->sq.count)\n \t\tcq->sq.next_to_use = 0;\n@@ -1025,7 +1018,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \n \tice_debug_cq(hw, (void *)desc, buf, buf_size);\n \n-\n \t/* save writeback AQ if requested */\n \tif (details->wb_desc)\n \t\tice_memcpy(details->wb_desc, desc_on_ring,\n@@ -1158,7 +1150,6 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \tice_debug_cq(hw, (void *)desc, e->msg_buf,\n \t\t cq->rq_buf_size);\n \n-\n \t/* Restore the original datalen and buffer address in the desc,\n \t * FW updates datalen to indicate the event message size\n \t */\ndiff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h\nindex b1214f670..8ad7857c8 100644\n--- a/drivers/net/ice/base/ice_controlq.h\n+++ b/drivers/net/ice/base/ice_controlq.h\n@@ -7,7 +7,6 @@\n \n #include \"ice_adminq_cmd.h\"\n \n-\n /* Maximum buffer lengths for all control queue types */\n #define ICE_AQ_MAX_BUF_LEN 4096\n #define ICE_MBXQ_MAX_BUF_LEN 4096\ndiff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h\nindex c9a567fb1..0ff3b9b34 100644\n--- a/drivers/net/ice/base/ice_devids.h\n+++ b/drivers/net/ice/base/ice_devids.h\n@@ -5,7 +5,6 @@\n #ifndef _ICE_DEVIDS_H_\n #define _ICE_DEVIDS_H_\n \n-\n /* Device IDs */\n /* Intel(R) Ethernet Controller E810-C for backplane */\n #define ICE_DEV_ID_E810C_BACKPLANE\t0x1591\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex 4ad816874..05cd39b17 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -808,7 +808,6 @@ ice_aq_download_pkg(struct ice_hw *hw, struct ice_buf_hdr *pkg_buf,\n \treturn status;\n }\n \n-\n /**\n * ice_aq_update_pkg\n * @hw: pointer to the hardware structure\n@@ -1180,7 +1179,6 @@ static enum ice_status ice_get_pkg_info(struct ice_hw *hw)\n \treturn status;\n }\n \n-\n /**\n * ice_verify_pkg - verify package\n * @pkg: pointer to the package buffer\n@@ -2084,7 +2082,6 @@ ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u8 fv_idx,\n \n /* PTG Management */\n \n-\n /**\n * ice_ptg_find_ptype - Search for packet type group using packet type (ptype)\n * @hw: pointer to the hardware structure\n@@ -2121,7 +2118,6 @@ void ice_ptg_alloc_val(struct ice_hw *hw, enum ice_block blk, u8 ptg)\n \thw->blk[blk].xlt1.ptg_tbl[ptg].in_use = true;\n }\n \n-\n /**\n * ice_ptg_remove_ptype - Removes ptype from a particular packet type group\n * @hw: pointer to the hardware structure\n@@ -2315,7 +2311,6 @@ ice_match_prop_lst(struct LIST_HEAD_TYPE *list1, struct LIST_HEAD_TYPE *list2)\n \n /* VSIG Management */\n \n-\n /**\n * ice_vsig_find_vsi - find a VSIG that contains a specified VSI\n * @hw: pointer to the hardware structure\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h\nindex 3b5c1c39a..137eaa7f8 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.h\n+++ b/drivers/net/ice/base/ice_flex_pipe.h\n@@ -46,7 +46,6 @@ bool ice_tunnel_port_in_use(struct ice_hw *hw, u16 port, u16 *index);\n bool\n ice_tunnel_get_type(struct ice_hw *hw, u16 port, enum ice_tunnel_type *type);\n \n-\n /* XLT2/VSI group functions */\n enum ice_status\n ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig);\ndiff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h\nindex 6f227adb8..92d432044 100644\n--- a/drivers/net/ice/base/ice_hw_autogen.h\n+++ b/drivers/net/ice/base/ice_hw_autogen.h\n@@ -6,8 +6,6 @@\n #ifndef _ICE_HW_AUTOGEN_H_\n #define _ICE_HW_AUTOGEN_H_\n \n-\n-\n #define GL_RDPU_CNTRL\t\t\t\t0x00052054 /* Reset Source: CORER */\n #define GL_RDPU_CNTRL_RX_PAD_EN_S\t\t0\n #define GL_RDPU_CNTRL_RX_PAD_EN_M\t\tBIT(0)\ndiff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h\nindex e77d4bf50..a97c63cc9 100644\n--- a/drivers/net/ice/base/ice_lan_tx_rx.h\n+++ b/drivers/net/ice/base/ice_lan_tx_rx.h\n@@ -173,7 +173,6 @@ struct ice_fltr_desc {\n \t\t\t(0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)\n #define ICE_FXD_FLTR_QW1_FDID_ZERO\t0x0ULL\n \n-\n enum ice_rx_desc_status_bits {\n \t/* Note: These are predefined bit offsets */\n \tICE_RX_DESC_STATUS_DD_S\t\t\t= 0,\n@@ -204,7 +203,6 @@ enum ice_rx_desc_status_bits {\n #define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S\n #define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S)\n \n-\n enum ice_rx_desc_fltstat_values {\n \tICE_RX_DESC_FLTSTAT_NO_DATA\t= 0,\n \tICE_RX_DESC_FLTSTAT_RSV_FD_ID\t= 1, /* 16byte desc? FD_ID : RSV */\n@@ -212,7 +210,6 @@ enum ice_rx_desc_fltstat_values {\n \tICE_RX_DESC_FLTSTAT_RSS_HASH\t= 3,\n };\n \n-\n #define ICE_RXD_QW1_ERROR_S\t19\n #define ICE_RXD_QW1_ERROR_M\t\t(0xFFUL << ICE_RXD_QW1_ERROR_S)\n \n@@ -310,7 +307,6 @@ enum ice_rx_ptype_payload_layer {\n \tICE_RX_PTYPE_PAYLOAD_LAYER_PAY4\t= 3,\n };\n \n-\n #define ICE_RXD_QW1_LEN_PBUF_S\t38\n #define ICE_RXD_QW1_LEN_PBUF_M\t(0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S)\n \n@@ -320,7 +316,6 @@ enum ice_rx_ptype_payload_layer {\n #define ICE_RXD_QW1_LEN_SPH_S\t63\n #define ICE_RXD_QW1_LEN_SPH_M\tBIT_ULL(ICE_RXD_QW1_LEN_SPH_S)\n \n-\n enum ice_rx_desc_ext_status_bits {\n \t/* Note: These are predefined bit offsets */\n \tICE_RX_DESC_EXT_STATUS_L2TAG2P_S\t= 0,\n@@ -331,7 +326,6 @@ enum ice_rx_desc_ext_status_bits {\n \tICE_RX_DESC_EXT_STATUS_PELONGB_S\t= 11,\n };\n \n-\n enum ice_rx_desc_pe_status_bits {\n \t/* Note: These are predefined bit offsets */\n \tICE_RX_DESC_PE_STATUS_QPID_S\t\t= 0, /* 18 BITS */\n@@ -352,7 +346,6 @@ enum ice_rx_desc_pe_status_bits {\n #define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M\t\\\n \t\t\t(0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S)\n \n-\n #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S\t19\n #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M\t\\\n \t\t\t(0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S)\n@@ -840,7 +833,6 @@ enum ice_rx_flex_desc_exstat_bits {\n \tICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3,\n };\n \n-\n #define ICE_RXQ_CTX_SIZE_DWORDS\t\t8\n #define ICE_RXQ_CTX_SZ\t\t\t(ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))\n #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS\t22\n@@ -1056,7 +1048,6 @@ enum ice_tx_ctx_desc_eipt_offload {\n #define ICE_TXD_CTX_QW0_L4T_CS_S\t23\n #define ICE_TXD_CTX_QW0_L4T_CS_M\tBIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)\n \n-\n #define ICE_LAN_TXQ_MAX_QGRPS\t127\n #define ICE_LAN_TXQ_MAX_QDIS\t1023\n \ndiff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex 66cfec641..e00942528 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -4,7 +4,6 @@\n \n #include \"ice_common.h\"\n \n-\n /**\n * ice_aq_read_nvm\n * @hw: pointer to the HW struct\n@@ -138,7 +137,6 @@ ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)\n \treturn status;\n }\n \n-\n /**\n * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ\n * @hw: pointer to the HW structure\n@@ -354,7 +352,6 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)\n \treturn ICE_SUCCESS;\n }\n \n-\n /**\n * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary\n * @hw: pointer to the HW structure\n@@ -380,7 +377,6 @@ ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)\n \treturn status;\n }\n \n-\n /**\n * ice_nvm_validate_checksum\n * @hw: pointer to the HW struct\ndiff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h\nindex 91f56f3fa..cdb691523 100644\n--- a/drivers/net/ice/base/ice_protocol_type.h\n+++ b/drivers/net/ice/base/ice_protocol_type.h\n@@ -114,7 +114,6 @@ enum ice_prot_id {\n \n #define ICE_VNI_OFFSET\t\t12 /* offset of VNI from ICE_PROT_UDP_OF */\n \n-\n #define ICE_MAC_OFOS_HW\t\t1\n #define ICE_MAC_IL_HW\t\t4\n #define ICE_ETYPE_OL_HW\t\t9\n@@ -148,7 +147,6 @@ struct ice_protocol_entry {\n \tu8 protocol_id;\n };\n \n-\n struct ice_ether_hdr {\n \tu8 dst_addr[ETH_ALEN];\n \tu8 src_addr[ETH_ALEN];\ndiff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nindex 1cfc3bc20..6732e291a 100644\n--- a/drivers/net/ice/base/ice_sched.c\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -4,7 +4,6 @@\n \n #include \"ice_sched.h\"\n \n-\n /**\n * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB\n * @pi: port information structure\n@@ -876,7 +875,6 @@ ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_l2_nodes,\n \treturn ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n }\n \n-\n /**\n * ice_sched_add_elems - add nodes to HW and SW DB\n * @pi: port information structure\n@@ -1366,7 +1364,6 @@ enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw)\n \t\tgoto sched_query_out;\n \t}\n \n-\n sched_query_out:\n \tice_free(hw, buf);\n \treturn status;\n@@ -2021,7 +2018,6 @@ enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle)\n \treturn ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_LAN);\n }\n \n-\n /**\n * ice_sched_is_tree_balanced - Check tree nodes are identical or not\n * @hw: pointer to the HW struct\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex 2437faead..00358e4db 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -6,7 +6,6 @@\n #include \"ice_flex_type.h\"\n #include \"ice_flow.h\"\n \n-\n #define ICE_ETH_DA_OFFSET\t\t0\n #define ICE_ETH_ETHTYPE_OFFSET\t\t12\n #define ICE_ETH_VLAN_TCI_OFFSET\t\t14\n@@ -743,7 +742,6 @@ ice_aq_get_sw_cfg(struct ice_hw *hw, struct ice_aqc_get_sw_cfg_resp *buf,\n \treturn status;\n }\n \n-\n /**\n * ice_alloc_sw - allocate resources specific to switch\n * @hw: pointer to the HW struct\n@@ -1787,13 +1785,11 @@ enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw)\n \t\t}\n \t} while (req_desc && !status);\n \n-\n out:\n \tice_free(hw, (void *)rbuf);\n \treturn status;\n }\n \n-\n /**\n * ice_fill_sw_info - Helper function to populate lb_en and lan_en\n * @hw: pointer to the hardware structure\n@@ -3424,7 +3420,6 @@ ice_remove_eth_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *em_list)\n \treturn ICE_SUCCESS;\n }\n \n-\n /**\n * ice_rem_sw_rule_info\n * @hw: pointer to the hardware structure\n@@ -3823,7 +3818,6 @@ ice_add_to_vsi_fltr_list(struct ice_hw *hw, u16 vsi_handle,\n \treturn status;\n }\n \n-\n /**\n * ice_determine_promisc_mask\n * @fi: filter info to parse\n@@ -4811,8 +4805,6 @@ ice_fill_valid_words(struct ice_adv_lkup_elem *rule,\n \treturn ret_val;\n }\n \n-\n-\n /**\n * ice_create_first_fit_recp_def - Create a recipe grouping\n * @hw: pointer to the hardware structure\ndiff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h\nindex 515ad3bb6..0f0a1e98e 100644\n--- a/drivers/net/ice/base/ice_switch.h\n+++ b/drivers/net/ice/base/ice_switch.h\n@@ -15,7 +15,6 @@\n #define ICE_FLTR_TX BIT(1)\n #define ICE_FLTR_TX_RX (ICE_FLTR_RX | ICE_FLTR_TX)\n \n-\n /* Worst case buffer length for ice_aqc_opc_get_res_alloc */\n #define ICE_MAX_RES_TYPES 0x80\n #define ICE_AQ_GET_RES_ALLOC_BUF_LEN \\\n@@ -391,7 +390,6 @@ enum ice_status\n ice_add_mac_with_counter(struct ice_hw *hw, struct ice_fltr_info *f_info);\n void ice_remove_vsi_fltr(struct ice_hw *hw, u16 vsi_handle);\n \n-\n /* Promisc/defport setup for VSIs */\n enum ice_status\n ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set,\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex deb614e37..150b4c5c5 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -134,10 +134,6 @@ static inline u32 ice_round_to_num(u32 N, u32 R)\n #define __ALWAYS_UNUSED\n #endif\n \n-\n-\n-\n-\n #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \\\n \t(((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \\\n \t ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \\\n@@ -384,7 +380,6 @@ struct ice_hw_common_caps {\n \tu8 proxy_support;\n };\n \n-\n /* Function specific capabilities */\n struct ice_hw_func_caps {\n \tstruct ice_hw_common_caps common_cap;\n@@ -401,7 +396,6 @@ struct ice_hw_dev_caps {\n \tu32 num_funcs;\n };\n \n-\n /* Information about MAC such as address, etc... */\n struct ice_mac_info {\n \tu8 lan_addr[ETH_ALEN];\n@@ -567,7 +561,6 @@ enum ice_rl_type {\n #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)\n #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)\n \n-\n /* The following tree example shows the naming conventions followed under\n * ice_port_info struct for default scheduler tree topology.\n *\n@@ -729,7 +722,6 @@ struct ice_switch_info {\n \tstruct ice_sw_recipe *recp_list;\n };\n \n-\n /* Port hardware description */\n struct ice_hw {\n \tu8 *hw_addr;\n@@ -787,7 +779,6 @@ struct ice_hw {\n \tu8 fw_patch;\t\t/* firmware patch version */\n \tu32 fw_build;\t\t/* firmware build number */\n \n-\n /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL\n * register. Used for determining the ITR/INTRL granularity during\n * initialization.\n", "prefixes": [ "v4", "01/30" ] }