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GET /api/patches/59331/?format=api
{ "id": 59331, "url": "https://patches.dpdk.org/api/patches/59331/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1568789674-11264-1-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1568789674-11264-1-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1568789674-11264-1-git-send-email-viacheslavo@mellanox.com", "date": "2019-09-18T06:54:34", "name": "net/mlx5: fix transmit doorbell register write barrier", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "700ce299007d143c9cf3dda63b5bb65e1d3480c8", "submitter": { "id": 1102, "url": "https://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1568789674-11264-1-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 6430, "url": "https://patches.dpdk.org/api/series/6430/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6430", "date": "2019-09-18T06:54:34", "name": "net/mlx5: fix transmit doorbell register write barrier", "version": 1, "mbox": "https://patches.dpdk.org/series/6430/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/59331/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/59331/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A55F21C00E;\n\tWed, 18 Sep 2019 08:54:38 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id 3C7C61BEF8\n\tfor <dev@dpdk.org>; Wed, 18 Sep 2019 08:54:37 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n\tviacheslavo@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 18 Sep 2019 09:54:35 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n\t[10.210.17.40])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x8I6sZkV026483;\n\tWed, 18 Sep 2019 09:54:35 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n\tby pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id\n\tx8I6sZH1011304; Wed, 18 Sep 2019 06:54:35 GMT", "(from viacheslavo@localhost)\n\tby pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id x8I6sZgr011303; \n\tWed, 18 Sep 2019 06:54:35 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n\tviacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com", "Date": "Wed, 18 Sep 2019 06:54:34 +0000", "Message-Id": "<1568789674-11264-1-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "Subject": "[dpdk-dev] [PATCH] net/mlx5: fix transmit doorbell register write\n\tbarrier", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The rdma core library can map doorbell register in two ways,\ndepending on the environment variable \"MLX5_SHUT_UP_BF\":\n\n - as regular cached memory, the variable is either missing or\n set to zero. This type of mapping may cause the significant\n doorbell register writing latency and requires explicit\n memory write barrier to mitigate this issue and prevent\n write combining.\n\n - as non-cached memory, the variable is present and set to\n not \"0\" value. This type of mapping may cause performance\n impact under heavy loading conditions but the explicit write\n memory barrier is not required and it may improve core\n performance.\n\nThis patch checks the mapping type and provides the memory\nbarrier after writing to tx doorbell register if it is needed.\nThe mapping type is extracted directly from the uar_mmap_offset\nfield in the queue properties.\n\nFixes: 18a1c20044c0 (\"net/mlx5: implement Tx burst template\")\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/net/mlx5/Makefile | 5 +++++\n drivers/net/mlx5/meson.build | 2 ++\n drivers/net/mlx5/mlx5_defs.h | 8 ++++++++\n drivers/net/mlx5/mlx5_rxtx.c | 17 ++++++++++++++++-\n drivers/net/mlx5/mlx5_rxtx.h | 1 +\n drivers/net/mlx5/mlx5_txq.c | 17 ++++++++++++++++-\n 6 files changed, 48 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/Makefile b/drivers/net/mlx5/Makefile\nindex d89a7b5..7100fa3 100644\n--- a/drivers/net/mlx5/Makefile\n+++ b/drivers/net/mlx5/Makefile\n@@ -189,6 +189,11 @@ mlx5_autoconf.h.new: $(RTE_SDK)/buildtools/auto-config-h.sh\n \t\tfunc mlx5dv_dr_action_create_dest_devx_tir \\\n \t\t$(AUTOCONF_OUTPUT)\n \t$Q sh -- '$<' '$@' \\\n+\t\tHAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD \\\n+\t\tinfiniband/mlx5dv.h \\\n+\t\tenum MLX5_MMAP_GET_NC_PAGES_CMD \\\n+\t\t$(AUTOCONF_OUTPUT)\n+\t$Q sh -- '$<' '$@' \\\n \t\tHAVE_ETHTOOL_LINK_MODE_25G \\\n \t\t/usr/include/linux/ethtool.h \\\n \t\tenum ETHTOOL_LINK_MODE_25000baseCR_Full_BIT \\\ndiff --git a/drivers/net/mlx5/meson.build b/drivers/net/mlx5/meson.build\nindex fb764fa..e56e018 100644\n--- a/drivers/net/mlx5/meson.build\n+++ b/drivers/net/mlx5/meson.build\n@@ -128,6 +128,8 @@ if build\n \t\t'mlx5dv_devx_obj_query_async' ],\n \t\t[ 'HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR', 'infiniband/mlx5dv.h',\n \t\t'mlx5dv_dr_action_create_dest_devx_tir' ],\n+\t\t[ 'HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD', 'infiniband/mlx5dv.h',\n+\t\t'MLX5_MMAP_GET_NC_PAGES_CMD' ],\n \t\t[ 'HAVE_MLX5DV_DR', 'infiniband/mlx5dv.h',\n \t\t'MLX5DV_DR_DOMAIN_TYPE_NIC_RX' ],\n \t\t[ 'HAVE_MLX5DV_DR_ESWITCH', 'infiniband/mlx5dv.h',\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex d7440fd..03a8086 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -115,6 +115,14 @@\n #define MLX5_UAR_PAGE_NUM_MAX 64\n #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1)\n \n+/* Fields of memory mapping type in offset parameter of mmap() */\n+#define MLX5_UAR_MMAP_CMD_SHIFT 8\n+#define MLX5_UAR_MMAP_CMD_MASK 0xff\n+\n+#ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD\n+#define MLX5_MMAP_GET_NC_PAGES_CMD 3\n+#endif\n+\n /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */\n #define MLX5_MPRQ_STRIDE_NUM_N 6U\n \ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex f540977..fa3aa15 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -4730,8 +4730,23 @@ enum mlx5_txcmp_code {\n \t * to improve latencies. The pure software related data treatment\n \t * can be completed after doorbell. Tx CQEs for this SQ are\n \t * processed in this thread only by the polling.\n+\t *\n+\t * The rdma core library can map doorbell register in two ways,\n+\t * depending on the environment variable \"MLX5_SHUT_UP_BF\":\n+\t *\n+\t * - as regular cached memory, the variable is either missing or\n+\t * set to zero. This type of mapping may cause the significant\n+\t * doorbell register writing latency and requires explicit\n+\t * memory write barrier to mitigate this issue and prevent\n+\t * write combining.\n+\t *\n+\t * - as non-cached memory, the variable is present and set to\n+\t * not \"0\" value. This type of mapping may cause performance\n+\t * impact under heavy loading conditions but the explicit write\n+\t * memory barrier is not required and it may improve core\n+\t * performance.\n \t */\n-\tmlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, 0);\n+\tmlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc);\n \t/* Not all of the mbufs may be stored into elts yet. */\n \tpart = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;\n \tif (!MLX5_TXOFF_CONFIG(INLINE) && part) {\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 4f73d91..ae3a763 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -277,6 +277,7 @@ struct mlx5_txq_data {\n \t/* When set TX offload for tunneled packets are supported. */\n \tuint16_t swp_en:1; /* Whether SW parser is enabled. */\n \tuint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */\n+\tuint16_t db_nc:1; /* Doorbell mapped to non-cached region. */\n \tuint16_t inlen_send; /* Ordinary send data inline size. */\n \tuint16_t inlen_empw; /* eMPW max packet size to inline. */\n \tuint16_t inlen_mode; /* Minimal data length to inline. */\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 2b7d6c0..7ec2ef3 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -18,6 +18,7 @@\n #pragma GCC diagnostic ignored \"-Wpedantic\"\n #endif\n #include <infiniband/verbs.h>\n+#include <infiniband/mlx5dv.h>\n #ifdef PEDANTIC\n #pragma GCC diagnostic error \"-Wpedantic\"\n #endif\n@@ -241,14 +242,21 @@\n {\n \tstruct mlx5_priv *priv = txq_ctrl->priv;\n \tstruct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));\n+\tconst size_t page_size = sysconf(_SC_PAGESIZE);\n+\tunsigned int cmd;\n #ifndef RTE_ARCH_64\n \tunsigned int lock_idx;\n-\tconst size_t page_size = sysconf(_SC_PAGESIZE);\n #endif\n \n \tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \tassert(ppriv);\n \tppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;\n+\t/* Check the doorbell register mapping type. */\n+\tcmd = txq_ctrl->uar_mmap_offset / page_size;\n+\tcmd >>= MLX5_UAR_MMAP_CMD_SHIFT;\n+\tcmd &= MLX5_UAR_MMAP_CMD_MASK;\n+\tif (cmd == MLX5_MMAP_GET_NC_PAGES_CMD)\n+\t\ttxq_ctrl->txq.db_nc = 1;\n #ifndef RTE_ARCH_64\n \t/* Assign an UAR lock according to UAR page number */\n \tlock_idx = (txq_ctrl->uar_mmap_offset / page_size) &\n@@ -281,6 +289,7 @@\n \tuintptr_t uar_va;\n \tuintptr_t offset;\n \tconst size_t page_size = sysconf(_SC_PAGESIZE);\n+\tunsigned int cmd;\n \n \tassert(ppriv);\n \t/*\n@@ -300,6 +309,12 @@\n \t}\n \taddr = RTE_PTR_ADD(addr, offset);\n \tppriv->uar_table[txq->idx] = addr;\n+\t/* Check the doorbell register mapping type. */\n+\tcmd = txq_ctrl->uar_mmap_offset / page_size;\n+\tcmd >>= MLX5_UAR_MMAP_CMD_SHIFT;\n+\tcmd &= MLX5_UAR_MMAP_CMD_MASK;\n+\tif (cmd == MLX5_MMAP_GET_NC_PAGES_CMD)\n+\t\ttxq_ctrl->txq.db_nc = 1;\n \treturn 0;\n }\n \n", "prefixes": [] }