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GET /api/patches/59162/?format=api
{ "id": 59162, "url": "https://patches.dpdk.org/api/patches/59162/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190912152416.2990-2-shshaikh@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190912152416.2990-2-shshaikh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190912152416.2990-2-shshaikh@marvell.com", "date": "2019-09-12T15:24:12", "name": "[v2,1/5] net/qede: refactor Rx and Tx queue setup", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "95a7302261c6434b23711e2287f91918dfbaa239", "submitter": { "id": 1210, "url": "https://patches.dpdk.org/api/people/1210/?format=api", "name": "Shahed Shaikh", "email": "shshaikh@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190912152416.2990-2-shshaikh@marvell.com/mbox/", "series": [ { "id": 6390, "url": "https://patches.dpdk.org/api/series/6390/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6390", "date": "2019-09-12T15:24:11", "name": "net/qede: fixes and enhancement", "version": 2, "mbox": "https://patches.dpdk.org/series/6390/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/59162/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/59162/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EDB641EAC5;\n\tThu, 12 Sep 2019 17:24:38 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 072751EAAE;\n\tThu, 12 Sep 2019 17:24:36 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx8CFMDji015760; Thu, 12 Sep 2019 08:24:36 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2uvc2jy6av-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 12 Sep 2019 08:24:36 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 12 Sep 2019 08:24:34 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 12 Sep 2019 08:24:34 -0700", "from dut1171.mv.qlogic.com (unknown [10.112.88.18])\n\tby maili.marvell.com (Postfix) with ESMTP id 14A553F703F;\n\tThu, 12 Sep 2019 08:24:34 -0700 (PDT)", "from dut1171.mv.qlogic.com (localhost [127.0.0.1])\n\tby dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id x8CFOXn1003063;\n\tThu, 12 Sep 2019 08:24:33 -0700", "(from root@localhost)\n\tby dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id x8CFOXTX003062;\n\tThu, 12 Sep 2019 08:24:33 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-type; s=pfpt0818;\n\tbh=gEuR/mN/5gndkCN2lTPWktarWeZdA7FTy47IJIGoTrg=; \n\tb=s3C+9sTmHo7QXlqPLgxffOBjFLViSIbGYI+6rqaWWoxDWao5HoFhID4DvZeqgPYNdgZv\n\tz3j38v/8Bri3AmqNLL1fi0aKbf4v3MFHuRsTu+XqJwG3Zxd79Q5tYeM7dAIhIYDuJYsq\n\t3cV3r4Gq+KbT+KS+SaeOvEhJNMcfzKI++YdpvDY2G7oVrAcpINnVrKS6ZN9X41UXxrSx\n\tXFf9XDlhHxGLBXwZrhVV7kTE0frZ7r1gsqbuvViZKpt6Ycb5TBoYGo8+2AnVLKpNEYL4\n\twDAuUnRQK6rU1SHG4ZWG8OInyNl59pBKTToadJaUhDRGEW1nKPLcQs5j8LvOql4cUlIc\n\tUg== ", "From": "Shahed Shaikh <shshaikh@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<rmody@marvell.com>, <jerinj@marvell.com>,\n\t<GR-Everest-DPDK-Dev@marvell.com>, <stable@dpdk.org>", "Date": "Thu, 12 Sep 2019 08:24:12 -0700", "Message-ID": "<20190912152416.2990-2-shshaikh@marvell.com>", "X-Mailer": "git-send-email 2.12.0", "In-Reply-To": "<20190912152416.2990-1-shshaikh@marvell.com>", "References": "<20190912152416.2990-1-shshaikh@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.70,1.0.8\n\tdefinitions=2019-09-12_08:2019-09-11,2019-09-12 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 1/5] net/qede: refactor Rx and Tx queue setup", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch refactors Rx and Tx queue setup flow required to allow\nodd number of queues to be configured in next patch.\n\nThis is the first patch of the series required to fix an issue\nwhere qede port initialization in ovs-dpdk fails due to 1 Rx/Tx queue\nconfiguration. Detailed explaination is given in next patch.\n\nFixes: 2af14ca79c0a (\"net/qede: support 100G\")\nCc: stable@dpdk.org\n\nSigned-off-by: Shahed Shaikh <shshaikh@marvell.com>\n---\n drivers/net/qede/qede_rxtx.c | 228 ++++++++++++++++++++++-------------\n 1 file changed, 141 insertions(+), 87 deletions(-)", "diff": "diff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c\nindex c38cbb905..cb8ac9bf6 100644\n--- a/drivers/net/qede/qede_rxtx.c\n+++ b/drivers/net/qede/qede_rxtx.c\n@@ -124,36 +124,20 @@ qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,\n \treturn QEDE_FLOOR_TO_CACHE_LINE_SIZE(rx_buf_size);\n }\n \n-int\n-qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n-\t\t uint16_t nb_desc, unsigned int socket_id,\n-\t\t __rte_unused const struct rte_eth_rxconf *rx_conf,\n-\t\t struct rte_mempool *mp)\n+static struct qede_rx_queue *\n+qede_alloc_rx_queue_mem(struct rte_eth_dev *dev,\n+\t\t\tuint16_t queue_idx,\n+\t\t\tuint16_t nb_desc,\n+\t\t\tunsigned int socket_id,\n+\t\t\tstruct rte_mempool *mp,\n+\t\t\tuint16_t bufsz)\n {\n \tstruct qede_dev *qdev = QEDE_INIT_QDEV(dev);\n \tstruct ecore_dev *edev = QEDE_INIT_EDEV(qdev);\n-\tstruct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;\n \tstruct qede_rx_queue *rxq;\n-\tuint16_t max_rx_pkt_len;\n-\tuint16_t bufsz;\n \tsize_t size;\n \tint rc;\n \n-\tPMD_INIT_FUNC_TRACE(edev);\n-\n-\t/* Note: Ring size/align is controlled by struct rte_eth_desc_lim */\n-\tif (!rte_is_power_of_2(nb_desc)) {\n-\t\tDP_ERR(edev, \"Ring size %u is not power of 2\\n\",\n-\t\t\t nb_desc);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Free memory prior to re-allocation if needed... */\n-\tif (dev->data->rx_queues[queue_idx] != NULL) {\n-\t\tqede_rx_queue_release(dev->data->rx_queues[queue_idx]);\n-\t\tdev->data->rx_queues[queue_idx] = NULL;\n-\t}\n-\n \t/* First allocate the rx queue data structure */\n \trxq = rte_zmalloc_socket(\"qede_rx_queue\", sizeof(struct qede_rx_queue),\n \t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n@@ -161,7 +145,7 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \tif (!rxq) {\n \t\tDP_ERR(edev, \"Unable to allocate memory for rxq on socket %u\",\n \t\t\t socket_id);\n-\t\treturn -ENOMEM;\n+\t\treturn NULL;\n \t}\n \n \trxq->qdev = qdev;\n@@ -170,27 +154,8 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \trxq->queue_id = queue_idx;\n \trxq->port_id = dev->data->port_id;\n \n-\tmax_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;\n-\n-\t/* Fix up RX buffer size */\n-\tbufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;\n-\t/* cache align the mbuf size to simplfy rx_buf_size calculation */\n-\tbufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);\n-\tif ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)\t||\n-\t (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {\n-\t\tif (!dev->data->scattered_rx) {\n-\t\t\tDP_INFO(edev, \"Forcing scatter-gather mode\\n\");\n-\t\t\tdev->data->scattered_rx = 1;\n-\t\t}\n-\t}\n-\n-\trc = qede_calc_rx_buf_size(dev, bufsz, max_rx_pkt_len);\n-\tif (rc < 0) {\n-\t\trte_free(rxq);\n-\t\treturn rc;\n-\t}\n \n-\trxq->rx_buf_size = rc;\n+\trxq->rx_buf_size = bufsz;\n \n \tDP_INFO(edev, \"mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\\n\",\n \t\tqdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);\n@@ -203,7 +168,7 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\tDP_ERR(edev, \"Memory allocation fails for sw_rx_ring on\"\n \t\t \" socket %u\\n\", socket_id);\n \t\trte_free(rxq);\n-\t\treturn -ENOMEM;\n+\t\treturn NULL;\n \t}\n \n \t/* Allocate FW Rx ring */\n@@ -221,7 +186,7 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\t \" on socket %u\\n\", socket_id);\n \t\trte_free(rxq->sw_rx_ring);\n \t\trte_free(rxq);\n-\t\treturn -ENOMEM;\n+\t\treturn NULL;\n \t}\n \n \t/* Allocate FW completion ring */\n@@ -240,14 +205,71 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\tqdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);\n \t\trte_free(rxq->sw_rx_ring);\n \t\trte_free(rxq);\n-\t\treturn -ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\treturn rxq;\n+}\n+\n+int\n+qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qid,\n+\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t __rte_unused const struct rte_eth_rxconf *rx_conf,\n+\t\t struct rte_mempool *mp)\n+{\n+\tstruct qede_dev *qdev = QEDE_INIT_QDEV(dev);\n+\tstruct ecore_dev *edev = QEDE_INIT_EDEV(qdev);\n+\tstruct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;\n+\tstruct qede_rx_queue *rxq;\n+\tuint16_t max_rx_pkt_len;\n+\tuint16_t bufsz;\n+\tint rc;\n+\n+\tPMD_INIT_FUNC_TRACE(edev);\n+\n+\t/* Note: Ring size/align is controlled by struct rte_eth_desc_lim */\n+\tif (!rte_is_power_of_2(nb_desc)) {\n+\t\tDP_ERR(edev, \"Ring size %u is not power of 2\\n\",\n+\t\t\t nb_desc);\n+\t\treturn -EINVAL;\n \t}\n \n-\tdev->data->rx_queues[queue_idx] = rxq;\n-\tqdev->fp_array[queue_idx].rxq = rxq;\n+\t/* Free memory prior to re-allocation if needed... */\n+\tif (dev->data->rx_queues[qid] != NULL) {\n+\t\tqede_rx_queue_release(dev->data->rx_queues[qid]);\n+\t\tdev->data->rx_queues[qid] = NULL;\n+\t}\n+\n+\tmax_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;\n+\n+\t/* Fix up RX buffer size */\n+\tbufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;\n+\t/* cache align the mbuf size to simplfy rx_buf_size calculation */\n+\tbufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);\n+\tif ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)\t||\n+\t (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {\n+\t\tif (!dev->data->scattered_rx) {\n+\t\t\tDP_INFO(edev, \"Forcing scatter-gather mode\\n\");\n+\t\t\tdev->data->scattered_rx = 1;\n+\t\t}\n+\t}\n+\n+\trc = qede_calc_rx_buf_size(dev, bufsz, max_rx_pkt_len);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\tbufsz = rc;\n+\n+\trxq = qede_alloc_rx_queue_mem(dev, qid, nb_desc,\n+\t\t\t\t socket_id, mp, bufsz);\n+\tif (!rxq)\n+\t\treturn -ENOMEM;\n+\n+\tdev->data->rx_queues[qid] = rxq;\n+\tqdev->fp_array[qid].rxq = rxq;\n \n \tDP_INFO(edev, \"rxq %d num_desc %u rx_buf_size=%u socket %u\\n\",\n-\t\t queue_idx, nb_desc, rxq->rx_buf_size, socket_id);\n+\t\t qid, nb_desc, rxq->rx_buf_size, socket_id);\n \n \treturn 0;\n }\n@@ -278,6 +300,17 @@ static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)\n \t}\n }\n \n+static void _qede_rx_queue_release(struct qede_dev *qdev,\n+\t\t\t\t struct ecore_dev *edev,\n+\t\t\t\t struct qede_rx_queue *rxq)\n+{\n+\tqede_rx_queue_release_mbufs(rxq);\n+\tqdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);\n+\tqdev->ops->common->chain_free(edev, &rxq->rx_comp_ring);\n+\trte_free(rxq->sw_rx_ring);\n+\trte_free(rxq);\n+}\n+\n void qede_rx_queue_release(void *rx_queue)\n {\n \tstruct qede_rx_queue *rxq = rx_queue;\n@@ -288,11 +321,7 @@ void qede_rx_queue_release(void *rx_queue)\n \t\tqdev = rxq->qdev;\n \t\tedev = QEDE_INIT_EDEV(qdev);\n \t\tPMD_INIT_FUNC_TRACE(edev);\n-\t\tqede_rx_queue_release_mbufs(rxq);\n-\t\tqdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);\n-\t\tqdev->ops->common->chain_free(edev, &rxq->rx_comp_ring);\n-\t\trte_free(rxq->sw_rx_ring);\n-\t\trte_free(rxq);\n+\t\t_qede_rx_queue_release(qdev, edev, rxq);\n \t}\n }\n \n@@ -306,8 +335,8 @@ static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n \tint hwfn_index;\n \tint rc;\n \n-\tif (rx_queue_id < eth_dev->data->nb_rx_queues) {\n-\t\trxq = eth_dev->data->rx_queues[rx_queue_id];\n+\tif (rx_queue_id < qdev->num_rx_queues) {\n+\t\trxq = qdev->fp_array[rx_queue_id].rxq;\n \t\thwfn_index = rx_queue_id % edev->num_hwfns;\n \t\tp_hwfn = &edev->hwfns[hwfn_index];\n \t\trc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,\n@@ -329,32 +358,18 @@ static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n \treturn rc;\n }\n \n-int\n-qede_tx_queue_setup(struct rte_eth_dev *dev,\n-\t\t uint16_t queue_idx,\n-\t\t uint16_t nb_desc,\n-\t\t unsigned int socket_id,\n-\t\t const struct rte_eth_txconf *tx_conf)\n+static struct qede_tx_queue *\n+qede_alloc_tx_queue_mem(struct rte_eth_dev *dev,\n+\t\t\tuint16_t queue_idx,\n+\t\t\tuint16_t nb_desc,\n+\t\t\tunsigned int socket_id,\n+\t\t\tconst struct rte_eth_txconf *tx_conf)\n {\n \tstruct qede_dev *qdev = dev->data->dev_private;\n \tstruct ecore_dev *edev = &qdev->edev;\n \tstruct qede_tx_queue *txq;\n \tint rc;\n \n-\tPMD_INIT_FUNC_TRACE(edev);\n-\n-\tif (!rte_is_power_of_2(nb_desc)) {\n-\t\tDP_ERR(edev, \"Ring size %u is not power of 2\\n\",\n-\t\t nb_desc);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Free memory prior to re-allocation if needed... */\n-\tif (dev->data->tx_queues[queue_idx] != NULL) {\n-\t\tqede_tx_queue_release(dev->data->tx_queues[queue_idx]);\n-\t\tdev->data->tx_queues[queue_idx] = NULL;\n-\t}\n-\n \ttxq = rte_zmalloc_socket(\"qede_tx_queue\", sizeof(struct qede_tx_queue),\n \t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n \n@@ -362,7 +377,7 @@ qede_tx_queue_setup(struct rte_eth_dev *dev,\n \t\tDP_ERR(edev,\n \t\t \"Unable to allocate memory for txq on socket %u\",\n \t\t socket_id);\n-\t\treturn -ENOMEM;\n+\t\treturn NULL;\n \t}\n \n \ttxq->nb_tx_desc = nb_desc;\n@@ -382,7 +397,7 @@ qede_tx_queue_setup(struct rte_eth_dev *dev,\n \t\t \"Unable to allocate memory for txbd ring on socket %u\",\n \t\t socket_id);\n \t\tqede_tx_queue_release(txq);\n-\t\treturn -ENOMEM;\n+\t\treturn NULL;\n \t}\n \n \t/* Allocate software ring */\n@@ -397,7 +412,7 @@ qede_tx_queue_setup(struct rte_eth_dev *dev,\n \t\t socket_id);\n \t\tqdev->ops->common->chain_free(edev, &txq->tx_pbl);\n \t\tqede_tx_queue_release(txq);\n-\t\treturn -ENOMEM;\n+\t\treturn NULL;\n \t}\n \n \ttxq->queue_id = queue_idx;\n@@ -408,12 +423,44 @@ qede_tx_queue_setup(struct rte_eth_dev *dev,\n \t tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :\n \t (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);\n \n-\tdev->data->tx_queues[queue_idx] = txq;\n-\tqdev->fp_array[queue_idx].txq = txq;\n-\n \tDP_INFO(edev,\n \t\t \"txq %u num_desc %u tx_free_thresh %u socket %u\\n\",\n \t\t queue_idx, nb_desc, txq->tx_free_thresh, socket_id);\n+\treturn txq;\n+}\n+\n+int\n+qede_tx_queue_setup(struct rte_eth_dev *dev,\n+\t\t uint16_t queue_idx,\n+\t\t uint16_t nb_desc,\n+\t\t unsigned int socket_id,\n+\t\t const struct rte_eth_txconf *tx_conf)\n+{\n+\tstruct qede_dev *qdev = dev->data->dev_private;\n+\tstruct ecore_dev *edev = &qdev->edev;\n+\tstruct qede_tx_queue *txq;\n+\n+\tPMD_INIT_FUNC_TRACE(edev);\n+\n+\tif (!rte_is_power_of_2(nb_desc)) {\n+\t\tDP_ERR(edev, \"Ring size %u is not power of 2\\n\",\n+\t\t nb_desc);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Free memory prior to re-allocation if needed... */\n+\tif (dev->data->tx_queues[queue_idx] != NULL) {\n+\t\tqede_tx_queue_release(dev->data->tx_queues[queue_idx]);\n+\t\tdev->data->tx_queues[queue_idx] = NULL;\n+\t}\n+\n+\ttxq = qede_alloc_tx_queue_mem(dev, queue_idx, nb_desc,\n+\t\t\t\t socket_id, tx_conf);\n+\tif (!txq)\n+\t\treturn -ENOMEM;\n+\n+\tdev->data->tx_queues[queue_idx] = txq;\n+\tqdev->fp_array[queue_idx].txq = txq;\n \n \treturn 0;\n }\n@@ -443,6 +490,16 @@ static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)\n \t}\n }\n \n+static void _qede_tx_queue_release(struct qede_dev *qdev,\n+\t\t\t\t struct ecore_dev *edev,\n+\t\t\t\t struct qede_tx_queue *txq)\n+{\n+\tqede_tx_queue_release_mbufs(txq);\n+\tqdev->ops->common->chain_free(edev, &txq->tx_pbl);\n+\trte_free(txq->sw_tx_ring);\n+\trte_free(txq);\n+}\n+\n void qede_tx_queue_release(void *tx_queue)\n {\n \tstruct qede_tx_queue *txq = tx_queue;\n@@ -453,10 +510,7 @@ void qede_tx_queue_release(void *tx_queue)\n \t\tqdev = txq->qdev;\n \t\tedev = QEDE_INIT_EDEV(qdev);\n \t\tPMD_INIT_FUNC_TRACE(edev);\n-\t\tqede_tx_queue_release_mbufs(txq);\n-\t\tqdev->ops->common->chain_free(edev, &txq->tx_pbl);\n-\t\trte_free(txq->sw_tx_ring);\n-\t\trte_free(txq);\n+\t\t_qede_tx_queue_release(qdev, edev, txq);\n \t}\n }\n \n", "prefixes": [ "v2", "1/5" ] }