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GET /api/patches/5871/?format=api
{ "id": 5871, "url": "https://patches.dpdk.org/api/patches/5871/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1435367948-20240-3-git-send-email-liang-min.wang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1435367948-20240-3-git-send-email-liang-min.wang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1435367948-20240-3-git-send-email-liang-min.wang@intel.com", "date": "2015-06-27T01:19:05", "name": "[dpdk-dev,v9,2/5] ixgbe: add ops to support ethtool ops", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d999fae621b0714a398da636f556c74dbd2cad96", "submitter": { "id": 250, "url": "https://patches.dpdk.org/api/people/250/?format=api", "name": "Liang-Min Larry Wang", "email": "liang-min.wang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1435367948-20240-3-git-send-email-liang-min.wang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/5871/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/5871/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 86E38CA3C;\n\tSat, 27 Jun 2015 03:19:20 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id 8E13CCA28\n\tfor <dev@dpdk.org>; Sat, 27 Jun 2015 03:19:15 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga103.fm.intel.com with ESMTP; 26 Jun 2015 18:19:15 -0700", "from lwang14-mobl6.amr.corp.intel.com ([10.127.184.59])\n\tby fmsmga001.fm.intel.com with ESMTP; 26 Jun 2015 18:19:14 -0700" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.13,687,1427785200\"; d=\"scan'208\";a=\"735602628\"", "From": "Liang-Min Larry Wang <liang-min.wang@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 26 Jun 2015 21:19:05 -0400", "Message-Id": "<1435367948-20240-3-git-send-email-liang-min.wang@intel.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1435367948-20240-1-git-send-email-liang-min.wang@intel.com>", "References": "<1432946276-9424-1-git-send-email-liang-min.wang@intel.com>\n\t<1435367948-20240-1-git-send-email-liang-min.wang@intel.com>", "Cc": "Liang-Min Larry Wang <liang-min.wang@intel.com>", "Subject": "[dpdk-dev] [PATCH v9 2/5] ixgbe: add ops to support ethtool ops", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "add function to support ethtool ops:\n- set_mac_addr\n- get_reg_length\n- get_regs\n- get_eeprom_length\n- get_eeprom\n- set_eeprom\n\nSigned-off-by: Liang-Min Larry Wang <liang-min.wang@intel.com>\n---\n drivers/net/ixgbe/ixgbe_ethdev.c | 190 +++++++++++++++++++-\n drivers/net/ixgbe/ixgbe_regs.h | 379 +++++++++++++++++++++++++++++++++++++++\n 2 files changed, 567 insertions(+), 2 deletions(-)\n create mode 100644 drivers/net/ixgbe/ixgbe_regs.h", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c\nindex f18550c..e2be855 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.c\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.c\n@@ -68,6 +68,9 @@\n #include \"ixgbe_ethdev.h\"\n #include \"ixgbe_bypass.h\"\n #include \"ixgbe_rxtx.h\"\n+#include \"base/ixgbe_type.h\"\n+#include \"base/ixgbe_phy.h\"\n+#include \"ixgbe_regs.h\"\n \n /*\n * High threshold controlling when to start sending XOFF frames. Must be at\n@@ -91,6 +94,7 @@\n \n #define IXGBE_MMW_SIZE_DEFAULT 0x4\n #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14\n+#define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */\n \n /*\n * Default values for RX/TX configuration\n@@ -179,6 +183,8 @@ static void ixgbe_dev_interrupt_delayed_handler(void *param);\n static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n \t\tuint32_t index, uint32_t pool);\n static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);\n+static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,\n+\t\t\t\t\t struct ether_addr *mac_addr);\n static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);\n \n /* For Virtual Function support */\n@@ -223,6 +229,8 @@ static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,\n \t\t\t\t struct ether_addr *mac_addr,\n \t\t\t\t uint32_t index, uint32_t pool);\n static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);\n+static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,\n+\t\t\t\t\t struct ether_addr *mac_addr);\n static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,\n \t\t\tstruct rte_eth_syn_filter *filter,\n \t\t\tbool add);\n@@ -260,6 +268,19 @@ static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);\n static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,\n \t\t\t\t struct ether_addr *mc_addr_set,\n \t\t\t\t uint32_t nb_mc_addr);\n+/* Ethtool op support */\n+static int ixgbe_get_reg_length(struct rte_eth_dev *dev);\n+static int ixgbe_get_regs(struct rte_eth_dev *dev,\n+\t\t\t struct rte_dev_reg_info *regs);\n+static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);\n+static int ixgbe_get_eeprom(struct rte_eth_dev *dev,\n+\t\t\t\tstruct rte_dev_eeprom_info *eeprom);\n+static int ixgbe_set_eeprom(struct rte_eth_dev *dev,\n+\t\t\t\tstruct rte_dev_eeprom_info *eeprom);\n+\n+static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);\n+static int ixgbevf_get_regs(struct rte_eth_dev *dev,\n+\t\t\t\tstruct rte_dev_reg_info *regs);\n \n /*\n * Define VF Stats MACRO for Non \"cleared on read\" register\n@@ -359,6 +380,7 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {\n \t.priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,\n \t.mac_addr_add = ixgbe_add_rar,\n \t.mac_addr_remove = ixgbe_remove_rar,\n+\t.mac_addr_set = ixgbe_set_default_mac_addr,\n \t.uc_hash_table_set = ixgbe_uc_hash_table_set,\n \t.uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,\n \t.mirror_rule_set = ixgbe_mirror_rule_set,\n@@ -386,6 +408,11 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {\n \t.rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,\n \t.filter_ctrl = ixgbe_dev_filter_ctrl,\n \t.set_mc_addr_list = ixgbe_dev_set_mc_addr_list,\n+\t.get_reg_length = ixgbe_get_reg_length,\n+\t.get_reg = ixgbe_get_regs,\n+\t.get_eeprom_length = ixgbe_get_eeprom_length,\n+\t.get_eeprom = ixgbe_get_eeprom,\n+\t.set_eeprom = ixgbe_set_eeprom,\n };\n \n /*\n@@ -412,6 +439,9 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops = {\n \t.mac_addr_add = ixgbevf_add_mac_addr,\n \t.mac_addr_remove = ixgbevf_remove_mac_addr,\n \t.set_mc_addr_list = ixgbe_dev_set_mc_addr_list,\n+\t.mac_addr_set = ixgbevf_set_default_mac_addr,\n+\t.get_reg_length = ixgbevf_get_reg_length,\n+\t.get_reg = ixgbevf_get_regs,\n };\n \n /**\n@@ -2902,6 +2932,14 @@ ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)\n \tixgbe_clear_rar(hw, index);\n }\n \n+static void\n+ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)\n+{\n+\tixgbe_remove_rar(dev, 0);\n+\n+\tixgbe_add_rar(dev, addr, 0, 0);\n+}\n+\n static int\n ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n {\n@@ -3741,6 +3779,14 @@ ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)\n \t}\n }\n \n+static void\n+ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\thw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);\n+}\n+\n #define MAC_TYPE_FILTER_SUP(type) do {\\\n \tif ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\\\n \t\t(type) != ixgbe_mac_X550)\\\n@@ -4481,8 +4527,8 @@ ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,\n \n static int\n ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,\n-\t\t\t struct ether_addr *mc_addr_set,\n-\t\t\t uint32_t nb_mc_addr)\n+\t\t\t struct ether_addr *mc_addr_set,\n+\t\t\t uint32_t nb_mc_addr)\n {\n \tstruct ixgbe_hw *hw;\n \tu8 *mc_addr_list;\n@@ -4493,6 +4539,146 @@ ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,\n \t\t\t\t\t ixgbe_dev_addr_list_itr, TRUE);\n }\n \n+static int\n+ixgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tint count = 0;\n+\tint g_ind = 0;\n+\tstruct reg_info *reg_group;\n+\tstruct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?\n+\t\t\t\t ixgbe_regs_mac_82598EB : ixgbe_regs_others;\n+\n+\treg_group = reg_set[g_ind++];\n+\twhile (reg_group) {\n+\t\tcount += ixgbe_regs_group_count(reg_group);\n+\t\treg_group = reg_set[g_ind++];\n+\t}\n+\n+\treturn count;\n+}\n+\n+static int\n+ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)\n+{\n+\tint count = 0;\n+\tint g_ind = 0;\n+\tstruct reg_info *reg_group;\n+\n+\treg_group = ixgbevf_regs[g_ind++];\n+\twhile (reg_group) {\n+\t\tcount += ixgbe_regs_group_count(reg_group);\n+\t\treg_group = ixgbevf_regs[g_ind++];\n+\t}\n+\n+\treturn count;\n+}\n+\n+static int\n+ixgbe_get_regs(struct rte_eth_dev *dev,\n+\t struct rte_dev_reg_info *regs)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t *regs_buff = regs->buf;\n+\tint g_ind = 0;\n+\tint count = 0;\n+\tstruct reg_info *reg_group;\n+\tstruct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?\n+\t\t\t\t ixgbe_regs_mac_82598EB : ixgbe_regs_others;\n+\n+\t/* Support only full register dump */\n+\tif ((regs->leng == 0) ||\n+\t (regs->leng == (uint32_t)ixgbe_get_reg_length(dev))) {\n+\t\tregs->version = hw->mac.type << 24 | hw->revision_id << 16 |\n+\t\t\thw->device_id;\n+\t\treg_group = reg_set[g_ind++];\n+\t\twhile (reg_group) {\n+\t\t\tcount += ixgbe_read_regs_group(dev, ®s_buff[count],\n+\t\t\t\treg_group);\n+\t\t\treg_group = reg_set[g_ind++];\n+\t\t}\n+\t\treturn 0;\n+\t}\n+\n+\treturn -ENOTSUP;\n+}\n+\n+static int\n+ixgbevf_get_regs(struct rte_eth_dev *dev,\n+\t\tstruct rte_dev_reg_info *regs)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t *regs_buff = regs->buf;\n+\tint g_ind = 0;\n+\tint count = 0;\n+\tstruct reg_info *reg_group;\n+\n+\t/* Support only full register dump */\n+\tif ((regs->leng == 0) ||\n+\t (regs->leng == (uint32_t)ixgbevf_get_reg_length(dev))) {\n+\t\tregs->version = hw->mac.type << 24 | hw->revision_id << 16 |\n+\t\t\thw->device_id;\n+\t\treg_group = ixgbevf_regs[g_ind++];\n+\t\twhile (reg_group) {\n+\t\t\tcount += ixgbe_read_regs_group(dev, ®s_buff[count],\n+\t\t\t\t\t\t reg_group);\n+\t\t\treg_group = ixgbevf_regs[g_ind++];\n+\t\t}\n+\t\treturn 0;\n+\t}\n+\n+\treturn -ENOTSUP;\n+}\n+\n+static int\n+ixgbe_get_eeprom_length(struct rte_eth_dev *dev)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\t/* Return unit is byte count */\n+\treturn hw->eeprom.word_size * 2;\n+}\n+\n+static int\n+ixgbe_get_eeprom(struct rte_eth_dev *dev,\n+\t\tstruct rte_dev_eeprom_info *in_eeprom)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n+\tuint16_t *data = in_eeprom->buf;\n+\tint first, leng;\n+\n+\tfirst = in_eeprom->offset >> 1;\n+\tleng = in_eeprom->leng >> 1;\n+\tif ((first >= hw->eeprom.word_size) ||\n+\t ((first + leng) >= hw->eeprom.word_size))\n+\t\treturn -EINVAL;\n+\n+\tin_eeprom->magic = hw->vendor_id | (hw->device_id << 16);\n+\n+\treturn eeprom->ops.read_buffer(hw, first, leng, data);\n+}\n+\n+static int\n+ixgbe_set_eeprom(struct rte_eth_dev *dev,\n+\t\tstruct rte_dev_eeprom_info *in_eeprom)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n+\tuint16_t *data = in_eeprom->buf;\n+\tint first, leng;\n+\n+\tfirst = in_eeprom->offset >> 1;\n+\tleng = in_eeprom->leng >> 1;\n+\tif ((first >= hw->eeprom.word_size) ||\n+\t ((first + leng) >= hw->eeprom.word_size))\n+\t\treturn -EINVAL;\n+\n+\tin_eeprom->magic = hw->vendor_id | (hw->device_id << 16);\n+\n+\treturn eeprom->ops.write_buffer(hw, first, leng, data);\n+}\n+\n static struct rte_driver rte_ixgbe_driver = {\n \t.type = PMD_PDEV,\n \t.init = rte_ixgbe_pmd_init,\ndiff --git a/drivers/net/ixgbe/ixgbe_regs.h b/drivers/net/ixgbe/ixgbe_regs.h\nnew file mode 100644\nindex 0000000..67d6439\n--- /dev/null\n+++ b/drivers/net/ixgbe/ixgbe_regs.h\n@@ -0,0 +1,379 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef _IXGBE_REGS_H_\n+#define _IXGBE_REGS_H_\n+\n+#include \"ixgbe_ethdev.h\"\n+\n+struct ixgbe_hw;\n+struct reg_info {\n+\tuint32_t base_addr;\n+\tuint32_t count;\n+\tuint32_t stride;\n+\tconst char *name;\n+} reg_info;\n+\n+static struct reg_info ixgbe_regs_general[] = {\n+\t{IXGBE_CTRL, 1, 1, \"IXGBE_CTRL\"},\n+\t{IXGBE_STATUS, 1, 1, \"IXGBE_STATUS\"},\n+\t{IXGBE_CTRL_EXT, 1, 1, \"IXGBE_CTRL_EXT\"},\n+\t{IXGBE_ESDP, 1, 1, \"IXGBE_ESDP\"},\n+\t{IXGBE_EODSDP, 1, 1, \"IXGBE_EODSDP\"},\n+\t{IXGBE_LEDCTL, 1, 1, \"IXGBE_LEDCTL\"},\n+\t{IXGBE_FRTIMER, 1, 1, \"IXGBE_FRTIMER\"},\n+\t{IXGBE_TCPTIMER, 1, 1, \"IXGBE_TCPTIMER\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbevf_regs_general[] = {\n+\t{IXGBE_CTRL, 1, 1, \"IXGBE_CTRL\"},\n+\t{IXGBE_STATUS, 1, 1, \"IXGBE_STATUS\"},\n+\t{IXGBE_VFLINKS, 1, 1, \"IXGBE_VFLINKS\"},\n+\t{IXGBE_FRTIMER, 1, 1, \"IXGBE_FRTIMER\"},\n+\t{IXGBE_VFMAILBOX, 1, 1, \"IXGBE_VFMAILBOX\"},\n+\t{IXGBE_VFMBMEM, 16, 4, \"IXGBE_VFMBMEM\"},\n+\t{IXGBE_VFRXMEMWRAP, 1, 1, \"IXGBE_VFRXMEMWRAP\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_nvm[] = {\n+\t{IXGBE_EEC, 1, 1, \"IXGBE_EEC\"},\n+\t{IXGBE_EERD, 1, 1, \"IXGBE_EERD\"},\n+\t{IXGBE_FLA, 1, 1, \"IXGBE_FLA\"},\n+\t{IXGBE_EEMNGCTL, 1, 1, \"IXGBE_EEMNGCTL\"},\n+\t{IXGBE_EEMNGDATA, 1, 1, \"IXGBE_EEMNGDATA\"},\n+\t{IXGBE_FLMNGCTL, 1, 1, \"IXGBE_FLMNGCTL\"},\n+\t{IXGBE_FLMNGDATA, 1, 1, \"IXGBE_FLMNGDATA\"},\n+\t{IXGBE_FLMNGCNT, 1, 1, \"IXGBE_FLMNGCNT\"},\n+\t{IXGBE_FLOP, 1, 1, \"IXGBE_FLOP\"},\n+\t{IXGBE_GRC, 1, 1, \"IXGBE_GRC\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_interrupt[] = {\n+\t{IXGBE_EICS, 1, 1, \"IXGBE_EICS\"},\n+\t{IXGBE_EIMS, 1, 1, \"IXGBE_EIMS\"},\n+\t{IXGBE_EIMC, 1, 1, \"IXGBE_EIMC\"},\n+\t{IXGBE_EIAC, 1, 1, \"IXGBE_EIAC\"},\n+\t{IXGBE_EIAM, 1, 1, \"IXGBE_EIAM\"},\n+\t{IXGBE_EITR(0), 24, 4, \"IXGBE_EITR\"},\n+\t{IXGBE_IVAR(0), 24, 4, \"IXGBE_IVAR\"},\n+\t{IXGBE_MSIXT, 1, 1, \"IXGBE_MSIXT\"},\n+\t{IXGBE_MSIXPBA, 1, 1, \"IXGBE_MSIXPBA\"},\n+\t{IXGBE_PBACL(0), 1, 4, \"IXGBE_PBACL\"},\n+\t{IXGBE_GPIE, 1, 1, \"\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbevf_regs_interrupt[] = {\n+\t{IXGBE_VTEICR, 1, 1, \"IXGBE_VTEICR\"},\n+\t{IXGBE_VTEICS, 1, 1, \"IXGBE_VTEICS\"},\n+\t{IXGBE_VTEIMS, 1, 1, \"IXGBE_VTEIMS\"},\n+\t{IXGBE_VTEIMC, 1, 1, \"IXGBE_VTEIMC\"},\n+\t{IXGBE_VTEIAM, 1, 1, \"IXGBE_VTEIAM\"},\n+\t{IXGBE_VTEITR(0), 2, 4, \"IXGBE_VTEITR\"},\n+\t{IXGBE_VTIVAR(0), 4, 4, \"IXGBE_VTIVAR\"},\n+\t{IXGBE_VTIVAR_MISC, 1, 1, \"IXGBE_VTIVAR_MISC\"},\n+\t{IXGBE_VTRSCINT(0), 2, 4, \"IXGBE_VTRSCINT\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_fctl_mac_82598EB[] = {\n+\t{IXGBE_PFCTOP, 1, 1, \"\"},\n+\t{IXGBE_FCTTV(0), 4, 4, \"\"},\n+\t{IXGBE_FCRTV, 1, 1, \"\"},\n+\t{IXGBE_TFCS, 1, 1, \"\"},\n+\t{IXGBE_FCRTL(0), 8, 8, \"IXGBE_FCRTL\"},\n+\t{IXGBE_FCRTH(0), 8, 8, \"IXGBE_FCRTH\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_fctl_others[] = {\n+\t{IXGBE_PFCTOP, 1, 1, \"\"},\n+\t{IXGBE_FCTTV(0), 4, 4, \"\"},\n+\t{IXGBE_FCRTV, 1, 1, \"\"},\n+\t{IXGBE_TFCS, 1, 1, \"\"},\n+\t{IXGBE_FCRTL_82599(0), 8, 4, \"IXGBE_FCRTL\"},\n+\t{IXGBE_FCRTH_82599(0), 8, 4, \"IXGBE_FCRTH\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_rxdma[] = {\n+\t{IXGBE_RDBAL(0), 64, 0x40, \"IXGBE_RDBAL\"},\n+\t{IXGBE_RDBAH(0), 64, 0x40, \"IXGBE_RDBAH\"},\n+\t{IXGBE_RDLEN(0), 64, 0x40, \"IXGBE_RDLEN\"},\n+\t{IXGBE_RDH(0), 64, 0x40, \"IXGBE_RDH\"},\n+\t{IXGBE_RDT(0), 64, 0x40, \"IXGBE_RDT\"},\n+\t{IXGBE_RXDCTL(0), 64, 0x40, \"IXGBE_RXDCTL\"},\n+\t{IXGBE_SRRCTL(0), 16, 0x4, \"IXGBE_SRRCTL\"},\n+\t{IXGBE_DCA_RXCTRL(0), 16, 4, \"IXGBE_DCA_RXCTRL\"},\n+\t{IXGBE_RDRXCTL, 1, 1, \"IXGBE_RDRXCTL\"},\n+\t{IXGBE_RXPBSIZE(0), 8, 4, \"IXGBE_RXPBSIZE\"},\n+\t{IXGBE_RXCTRL, 1, 1, \"IXGBE_RXCTRL\"},\n+\t{IXGBE_DROPEN, 1, 1, \"IXGBE_DROPEN\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbevf_regs_rxdma[] = {\n+\t{IXGBE_RDBAL(0), 8, 0x40, \"IXGBE_RDBAL\"},\n+\t{IXGBE_RDBAH(0), 8, 0x40, \"IXGBE_RDBAH\"},\n+\t{IXGBE_RDLEN(0), 8, 0x40, \"IXGBE_RDLEN\"},\n+\t{IXGBE_RDH(0), 8, 0x40, \"IXGBE_RDH\"},\n+\t{IXGBE_RDT(0), 8, 0x40, \"IXGBE_RDT\"},\n+\t{IXGBE_RXDCTL(0), 8, 0x40, \"IXGBE_RXDCTL\"},\n+\t{IXGBE_SRRCTL(0), 8, 0x40, \"IXGBE_SRRCTL\"},\n+\t{IXGBE_VFPSRTYPE, 1, 1,\t\"IXGBE_VFPSRTYPE\"},\n+\t{IXGBE_VFRSCCTL(0), 8, 0x40, \"IXGBE_VFRSCCTL\"},\n+\t{IXGBE_PVFDCA_RXCTRL(0), 8, 0x40, \"IXGBE_PVFDCA_RXCTRL\"},\n+\t{IXGBE_PVFDCA_TXCTRL(0), 8, 0x40, \"IXGBE_PVFDCA_TXCTRL\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_rx[] = {\n+\t{IXGBE_RXCSUM, 1, 1, \"IXGBE_RXCSUM\"},\n+\t{IXGBE_RFCTL, 1, 1, \"IXGBE_RFCTL\"},\n+\t{IXGBE_RAL(0), 16, 8, \"IXGBE_RAL\"},\n+\t{IXGBE_RAH(0), 16, 8, \"IXGBE_RAH\"},\n+\t{IXGBE_PSRTYPE(0), 1, 4, \"IXGBE_PSRTYPE\"},\n+\t{IXGBE_FCTRL, 1, 1, \"IXGBE_FCTRL\"},\n+\t{IXGBE_VLNCTRL, 1, 1, \"IXGBE_VLNCTRL\"},\n+\t{IXGBE_MCSTCTRL, 1, 1, \"IXGBE_MCSTCTRL\"},\n+\t{IXGBE_MRQC, 1, 1, \"IXGBE_MRQC\"},\n+\t{IXGBE_VMD_CTL, 1, 1, \"IXGBE_VMD_CTL\"},\n+\t{IXGBE_IMIR(0), 8, 4, \"IXGBE_IMIR\"},\n+\t{IXGBE_IMIREXT(0), 8, 4, \"IXGBE_IMIREXT\"},\n+\t{IXGBE_IMIRVP, 1, 1, \"IXGBE_IMIRVP\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_tx[] = {\n+\t{IXGBE_TDBAL(0), 32, 0x40, \"IXGBE_TDBAL\"},\n+\t{IXGBE_TDBAH(0), 32, 0x40, \"IXGBE_TDBAH\"},\n+\t{IXGBE_TDLEN(0), 32, 0x40, \"IXGBE_TDLEN\"},\n+\t{IXGBE_TDH(0), 32, 0x40, \"IXGBE_TDH\"},\n+\t{IXGBE_TDT(0), 32, 0x40, \"IXGBE_TDT\"},\n+\t{IXGBE_TXDCTL(0), 32, 0x40, \"IXGBE_TXDCTL\"},\n+\t{IXGBE_TDWBAL(0), 32, 0x40, \"IXGBE_TDWBAL\"},\n+\t{IXGBE_TDWBAH(0), 32, 0x40, \"IXGBE_TDWBAH\"},\n+\t{IXGBE_DTXCTL, 1, 1, \"IXGBE_DTXCTL\"},\n+\t{IXGBE_DCA_TXCTRL(0), 16, 4, \"IXGBE_DCA_TXCTRL\"},\n+\t{IXGBE_TXPBSIZE(0), 8, 4, \"IXGBE_TXPBSIZE\"},\n+\t{IXGBE_MNGTXMAP, 1, 1, \"IXGBE_MNGTXMAP\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbevf_regs_tx[] = {\n+\t{IXGBE_TDBAL(0), 4, 0x40, \"IXGBE_TDBAL\"},\n+\t{IXGBE_TDBAH(0), 4, 0x40, \"IXGBE_TDBAH\"},\n+\t{IXGBE_TDLEN(0), 4, 0x40, \"IXGBE_TDLEN\"},\n+\t{IXGBE_TDH(0), 4, 0x40, \"IXGBE_TDH\"},\n+\t{IXGBE_TDT(0), 4, 0x40, \"IXGBE_TDT\"},\n+\t{IXGBE_TXDCTL(0), 4, 0x40, \"IXGBE_TXDCTL\"},\n+\t{IXGBE_TDWBAL(0), 4, 0x40, \"IXGBE_TDWBAL\"},\n+\t{IXGBE_TDWBAH(0), 4, 0x40, \"IXGBE_TDWBAH\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_wakeup[] = {\n+\t{IXGBE_WUC, 1, 1, \"IXGBE_WUC\"},\n+\t{IXGBE_WUFC, 1, 1, \"IXGBE_WUFC\"},\n+\t{IXGBE_WUS, 1, 1, \"IXGBE_WUS\"},\n+\t{IXGBE_IPAV, 1, 1, \"IXGBE_IPAV\"},\n+\t{IXGBE_IP4AT, 1, 1, \"IXGBE_IP4AT\"},\n+\t{IXGBE_IP6AT, 1, 1, \"IXGBE_IP6AT\"},\n+\t{IXGBE_WUPL, 1, 1, \"IXGBE_WUPL\"},\n+\t{IXGBE_WUPM, 1, 1, \"IXGBE_WUPM\"},\n+\t{IXGBE_FHFT(0), 1, 1, \"IXGBE_FHFT\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_dcb[] = {\n+\t{IXGBE_RMCS, 1, 1, \"IXGBE_RMCS\"},\n+\t{IXGBE_DPMCS, 1, 1, \"IXGBE_DPMCS\"},\n+\t{IXGBE_PDPMCS, 1, 1, \"IXGBE_PDPMCS\"},\n+\t{IXGBE_RUPPBMR, 1, 1, \"IXGBE_RUPPBMR\"},\n+\t{IXGBE_RT2CR(0), 8, 4, \"IXGBE_RT2CR\"},\n+\t{IXGBE_RT2SR(0), 8, 4, \"IXGBE_RT2SR\"},\n+\t{IXGBE_TDTQ2TCCR(0), 8, 0x40, \"IXGBE_TDTQ2TCCR\"},\n+\t{IXGBE_TDTQ2TCSR(0), 8, 0x40, \"IXGBE_TDTQ2TCSR\"},\n+\t{IXGBE_TDPT2TCCR(0), 8, 4, \"IXGBE_TDPT2TCCR\"},\n+\t{IXGBE_TDPT2TCSR(0), 8, 4, \"IXGBE_TDPT2TCSR\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_mac[] = {\n+\t{IXGBE_PCS1GCFIG, 1, 1, \"IXGBE_PCS1GCFIG\"},\n+\t{IXGBE_PCS1GLCTL, 1, 1, \"IXGBE_PCS1GLCTL\"},\n+\t{IXGBE_PCS1GLSTA, 1, 1, \"IXGBE_PCS1GLSTA\"},\n+\t{IXGBE_PCS1GDBG0, 1, 1, \"IXGBE_PCS1GDBG0\"},\n+\t{IXGBE_PCS1GDBG1, 1, 1, \"IXGBE_PCS1GDBG1\"},\n+\t{IXGBE_PCS1GANA, 1, 1, \"IXGBE_PCS1GANA\"},\n+\t{IXGBE_PCS1GANLP, 1, 1, \"IXGBE_PCS1GANLP\"},\n+\t{IXGBE_PCS1GANNP, 1, 1, \"IXGBE_PCS1GANNP\"},\n+\t{IXGBE_PCS1GANLPNP, 1, 1, \"IXGBE_PCS1GANLPNP\"},\n+\t{IXGBE_HLREG0, 1, 1, \"IXGBE_HLREG0\"},\n+\t{IXGBE_HLREG1, 1, 1, \"IXGBE_HLREG1\"},\n+\t{IXGBE_PAP, 1, 1, \"IXGBE_PAP\"},\n+\t{IXGBE_MACA, 1, 1, \"IXGBE_MACA\"},\n+\t{IXGBE_APAE, 1, 1, \"IXGBE_APAE\"},\n+\t{IXGBE_ARD, 1, 1, \"IXGBE_ARD\"},\n+\t{IXGBE_AIS, 1, 1, \"IXGBE_AIS\"},\n+\t{IXGBE_MSCA, 1, 1, \"IXGBE_MSCA\"},\n+\t{IXGBE_MSRWD, 1, 1, \"IXGBE_MSRWD\"},\n+\t{IXGBE_MLADD, 1, 1, \"IXGBE_MLADD\"},\n+\t{IXGBE_MHADD, 1, 1, \"IXGBE_MHADD\"},\n+\t{IXGBE_TREG, 1, 1, \"IXGBE_TREG\"},\n+\t{IXGBE_PCSS1, 1, 1, \"IXGBE_PCSS1\"},\n+\t{IXGBE_PCSS2, 1, 1, \"IXGBE_PCSS2\"},\n+\t{IXGBE_XPCSS, 1, 1, \"IXGBE_XPCSS\"},\n+\t{IXGBE_SERDESC, 1, 1, \"IXGBE_SERDESC\"},\n+\t{IXGBE_MACS, 1, 1, \"IXGBE_MACS\"},\n+\t{IXGBE_AUTOC, 1, 1, \"IXGBE_AUTOC\"},\n+\t{IXGBE_LINKS, 1, 1, \"IXGBE_LINKS\"},\n+\t{IXGBE_AUTOC2, 1, 1, \"IXGBE_AUTOC2\"},\n+\t{IXGBE_AUTOC3, 1, 1, \"IXGBE_AUTOC3\"},\n+\t{IXGBE_ANLP1, 1, 1, \"IXGBE_ANLP1\"},\n+\t{IXGBE_ANLP2, 1, 1, \"IXGBE_ANLP2\"},\n+\t{IXGBE_ATLASCTL, 1, 1, \"IXGBE_ATLASCTL\"},\n+\t{0, 0, 0, \"\"}\n+};\n+\n+static struct reg_info ixgbe_regs_diagnostic[] = {\n+\t{IXGBE_RDSTATCTL, 1, 1, \"IXGBE_RDSTATCTL\"},\n+\t{IXGBE_RDSTAT(0), 8, 4, \"IXGBE_RDSTAT\"},\n+\t{IXGBE_RDHMPN, 1, 1, \"IXGBE_RDHMPN\"},\n+\t{IXGBE_RIC_DW(0), 4, 4, \"IXGBE_RIC_DW\"},\n+\t{IXGBE_RDPROBE, 1, 1, \"IXGBE_RDPROBE\"},\n+\t{IXGBE_TDHMPN, 1, 1, \"IXGBE_TDHMPN\"},\n+\t{IXGBE_TIC_DW(0), 4, 4, \"IXGBE_TIC_DW\"},\n+\t{IXGBE_TDPROBE, 1, 1, \"IXGBE_TDPROBE\"},\n+\t{IXGBE_TXBUFCTRL, 1, 1, \"IXGBE_TXBUFCTRL\"},\n+\t{IXGBE_TXBUFDATA0, 1, 1, \"IXGBE_TXBUFDATA0\"},\n+\t{IXGBE_TXBUFDATA1, 1, 1, \"IXGBE_TXBUFDATA1\"},\n+\t{IXGBE_TXBUFDATA2, 1, 1, \"IXGBE_TXBUFDATA2\"},\n+\t{IXGBE_TXBUFDATA3, 1, 1, \"IXGBE_TXBUFDATA3\"},\n+\t{IXGBE_RXBUFCTRL, 1, 1, \"IXGBE_RXBUFCTRL\"},\n+\t{IXGBE_RXBUFDATA0, 1, 1, \"IXGBE_RXBUFDATA0\"},\n+\t{IXGBE_RXBUFDATA1, 1, 1, \"IXGBE_RXBUFDATA1\"},\n+\t{IXGBE_RXBUFDATA2, 1, 1, \"IXGBE_RXBUFDATA2\"},\n+\t{IXGBE_RXBUFDATA3, 1, 1, \"IXGBE_RXBUFDATA3\"},\n+\t{IXGBE_PCIE_DIAG(0), 8, 4, \"\"},\n+\t{IXGBE_RFVAL, 1, 1, \"IXGBE_RFVAL\"},\n+\t{IXGBE_MDFTC1, 1, 1, \"IXGBE_MDFTC1\"},\n+\t{IXGBE_MDFTC2, 1, 1, \"IXGBE_MDFTC2\"},\n+\t{IXGBE_MDFTFIFO1, 1, 1, \"IXGBE_MDFTFIFO1\"},\n+\t{IXGBE_MDFTFIFO2, 1, 1, \"IXGBE_MDFTFIFO2\"},\n+\t{IXGBE_MDFTS, 1, 1, \"IXGBE_MDFTS\"},\n+\t{IXGBE_PCIEECCCTL, 1, 1, \"IXGBE_PCIEECCCTL\"},\n+\t{IXGBE_PBTXECC, 1, 1, \"IXGBE_PBTXECC\"},\n+\t{IXGBE_PBRXECC, 1, 1, \"IXGBE_PBRXECC\"},\n+\t{IXGBE_MFLCN, 1, 1, \"IXGBE_MFLCN\"},\n+\t{0, 0, 0, \"\"},\n+};\n+\n+/* PF registers */\n+static struct reg_info *ixgbe_regs_others[] = {\n+\t\t\t\tixgbe_regs_general,\n+\t\t\t\tixgbe_regs_nvm, ixgbe_regs_interrupt,\n+\t\t\t\tixgbe_regs_fctl_others,\n+\t\t\t\tixgbe_regs_rxdma,\n+\t\t\t\tixgbe_regs_rx,\n+\t\t\t\tixgbe_regs_tx,\n+\t\t\t\tixgbe_regs_wakeup,\n+\t\t\t\tixgbe_regs_dcb,\n+\t\t\t\tixgbe_regs_mac,\n+\t\t\t\tixgbe_regs_diagnostic,\n+\t\t\t\tNULL};\n+\n+static struct reg_info *ixgbe_regs_mac_82598EB[] = {\n+\t\t\t\tixgbe_regs_general,\n+\t\t\t\tixgbe_regs_nvm,\n+\t\t\t\tixgbe_regs_interrupt,\n+\t\t\t\tixgbe_regs_fctl_mac_82598EB,\n+\t\t\t\tixgbe_regs_rxdma,\n+\t\t\t\tixgbe_regs_rx,\n+\t\t\t\tixgbe_regs_tx,\n+\t\t\t\tixgbe_regs_wakeup,\n+\t\t\t\tixgbe_regs_dcb,\n+\t\t\t\tixgbe_regs_mac,\n+\t\t\t\tixgbe_regs_diagnostic,\n+\t\t\t\tNULL};\n+\n+/* VF registers */\n+static struct reg_info *ixgbevf_regs[] = {\n+\t\t\t\tixgbevf_regs_general,\n+\t\t\t\tixgbevf_regs_interrupt,\n+\t\t\t\tixgbevf_regs_rxdma,\n+\t\t\t\tixgbevf_regs_tx,\n+\t\t\t\tNULL};\n+\n+static inline int\n+ixgbe_read_regs(struct ixgbe_hw *hw, struct reg_info *reg, uint32_t *reg_buf)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < reg->count; i++)\n+\t\treg_buf[i] = IXGBE_READ_REG(hw,\n+\t\t\t\t\treg->base_addr + i * reg->stride);\n+\treturn reg->count;\n+};\n+\n+static inline int\n+ixgbe_regs_group_count(struct reg_info *regs)\n+{\n+\tint count = 0;\n+\tint i = 0;\n+\n+\twhile (regs[i].count) {\n+\t\tcount += regs[i].count;\n+\t\ti++;\n+\t}\n+\treturn count;\n+};\n+\n+static inline int\n+ixgbe_read_regs_group(struct rte_eth_dev *dev, uint32_t *reg_buf,\n+\t\t\t\t\t struct reg_info *regs)\n+{\n+\tint count = 0;\n+\tint i = 0;\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\twhile (regs[i].count) {\n+\t\tcount += ixgbe_read_regs(hw, ®s[i], ®_buf[count]);\n+\t\ti++;\n+\t}\n+\treturn count;\n+};\n+\n+#endif /* _IXGBE_REGS_H_ */\n", "prefixes": [ "dpdk-dev", "v9", "2/5" ] }