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{
    "id": 58546,
    "url": "https://patches.dpdk.org/api/patches/58546/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190903221522.151382-3-ying.a.wang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190903221522.151382-3-ying.a.wang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190903221522.151382-3-ying.a.wang@intel.com",
    "date": "2019-09-03T22:15:20",
    "name": "[2/4] net/ice: rework for generic flow enabling",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "7eba5b5d023b0642cf470fdb519979775338c1ec",
    "submitter": {
        "id": 1280,
        "url": "https://patches.dpdk.org/api/people/1280/?format=api",
        "name": "Ying Wang",
        "email": "ying.a.wang@intel.com"
    },
    "delegate": {
        "id": 31221,
        "url": "https://patches.dpdk.org/api/users/31221/?format=api",
        "username": "yexl",
        "first_name": "xiaolong",
        "last_name": "ye",
        "email": "xiaolong.ye@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190903221522.151382-3-ying.a.wang@intel.com/mbox/",
    "series": [
        {
            "id": 6228,
            "url": "https://patches.dpdk.org/api/series/6228/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6228",
            "date": "2019-09-03T22:15:18",
            "name": "rework for ice generic flow framework and switch filter",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/6228/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/58546/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/58546/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E70661ECF5;\n\tWed,  4 Sep 2019 08:37:16 +0200 (CEST)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id C940E1ECF5\n\tfor <dev@dpdk.org>; Wed,  4 Sep 2019 08:37:14 +0200 (CEST)",
            "from fmsmga004.fm.intel.com ([10.253.24.48])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t03 Sep 2019 23:37:14 -0700",
            "from npg-dpdk-cvl-yingwang-117d84.sh.intel.com ([10.67.117.84])\n\tby fmsmga004.fm.intel.com with ESMTP; 03 Sep 2019 23:37:11 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.64,465,1559545200\"; d=\"scan'208\";a=\"207359986\"",
        "From": "Ying Wang <ying.a.wang@intel.com>",
        "To": "qi.z.zhang@intel.com",
        "Cc": "xiaolong.ye@intel.com, qiming.yang@intel.com, dev@dpdk.org,\n\tying.a.wang@intel.com, wei.zhao1@intel.com",
        "Date": "Wed,  4 Sep 2019 06:15:20 +0800",
        "Message-Id": "<20190903221522.151382-3-ying.a.wang@intel.com>",
        "X-Mailer": "git-send-email 2.15.1",
        "In-Reply-To": "<20190903221522.151382-1-ying.a.wang@intel.com>",
        "References": "<20190903221522.151382-1-ying.a.wang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 2/4] net/ice: rework for generic flow enabling",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The patch reworks the generic flow API (rte_flow) implementation.\nIt introduces an abstract layer which provides a unified interface\nfor low-level filter engine (switch, fdir, hash) to register supported\npatterns and actions and implement flow validate/create/destroy/flush/\nquery activities.\n\nThe patch also removes the existing switch filter implementation to\navoid compile error. Switch filter implementation for the new framework\nwill be added in the following patch.\n\nSigned-off-by: Ying Wang <ying.a.wang@intel.com>\n---\n drivers/net/ice/ice_ethdev.c        |  22 +-\n drivers/net/ice/ice_ethdev.h        |  15 +-\n drivers/net/ice/ice_generic_flow.c  | 768 +++++++++++++++--------------------\n drivers/net/ice/ice_generic_flow.h  | 782 ++++++++----------------------------\n drivers/net/ice/ice_switch_filter.c | 511 -----------------------\n drivers/net/ice/ice_switch_filter.h |  18 -\n 6 files changed, 525 insertions(+), 1591 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 4e0645db1..647aca3ed 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -15,7 +15,7 @@\n #include \"base/ice_dcb.h\"\n #include \"ice_ethdev.h\"\n #include \"ice_rxtx.h\"\n-#include \"ice_switch_filter.h\"\n+#include \"ice_generic_flow.h\"\n \n /* devargs */\n #define ICE_SAFE_MODE_SUPPORT_ARG \"safe-mode-support\"\n@@ -1677,7 +1677,11 @@ ice_dev_init(struct rte_eth_dev *dev)\n \t/* get base queue pairs index  in the device */\n \tice_base_queue_get(pf);\n \n-\tTAILQ_INIT(&pf->flow_list);\n+\tret = ice_flow_init(ad);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to initialize flow\");\n+\t\treturn ret;\n+\t}\n \n \treturn 0;\n \n@@ -1796,6 +1800,8 @@ ice_dev_close(struct rte_eth_dev *dev)\n {\n \tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ice_adapter *ad =\n+\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \n \t/* Since stop will make link down, then the link event will be\n \t * triggered, disable the irq firstly to avoid the port_infoe etc\n@@ -1806,6 +1812,8 @@ ice_dev_close(struct rte_eth_dev *dev)\n \n \tice_dev_stop(dev);\n \n+\tice_flow_uninit(ad);\n+\n \t/* release all queue resource */\n \tice_free_queues(dev);\n \n@@ -1822,8 +1830,6 @@ ice_dev_uninit(struct rte_eth_dev *dev)\n {\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n-\tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n-\tstruct rte_flow *p_flow;\n \n \tice_dev_close(dev);\n \n@@ -1840,14 +1846,6 @@ ice_dev_uninit(struct rte_eth_dev *dev)\n \t/* unregister callback func from eal lib */\n \trte_intr_callback_unregister(intr_handle,\n \t\t\t\t     ice_interrupt_handler, dev);\n-\n-\t/* Remove all flows */\n-\twhile ((p_flow = TAILQ_FIRST(&pf->flow_list))) {\n-\t\tTAILQ_REMOVE(&pf->flow_list, p_flow, node);\n-\t\tice_free_switch_filter_rule(p_flow->rule);\n-\t\trte_free(p_flow);\n-\t}\n-\n \treturn 0;\n }\n \ndiff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h\nindex 9bf5de08d..d1d07641d 100644\n--- a/drivers/net/ice/ice_ethdev.h\n+++ b/drivers/net/ice/ice_ethdev.h\n@@ -241,16 +241,14 @@ struct ice_vsi {\n \tbool offset_loaded;\n };\n \n-extern const struct rte_flow_ops ice_flow_ops;\n-\n-/* Struct to store flow created. */\n-struct rte_flow {\n-\tTAILQ_ENTRY(rte_flow) node;\n-\tvoid *rule;\n-};\n \n+struct rte_flow;\n TAILQ_HEAD(ice_flow_list, rte_flow);\n \n+\n+struct ice_flow_parser;\n+TAILQ_HEAD(ice_parser_list, ice_flow_parser);\n+\n struct ice_pf {\n \tstruct ice_adapter *adapter; /* The adapter this PF associate to */\n \tstruct ice_vsi *main_vsi; /* pointer to main VSI structure */\n@@ -278,6 +276,9 @@ struct ice_pf {\n \tbool offset_loaded;\n \tbool adapter_stopped;\n \tstruct ice_flow_list flow_list;\n+\tstruct ice_parser_list rss_parser_list;\n+\tstruct ice_parser_list perm_parser_list;\n+\tstruct ice_parser_list dist_parser_list;\n };\n \n /**\ndiff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c\nindex 1c0adc779..aa11d6170 100644\n--- a/drivers/net/ice/ice_generic_flow.c\n+++ b/drivers/net/ice/ice_generic_flow.c\n@@ -17,7 +17,22 @@\n \n #include \"ice_ethdev.h\"\n #include \"ice_generic_flow.h\"\n-#include \"ice_switch_filter.h\"\n+\n+/**\n+ * Non-pipeline mode, fdir and swith both used as distributor,\n+ * fdir used first, switch used as fdir's backup.\n+ */\n+#define ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY 0\n+/*Pipeline mode, switch used at permission stage*/\n+#define ICE_FLOW_CLASSIFY_STAGE_PERMISSION 1\n+/*Pipeline mode, fdir used at distributor stage*/\n+#define ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR 2\n+\n+static int ice_pipeline_stage =\n+\t\tICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY;\n+\n+static struct ice_engine_list engine_list =\n+\t\tTAILQ_HEAD_INITIALIZER(engine_list);\n \n static int ice_flow_validate(struct rte_eth_dev *dev,\n \t\tconst struct rte_flow_attr *attr,\n@@ -34,17 +49,153 @@ static int ice_flow_destroy(struct rte_eth_dev *dev,\n \t\tstruct rte_flow_error *error);\n static int ice_flow_flush(struct rte_eth_dev *dev,\n \t\tstruct rte_flow_error *error);\n+static int ice_flow_query_count(struct rte_eth_dev *dev,\n+\t\tstruct rte_flow *flow,\n+\t\tconst struct rte_flow_action *actions,\n+\t\tvoid *data,\n+\t\tstruct rte_flow_error *error);\n \n const struct rte_flow_ops ice_flow_ops = {\n \t.validate = ice_flow_validate,\n \t.create = ice_flow_create,\n \t.destroy = ice_flow_destroy,\n \t.flush = ice_flow_flush,\n+\t.query = ice_flow_query_count,\n };\n \n+\n+void\n+ice_register_flow_engine(struct ice_flow_engine *engine)\n+{\n+\tTAILQ_INSERT_TAIL(&engine_list, engine, node);\n+}\n+\n+int\n+ice_flow_init(struct ice_adapter *ad)\n+{\n+\tint ret = 0;\n+\tstruct ice_pf *pf = &ad->pf;\n+\tvoid *temp;\n+\tstruct ice_flow_engine *engine = NULL;\n+\n+\tTAILQ_INIT(&pf->flow_list);\n+\tTAILQ_INIT(&pf->rss_parser_list);\n+\tTAILQ_INIT(&pf->perm_parser_list);\n+\tTAILQ_INIT(&pf->dist_parser_list);\n+\n+\tTAILQ_FOREACH_SAFE(engine, &engine_list, node, temp) {\n+\t\tif (engine->init == NULL)\n+\t\t\treturn -EINVAL;\n+\n+\t\tret = engine->init(ad);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n+\n+void\n+ice_flow_uninit(struct ice_adapter *ad)\n+{\n+\tstruct ice_pf *pf = &ad->pf;\n+\tstruct ice_flow_engine *engine;\n+\tstruct rte_flow *p_flow;\n+\tstruct ice_flow_parser *p_parser;\n+\tvoid *temp;\n+\n+\tTAILQ_FOREACH_SAFE(engine, &engine_list, node, temp) {\n+\t\tif (engine->uninit)\n+\t\t\tengine->uninit(ad);\n+\t}\n+\n+\t/* Remove all flows */\n+\twhile ((p_flow = TAILQ_FIRST(&pf->flow_list))) {\n+\t\tTAILQ_REMOVE(&pf->flow_list, p_flow, node);\n+\t\tif (p_flow->engine->free)\n+\t\t\tp_flow->engine->free(p_flow);\n+\t\trte_free(p_flow);\n+\t}\n+\n+\t/* Cleanup parser list */\n+\twhile ((p_parser = TAILQ_FIRST(&pf->rss_parser_list)))\n+\t\tTAILQ_REMOVE(&pf->rss_parser_list, p_parser, node);\n+\n+\twhile ((p_parser = TAILQ_FIRST(&pf->perm_parser_list)))\n+\t\tTAILQ_REMOVE(&pf->perm_parser_list, p_parser, node);\n+\n+\twhile ((p_parser = TAILQ_FIRST(&pf->dist_parser_list)))\n+\t\tTAILQ_REMOVE(&pf->dist_parser_list, p_parser, node);\n+}\n+\n+int\n+ice_register_parser(struct ice_flow_parser *parser,\n+\t\tstruct ice_adapter *ad)\n+{\n+\tstruct ice_parser_list *list = NULL;\n+\tstruct ice_pf *pf = &ad->pf;\n+\n+\tswitch (parser->stage) {\n+\tcase ICE_FLOW_STAGE_RSS:\n+\t\tlist = &pf->rss_parser_list;\n+\t\tbreak;\n+\tcase ICE_FLOW_STAGE_PERMISSION:\n+\t\tlist = &pf->perm_parser_list;\n+\t\tbreak;\n+\tcase ICE_FLOW_STAGE_DISTRIBUTOR:\n+\t\tlist = &pf->dist_parser_list;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (ad->devargs.pipeline_mode_support)\n+\t\tTAILQ_INSERT_TAIL(list, parser, node);\n+\telse {\n+\t\tif (parser->engine->type == ICE_FLOW_ENGINE_SWITCH\n+\t\t\t|| parser->engine->type == ICE_FLOW_ENGINE_HASH)\n+\t\t\tTAILQ_INSERT_TAIL(list, parser, node);\n+\t\telse if (parser->engine->type == ICE_FLOW_ENGINE_FDIR)\n+\t\t\tTAILQ_INSERT_HEAD(list, parser, node);\n+\t\telse\n+\t\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\n+void\n+ice_unregister_parser(struct ice_flow_parser *parser,\n+\t\tstruct ice_adapter *ad)\n+{\n+\tstruct ice_pf *pf = &ad->pf;\n+\tstruct ice_parser_list *list;\n+\tstruct ice_flow_parser *p_parser;\n+\tvoid *temp;\n+\n+\tswitch (parser->stage) {\n+\tcase ICE_FLOW_STAGE_RSS:\n+\t\tlist = &pf->rss_parser_list;\n+\t\tbreak;\n+\tcase ICE_FLOW_STAGE_PERMISSION:\n+\t\tlist = &pf->perm_parser_list;\n+\t\tbreak;\n+\tcase ICE_FLOW_STAGE_DISTRIBUTOR:\n+\t\tlist = &pf->dist_parser_list;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\tTAILQ_FOREACH_SAFE(p_parser, list, node, temp) {\n+\t\tif (p_parser->engine->type == parser->engine->type)\n+\t\t\tTAILQ_REMOVE(list, p_parser, node);\n+\t}\n+\n+}\n+\n static int\n-ice_flow_valid_attr(const struct rte_flow_attr *attr,\n-\t\t     struct rte_flow_error *error)\n+ice_flow_valid_attr(struct ice_adapter *ad,\n+\t\tconst struct rte_flow_attr *attr,\n+\t\tstruct rte_flow_error *error)\n {\n \t/* Must be input direction */\n \tif (!attr->ingress) {\n@@ -61,15 +212,25 @@ ice_flow_valid_attr(const struct rte_flow_attr *attr,\n \t\t\t\t   attr, \"Not support egress.\");\n \t\treturn -rte_errno;\n \t}\n-\n-\t/* Not supported */\n-\tif (attr->priority) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,\n-\t\t\t\t   attr, \"Not support priority.\");\n-\t\treturn -rte_errno;\n+\t/* Check pipeline mode support to set classification stage */\n+\tif (ad->devargs.pipeline_mode_support) {\n+\t\tif (0 == attr->priority)\n+\t\t\tice_pipeline_stage =\n+\t\t\t\tICE_FLOW_CLASSIFY_STAGE_PERMISSION;\n+\t\telse\n+\t\t\tice_pipeline_stage =\n+\t\t\t\tICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR;\n+\t} else {\n+\t\tice_pipeline_stage =\n+\t\t\tICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY;\n+\t\t/* Not supported */\n+\t\tif (attr->priority) {\n+\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,\n+\t\t\t\t\t   attr, \"Not support priority.\");\n+\t\t\treturn -rte_errno;\n+\t\t}\n \t}\n-\n \t/* Not supported */\n \tif (attr->group) {\n \t\trte_flow_error_set(error, EINVAL,\n@@ -102,7 +263,7 @@ ice_find_first_item(const struct rte_flow_item *item, bool is_void)\n /* Skip all VOID items of the pattern */\n static void\n ice_pattern_skip_void_item(struct rte_flow_item *items,\n-\t\t\t    const struct rte_flow_item *pattern)\n+\t\t\tconst struct rte_flow_item *pattern)\n {\n \tuint32_t cpy_count = 0;\n \tconst struct rte_flow_item *pb = pattern, *pe = pattern;\n@@ -124,7 +285,6 @@ ice_pattern_skip_void_item(struct rte_flow_item *items,\n \t\titems += cpy_count;\n \n \t\tif (pe->type == RTE_FLOW_ITEM_TYPE_END) {\n-\t\t\tpb = pe;\n \t\t\tbreak;\n \t\t}\n \n@@ -151,11 +311,15 @@ ice_match_pattern(enum rte_flow_item_type *item_array,\n \t\titem->type == RTE_FLOW_ITEM_TYPE_END);\n }\n \n-static uint64_t ice_flow_valid_pattern(const struct rte_flow_item pattern[],\n+struct ice_pattern_match_item *\n+ice_search_pattern_match_item(const struct rte_flow_item pattern[],\n+\t\tstruct ice_pattern_match_item *array,\n+\t\tuint32_t array_len,\n \t\tstruct rte_flow_error *error)\n {\n \tuint16_t i = 0;\n-\tuint64_t inset;\n+\tstruct ice_pattern_match_item *pattern_match_item;\n+\t/* need free by each filter */\n \tstruct rte_flow_item *items; /* used for pattern without VOID items */\n \tuint32_t item_num = 0; /* non-void item number */\n \n@@ -172,451 +336,149 @@ static uint64_t ice_flow_valid_pattern(const struct rte_flow_item pattern[],\n \tif (!items) {\n \t\trte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,\n \t\t\t\t   NULL, \"No memory for PMD internal items.\");\n-\t\treturn -ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tpattern_match_item = rte_zmalloc(\"ice_pattern_match_item\",\n+\t\t\tsizeof(struct ice_pattern_match_item), 0);\n+\tif (!pattern_match_item) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory.\");\n+\t\treturn NULL;\n \t}\n-\n \tice_pattern_skip_void_item(items, pattern);\n \n-\tfor (i = 0; i < RTE_DIM(ice_supported_patterns); i++)\n-\t\tif (ice_match_pattern(ice_supported_patterns[i].items,\n+\tfor (i = 0; i < array_len; i++)\n+\t\tif (ice_match_pattern(array[i].pattern_list,\n \t\t\t\t      items)) {\n-\t\t\tinset = ice_supported_patterns[i].sw_fields;\n+\t\t\tpattern_match_item->input_set_mask =\n+\t\t\t\tarray[i].input_set_mask;\n+\t\t\tpattern_match_item->pattern_list =\n+\t\t\t\tarray[i].pattern_list;\n+\t\t\tpattern_match_item->meta = array[i].meta;\n \t\t\trte_free(items);\n-\t\t\treturn inset;\n+\t\t\treturn pattern_match_item;\n \t\t}\n \trte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t   pattern, \"Unsupported pattern\");\n \n \trte_free(items);\n-\treturn 0;\n-}\n-\n-static uint64_t ice_get_flow_field(const struct rte_flow_item pattern[],\n-\t\t\tstruct rte_flow_error *error)\n-{\n-\tconst struct rte_flow_item *item = pattern;\n-\tconst struct rte_flow_item_eth *eth_spec, *eth_mask;\n-\tconst struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;\n-\tconst struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;\n-\tconst struct rte_flow_item_tcp *tcp_spec, *tcp_mask;\n-\tconst struct rte_flow_item_udp *udp_spec, *udp_mask;\n-\tconst struct rte_flow_item_sctp *sctp_spec, *sctp_mask;\n-\tconst struct rte_flow_item_icmp *icmp_mask;\n-\tconst struct rte_flow_item_icmp6 *icmp6_mask;\n-\tconst struct rte_flow_item_vxlan *vxlan_spec, *vxlan_mask;\n-\tconst struct rte_flow_item_nvgre *nvgre_spec, *nvgre_mask;\n-\tenum rte_flow_item_type item_type;\n-\tuint8_t  ipv6_addr_mask[16] = {\n-\t\t0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n-\t\t0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };\n-\tuint64_t input_set = ICE_INSET_NONE;\n-\tbool is_tunnel = false;\n-\n-\tfor (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {\n-\t\tif (item->last) {\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t   item,\n-\t\t\t\t\t   \"Not support range\");\n-\t\t\treturn 0;\n-\t\t}\n-\t\titem_type = item->type;\n-\t\tswitch (item_type) {\n-\t\tcase RTE_FLOW_ITEM_TYPE_ETH:\n-\t\t\teth_spec = item->spec;\n-\t\t\teth_mask = item->mask;\n-\n-\t\t\tif (eth_spec && eth_mask) {\n-\t\t\t\tif (rte_is_broadcast_ether_addr(&eth_mask->src))\n-\t\t\t\t\tinput_set |= ICE_INSET_SMAC;\n-\t\t\t\tif (rte_is_broadcast_ether_addr(&eth_mask->dst))\n-\t\t\t\t\tinput_set |= ICE_INSET_DMAC;\n-\t\t\t\tif (eth_mask->type == RTE_BE16(0xffff))\n-\t\t\t\t\tinput_set |= ICE_INSET_ETHERTYPE;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n-\t\t\tipv4_spec = item->spec;\n-\t\t\tipv4_mask = item->mask;\n-\n-\t\t\tif (!(ipv4_spec && ipv4_mask))\n-\t\t\t\tbreak;\n-\n-\t\t\t/* Check IPv4 mask and update input set */\n-\t\t\tif (ipv4_mask->hdr.version_ihl ||\n-\t\t\t    ipv4_mask->hdr.total_length ||\n-\t\t\t    ipv4_mask->hdr.packet_id ||\n-\t\t\t    ipv4_mask->hdr.hdr_checksum) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t   item,\n-\t\t\t\t\t   \"Invalid IPv4 mask.\");\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\n-\t\t\tif (is_tunnel) {\n-\t\t\t\tif (ipv4_mask->hdr.src_addr == UINT32_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_IPV4_SRC;\n-\t\t\t\tif (ipv4_mask->hdr.dst_addr == UINT32_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_IPV4_DST;\n-\t\t\t\tif (ipv4_mask->hdr.time_to_live == UINT8_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_IPV4_TTL;\n-\t\t\t\tif (ipv4_mask->hdr.next_proto_id == UINT8_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_IPV4_PROTO;\n-\t\t\t} else {\n-\t\t\t\tif (ipv4_mask->hdr.src_addr == UINT32_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV4_SRC;\n-\t\t\t\tif (ipv4_mask->hdr.dst_addr == UINT32_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV4_DST;\n-\t\t\t\tif (ipv4_mask->hdr.time_to_live == UINT8_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV4_TTL;\n-\t\t\t\tif (ipv4_mask->hdr.next_proto_id == UINT8_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV4_PROTO;\n-\t\t\t\tif (ipv4_mask->hdr.type_of_service == UINT8_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV4_TOS;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_IPV6:\n-\t\t\tipv6_spec = item->spec;\n-\t\t\tipv6_mask = item->mask;\n-\n-\t\t\tif (!(ipv6_spec && ipv6_mask))\n-\t\t\t\tbreak;\n-\n-\t\t\tif (ipv6_mask->hdr.payload_len) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t   item,\n-\t\t\t\t\t   \"Invalid IPv6 mask\");\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\n-\t\t\tif (is_tunnel) {\n-\t\t\t\tif (!memcmp(ipv6_mask->hdr.src_addr,\n-\t\t\t\t\t    ipv6_addr_mask,\n-\t\t\t\t\t    RTE_DIM(ipv6_mask->hdr.src_addr)))\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_IPV6_SRC;\n-\t\t\t\tif (!memcmp(ipv6_mask->hdr.dst_addr,\n-\t\t\t\t\t    ipv6_addr_mask,\n-\t\t\t\t\t    RTE_DIM(ipv6_mask->hdr.dst_addr)))\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_IPV6_DST;\n-\t\t\t\tif (ipv6_mask->hdr.proto == UINT8_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_IPV6_PROTO;\n-\t\t\t\tif (ipv6_mask->hdr.hop_limits == UINT8_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_IPV6_TTL;\n-\t\t\t} else {\n-\t\t\t\tif (!memcmp(ipv6_mask->hdr.src_addr,\n-\t\t\t\t\t    ipv6_addr_mask,\n-\t\t\t\t\t    RTE_DIM(ipv6_mask->hdr.src_addr)))\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV6_SRC;\n-\t\t\t\tif (!memcmp(ipv6_mask->hdr.dst_addr,\n-\t\t\t\t\t    ipv6_addr_mask,\n-\t\t\t\t\t    RTE_DIM(ipv6_mask->hdr.dst_addr)))\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV6_DST;\n-\t\t\t\tif (ipv6_mask->hdr.proto == UINT8_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV6_PROTO;\n-\t\t\t\tif (ipv6_mask->hdr.hop_limits == UINT8_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV6_HOP_LIMIT;\n-\t\t\t\tif ((ipv6_mask->hdr.vtc_flow &\n-\t\t\t\t\trte_cpu_to_be_32(RTE_IPV6_HDR_TC_MASK))\n-\t\t\t\t\t\t== rte_cpu_to_be_32\n-\t\t\t\t\t\t(RTE_IPV6_HDR_TC_MASK))\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV6_TOS;\n-\t\t\t}\n-\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_UDP:\n-\t\t\tudp_spec = item->spec;\n-\t\t\tudp_mask = item->mask;\n-\n-\t\t\tif (!(udp_spec && udp_mask))\n-\t\t\t\tbreak;\n-\n-\t\t\t/* Check UDP mask and update input set*/\n-\t\t\tif (udp_mask->hdr.dgram_len ||\n-\t\t\t    udp_mask->hdr.dgram_cksum) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t\t   item,\n-\t\t\t\t\t\t   \"Invalid UDP mask\");\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\n-\t\t\tif (is_tunnel) {\n-\t\t\t\tif (udp_mask->hdr.src_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_SRC_PORT;\n-\t\t\t\tif (udp_mask->hdr.dst_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_DST_PORT;\n-\t\t\t} else {\n-\t\t\t\tif (udp_mask->hdr.src_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_SRC_PORT;\n-\t\t\t\tif (udp_mask->hdr.dst_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_DST_PORT;\n-\t\t\t}\n-\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_TCP:\n-\t\t\ttcp_spec = item->spec;\n-\t\t\ttcp_mask = item->mask;\n-\n-\t\t\tif (!(tcp_spec && tcp_mask))\n-\t\t\t\tbreak;\n-\n-\t\t\t/* Check TCP mask and update input set */\n-\t\t\tif (tcp_mask->hdr.sent_seq ||\n-\t\t\t    tcp_mask->hdr.recv_ack ||\n-\t\t\t    tcp_mask->hdr.data_off ||\n-\t\t\t    tcp_mask->hdr.tcp_flags ||\n-\t\t\t    tcp_mask->hdr.rx_win ||\n-\t\t\t    tcp_mask->hdr.cksum ||\n-\t\t\t    tcp_mask->hdr.tcp_urp) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t\t   item,\n-\t\t\t\t\t\t   \"Invalid TCP mask\");\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\n-\t\t\tif (is_tunnel) {\n-\t\t\t\tif (tcp_mask->hdr.src_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_SRC_PORT;\n-\t\t\t\tif (tcp_mask->hdr.dst_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_DST_PORT;\n-\t\t\t} else {\n-\t\t\t\tif (tcp_mask->hdr.src_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_SRC_PORT;\n-\t\t\t\tif (tcp_mask->hdr.dst_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_DST_PORT;\n-\t\t\t}\n-\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_SCTP:\n-\t\t\tsctp_spec = item->spec;\n-\t\t\tsctp_mask = item->mask;\n-\n-\t\t\tif (!(sctp_spec && sctp_mask))\n-\t\t\t\tbreak;\n-\n-\t\t\t/* Check SCTP mask and update input set */\n-\t\t\tif (sctp_mask->hdr.cksum) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t   item,\n-\t\t\t\t\t   \"Invalid SCTP mask\");\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\n-\t\t\tif (is_tunnel) {\n-\t\t\t\tif (sctp_mask->hdr.src_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_SRC_PORT;\n-\t\t\t\tif (sctp_mask->hdr.dst_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_TUN_DST_PORT;\n-\t\t\t} else {\n-\t\t\t\tif (sctp_mask->hdr.src_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_SRC_PORT;\n-\t\t\t\tif (sctp_mask->hdr.dst_port == UINT16_MAX)\n-\t\t\t\t\tinput_set |= ICE_INSET_DST_PORT;\n-\t\t\t}\n-\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_ICMP:\n-\t\t\ticmp_mask = item->mask;\n-\t\t\tif (icmp_mask->hdr.icmp_code ||\n-\t\t\t    icmp_mask->hdr.icmp_cksum ||\n-\t\t\t    icmp_mask->hdr.icmp_ident ||\n-\t\t\t    icmp_mask->hdr.icmp_seq_nb) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t\t   item,\n-\t\t\t\t\t\t   \"Invalid ICMP mask\");\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\n-\t\t\tif (icmp_mask->hdr.icmp_type == UINT8_MAX)\n-\t\t\t\tinput_set |= ICE_INSET_ICMP;\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_ICMP6:\n-\t\t\ticmp6_mask = item->mask;\n-\t\t\tif (icmp6_mask->code ||\n-\t\t\t    icmp6_mask->checksum) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t\t   item,\n-\t\t\t\t\t\t   \"Invalid ICMP6 mask\");\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\n-\t\t\tif (icmp6_mask->type == UINT8_MAX)\n-\t\t\t\tinput_set |= ICE_INSET_ICMP6;\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n-\t\t\tvxlan_spec = item->spec;\n-\t\t\tvxlan_mask = item->mask;\n-\t\t\t/* Check if VXLAN item is used to describe protocol.\n-\t\t\t * If yes, both spec and mask should be NULL.\n-\t\t\t * If no, both spec and mask shouldn't be NULL.\n-\t\t\t */\n-\t\t\tif ((!vxlan_spec && vxlan_mask) ||\n-\t\t\t    (vxlan_spec && !vxlan_mask)) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t   item,\n-\t\t\t\t\t   \"Invalid VXLAN item\");\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\t\t\tif (vxlan_mask && vxlan_mask->vni[0] == UINT8_MAX &&\n-\t\t\t\t\tvxlan_mask->vni[1] == UINT8_MAX &&\n-\t\t\t\t\tvxlan_mask->vni[2] == UINT8_MAX)\n-\t\t\t\tinput_set |= ICE_INSET_TUN_ID;\n-\t\t\tis_tunnel = 1;\n-\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_NVGRE:\n-\t\t\tnvgre_spec = item->spec;\n-\t\t\tnvgre_mask = item->mask;\n-\t\t\t/* Check if NVGRE item is used to describe protocol.\n-\t\t\t * If yes, both spec and mask should be NULL.\n-\t\t\t * If no, both spec and mask shouldn't be NULL.\n-\t\t\t */\n-\t\t\tif ((!nvgre_spec && nvgre_mask) ||\n-\t\t\t    (nvgre_spec && !nvgre_mask)) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t   item,\n-\t\t\t\t\t   \"Invalid NVGRE item\");\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\t\t\tif (nvgre_mask && nvgre_mask->tni[0] == UINT8_MAX &&\n-\t\t\t\t\tnvgre_mask->tni[1] == UINT8_MAX &&\n-\t\t\t\t\tnvgre_mask->tni[2] == UINT8_MAX)\n-\t\t\t\tinput_set |= ICE_INSET_TUN_ID;\n-\t\t\tis_tunnel = 1;\n-\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ITEM_TYPE_VOID:\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t   item,\n-\t\t\t\t\t   \"Invalid pattern\");\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\treturn input_set;\n-}\n-\n-static int ice_flow_valid_inset(const struct rte_flow_item pattern[],\n-\t\t\tuint64_t inset, struct rte_flow_error *error)\n-{\n-\tuint64_t fields;\n-\n-\t/* get valid field */\n-\tfields = ice_get_flow_field(pattern, error);\n-\tif (!fields || fields & (~inset)) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM_SPEC,\n-\t\t\t\t   pattern,\n-\t\t\t\t   \"Invalid input set\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\treturn 0;\n+\trte_free(pattern_match_item);\n+\treturn NULL;\n }\n \n-static int ice_flow_valid_action(struct rte_eth_dev *dev,\n-\t\t\t\tconst struct rte_flow_action *actions,\n-\t\t\t\tstruct rte_flow_error *error)\n+static struct ice_flow_engine *\n+ice_parse_engine(struct ice_adapter *ad,\n+\t\tstruct ice_parser_list *parser_list,\n+\t\tconst struct rte_flow_item pattern[],\n+\t\tconst struct rte_flow_action actions[],\n+\t\tvoid **meta,\n+\t\tstruct rte_flow_error *error)\n {\n-\tconst struct rte_flow_action_queue *act_q;\n-\tuint16_t queue;\n-\tconst struct rte_flow_action *action;\n-\tfor (action = actions; action->type !=\n-\t\t\tRTE_FLOW_ACTION_TYPE_END; action++) {\n-\t\tswitch (action->type) {\n-\t\tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n-\t\t\tact_q = action->conf;\n-\t\t\tqueue = act_q->index;\n-\t\t\tif (queue >= dev->data->nb_rx_queues) {\n-\t\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION,\n-\t\t\t\t\t\tactions, \"Invalid queue ID for\"\n-\t\t\t\t\t\t\" switch filter.\");\n-\t\t\t\treturn -rte_errno;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ACTION_TYPE_DROP:\n-\t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ACTION, actions,\n-\t\t\t\t\t   \"Invalid action.\");\n-\t\t\treturn -rte_errno;\n-\t\t}\n+\tstruct ice_flow_engine *engine = NULL;\n+\tstruct ice_flow_parser *parser = NULL;\n+\tvoid *temp;\n+\tTAILQ_FOREACH_SAFE(parser, parser_list, node, temp) {\n+\t\tif (parser->parse_pattern_action(ad, parser->array,\n+\t\t\t\tparser->array_len, pattern, actions,\n+\t\t\t\tmeta, error) < 0)\n+\t\t\tcontinue;\n+\t\tengine = parser->engine;\n+\t\tbreak;\n \t}\n-\treturn 0;\n+\treturn engine;\n }\n \n static int\n-ice_flow_validate(struct rte_eth_dev *dev,\n-\t\t   const struct rte_flow_attr *attr,\n-\t\t   const struct rte_flow_item pattern[],\n-\t\t   const struct rte_flow_action actions[],\n-\t\t   struct rte_flow_error *error)\n+ice_flow_validate_filter(struct rte_eth_dev *dev,\n+\t\tconst struct rte_flow_attr *attr,\n+\t\tconst struct rte_flow_item pattern[],\n+\t\tconst struct rte_flow_action actions[],\n+\t\tstruct ice_flow_engine **engine,\n+\t\tvoid **meta,\n+\t\tstruct rte_flow_error *error)\n {\n-\tuint64_t inset = 0;\n \tint ret = ICE_ERR_NOT_SUPPORTED;\n+\tstruct ice_adapter *ad =\n+\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \n \tif (!pattern) {\n \t\trte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,\n-\t\t\t\t   NULL, \"NULL pattern.\");\n+\t\t\t\tNULL, \"NULL pattern.\");\n \t\treturn -rte_errno;\n \t}\n \n \tif (!actions) {\n \t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t   RTE_FLOW_ERROR_TYPE_ACTION_NUM,\n-\t\t\t\t   NULL, \"NULL action.\");\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION_NUM,\n+\t\t\t\tNULL, \"NULL action.\");\n \t\treturn -rte_errno;\n \t}\n-\n \tif (!attr) {\n \t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t   RTE_FLOW_ERROR_TYPE_ATTR,\n-\t\t\t\t   NULL, \"NULL attribute.\");\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ATTR,\n+\t\t\t\tNULL, \"NULL attribute.\");\n \t\treturn -rte_errno;\n \t}\n \n-\tret = ice_flow_valid_attr(attr, error);\n+\tret = ice_flow_valid_attr(ad, attr, error);\n \tif (ret)\n \t\treturn ret;\n \n-\tinset = ice_flow_valid_pattern(pattern, error);\n-\tif (!inset)\n-\t\treturn -rte_errno;\n-\n-\tret = ice_flow_valid_inset(pattern, inset, error);\n-\tif (ret)\n-\t\treturn ret;\n+\t*engine = ice_parse_engine(ad, &pf->rss_parser_list, pattern, actions,\n+\t\t\tmeta, error);\n+\tif (*engine != NULL)\n+\t\treturn 0;\n+\n+\tswitch (ice_pipeline_stage) {\n+\tcase ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY:\n+\tcase ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR:\n+\t\t*engine = ice_parse_engine(ad, &pf->dist_parser_list, pattern,\n+\t\t\t\tactions, meta, error);\n+\t\tbreak;\n+\tcase ICE_FLOW_CLASSIFY_STAGE_PERMISSION:\n+\t\t*engine = ice_parse_engine(ad, &pf->perm_parser_list, pattern,\n+\t\t\t\tactions, meta, error);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n \n-\tret = ice_flow_valid_action(dev, actions, error);\n-\tif (ret)\n-\t\treturn ret;\n+\tif (*engine == NULL)\n+\t\treturn -EINVAL;\n \n \treturn 0;\n }\n \n+static int\n+ice_flow_validate(struct rte_eth_dev *dev,\n+\t\tconst struct rte_flow_attr *attr,\n+\t\tconst struct rte_flow_item pattern[],\n+\t\tconst struct rte_flow_action actions[],\n+\t\tstruct rte_flow_error *error)\n+{\n+\tint ret = ICE_ERR_NOT_SUPPORTED;\n+\tvoid *meta = NULL;\n+\tstruct ice_flow_engine *engine = NULL;\n+\n+\tret = ice_flow_validate_filter(dev, attr, pattern, actions,\n+\t\t\t&engine, &meta, error);\n+\treturn ret;\n+}\n+\n static struct rte_flow *\n ice_flow_create(struct rte_eth_dev *dev,\n-\t\t const struct rte_flow_attr *attr,\n-\t\t const struct rte_flow_item pattern[],\n-\t\t const struct rte_flow_action actions[],\n-\t\t struct rte_flow_error *error)\n+\t\tconst struct rte_flow_attr *attr,\n+\t\tconst struct rte_flow_item pattern[],\n+\t\tconst struct rte_flow_action actions[],\n+\t\tstruct rte_flow_error *error)\n {\n \tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tstruct rte_flow *flow = NULL;\n-\tint ret;\n+\tint ret = 0;\n+\tstruct ice_adapter *ad =\n+\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tstruct ice_flow_engine *engine = NULL;\n+\tvoid *meta = NULL;\n \n \tflow = rte_zmalloc(\"ice_flow\", sizeof(struct rte_flow), 0);\n \tif (!flow) {\n@@ -626,65 +488,105 @@ ice_flow_create(struct rte_eth_dev *dev,\n \t\treturn flow;\n \t}\n \n-\tret = ice_flow_validate(dev, attr, pattern, actions, error);\n+\tret = ice_flow_validate_filter(dev, attr, pattern, actions,\n+\t\t\t&engine, &meta, error);\n \tif (ret < 0)\n \t\tgoto free_flow;\n \n-\tret = ice_create_switch_filter(pf, pattern, actions, flow, error);\n+\tif (engine->create == NULL)\n+\t\tgoto free_flow;\n+\n+\tret = engine->create(ad, flow, meta, error);\n \tif (ret)\n \t\tgoto free_flow;\n \n+\tflow->engine = engine;\n \tTAILQ_INSERT_TAIL(&pf->flow_list, flow, node);\n \treturn flow;\n \n free_flow:\n-\trte_flow_error_set(error, -ret,\n-\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n-\t\t\t   \"Failed to create flow.\");\n+\tPMD_DRV_LOG(ERR, \"Failed to create flow\");\n \trte_free(flow);\n \treturn NULL;\n }\n \n static int\n ice_flow_destroy(struct rte_eth_dev *dev,\n-\t\t struct rte_flow *flow,\n-\t\t struct rte_flow_error *error)\n+\t\tstruct rte_flow *flow,\n+\t\tstruct rte_flow_error *error)\n {\n \tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct ice_adapter *ad =\n+\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tint ret = 0;\n \n-\tret = ice_destroy_switch_filter(pf, flow, error);\n-\n+\tif (!flow || !flow->engine->destroy) {\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_HANDLE,\n+\t\t\t\tNULL, \"NULL flow or NULL destroy\");\n+\t\treturn -rte_errno;\n+\t}\n+\tret = flow->engine->destroy(ad, flow, error);\n \tif (!ret) {\n \t\tTAILQ_REMOVE(&pf->flow_list, flow, node);\n \t\trte_free(flow);\n-\t} else {\n-\t\trte_flow_error_set(error, -ret,\n-\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n-\t\t\t\t   \"Failed to destroy flow.\");\n-\t}\n+\t} else\n+\t\tPMD_DRV_LOG(ERR, \"Failed to destroy flow\");\n \n \treturn ret;\n }\n \n static int\n ice_flow_flush(struct rte_eth_dev *dev,\n-\t       struct rte_flow_error *error)\n+\t\tstruct rte_flow_error *error)\n {\n \tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n-\tstruct rte_flow *p_flow;\n+\tstruct rte_flow *p_flow = NULL;\n \tvoid *temp;\n \tint ret = 0;\n \n \tTAILQ_FOREACH_SAFE(p_flow, &pf->flow_list, node, temp) {\n \t\tret = ice_flow_destroy(dev, p_flow, error);\n \t\tif (ret) {\n-\t\t\trte_flow_error_set(error, -ret,\n-\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n-\t\t\t\t\t   \"Failed to flush SW flows.\");\n-\t\t\treturn -rte_errno;\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to flush flows\");\n+\t\t\treturn -EINVAL;\n \t\t}\n \t}\n \n \treturn ret;\n }\n+\n+static int\n+ice_flow_query_count(struct rte_eth_dev *dev,\n+\t\tstruct rte_flow *flow,\n+\t\tconst struct rte_flow_action *actions,\n+\t\tvoid *data,\n+\t\tstruct rte_flow_error *error)\n+{\n+\tint ret = -EINVAL;\n+\tstruct ice_adapter *ad =\n+\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\n+\tif (!flow || !flow->engine->query) {\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_HANDLE,\n+\t\t\t\tNULL, \"NULL flow or NULL query\");\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tfor (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {\n+\t\tswitch (actions->type) {\n+\t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n+\t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_COUNT:\n+\t\t\tret = flow->engine->query(ad, flow, data, error);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\tactions,\n+\t\t\t\t\t\"action not supported\");\n+\t\t}\n+\t}\n+\treturn ret;\n+}\ndiff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h\nindex 1953905f7..3dac38b4e 100644\n--- a/drivers/net/ice/ice_generic_flow.h\n+++ b/drivers/net/ice/ice_generic_flow.h\n@@ -7,615 +7,177 @@\n \n #include <rte_flow_driver.h>\n \n-struct ice_flow_pattern {\n-\tenum rte_flow_item_type *items;\n-\tuint64_t sw_fields;\n-};\n-\n-#define ICE_INSET_NONE            0x00000000000000000ULL\n-\n-/* bit0 ~ bit 7 */\n-#define ICE_INSET_SMAC            0x0000000000000001ULL\n-#define ICE_INSET_DMAC            0x0000000000000002ULL\n-#define ICE_INSET_ETHERTYPE       0x0000000000000020ULL\n-\n-/* bit 8 ~ bit 15 */\n-#define ICE_INSET_IPV4_SRC        0x0000000000000100ULL\n-#define ICE_INSET_IPV4_DST        0x0000000000000200ULL\n-#define ICE_INSET_IPV6_SRC        0x0000000000000400ULL\n-#define ICE_INSET_IPV6_DST        0x0000000000000800ULL\n-#define ICE_INSET_SRC_PORT        0x0000000000001000ULL\n-#define ICE_INSET_DST_PORT        0x0000000000002000ULL\n-#define ICE_INSET_ARP             0x0000000000004000ULL\n-\n-/* bit 16 ~ bit 31 */\n-#define ICE_INSET_IPV4_TOS        0x0000000000010000ULL\n-#define ICE_INSET_IPV4_PROTO      0x0000000000020000ULL\n-#define ICE_INSET_IPV4_TTL        0x0000000000040000ULL\n-#define ICE_INSET_IPV6_TOS        0x0000000000100000ULL\n-#define ICE_INSET_IPV6_PROTO      0x0000000000200000ULL\n-#define ICE_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL\n-#define ICE_INSET_ICMP            0x0000000001000000ULL\n-#define ICE_INSET_ICMP6           0x0000000002000000ULL\n-\n-/* bit 32 ~ bit 47, tunnel fields */\n-#define ICE_INSET_TUN_SMAC           0x0000000100000000ULL\n-#define ICE_INSET_TUN_DMAC           0x0000000200000000ULL\n-#define ICE_INSET_TUN_IPV4_SRC       0x0000000400000000ULL\n-#define ICE_INSET_TUN_IPV4_DST       0x0000000800000000ULL\n-#define ICE_INSET_TUN_IPV4_TTL       0x0000001000000000ULL\n-#define ICE_INSET_TUN_IPV4_PROTO     0x0000002000000000ULL\n-#define ICE_INSET_TUN_IPV6_SRC       0x0000004000000000ULL\n-#define ICE_INSET_TUN_IPV6_DST       0x0000008000000000ULL\n-#define ICE_INSET_TUN_IPV6_TTL       0x0000010000000000ULL\n-#define ICE_INSET_TUN_IPV6_PROTO     0x0000020000000000ULL\n-#define ICE_INSET_TUN_SRC_PORT       0x0000040000000000ULL\n-#define ICE_INSET_TUN_DST_PORT       0x0000080000000000ULL\n-#define ICE_INSET_TUN_ID             0x0000100000000000ULL\n-\n-/* bit 48 ~ bit 55 */\n-#define ICE_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL\n-\n-#define ICE_FLAG_VLAN_INNER  0x00000001ULL\n-#define ICE_FLAG_VLAN_OUTER  0x00000002ULL\n-\n-#define INSET_ETHER ( \\\n-\tICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE)\n-#define INSET_MAC_IPV4 ( \\\n-\tICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \\\n-\tICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS)\n-#define INSET_MAC_IPV4_L4 ( \\\n-\tICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \\\n-\tICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS | ICE_INSET_DST_PORT | \\\n-\tICE_INSET_SRC_PORT)\n-#define INSET_MAC_IPV4_ICMP ( \\\n-\tICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \\\n-\tICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS | ICE_INSET_ICMP)\n-#define INSET_MAC_IPV6 ( \\\n-\tICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \\\n-\tICE_INSET_IPV6_TOS | ICE_INSET_IPV6_HOP_LIMIT)\n-#define INSET_MAC_IPV6_L4 ( \\\n-\tICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \\\n-\tICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_IPV6_TOS | \\\n-\tICE_INSET_DST_PORT | ICE_INSET_SRC_PORT)\n-#define INSET_MAC_IPV6_ICMP ( \\\n-\tICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \\\n-\tICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_IPV6_TOS | ICE_INSET_ICMP6)\n-#define INSET_TUNNEL_IPV4_TYPE1 ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_IPV4_TTL | ICE_INSET_TUN_IPV4_PROTO | \\\n-\tICE_INSET_TUN_ID)\n-#define INSET_TUNNEL_IPV4_TYPE2 ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_IPV4_TTL | ICE_INSET_TUN_IPV4_PROTO | \\\n-\tICE_INSET_TUN_SRC_PORT | ICE_INSET_TUN_DST_PORT | \\\n-\tICE_INSET_TUN_ID)\n-#define INSET_TUNNEL_IPV4_TYPE3 ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_IPV4_TTL | ICE_INSET_ICMP | \\\n-\tICE_INSET_TUN_ID)\n-#define INSET_TUNNEL_IPV6_TYPE1 ( \\\n-\tICE_INSET_TUN_IPV6_SRC | ICE_INSET_TUN_IPV6_DST | \\\n-\tICE_INSET_TUN_IPV6_TTL | ICE_INSET_TUN_IPV6_PROTO | \\\n-\tICE_INSET_TUN_ID)\n-#define INSET_TUNNEL_IPV6_TYPE2 ( \\\n-\tICE_INSET_TUN_IPV6_SRC | ICE_INSET_TUN_IPV6_DST | \\\n-\tICE_INSET_TUN_IPV6_TTL | ICE_INSET_TUN_IPV6_PROTO | \\\n-\tICE_INSET_TUN_SRC_PORT | ICE_INSET_TUN_DST_PORT | \\\n-\tICE_INSET_TUN_ID)\n-#define INSET_TUNNEL_IPV6_TYPE3 ( \\\n-\tICE_INSET_TUN_IPV6_SRC | ICE_INSET_TUN_IPV6_DST | \\\n-\tICE_INSET_TUN_IPV6_TTL | ICE_INSET_ICMP6 | \\\n-\tICE_INSET_TUN_ID)\n-\n-/* L2 */\n-static enum rte_flow_item_type pattern_ethertype[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-/* non-tunnel IPv4 */\n-static enum rte_flow_item_type pattern_ipv4[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_udp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_tcp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_TCP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_sctp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_SCTP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_icmp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_ICMP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-/* non-tunnel IPv6 */\n-static enum rte_flow_item_type pattern_ipv6[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv6_udp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv6_tcp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_TCP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv6_sctp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_SCTP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv6_icmp6[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_ICMP6,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-/* IPv4 VXLAN IPv4 */\n-static enum rte_flow_item_type pattern_ipv4_vxlan_ipv4[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_ipv4_udp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_ipv4_tcp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_TCP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_ipv4_sctp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_SCTP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_ipv4_icmp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_ICMP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-/* IPv4 VXLAN MAC IPv4 */\n-static enum rte_flow_item_type pattern_ipv4_vxlan_eth_ipv4[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_eth_ipv4_udp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_eth_ipv4_tcp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_TCP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_eth_ipv4_sctp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_SCTP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_eth_ipv4_icmp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_ICMP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-/* IPv4 VXLAN IPv6 */\n-static enum rte_flow_item_type pattern_ipv4_vxlan_ipv6[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_ipv6_udp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_ipv6_tcp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_TCP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_ipv6_sctp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_SCTP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_ipv6_icmp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_ICMP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-/* IPv4 VXLAN MAC IPv6 */\n-static enum rte_flow_item_type pattern_ipv4_vxlan_eth_ipv6[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_eth_ipv6_udp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_eth_ipv6_tcp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_TCP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_eth_ipv6_sctp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_SCTP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_vxlan_eth_ipv6_icmp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_VXLAN,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_ICMP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-/* IPv4 NVGRE IPv4 */\n-static enum rte_flow_item_type pattern_ipv4_nvgre_ipv4[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_ipv4_udp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_ipv4_tcp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_TCP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_ipv4_sctp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_SCTP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_ipv4_icmp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_ICMP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-/* IPv4 NVGRE MAC IPv4 */\n-static enum rte_flow_item_type pattern_ipv4_nvgre_eth_ipv4[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_eth_ipv4_udp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_eth_ipv4_tcp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_TCP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_eth_ipv4_sctp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_SCTP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_eth_ipv4_icmp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_ICMP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-/* IPv4 NVGRE IPv6 */\n-static enum rte_flow_item_type pattern_ipv4_nvgre_ipv6[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_ipv6_udp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_ipv6_tcp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_TCP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_ipv6_sctp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_SCTP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-\n-/* IPv4 NVGRE MAC IPv6 */\n-static enum rte_flow_item_type pattern_ipv4_nvgre_eth_ipv6[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_eth_ipv6_udp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_UDP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_eth_ipv6_tcp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_TCP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static enum rte_flow_item_type pattern_ipv4_nvgre_eth_ipv6_sctp[] = {\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV4,\n-\tRTE_FLOW_ITEM_TYPE_NVGRE,\n-\tRTE_FLOW_ITEM_TYPE_ETH,\n-\tRTE_FLOW_ITEM_TYPE_IPV6,\n-\tRTE_FLOW_ITEM_TYPE_SCTP,\n-\tRTE_FLOW_ITEM_TYPE_END,\n-};\n-\n-static struct ice_flow_pattern ice_supported_patterns[] = {\n-\t{pattern_ethertype, INSET_ETHER},\n-\t{pattern_ipv4, INSET_MAC_IPV4},\n-\t{pattern_ipv4_udp, INSET_MAC_IPV4_L4},\n-\t{pattern_ipv4_sctp, INSET_MAC_IPV4_L4},\n-\t{pattern_ipv4_tcp, INSET_MAC_IPV4_L4},\n-\t{pattern_ipv4_icmp, INSET_MAC_IPV4_ICMP},\n-\t{pattern_ipv6, INSET_MAC_IPV6},\n-\t{pattern_ipv6_udp, INSET_MAC_IPV6_L4},\n-\t{pattern_ipv6_sctp, INSET_MAC_IPV6_L4},\n-\t{pattern_ipv6_tcp, INSET_MAC_IPV6_L4},\n-\t{pattern_ipv6_icmp6, INSET_MAC_IPV6_ICMP},\n-\t{pattern_ipv4_vxlan_ipv4, INSET_TUNNEL_IPV4_TYPE1},\n-\t{pattern_ipv4_vxlan_ipv4_udp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_vxlan_ipv4_tcp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_vxlan_ipv4_sctp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_vxlan_ipv4_icmp, INSET_TUNNEL_IPV4_TYPE3},\n-\t{pattern_ipv4_vxlan_eth_ipv4, INSET_TUNNEL_IPV4_TYPE1},\n-\t{pattern_ipv4_vxlan_eth_ipv4_udp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_vxlan_eth_ipv4_tcp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_vxlan_eth_ipv4_sctp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_vxlan_eth_ipv4_icmp, INSET_TUNNEL_IPV4_TYPE3},\n-\t{pattern_ipv4_vxlan_ipv6, INSET_TUNNEL_IPV6_TYPE1},\n-\t{pattern_ipv4_vxlan_ipv6_udp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_vxlan_ipv6_tcp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_vxlan_ipv6_sctp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_vxlan_ipv6_icmp, INSET_TUNNEL_IPV6_TYPE3},\n-\t{pattern_ipv4_vxlan_eth_ipv6, INSET_TUNNEL_IPV6_TYPE1},\n-\t{pattern_ipv4_vxlan_eth_ipv6_udp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_vxlan_eth_ipv6_tcp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_vxlan_eth_ipv6_sctp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_vxlan_eth_ipv6_icmp, INSET_TUNNEL_IPV6_TYPE3},\n-\t{pattern_ipv4_nvgre_ipv4, INSET_TUNNEL_IPV4_TYPE1},\n-\t{pattern_ipv4_nvgre_ipv4_udp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_nvgre_ipv4_tcp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_nvgre_ipv4_sctp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_nvgre_ipv4_icmp, INSET_TUNNEL_IPV4_TYPE3},\n-\t{pattern_ipv4_nvgre_eth_ipv4, INSET_TUNNEL_IPV4_TYPE1},\n-\t{pattern_ipv4_nvgre_eth_ipv4_udp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_nvgre_eth_ipv4_tcp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_nvgre_eth_ipv4_sctp, INSET_TUNNEL_IPV4_TYPE2},\n-\t{pattern_ipv4_nvgre_eth_ipv4_icmp, INSET_TUNNEL_IPV4_TYPE3},\n-\t{pattern_ipv4_nvgre_ipv6, INSET_TUNNEL_IPV6_TYPE1},\n-\t{pattern_ipv4_nvgre_ipv6_udp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_nvgre_ipv6_tcp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_nvgre_ipv6_sctp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_nvgre_eth_ipv6, INSET_TUNNEL_IPV6_TYPE1},\n-\t{pattern_ipv4_nvgre_eth_ipv6_udp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_nvgre_eth_ipv6_tcp, INSET_TUNNEL_IPV6_TYPE2},\n-\t{pattern_ipv4_nvgre_eth_ipv6_sctp, INSET_TUNNEL_IPV6_TYPE2},\n-};\n+#define ICE_INSET_NONE               0ULL\n+\n+/* bit0 ~ bit 11 */\n+#define ICE_INSET_SMAC               (1ULL << 0)\n+#define ICE_INSET_DMAC               (1ULL << 1)\n+#define ICE_INSET_VLAN_INNER         (1ULL << 2)\n+#define ICE_INSET_VLAN_OUTER         (1ULL << 3)\n+#define ICE_INSET_ETHERTYPE          (1ULL << 4)\n+#define ICE_INSET_ARP_SHA            (1ULL << 5)\n+#define ICE_INSET_ARP_SPA            (1ULL << 6)\n+#define ICE_INSET_ARP_THA            (1ULL << 7)\n+#define ICE_INSET_ARP_TPA            (1ULL << 8)\n+#define ICE_INSET_ARP_OP             (1ULL << 9)\n+\n+/* bit 12 ~ bit 23 */\n+#define ICE_INSET_IPV4_SRC           (1ULL << 12)\n+#define ICE_INSET_IPV4_DST           (1ULL << 13)\n+#define ICE_INSET_IPV4_TOS           (1ULL << 14)\n+#define ICE_INSET_IPV4_PROTO         (1ULL << 15)\n+#define ICE_INSET_IPV4_TTL           (1ULL << 16)\n+#define ICE_INSET_IPV6_SRC           (1ULL << 17)\n+#define ICE_INSET_IPV6_DST           (1ULL << 18)\n+#define ICE_INSET_IPV6_NEXT_HDR      (1ULL << 19)\n+#define ICE_INSET_IPV6_HOP_LIMIT     (1ULL << 20)\n+#define ICE_INSET_IPV6_TC            (1ULL << 21)\n+#define ICE_INSET_TCP_FLAGS          (1ULL << 22)\n+\n+/* bit 24 ~ bit 35 */\n+#define ICE_INSET_ICMP_TYPE          (1ULL << 24)\n+#define ICE_INSET_ICMP_CODE          (1ULL << 25)\n+#define ICE_INSET_ICMP6_TYPE         (1ULL << 26)\n+#define ICE_INSET_ICMP6_CODE         (1ULL << 27)\n+#define ICE_INSET_TCP_SRC_PORT       (1ULL << 28)\n+#define ICE_INSET_TCP_DST_PORT       (1ULL << 29)\n+#define ICE_INSET_UDP_SRC_PORT       (1ULL << 30)\n+#define ICE_INSET_UDP_DST_PORT       (1ULL << 31)\n+#define ICE_INSET_SCTP_SRC_PORT      (1ULL << 32)\n+#define ICE_INSET_SCTP_DST_PORT      (1ULL << 33)\n+#define ICE_INSET_ICMP_SRC_PORT      (1ULL << 34)\n+#define ICE_INSET_ICMP_DST_PORT      (1ULL << 35)\n+\n+/* bit 36 ~ bit 59, tunnel fields */\n+#define ICE_INSET_TUN_SMAC           (1ULL << 36)\n+#define ICE_INSET_TUN_DMAC           (1ULL << 37)\n+#define ICE_INSET_TUN_IPV4_SRC       (1ULL << 38)\n+#define ICE_INSET_TUN_IPV4_DST       (1ULL << 39)\n+#define ICE_INSET_TUN_IPV4_TTL       (1ULL << 40)\n+#define ICE_INSET_TUN_IPV4_PROTO     (1ULL << 41)\n+#define ICE_INSET_TUN_IPV4_TOS       (1ULL << 42)\n+#define ICE_INSET_TUN_IPV6_SRC       (1ULL << 43)\n+#define ICE_INSET_TUN_IPV6_DST       (1ULL << 44)\n+#define ICE_INSET_TUN_IPV6_HOP_LIMIT (1ULL << 45)\n+#define ICE_INSET_TUN_IPV6_NEXT_HDR  (1ULL << 46)\n+#define ICE_INSET_TUN_IPV6_TC        (1ULL << 47)\n+#define ICE_INSET_TUN_SRC_PORT       (1ULL << 48)\n+#define ICE_INSET_TUN_DST_PORT       (1ULL << 49)\n+#define ICE_INSET_TUN_ICMP_TYPE      (1ULL << 50)\n+#define ICE_INSET_TUN_ICMP_CODE      (1ULL << 51)\n+#define ICE_INSET_TUN_ICMP6_TYPE     (1ULL << 52)\n+#define ICE_INSET_TUN_ICMP6_CODE     (1ULL << 53)\n+#define ICE_INSET_TUN_ID             (1ULL << 54)\n+#define ICE_INSET_TUN_TYPE           (1ULL << 55)\n+#define ICE_INSET_GTPU_TEID          (1ULL << 56)\n+#define ICE_INSET_GTPU_QFI           (1ULL << 57)\n+#define ICE_INSET_GTP_EH_PDU         (1ULL << 58)\n+#define ICE_INSET_TUN_TCP_FLAGS      (1ULL << 59)\n+\n+/* bit 60 ~ bit 63 */\n+#define ICE_INSET_LAST_ETHER_TYPE    (1ULL << 60)\n+\n+\n+struct ice_adapter;\n+\n+extern const struct rte_flow_ops ice_flow_ops;\n+\n+/* engine types. */\n+enum ice_flow_engine_type {\n+\tICE_FLOW_ENGINE_NONE = 0,\n+\tICE_FLOW_ENGINE_FDIR,\n+\tICE_FLOW_ENGINE_SWITCH,\n+\tICE_FLOW_ENGINE_HASH,\n+\tICE_FLOW_ENGINE_ACL,\n+\tICE_FLOW_ENGINE_MAX,\n+};\n+\n+/**\n+ * classification stages.\n+ * for non-pipeline mode, we have two classification stages: Distributor/RSS\n+ * for pipeline-mode we have three classification stages:\n+ * Permission/Distributor/RSS\n+ */\n+enum ice_flow_classification_stage {\n+\tICE_FLOW_STAGE_NONE = 0,\n+\tICE_FLOW_STAGE_RSS,\n+\tICE_FLOW_STAGE_PERMISSION,\n+\tICE_FLOW_STAGE_DISTRIBUTOR,\n+\tICE_FLOW_STAGE_MAX,\n+};\n+\n+/* pattern structure */\n+struct ice_pattern_match_item {\n+\tenum rte_flow_item_type *pattern_list;\n+\t/* pattern_list must end with RTE_FLOW_ITEM_TYPE_END */\n+\tuint64_t input_set_mask;\n+\tuint64_t meta;\n+};\n+\n+typedef int (*engine_init_t)(struct ice_adapter *ad);\n+typedef void (*engine_uninit_t)(struct ice_adapter *ad);\n+typedef int (*engine_create_t)(struct ice_adapter *ad,\n+\t\tstruct rte_flow *flow,\n+\t\tvoid *meta,\n+\t\tstruct rte_flow_error *error);\n+typedef int (*engine_destroy_t)(struct ice_adapter *ad,\n+\t\tstruct rte_flow *flow,\n+\t\tstruct rte_flow_error *error);\n+typedef int (*engine_query_t)(struct ice_adapter *ad,\n+\t\tstruct rte_flow *flow,\n+\t\tvoid *data,\n+\t\tstruct rte_flow_error *error);\n+typedef void (*engine_free_t) (struct rte_flow *flow);\n+typedef int (*parse_pattern_action_t)(struct ice_adapter *ad,\n+\t\tstruct ice_pattern_match_item *array,\n+\t\tuint32_t array_len,\n+\t\tconst struct rte_flow_item pattern[],\n+\t\tconst struct rte_flow_action actions[],\n+\t\tvoid **meta,\n+\t\tstruct rte_flow_error *error);\n+\n+/* Struct to store engine created. */\n+struct ice_flow_engine {\n+\tTAILQ_ENTRY(ice_flow_engine) node;\n+\tengine_init_t init;\n+\tengine_uninit_t uninit;\n+\tengine_create_t create;\n+\tengine_destroy_t destroy;\n+\tengine_query_t query;\n+\tengine_free_t free;\n+\tenum ice_flow_engine_type type;\n+};\n+TAILQ_HEAD(ice_engine_list, ice_flow_engine);\n+\n+/* Struct to store flow created. */\n+struct rte_flow {\n+TAILQ_ENTRY(rte_flow) node;\n+\tstruct ice_flow_engine *engine;\n+\tvoid *rule;\n+};\n+\n+/* Struct to store parser created. */\n+struct ice_flow_parser {\n+\tTAILQ_ENTRY(ice_flow_parser) node;\n+\tstruct ice_flow_engine *engine;\n+\tstruct ice_pattern_match_item *array;\n+\tuint32_t array_len;\n+\tparse_pattern_action_t parse_pattern_action;\n+\tenum ice_flow_classification_stage stage;\n+};\n+\n+void ice_register_flow_engine(struct ice_flow_engine *engine);\n+int ice_flow_init(struct ice_adapter *ad);\n+void ice_flow_uninit(struct ice_adapter *ad);\n+int ice_register_parser(struct ice_flow_parser *parser,\n+\t\tstruct ice_adapter *ad);\n+void ice_unregister_parser(struct ice_flow_parser *parser,\n+\t\tstruct ice_adapter *ad);\n+struct ice_pattern_match_item *\n+ice_search_pattern_match_item(\n+\t\tconst struct rte_flow_item pattern[],\n+\t\tstruct ice_pattern_match_item *array,\n+\t\tuint32_t array_len,\n+\t\tstruct rte_flow_error *error);\n \n #endif\ndiff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c\nindex b88b4f59a..6b72bf252 100644\n--- a/drivers/net/ice/ice_switch_filter.c\n+++ b/drivers/net/ice/ice_switch_filter.c\n@@ -2,515 +2,4 @@\n  * Copyright(c) 2019 Intel Corporation\n  */\n \n-#include <sys/queue.h>\n-#include <stdio.h>\n-#include <errno.h>\n-#include <stdint.h>\n-#include <string.h>\n-#include <unistd.h>\n-#include <stdarg.h>\n \n-#include <rte_debug.h>\n-#include <rte_ether.h>\n-#include <rte_ethdev_driver.h>\n-#include <rte_log.h>\n-#include <rte_malloc.h>\n-#include <rte_eth_ctrl.h>\n-#include <rte_tailq.h>\n-#include <rte_flow_driver.h>\n-\n-#include \"ice_logs.h\"\n-#include \"base/ice_type.h\"\n-#include \"ice_switch_filter.h\"\n-\n-static int\n-ice_parse_switch_filter(const struct rte_flow_item pattern[],\n-\t\t\tconst struct rte_flow_action actions[],\n-\t\t\tstruct rte_flow_error *error,\n-\t\t\tstruct ice_adv_lkup_elem *list,\n-\t\t\tuint16_t *lkups_num,\n-\t\t\tenum ice_sw_tunnel_type tun_type)\n-{\n-\tconst struct rte_flow_item *item = pattern;\n-\tenum rte_flow_item_type item_type;\n-\tconst struct rte_flow_item_eth *eth_spec, *eth_mask;\n-\tconst struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;\n-\tconst struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;\n-\tconst struct rte_flow_item_tcp *tcp_spec, *tcp_mask;\n-\tconst struct rte_flow_item_udp *udp_spec, *udp_mask;\n-\tconst struct rte_flow_item_sctp *sctp_spec, *sctp_mask;\n-\tconst struct rte_flow_item_nvgre  *nvgre_spec, *nvgre_mask;\n-\tconst struct rte_flow_item_vxlan  *vxlan_spec, *vxlan_mask;\n-\tuint16_t j, t = 0;\n-\tuint16_t tunnel_valid = 0;\n-\n-\tfor (item = pattern; item->type !=\n-\t\t\tRTE_FLOW_ITEM_TYPE_END; item++) {\n-\t\titem_type = item->type;\n-\n-\t\tswitch (item_type) {\n-\t\tcase RTE_FLOW_ITEM_TYPE_ETH:\n-\t\t\teth_spec = item->spec;\n-\t\t\teth_mask = item->mask;\n-\t\t\tif (eth_spec && eth_mask) {\n-\t\t\t\tlist[t].type = (tun_type == ICE_NON_TUN) ?\n-\t\t\t\t\tICE_MAC_OFOS : ICE_MAC_IL;\n-\t\t\t\tstruct ice_ether_hdr *h;\n-\t\t\t\tstruct ice_ether_hdr *m;\n-\t\t\t\tuint16_t i = 0;\n-\t\t\t\th = &list[t].h_u.eth_hdr;\n-\t\t\t\tm = &list[t].m_u.eth_hdr;\n-\t\t\t\tfor (j = 0; j < RTE_ETHER_ADDR_LEN; j++) {\n-\t\t\t\t\tif (eth_mask->src.addr_bytes[j] ==\n-\t\t\t\t\t\t\t\tUINT8_MAX) {\n-\t\t\t\t\t\th->src_addr[j] =\n-\t\t\t\t\t\teth_spec->src.addr_bytes[j];\n-\t\t\t\t\t\tm->src_addr[j] =\n-\t\t\t\t\t\teth_mask->src.addr_bytes[j];\n-\t\t\t\t\t\ti = 1;\n-\t\t\t\t\t}\n-\t\t\t\t\tif (eth_mask->dst.addr_bytes[j] ==\n-\t\t\t\t\t\t\t\tUINT8_MAX) {\n-\t\t\t\t\t\th->dst_addr[j] =\n-\t\t\t\t\t\teth_spec->dst.addr_bytes[j];\n-\t\t\t\t\t\tm->dst_addr[j] =\n-\t\t\t\t\t\teth_mask->dst.addr_bytes[j];\n-\t\t\t\t\t\ti = 1;\n-\t\t\t\t\t}\n-\t\t\t\t}\n-\t\t\t\tif (i)\n-\t\t\t\t\tt++;\n-\t\t\t\tif (eth_mask->type == UINT16_MAX) {\n-\t\t\t\t\tlist[t].type = ICE_ETYPE_OL;\n-\t\t\t\t\tlist[t].h_u.ethertype.ethtype_id =\n-\t\t\t\t\t\teth_spec->type;\n-\t\t\t\t\tlist[t].m_u.ethertype.ethtype_id =\n-\t\t\t\t\t\tUINT16_MAX;\n-\t\t\t\t\tt++;\n-\t\t\t\t}\n-\t\t\t} else if (!eth_spec && !eth_mask) {\n-\t\t\t\tlist[t].type = (tun_type == ICE_NON_TUN) ?\n-\t\t\t\t\tICE_MAC_OFOS : ICE_MAC_IL;\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n-\t\t\tipv4_spec = item->spec;\n-\t\t\tipv4_mask = item->mask;\n-\t\t\tif (ipv4_spec && ipv4_mask) {\n-\t\t\t\tlist[t].type = (tun_type == ICE_NON_TUN) ?\n-\t\t\t\t\tICE_IPV4_OFOS : ICE_IPV4_IL;\n-\t\t\t\tif (ipv4_mask->hdr.src_addr == UINT32_MAX) {\n-\t\t\t\t\tlist[t].h_u.ipv4_hdr.src_addr =\n-\t\t\t\t\t\tipv4_spec->hdr.src_addr;\n-\t\t\t\t\tlist[t].m_u.ipv4_hdr.src_addr =\n-\t\t\t\t\t\tUINT32_MAX;\n-\t\t\t\t}\n-\t\t\t\tif (ipv4_mask->hdr.dst_addr == UINT32_MAX) {\n-\t\t\t\t\tlist[t].h_u.ipv4_hdr.dst_addr =\n-\t\t\t\t\t\tipv4_spec->hdr.dst_addr;\n-\t\t\t\t\tlist[t].m_u.ipv4_hdr.dst_addr =\n-\t\t\t\t\t\tUINT32_MAX;\n-\t\t\t\t}\n-\t\t\t\tif (ipv4_mask->hdr.time_to_live == UINT8_MAX) {\n-\t\t\t\t\tlist[t].h_u.ipv4_hdr.time_to_live =\n-\t\t\t\t\t\tipv4_spec->hdr.time_to_live;\n-\t\t\t\t\tlist[t].m_u.ipv4_hdr.time_to_live =\n-\t\t\t\t\t\tUINT8_MAX;\n-\t\t\t\t}\n-\t\t\t\tif (ipv4_mask->hdr.next_proto_id == UINT8_MAX) {\n-\t\t\t\t\tlist[t].h_u.ipv4_hdr.protocol =\n-\t\t\t\t\t\tipv4_spec->hdr.next_proto_id;\n-\t\t\t\t\tlist[t].m_u.ipv4_hdr.protocol =\n-\t\t\t\t\t\tUINT8_MAX;\n-\t\t\t\t}\n-\t\t\t\tif (ipv4_mask->hdr.type_of_service ==\n-\t\t\t\t\t\tUINT8_MAX) {\n-\t\t\t\t\tlist[t].h_u.ipv4_hdr.tos =\n-\t\t\t\t\t\tipv4_spec->hdr.type_of_service;\n-\t\t\t\t\tlist[t].m_u.ipv4_hdr.tos = UINT8_MAX;\n-\t\t\t\t}\n-\t\t\t\tt++;\n-\t\t\t} else if (!ipv4_spec && !ipv4_mask) {\n-\t\t\t\tlist[t].type = (tun_type == ICE_NON_TUN) ?\n-\t\t\t\t\tICE_IPV4_OFOS : ICE_IPV4_IL;\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ITEM_TYPE_IPV6:\n-\t\t\tipv6_spec = item->spec;\n-\t\t\tipv6_mask = item->mask;\n-\t\t\tif (ipv6_spec && ipv6_mask) {\n-\t\t\t\tlist[t].type = (tun_type == ICE_NON_TUN) ?\n-\t\t\t\t\tICE_IPV6_OFOS : ICE_IPV6_IL;\n-\t\t\t\tstruct ice_ipv6_hdr *f;\n-\t\t\t\tstruct ice_ipv6_hdr *s;\n-\t\t\t\tf = &list[t].h_u.ipv6_hdr;\n-\t\t\t\ts = &list[t].m_u.ipv6_hdr;\n-\t\t\t\tfor (j = 0; j < ICE_IPV6_ADDR_LENGTH; j++) {\n-\t\t\t\t\tif (ipv6_mask->hdr.src_addr[j] ==\n-\t\t\t\t\t\t\t\tUINT8_MAX) {\n-\t\t\t\t\t\tf->src_addr[j] =\n-\t\t\t\t\t\tipv6_spec->hdr.src_addr[j];\n-\t\t\t\t\t\ts->src_addr[j] =\n-\t\t\t\t\t\tipv6_mask->hdr.src_addr[j];\n-\t\t\t\t\t}\n-\t\t\t\t\tif (ipv6_mask->hdr.dst_addr[j] ==\n-\t\t\t\t\t\t\t\tUINT8_MAX) {\n-\t\t\t\t\t\tf->dst_addr[j] =\n-\t\t\t\t\t\tipv6_spec->hdr.dst_addr[j];\n-\t\t\t\t\t\ts->dst_addr[j] =\n-\t\t\t\t\t\tipv6_mask->hdr.dst_addr[j];\n-\t\t\t\t\t}\n-\t\t\t\t}\n-\t\t\t\tif (ipv6_mask->hdr.proto == UINT8_MAX) {\n-\t\t\t\t\tf->next_hdr =\n-\t\t\t\t\t\tipv6_spec->hdr.proto;\n-\t\t\t\t\ts->next_hdr = UINT8_MAX;\n-\t\t\t\t}\n-\t\t\t\tif (ipv6_mask->hdr.hop_limits == UINT8_MAX) {\n-\t\t\t\t\tf->hop_limit =\n-\t\t\t\t\t\tipv6_spec->hdr.hop_limits;\n-\t\t\t\t\ts->hop_limit = UINT8_MAX;\n-\t\t\t\t}\n-\t\t\t\tt++;\n-\t\t\t} else if (!ipv6_spec && !ipv6_mask) {\n-\t\t\t\tlist[t].type = (tun_type == ICE_NON_TUN) ?\n-\t\t\t\t\tICE_IPV4_OFOS : ICE_IPV4_IL;\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ITEM_TYPE_UDP:\n-\t\t\tudp_spec = item->spec;\n-\t\t\tudp_mask = item->mask;\n-\t\t\tif (udp_spec && udp_mask) {\n-\t\t\t\tif (tun_type == ICE_SW_TUN_VXLAN &&\n-\t\t\t\t\t\ttunnel_valid == 0)\n-\t\t\t\t\tlist[t].type = ICE_UDP_OF;\n-\t\t\t\telse\n-\t\t\t\t\tlist[t].type = ICE_UDP_ILOS;\n-\t\t\t\tif (udp_mask->hdr.src_port == UINT16_MAX) {\n-\t\t\t\t\tlist[t].h_u.l4_hdr.src_port =\n-\t\t\t\t\t\tudp_spec->hdr.src_port;\n-\t\t\t\t\tlist[t].m_u.l4_hdr.src_port =\n-\t\t\t\t\t\tudp_mask->hdr.src_port;\n-\t\t\t\t}\n-\t\t\t\tif (udp_mask->hdr.dst_port == UINT16_MAX) {\n-\t\t\t\t\tlist[t].h_u.l4_hdr.dst_port =\n-\t\t\t\t\t\tudp_spec->hdr.dst_port;\n-\t\t\t\t\tlist[t].m_u.l4_hdr.dst_port =\n-\t\t\t\t\t\tudp_mask->hdr.dst_port;\n-\t\t\t\t}\n-\t\t\t\tt++;\n-\t\t\t} else if (!udp_spec && !udp_mask) {\n-\t\t\t\tlist[t].type = ICE_UDP_ILOS;\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ITEM_TYPE_TCP:\n-\t\t\ttcp_spec = item->spec;\n-\t\t\ttcp_mask = item->mask;\n-\t\t\tif (tcp_spec && tcp_mask) {\n-\t\t\t\tlist[t].type = ICE_TCP_IL;\n-\t\t\t\tif (tcp_mask->hdr.src_port == UINT16_MAX) {\n-\t\t\t\t\tlist[t].h_u.l4_hdr.src_port =\n-\t\t\t\t\t\ttcp_spec->hdr.src_port;\n-\t\t\t\t\tlist[t].m_u.l4_hdr.src_port =\n-\t\t\t\t\t\ttcp_mask->hdr.src_port;\n-\t\t\t\t}\n-\t\t\t\tif (tcp_mask->hdr.dst_port == UINT16_MAX) {\n-\t\t\t\t\tlist[t].h_u.l4_hdr.dst_port =\n-\t\t\t\t\t\ttcp_spec->hdr.dst_port;\n-\t\t\t\t\tlist[t].m_u.l4_hdr.dst_port =\n-\t\t\t\t\t\ttcp_mask->hdr.dst_port;\n-\t\t\t\t}\n-\t\t\t\tt++;\n-\t\t\t} else if (!tcp_spec && !tcp_mask) {\n-\t\t\t\tlist[t].type = ICE_TCP_IL;\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ITEM_TYPE_SCTP:\n-\t\t\tsctp_spec = item->spec;\n-\t\t\tsctp_mask = item->mask;\n-\t\t\tif (sctp_spec && sctp_mask) {\n-\t\t\t\tlist[t].type = ICE_SCTP_IL;\n-\t\t\t\tif (sctp_mask->hdr.src_port == UINT16_MAX) {\n-\t\t\t\t\tlist[t].h_u.sctp_hdr.src_port =\n-\t\t\t\t\t\tsctp_spec->hdr.src_port;\n-\t\t\t\t\tlist[t].m_u.sctp_hdr.src_port =\n-\t\t\t\t\t\tsctp_mask->hdr.src_port;\n-\t\t\t\t}\n-\t\t\t\tif (sctp_mask->hdr.dst_port == UINT16_MAX) {\n-\t\t\t\t\tlist[t].h_u.sctp_hdr.dst_port =\n-\t\t\t\t\t\tsctp_spec->hdr.dst_port;\n-\t\t\t\t\tlist[t].m_u.sctp_hdr.dst_port =\n-\t\t\t\t\t\tsctp_mask->hdr.dst_port;\n-\t\t\t\t}\n-\t\t\t\tt++;\n-\t\t\t} else if (!sctp_spec && !sctp_mask) {\n-\t\t\t\tlist[t].type = ICE_SCTP_IL;\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n-\t\t\tvxlan_spec = item->spec;\n-\t\t\tvxlan_mask = item->mask;\n-\t\t\ttunnel_valid = 1;\n-\t\t\tif (vxlan_spec && vxlan_mask) {\n-\t\t\t\tlist[t].type = ICE_VXLAN;\n-\t\t\t\tif (vxlan_mask->vni[0] == UINT8_MAX &&\n-\t\t\t\t\tvxlan_mask->vni[1] == UINT8_MAX &&\n-\t\t\t\t\tvxlan_mask->vni[2] == UINT8_MAX) {\n-\t\t\t\t\tlist[t].h_u.tnl_hdr.vni =\n-\t\t\t\t\t\t(vxlan_spec->vni[2] << 16) |\n-\t\t\t\t\t\t(vxlan_spec->vni[1] << 8) |\n-\t\t\t\t\t\tvxlan_spec->vni[0];\n-\t\t\t\t\tlist[t].m_u.tnl_hdr.vni =\n-\t\t\t\t\t\tUINT32_MAX;\n-\t\t\t\t}\n-\t\t\t\tt++;\n-\t\t\t} else if (!vxlan_spec && !vxlan_mask) {\n-\t\t\t\tlist[t].type = ICE_VXLAN;\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ITEM_TYPE_NVGRE:\n-\t\t\tnvgre_spec = item->spec;\n-\t\t\tnvgre_mask = item->mask;\n-\t\t\ttunnel_valid = 1;\n-\t\t\tif (nvgre_spec && nvgre_mask) {\n-\t\t\t\tlist[t].type = ICE_NVGRE;\n-\t\t\t\tif (nvgre_mask->tni[0] == UINT8_MAX &&\n-\t\t\t\t\tnvgre_mask->tni[1] == UINT8_MAX &&\n-\t\t\t\t\tnvgre_mask->tni[2] == UINT8_MAX) {\n-\t\t\t\t\tlist[t].h_u.nvgre_hdr.tni_flow =\n-\t\t\t\t\t\t(nvgre_spec->tni[2] << 16) |\n-\t\t\t\t\t\t(nvgre_spec->tni[1] << 8) |\n-\t\t\t\t\t\tnvgre_spec->tni[0];\n-\t\t\t\t\tlist[t].m_u.nvgre_hdr.tni_flow =\n-\t\t\t\t\t\tUINT32_MAX;\n-\t\t\t\t}\n-\t\t\t\tt++;\n-\t\t\t} else if (!nvgre_spec && !nvgre_mask) {\n-\t\t\t\tlist[t].type = ICE_NVGRE;\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ITEM_TYPE_VOID:\n-\t\tcase RTE_FLOW_ITEM_TYPE_END:\n-\t\t\tbreak;\n-\n-\t\tdefault:\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM, actions,\n-\t\t\t\t   \"Invalid pattern item.\");\n-\t\t\tgoto out;\n-\t\t}\n-\t}\n-\n-\t*lkups_num = t;\n-\n-\treturn 0;\n-out:\n-\treturn -rte_errno;\n-}\n-\n-/* By now ice switch filter action code implement only\n- * supports QUEUE or DROP.\n- */\n-static int\n-ice_parse_switch_action(struct ice_pf *pf,\n-\t\t\t\t const struct rte_flow_action *actions,\n-\t\t\t\t struct rte_flow_error *error,\n-\t\t\t\t struct ice_adv_rule_info *rule_info)\n-{\n-\tstruct ice_vsi *vsi = pf->main_vsi;\n-\tconst struct rte_flow_action_queue *act_q;\n-\tuint16_t base_queue;\n-\tconst struct rte_flow_action *action;\n-\tenum rte_flow_action_type action_type;\n-\n-\tbase_queue = pf->base_queue;\n-\tfor (action = actions; action->type !=\n-\t\t\tRTE_FLOW_ACTION_TYPE_END; action++) {\n-\t\taction_type = action->type;\n-\t\tswitch (action_type) {\n-\t\tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n-\t\t\tact_q = action->conf;\n-\t\t\trule_info->sw_act.fltr_act =\n-\t\t\t\tICE_FWD_TO_Q;\n-\t\t\trule_info->sw_act.fwd_id.q_id =\n-\t\t\t\tbase_queue + act_q->index;\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_DROP:\n-\t\t\trule_info->sw_act.fltr_act =\n-\t\t\t\tICE_DROP_PACKET;\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n-\t\t\tbreak;\n-\n-\t\tdefault:\n-\t\t\trte_flow_error_set(error,\n-\t\t\t\tEINVAL,\n-\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\tactions,\n-\t\t\t\t\"Invalid action type\");\n-\t\t\treturn -rte_errno;\n-\t\t}\n-\t}\n-\n-\trule_info->sw_act.vsi_handle = vsi->idx;\n-\trule_info->rx = 1;\n-\trule_info->sw_act.src = vsi->idx;\n-\trule_info->priority = 5;\n-\n-\treturn 0;\n-}\n-\n-static int\n-ice_switch_rule_set(struct ice_pf *pf,\n-\t\t\tstruct ice_adv_lkup_elem *list,\n-\t\t\tuint16_t lkups_cnt,\n-\t\t\tstruct ice_adv_rule_info *rule_info,\n-\t\t\tstruct rte_flow *flow,\n-\t\t\tstruct rte_flow_error *error)\n-{\n-\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n-\tint ret;\n-\tstruct ice_rule_query_data rule_added = {0};\n-\tstruct ice_rule_query_data *filter_ptr;\n-\n-\tif (lkups_cnt > ICE_MAX_CHAIN_WORDS) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\tRTE_FLOW_ERROR_TYPE_ITEM, NULL,\n-\t\t\t\"item number too large for rule\");\n-\t\treturn -rte_errno;\n-\t}\n-\tif (!list) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\tRTE_FLOW_ERROR_TYPE_ITEM, NULL,\n-\t\t\t\"lookup list should not be NULL\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\tret = ice_add_adv_rule(hw, list, lkups_cnt, rule_info, &rule_added);\n-\n-\tif (!ret) {\n-\t\tfilter_ptr = rte_zmalloc(\"ice_switch_filter\",\n-\t\t\tsizeof(struct ice_rule_query_data), 0);\n-\t\tif (!filter_ptr) {\n-\t\t\tPMD_DRV_LOG(ERR, \"failed to allocate memory\");\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tflow->rule = filter_ptr;\n-\t\trte_memcpy(filter_ptr,\n-\t\t\t&rule_added,\n-\t\t\tsizeof(struct ice_rule_query_data));\n-\t}\n-\n-\treturn ret;\n-}\n-\n-int\n-ice_create_switch_filter(struct ice_pf *pf,\n-\t\t\tconst struct rte_flow_item pattern[],\n-\t\t\tconst struct rte_flow_action actions[],\n-\t\t\tstruct rte_flow *flow,\n-\t\t\tstruct rte_flow_error *error)\n-{\n-\tint ret = 0;\n-\tstruct ice_adv_rule_info rule_info = {0};\n-\tstruct ice_adv_lkup_elem *list = NULL;\n-\tuint16_t lkups_num = 0;\n-\tconst struct rte_flow_item *item = pattern;\n-\tuint16_t item_num = 0;\n-\tenum ice_sw_tunnel_type tun_type = ICE_NON_TUN;\n-\n-\tfor (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {\n-\t\titem_num++;\n-\t\tif (item->type == RTE_FLOW_ITEM_TYPE_VXLAN)\n-\t\t\ttun_type = ICE_SW_TUN_VXLAN;\n-\t\tif (item->type == RTE_FLOW_ITEM_TYPE_NVGRE)\n-\t\t\ttun_type = ICE_SW_TUN_NVGRE;\n-\t\t/* reserve one more memory slot for ETH which may\n-\t\t * consume 2 lookup items.\n-\t\t */\n-\t\tif (item->type == RTE_FLOW_ITEM_TYPE_ETH)\n-\t\t\titem_num++;\n-\t}\n-\trule_info.tun_type = tun_type;\n-\n-\tlist = rte_zmalloc(NULL, item_num * sizeof(*list), 0);\n-\tif (!list) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n-\t\t\t\t   \"No memory for PMD internal items\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\tret = ice_parse_switch_filter(pattern, actions, error,\n-\t\t\tlist, &lkups_num, tun_type);\n-\tif (ret)\n-\t\tgoto error;\n-\n-\tret = ice_parse_switch_action(pf, actions, error, &rule_info);\n-\tif (ret)\n-\t\tgoto error;\n-\n-\tret = ice_switch_rule_set(pf, list, lkups_num, &rule_info, flow, error);\n-\tif (ret)\n-\t\tgoto error;\n-\n-\trte_free(list);\n-\treturn 0;\n-\n-error:\n-\trte_free(list);\n-\n-\treturn -rte_errno;\n-}\n-\n-int\n-ice_destroy_switch_filter(struct ice_pf *pf,\n-\t\t\tstruct rte_flow *flow,\n-\t\t\tstruct rte_flow_error *error)\n-{\n-\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n-\tint ret;\n-\tstruct ice_rule_query_data *filter_ptr;\n-\n-\tfilter_ptr = (struct ice_rule_query_data *)\n-\t\t\tflow->rule;\n-\n-\tif (!filter_ptr) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\tRTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n-\t\t\t\"no such flow\"\n-\t\t\t\" create by switch filter\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\tret = ice_rem_adv_rule_by_id(hw, filter_ptr);\n-\tif (ret) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\tRTE_FLOW_ERROR_TYPE_HANDLE, NULL,\n-\t\t\t\"fail to destroy switch filter rule\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\trte_free(filter_ptr);\n-\treturn ret;\n-}\n-\n-void\n-ice_free_switch_filter_rule(void *rule)\n-{\n-\tstruct ice_rule_query_data *filter_ptr;\n-\n-\tfilter_ptr = (struct ice_rule_query_data *)rule;\n-\n-\trte_free(filter_ptr);\n-}\ndiff --git a/drivers/net/ice/ice_switch_filter.h b/drivers/net/ice/ice_switch_filter.h\nindex cea47990e..5afcddeaf 100644\n--- a/drivers/net/ice/ice_switch_filter.h\n+++ b/drivers/net/ice/ice_switch_filter.h\n@@ -2,23 +2,5 @@\n  * Copyright(c) 2019 Intel Corporation\n  */\n \n-#ifndef _ICE_SWITCH_FILTER_H_\n-#define _ICE_SWITCH_FILTER_H_\n \n-#include \"base/ice_switch.h\"\n-#include \"base/ice_type.h\"\n-#include \"ice_ethdev.h\"\n \n-int\n-ice_create_switch_filter(struct ice_pf *pf,\n-\t\t\tconst struct rte_flow_item pattern[],\n-\t\t\tconst struct rte_flow_action actions[],\n-\t\t\tstruct rte_flow *flow,\n-\t\t\tstruct rte_flow_error *error);\n-int\n-ice_destroy_switch_filter(struct ice_pf *pf,\n-\t\t\tstruct rte_flow *flow,\n-\t\t\tstruct rte_flow_error *error);\n-void\n-ice_free_switch_filter_rule(void *rule);\n-#endif /* _ICE_SWITCH_FILTER_H_ */\n",
    "prefixes": [
        "2/4"
    ]
}