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GET /api/patches/58198/?format=api
{ "id": 58198, "url": "https://patches.dpdk.org/api/patches/58198/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190829023421.112551-6-leyi.rong@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190829023421.112551-6-leyi.rong@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190829023421.112551-6-leyi.rong@intel.com", "date": "2019-08-29T02:34:20", "name": "[5/6] net/ice: switch to flexible descriptor in SSE path", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d41f04e23d51a76c93c0b024c9682e09df1631ba", "submitter": { "id": 1204, "url": "https://patches.dpdk.org/api/people/1204/?format=api", "name": "Leyi Rong", "email": "leyi.rong@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190829023421.112551-6-leyi.rong@intel.com/mbox/", "series": [ { "id": 6159, "url": "https://patches.dpdk.org/api/series/6159/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6159", "date": "2019-08-29T02:34:17", "name": "enable Rx flexible descriptor", "version": 1, "mbox": "https://patches.dpdk.org/series/6159/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/58198/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/58198/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A05051E8B8;\n\tThu, 29 Aug 2019 04:36:57 +0200 (CEST)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby dpdk.org (Postfix) with ESMTP id 801341E53B\n\tfor <dev@dpdk.org>; Thu, 29 Aug 2019 04:36:03 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n\tby orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 Aug 2019 19:36:03 -0700", "from dpdk-lrong-srv-04.sh.intel.com ([10.67.119.187])\n\tby fmsmga007.fm.intel.com with ESMTP; 28 Aug 2019 19:36:00 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,442,1559545200\"; d=\"scan'208\";a=\"182205443\"", "From": "Leyi Rong <leyi.rong@intel.com>", "To": "qi.z.zhang@intel.com, xiaolong.ye@intel.com, haiyue.wang@intel.com,\n\twenzhuo.lu@intel.com", "Cc": "dev@dpdk.org", "Date": "Thu, 29 Aug 2019 10:34:20 +0800", "Message-Id": "<20190829023421.112551-6-leyi.rong@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190829023421.112551-1-leyi.rong@intel.com>", "References": "<20190829023421.112551-1-leyi.rong@intel.com>", "Subject": "[dpdk-dev] [PATCH 5/6] net/ice: switch to flexible descriptor in\n\tSSE path", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Wenzhuo Lu <wenzhuo.lu@intel.com>\n\nWith this path, the flexible descriptor is supported\nin SSE path. And the legacy descriptor is not supported.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/ice/ice_rxtx_vec_sse.c | 243 ++++++++++++++---------------\n 1 file changed, 115 insertions(+), 128 deletions(-)", "diff": "diff --git a/drivers/net/ice/ice_rxtx_vec_sse.c b/drivers/net/ice/ice_rxtx_vec_sse.c\nindex 967a7b16b..aea00ecd0 100644\n--- a/drivers/net/ice/ice_rxtx_vec_sse.c\n+++ b/drivers/net/ice/ice_rxtx_vec_sse.c\n@@ -15,14 +15,14 @@ ice_rxq_rearm(struct ice_rx_queue *rxq)\n {\n \tint i;\n \tuint16_t rx_id;\n-\tvolatile union ice_rx_desc *rxdp;\n+\tvolatile union ice_rx_flex_desc *rxdp;\n \tstruct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];\n \tstruct rte_mbuf *mb0, *mb1;\n \t__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,\n \t\t\t\t\t RTE_PKTMBUF_HEADROOM);\n \t__m128i dma_addr0, dma_addr1;\n \n-\trxdp = rxq->rx_ring + rxq->rxrearm_start;\n+\trxdp = (union ice_rx_flex_desc *)rxq->rx_ring + rxq->rxrearm_start;\n \n \t/* Pull 'n' more MBUFs into the software ring */\n \tif (rte_mempool_get_bulk(rxq->mp,\n@@ -88,93 +88,96 @@ ice_rx_desc_to_olflags_v(struct ice_rx_queue *rxq, __m128i descs[4],\n \tconst __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);\n \t__m128i rearm0, rearm1, rearm2, rearm3;\n \n-\t__m128i vlan0, vlan1, rss, l3_l4e;\n+\t__m128i tmp_desc, flags, rss, vlan;\n \n-\t/* mask everything except RSS, flow director and VLAN flags\n-\t * bit2 is for VLAN tag, bit11 for flow director indication\n-\t * bit13:12 for RSS indication.\n+\t/* mask everything except checksum, RSS and VLAN flags.\n+\t * bit6:4 for checksum.\n+\t * bit12 for RSS indication.\n+\t * bit13 for VLAN indication.\n \t */\n-\tconst __m128i rss_vlan_msk = _mm_set_epi32(0x1c03804, 0x1c03804,\n-\t\t\t\t\t\t 0x1c03804, 0x1c03804);\n+\tconst __m128i desc_mask = _mm_set_epi32(0x3070, 0x3070,\n+\t\t\t\t\t\t0x3070, 0x3070);\n \n-\tconst __m128i cksum_mask = _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD |\n-\t\t\t\t\t\t PKT_RX_IP_CKSUM_BAD |\n-\t\t\t\t\t\t PKT_RX_L4_CKSUM_GOOD |\n-\t\t\t\t\t\t PKT_RX_L4_CKSUM_BAD |\n+\tconst __m128i cksum_mask = _mm_set_epi32(PKT_RX_IP_CKSUM_MASK |\n+\t\t\t\t\t\t PKT_RX_L4_CKSUM_MASK |\n \t\t\t\t\t\t PKT_RX_EIP_CKSUM_BAD,\n-\t\t\t\t\t\t PKT_RX_IP_CKSUM_GOOD |\n-\t\t\t\t\t\t PKT_RX_IP_CKSUM_BAD |\n-\t\t\t\t\t\t PKT_RX_L4_CKSUM_GOOD |\n-\t\t\t\t\t\t PKT_RX_L4_CKSUM_BAD |\n+\t\t\t\t\t\t PKT_RX_IP_CKSUM_MASK |\n+\t\t\t\t\t\t PKT_RX_L4_CKSUM_MASK |\n \t\t\t\t\t\t PKT_RX_EIP_CKSUM_BAD,\n-\t\t\t\t\t\t PKT_RX_IP_CKSUM_GOOD |\n-\t\t\t\t\t\t PKT_RX_IP_CKSUM_BAD |\n-\t\t\t\t\t\t PKT_RX_L4_CKSUM_GOOD |\n-\t\t\t\t\t\t PKT_RX_L4_CKSUM_BAD |\n+\t\t\t\t\t\t PKT_RX_IP_CKSUM_MASK |\n+\t\t\t\t\t\t PKT_RX_L4_CKSUM_MASK |\n \t\t\t\t\t\t PKT_RX_EIP_CKSUM_BAD,\n-\t\t\t\t\t\t PKT_RX_IP_CKSUM_GOOD |\n-\t\t\t\t\t\t PKT_RX_IP_CKSUM_BAD |\n-\t\t\t\t\t\t PKT_RX_L4_CKSUM_GOOD |\n-\t\t\t\t\t\t PKT_RX_L4_CKSUM_BAD |\n+\t\t\t\t\t\t PKT_RX_IP_CKSUM_MASK |\n+\t\t\t\t\t\t PKT_RX_L4_CKSUM_MASK |\n \t\t\t\t\t\t PKT_RX_EIP_CKSUM_BAD);\n \n-\t/* map rss and vlan type to rss hash and vlan flag */\n-\tconst __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,\n-\t\t\t0, 0, 0, 0,\n-\t\t\t0, 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,\n-\t\t\t0, 0, 0, 0);\n-\n-\tconst __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,\n-\t\t\t0, 0, 0, 0,\n-\t\t\tPKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,\n-\t\t\t0, 0, PKT_RX_FDIR, 0);\n-\n-\tconst __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,\n+\t/* map the checksum, rss and vlan fields to the checksum, rss\n+\t * and vlan flag\n+\t */\n+\tconst __m128i cksum_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,\n \t\t\t/* shift right 1 bit to make sure it not exceed 255 */\n \t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n \t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n-\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |\n-\t\t\t PKT_RX_L4_CKSUM_BAD) >> 1,\n-\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,\n-\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |\n+\t\t\t PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |\n+\t\t\t PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |\n+\t\t\t PKT_RX_IP_CKSUM_GOOD) >> 1,\n \t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,\n-\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,\n-\t\t\tPKT_RX_IP_CKSUM_BAD >> 1,\n-\t\t\t(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);\n-\n-\tvlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);\n-\tvlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);\n-\tvlan0 = _mm_unpacklo_epi64(vlan0, vlan1);\n-\n-\tvlan1 = _mm_and_si128(vlan0, rss_vlan_msk);\n-\tvlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);\n+\t\t\t(PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,\n+\t\t\t(PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);\n \n-\trss = _mm_srli_epi32(vlan1, 11);\n-\trss = _mm_shuffle_epi8(rss_flags, rss);\n+\tconst __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\tPKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0);\n \n-\tl3_l4e = _mm_srli_epi32(vlan1, 22);\n-\tl3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);\n+\tconst __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\t0, 0, 0, 0,\n+\t\t\tPKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,\n+\t\t\tPKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0, 0);\n+\n+\t/* merge 4 descriptors */\n+\tflags = _mm_unpackhi_epi32(descs[0], descs[1]);\n+\ttmp_desc = _mm_unpackhi_epi32(descs[2], descs[3]);\n+\ttmp_desc = _mm_unpacklo_epi64(flags, tmp_desc);\n+\ttmp_desc = _mm_and_si128(flags, desc_mask);\n+\n+\t/* checksum flags */\n+\ttmp_desc = _mm_srli_epi32(tmp_desc, 4);\n+\tflags = _mm_shuffle_epi8(cksum_flags, tmp_desc);\n \t/* then we shift left 1 bit */\n-\tl3_l4e = _mm_slli_epi32(l3_l4e, 1);\n-\t/* we need to mask out the reduntant bits */\n-\tl3_l4e = _mm_and_si128(l3_l4e, cksum_mask);\n+\tflags = _mm_slli_epi32(flags, 1);\n+\t/* we need to mask out the reduntant bits introduced by RSS or\n+\t * VLAN fields.\n+\t */\n+\tflags = _mm_and_si128(flags, cksum_mask);\n+\n+\t/* RSS, VLAN flag */\n+\ttmp_desc = _mm_srli_epi32(tmp_desc, 8);\n+\trss = _mm_shuffle_epi8(rss_flags, tmp_desc);\n+\tvlan = _mm_shuffle_epi8(vlan_flags, tmp_desc);\n \n-\tvlan0 = _mm_or_si128(vlan0, rss);\n-\tvlan0 = _mm_or_si128(vlan0, l3_l4e);\n+\t/* merge the flags */\n+\tflags = _mm_or_si128(flags, rss);\n+\tflags = _mm_or_si128(flags, vlan);\n \n \t/**\n \t * At this point, we have the 4 sets of flags in the low 16-bits\n-\t * of each 32-bit value in vlan0.\n+\t * of each 32-bit value in flags.\n \t * We want to extract these, and merge them with the mbuf init data\n \t * so we can do a single 16-byte write to the mbuf to set the flags\n \t * and all the other initialization fields. Extracting the\n \t * appropriate flags means that we have to do a shift and blend for\n \t * each mbuf before we do the write.\n \t */\n-\trearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10);\n-\trearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10);\n-\trearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10);\n-\trearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);\n+\trearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 8), 0x10);\n+\trearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 4), 0x10);\n+\trearm2 = _mm_blend_epi16(mbuf_init, flags, 0x10);\n+\trearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(flags, 4), 0x10);\n \n \t/* write the rearm data and the olflags in one write */\n \tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n@@ -187,22 +190,24 @@ ice_rx_desc_to_olflags_v(struct ice_rx_queue *rxq, __m128i descs[4],\n \t_mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);\n }\n \n-#define PKTLEN_SHIFT 10\n-\n static inline void\n ice_rx_desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,\n \t\t uint32_t *ptype_tbl)\n {\n-\t__m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);\n-\t__m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);\n-\n-\tptype0 = _mm_srli_epi64(ptype0, 30);\n-\tptype1 = _mm_srli_epi64(ptype1, 30);\n-\n-\trx_pkts[0]->packet_type = ptype_tbl[_mm_extract_epi8(ptype0, 0)];\n-\trx_pkts[1]->packet_type = ptype_tbl[_mm_extract_epi8(ptype0, 8)];\n-\trx_pkts[2]->packet_type = ptype_tbl[_mm_extract_epi8(ptype1, 0)];\n-\trx_pkts[3]->packet_type = ptype_tbl[_mm_extract_epi8(ptype1, 8)];\n+\tconst __m128i ptype_mask = _mm_set_epi16(0, ICE_RX_FLEX_DESC_PTYPE_M,\n+\t\t\t\t\t\t 0, ICE_RX_FLEX_DESC_PTYPE_M,\n+\t\t\t\t\t\t 0, ICE_RX_FLEX_DESC_PTYPE_M,\n+\t\t\t\t\t\t 0, ICE_RX_FLEX_DESC_PTYPE_M);\n+\t__m128i ptype_01 = _mm_unpacklo_epi32(descs[0], descs[1]);\n+\t__m128i ptype_23 = _mm_unpacklo_epi32(descs[2], descs[3]);\n+\t__m128i ptype_all = _mm_unpacklo_epi64(ptype_01, ptype_23);\n+\n+\tptype_all = _mm_and_si128(ptype_all, ptype_mask);\n+\n+\trx_pkts[0]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 1)];\n+\trx_pkts[1]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 3)];\n+\trx_pkts[2]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 5)];\n+\trx_pkts[3]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 7)];\n }\n \n /**\n@@ -215,21 +220,39 @@ static inline uint16_t\n _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t uint16_t nb_pkts, uint8_t *split_packet)\n {\n-\tvolatile union ice_rx_desc *rxdp;\n+\tvolatile union ice_rx_flex_desc *rxdp;\n \tstruct ice_rx_entry *sw_ring;\n \tuint16_t nb_pkts_recd;\n \tint pos;\n \tuint64_t var;\n-\t__m128i shuf_msk;\n \tuint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;\n-\n \t__m128i crc_adjust = _mm_set_epi16\n-\t\t\t\t(0, 0, 0, /* ignore non-length fields */\n+\t\t\t\t(0, 0, 0, /* ignore non-length fields */\n \t\t\t\t -rxq->crc_len, /* sub crc on data_len */\n \t\t\t\t 0, /* ignore high-16bits of pkt_len */\n \t\t\t\t -rxq->crc_len, /* sub crc on pkt_len */\n-\t\t\t\t 0, 0 /* ignore pkt_type field */\n+\t\t\t\t 0, 0 /* ignore pkt_type field */\n \t\t\t\t);\n+\tconst __m128i zero = _mm_setzero_si128();\n+\t/* mask to shuffle from desc. to mbuf */\n+\tconst __m128i shuf_msk = _mm_set_epi8\n+\t\t\t(0xFF, 0xFF, 0xFF, 0xFF, /* rss not supported */\n+\t\t\t 11, 10, /* octet 10~11, 16 bits vlan_macip */\n+\t\t\t 5, 4, /* octet 4~5, 16 bits data_len */\n+\t\t\t 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n+\t\t\t 5, 4, /* octet 4~5, low 16 bits pkt_len */\n+\t\t\t 0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t 0xFF, 0xFF /* pkt_type set as unknown */\n+\t\t\t);\n+\tconst __m128i eop_shuf_mask = _mm_set_epi8(0xFF, 0xFF,\n+\t\t\t\t\t\t 0xFF, 0xFF,\n+\t\t\t\t\t\t 0xFF, 0xFF,\n+\t\t\t\t\t\t 0xFF, 0xFF,\n+\t\t\t\t\t\t 0xFF, 0xFF,\n+\t\t\t\t\t\t 0xFF, 0xFF,\n+\t\t\t\t\t\t 0x04, 0x0C,\n+\t\t\t\t\t\t 0x00, 0x08);\n+\n \t/**\n \t * compile-time check the above crc_adjust layout is correct.\n \t * NOTE: the first field (lowest address) is given last in set_epi16\n@@ -239,7 +262,13 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t\t offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n \tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n \t\t\t offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n-\t__m128i dd_check, eop_check;\n+\n+\t/* 4 packets DD mask */\n+\tconst __m128i dd_check = _mm_set_epi64x(0x0000000100000001LL,\n+\t\t\t\t\t\t0x0000000100000001LL);\n+\t/* 4 packets EOP mask */\n+\tconst __m128i eop_check = _mm_set_epi64x(0x0000000200000002LL,\n+\t\t\t\t\t\t 0x0000000200000002LL);\n \n \t/* nb_pkts shall be less equal than ICE_MAX_RX_BURST */\n \tnb_pkts = RTE_MIN(nb_pkts, ICE_MAX_RX_BURST);\n@@ -250,7 +279,7 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t/* Just the act of getting into the function from the application is\n \t * going to cost about 7 cycles\n \t */\n-\trxdp = rxq->rx_ring + rxq->rx_tail;\n+\trxdp = (union ice_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;\n \n \trte_prefetch0(rxdp);\n \n@@ -263,26 +292,10 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t/* Before we start moving massive data around, check to see if\n \t * there is actually a packet available\n \t */\n-\tif (!(rxdp->wb.qword1.status_error_len &\n-\t rte_cpu_to_le_32(1 << ICE_RX_DESC_STATUS_DD_S)))\n+\tif (!(rxdp->wb.status_error0 &\n+\t rte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))\n \t\treturn 0;\n \n-\t/* 4 packets DD mask */\n-\tdd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);\n-\n-\t/* 4 packets EOP mask */\n-\teop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);\n-\n-\t/* mask to shuffle from desc. to mbuf */\n-\tshuf_msk = _mm_set_epi8\n-\t\t\t(7, 6, 5, 4, /* octet 4~7, 32bits rss */\n-\t\t\t 3, 2, /* octet 2~3, low 16 bits vlan_macip */\n-\t\t\t 15, 14, /* octet 15~14, 16 bits data_len */\n-\t\t\t 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n-\t\t\t 15, 14, /* octet 15~14, low 16 bits pkt_len */\n-\t\t\t 0xFF, 0xFF, /* pkt_type set as unknown */\n-\t\t\t 0xFF, 0xFF /*pkt_type set as unknown */\n-\t\t\t);\n \t/**\n \t * Compile-time verify the shuffle mask\n \t * NOTE: some field positions already verified above, but duplicated\n@@ -315,7 +328,7 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t rxdp += ICE_DESCS_PER_LOOP) {\n \t\t__m128i descs[ICE_DESCS_PER_LOOP];\n \t\t__m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;\n-\t\t__m128i zero, staterr, sterr_tmp1, sterr_tmp2;\n+\t\t__m128i staterr, sterr_tmp1, sterr_tmp2;\n \t\t/* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */\n \t\t__m128i mbp1;\n #if defined(RTE_ARCH_X86_64)\n@@ -359,14 +372,6 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t/* avoid compiler reorder optimization */\n \t\trte_compiler_barrier();\n \n-\t\t/* pkt 3,4 shift the pktlen field to be 16-bit aligned*/\n-\t\tconst __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);\n-\t\tconst __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);\n-\n-\t\t/* merge the now-aligned packet length fields back in */\n-\t\tdescs[3] = _mm_blend_epi16(descs[3], len3, 0x80);\n-\t\tdescs[2] = _mm_blend_epi16(descs[2], len2, 0x80);\n-\n \t\t/* D.1 pkt 3,4 convert format from desc to pktmbuf */\n \t\tpkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);\n \t\tpkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);\n@@ -382,20 +387,11 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\tpkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);\n \t\tpkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);\n \n-\t\t/* pkt 1,2 shift the pktlen field to be 16-bit aligned*/\n-\t\tconst __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);\n-\t\tconst __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);\n-\n-\t\t/* merge the now-aligned packet length fields back in */\n-\t\tdescs[1] = _mm_blend_epi16(descs[1], len1, 0x80);\n-\t\tdescs[0] = _mm_blend_epi16(descs[0], len0, 0x80);\n-\n \t\t/* D.1 pkt 1,2 convert format from desc to pktmbuf */\n \t\tpkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);\n \t\tpkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);\n \n \t\t/* C.2 get 4 pkts staterr value */\n-\t\tzero = _mm_xor_si128(dd_check, dd_check);\n \t\tstaterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);\n \n \t\t/* D.3 copy final 3,4 data to rx_pkts */\n@@ -412,15 +408,6 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \n \t\t/* C* extract and record EOP bit */\n \t\tif (split_packet) {\n-\t\t\t__m128i eop_shuf_mask = _mm_set_epi8(0xFF, 0xFF,\n-\t\t\t\t\t\t\t 0xFF, 0xFF,\n-\t\t\t\t\t\t\t 0xFF, 0xFF,\n-\t\t\t\t\t\t\t 0xFF, 0xFF,\n-\t\t\t\t\t\t\t 0xFF, 0xFF,\n-\t\t\t\t\t\t\t 0xFF, 0xFF,\n-\t\t\t\t\t\t\t 0x04, 0x0C,\n-\t\t\t\t\t\t\t 0x00, 0x08);\n-\n \t\t\t/* and with mask to extract bits, flipping 1-0 */\n \t\t\t__m128i eop_bits = _mm_andnot_si128(staterr, eop_check);\n \t\t\t/* the staterr values are not in order, as the count\n", "prefixes": [ "5/6" ] }