Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 57853,
    "url": "https://patches.dpdk.org/api/patches/57853/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1566568031-45991-15-git-send-email-xavier.huwei@huawei.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1566568031-45991-15-git-send-email-xavier.huwei@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1566568031-45991-15-git-send-email-xavier.huwei@huawei.com",
    "date": "2019-08-23T13:47:03",
    "name": "[14/22] net/hns3: add support for hns3 VF PMD driver",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "dd3a1d7d8d3e7a3042772b4c4ba7d675e2c13cc3",
    "submitter": {
        "id": 1405,
        "url": "https://patches.dpdk.org/api/people/1405/?format=api",
        "name": "Wei Hu (Xavier)",
        "email": "xavier.huwei@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1566568031-45991-15-git-send-email-xavier.huwei@huawei.com/mbox/",
    "series": [
        {
            "id": 6114,
            "url": "https://patches.dpdk.org/api/series/6114/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6114",
            "date": "2019-08-23T13:46:49",
            "name": "add hns3 ethernet PMD driver",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/6114/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/57853/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/57853/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 33E801C022;\n\tFri, 23 Aug 2019 15:50:03 +0200 (CEST)",
            "from huawei.com (szxga07-in.huawei.com [45.249.212.35])\n\tby dpdk.org (Postfix) with ESMTP id 265A91BFC9\n\tfor <dev@dpdk.org>; Fri, 23 Aug 2019 15:49:39 +0200 (CEST)",
            "from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59])\n\tby Forcepoint Email with ESMTP id D08553656F6DA939A931;\n\tFri, 23 Aug 2019 21:49:36 +0800 (CST)",
            "from localhost.localdomain (10.67.212.132) by\n\tDGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP\n\tServer id 14.3.439.0; Fri, 23 Aug 2019 21:49:29 +0800"
        ],
        "From": "\"Wei Hu (Xavier)\" <xavier.huwei@huawei.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<linuxarm@huawei.com>, <xavier_huwei@163.com>, <liudongdong3@huawei.com>,\n\t<forest.zhouchang@huawei.com>",
        "Date": "Fri, 23 Aug 2019 21:47:03 +0800",
        "Message-ID": "<1566568031-45991-15-git-send-email-xavier.huwei@huawei.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>",
        "References": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.67.212.132]",
        "X-CFilter-Loop": "Reflected",
        "Subject": "[dpdk-dev] [PATCH 14/22] net/hns3: add support for hns3 VF PMD\n\tdriver",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch adds support for hns3 VF PMD driver.\n\nIn current version, we only support VF device is bound to vfio_pci or\nigb_uio and then taken over by DPDK when PF device is taken over by kernel\nmode hns3 ethdev driver, VF is not supported when PF devcie is taken over\nby DPDK.\n\nSigned-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>\nSigned-off-by: Chunsong Feng <fengchunsong@huawei.com>\nSigned-off-by: Min Hu (Connor) <humin29@huawei.com>\nSigned-off-by: Hao Chen <chenhao164@huawei.com>\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\n---\n drivers/net/hns3/hns3_ethdev_vf.c | 1287 +++++++++++++++++++++++++++++++++++++\n 1 file changed, 1287 insertions(+)\n create mode 100644 drivers/net/hns3/hns3_ethdev_vf.c",
    "diff": "diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nnew file mode 100644\nindex 0000000..43b27ed\n--- /dev/null\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -0,0 +1,1287 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2019 Hisilicon Limited.\n+ */\n+\n+#include <arpa/inet.h>\n+#include <errno.h>\n+#include <stdio.h>\n+#include <stdbool.h>\n+#include <string.h>\n+#include <sys/queue.h>\n+#include <sys/time.h>\n+#include <inttypes.h>\n+#include <unistd.h>\n+#include <arpa/inet.h>\n+#include <rte_alarm.h>\n+#include <rte_atomic.h>\n+#include <rte_bus_pci.h>\n+#include <rte_byteorder.h>\n+#include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_debug.h>\n+#include <rte_dev.h>\n+#include <rte_eal.h>\n+#include <rte_ether.h>\n+#include <rte_ethdev_driver.h>\n+#include <rte_ethdev_pci.h>\n+#include <rte_interrupts.h>\n+#include <rte_io.h>\n+#include <rte_log.h>\n+#include <rte_pci.h>\n+\n+#include \"hns3_cmd.h\"\n+#include \"hns3_mbx.h\"\n+#include \"hns3_rss.h\"\n+#include \"hns3_fdir.h\"\n+#include \"hns3_ethdev.h\"\n+#include \"hns3_logs.h\"\n+#include \"hns3_regs.h\"\n+#include \"hns3_dcb.h\"\n+\n+#define HNS3VF_KEEP_ALIVE_INTERVAL\t2000000 /* us */\n+#define HNS3VF_SERVICE_INTERVAL\t\t1000000 /* us */\n+\n+#define HNS3VF_RESET_WAIT_MS\t20\n+#define HNS3VF_RESET_WAIT_CNT\t2000\n+\n+static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n+static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);\n+\n+static int\n+hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,\n+\t\t    __attribute__ ((unused)) uint32_t idx,\n+\t\t    __attribute__ ((unused)) uint32_t pool)\n+{\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tchar mac_str[RTE_ETHER_ADDR_FMT_SIZE];\n+\tint ret;\n+\n+\trte_spinlock_lock(&hw->lock);\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,\n+\t\t\t\tHNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,\n+\t\t\t\tRTE_ETHER_ADDR_LEN, false, NULL, 0);\n+\trte_spinlock_unlock(&hw->lock);\n+\tif (ret) {\n+\t\trte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,\n+\t\t\t\t      mac_addr);\n+\t\thns3_err(hw, \"Failed to add mac addr(%s) for vf: %d\", mac_str,\n+\t\t\t ret);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static void\n+hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)\n+{\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\t/* index will be checked by upper level rte interface */\n+\tstruct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];\n+\tchar mac_str[RTE_ETHER_ADDR_FMT_SIZE];\n+\tint ret;\n+\n+\trte_spinlock_lock(&hw->lock);\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,\n+\t\t\t\tHNS3_MBX_MAC_VLAN_UC_REMOVE,\n+\t\t\t\tmac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,\n+\t\t\t\tNULL, 0);\n+\trte_spinlock_unlock(&hw->lock);\n+\tif (ret) {\n+\t\trte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,\n+\t\t\t\t      mac_addr);\n+\t\thns3_err(hw, \"Failed to remove mac addr(%s) for vf: %d\",\n+\t\t\t mac_str, ret);\n+\t}\n+}\n+\n+static int\n+hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,\n+\t\t\t    struct rte_ether_addr *mac_addr)\n+{\n+#define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct rte_ether_addr *old_addr;\n+\tuint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */\n+\tchar mac_str[RTE_ETHER_ADDR_FMT_SIZE];\n+\tint ret;\n+\n+\tif (!rte_is_valid_assigned_ether_addr(mac_addr)) {\n+\t\trte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,\n+\t\t\t\t      mac_addr);\n+\t\thns3_err(hw, \"Failed to set mac addr, addr(%s) invalid.\",\n+\t\t\t mac_str);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\told_addr = (struct rte_ether_addr *)hw->mac.mac_addr;\n+\trte_spinlock_lock(&hw->lock);\n+\tmemcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);\n+\tmemcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,\n+\t       RTE_ETHER_ADDR_LEN);\n+\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,\n+\t\t\t\tHNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,\n+\t\t\t\tHNS3_TWO_ETHER_ADDR_LEN, false, NULL, 0);\n+\tif (ret) {\n+\t\trte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,\n+\t\t\t\t      mac_addr);\n+\t\thns3_err(hw, \"Failed to set mac addr(%s) for vf: %d\", mac_str,\n+\t\t\t ret);\n+\t}\n+\n+\trte_ether_addr_copy(mac_addr,\n+\t\t\t    (struct rte_ether_addr *)hw->mac.mac_addr);\n+\trte_spinlock_unlock(&hw->lock);\n+\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct rte_ether_addr *addr;\n+\tenum hns3_mbx_mac_vlan_subcode opcode;\n+\tchar mac_str[RTE_ETHER_ADDR_FMT_SIZE];\n+\tint ret = 0;\n+\tint i;\n+\n+\tif (del)\n+\t\topcode = HNS3_MBX_MAC_VLAN_UC_REMOVE;\n+\telse\n+\t\topcode = HNS3_MBX_MAC_VLAN_UC_ADD;\n+\tfor (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {\n+\t\taddr = &hw->data->mac_addrs[i];\n+\t\tif (!rte_is_valid_assigned_ether_addr(addr))\n+\t\t\tcontinue;\n+\t\trte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);\n+\t\thns3_dbg(hw, \"rm mac addr: %s\", mac_str);\n+\t\tret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, opcode,\n+\t\t\t\t\taddr->addr_bytes, RTE_ETHER_ADDR_LEN,\n+\t\t\t\t\tfalse, NULL, 0);\n+\t\tif (ret) {\n+\t\t\thns3_err(hw, \"Failed to remove mac addr for vf: %d\",\n+\t\t\t\t ret);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_add_mc_mac_addr(struct hns3_adapter *hns,\n+\t\t       struct rte_ether_addr *mac_addr)\n+{\n+\tchar mac_str[RTE_ETHER_ADDR_FMT_SIZE];\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,\n+\t\t\t\tHNS3_MBX_MAC_VLAN_MC_ADD,\n+\t\t\t\tmac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,\n+\t\t\t\tNULL, 0);\n+\tif (ret) {\n+\t\trte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,\n+\t\t\t\t      mac_addr);\n+\t\thns3_err(hw, \"Failed to add mc mac addr(%s) for vf: %d\",\n+\t\t\t mac_str, ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3vf_remove_mc_mac_addr(struct hns3_adapter *hns,\n+\t\t\t  struct rte_ether_addr *mac_addr)\n+{\n+\tchar mac_str[RTE_ETHER_ADDR_FMT_SIZE];\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,\n+\t\t\t\tHNS3_MBX_MAC_VLAN_MC_REMOVE,\n+\t\t\t\tmac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,\n+\t\t\t\tNULL, 0);\n+\tif (ret) {\n+\t\trte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,\n+\t\t\t\t      mac_addr);\n+\t\thns3_err(hw, \"Failed to remove mc mac addr(%s) for vf: %d\",\n+\t\t\t mac_str, ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,\n+\t\t\t    struct rte_ether_addr *mc_addr_set,\n+\t\t\t    uint32_t nb_mc_addr)\n+{\n+\tstruct hns3_adapter *hns = dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct rte_ether_addr *addr;\n+\tchar mac_str[RTE_ETHER_ADDR_FMT_SIZE];\n+\tint cur_addr_num;\n+\tint set_addr_num;\n+\tint num;\n+\tint ret;\n+\tint i;\n+\n+\tif (nb_mc_addr > HNS3_MC_MACADDR_NUM) {\n+\t\thns3_err(hw, \"Failed to set mc mac addr, nb_mc_addr(%d) \"\n+\t\t\t \"invalid. valid range: 0~%d\",\n+\t\t\t nb_mc_addr, HNS3_MC_MACADDR_NUM);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tset_addr_num = (int)nb_mc_addr;\n+\tfor (i = 0; i < set_addr_num; i++) {\n+\t\taddr = &mc_addr_set[i];\n+\t\tif (!rte_is_multicast_ether_addr(addr)) {\n+\t\t\trte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,\n+\t\t\t\t\t      addr);\n+\t\t\thns3_err(hw,\n+\t\t\t\t \"Failed to set mc mac addr, addr(%s) invalid.\",\n+\t\t\t\t mac_str);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\trte_spinlock_lock(&hw->lock);\n+\tcur_addr_num = hw->mc_addrs_num;\n+\tfor (i = 0; i < cur_addr_num; i++) {\n+\t\tnum = cur_addr_num - i - 1;\n+\t\taddr = &hw->mc_addrs[num];\n+\t\tret = hns3vf_remove_mc_mac_addr(hns, addr);\n+\t\tif (ret) {\n+\t\t\trte_spinlock_unlock(&hw->lock);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\thw->mc_addrs_num--;\n+\t}\n+\n+\tfor (i = 0; i < set_addr_num; i++) {\n+\t\taddr = &mc_addr_set[i];\n+\t\tret = hns3vf_add_mc_mac_addr(hns, addr);\n+\t\tif (ret) {\n+\t\t\trte_spinlock_unlock(&hw->lock);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\trte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);\n+\t\thw->mc_addrs_num++;\n+\t}\n+\trte_spinlock_unlock(&hw->lock);\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)\n+{\n+\tchar mac_str[RTE_ETHER_ADDR_FMT_SIZE];\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct rte_ether_addr *addr;\n+\tint err = 0;\n+\tint ret;\n+\tint i;\n+\n+\tfor (i = 0; i < hw->mc_addrs_num; i++) {\n+\t\taddr = &hw->mc_addrs[i];\n+\t\tif (!rte_is_multicast_ether_addr(addr))\n+\t\t\tcontinue;\n+\t\tif (del)\n+\t\t\tret = hns3vf_remove_mc_mac_addr(hns, addr);\n+\t\telse\n+\t\t\tret = hns3vf_add_mc_mac_addr(hns, addr);\n+\t\tif (ret) {\n+\t\t\terr = ret;\n+\t\t\trte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,\n+\t\t\t\t\t      addr);\n+\t\t\thns3_err(hw, \"Failed to %s mc mac addr: %s for vf: %d\",\n+\t\t\t\t del ? \"Remove\" : \"Restore\", mac_str, ret);\n+\t\t}\n+\t}\n+\treturn err;\n+}\n+\n+static int\n+hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc)\n+{\n+\tstruct hns3_mbx_vf_to_pf_cmd *req;\n+\tstruct hns3_cmd_desc desc;\n+\tint ret;\n+\n+\treq = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;\n+\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);\n+\treq->msg[0] = HNS3_MBX_SET_PROMISC_MODE;\n+\treq->msg[1] = en_bc_pmc ? 1 : 0;\n+\n+\tret = hns3_cmd_send(hw, &desc, 1);\n+\tif (ret)\n+\t\thns3_err(hw, \"Set promisc mode fail, status is %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_dev_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct hns3_rss_conf *rss_cfg = &hw->rss_info;\n+\tstruct rte_eth_conf *conf = &dev->data->dev_conf;\n+\tenum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;\n+\tuint16_t nb_rx_q = dev->data->nb_rx_queues;\n+\tuint16_t nb_tx_q = dev->data->nb_tx_queues;\n+\tstruct rte_eth_rss_conf rss_conf;\n+\tuint16_t mtu;\n+\tint ret;\n+\n+\t/*\n+\t * Hardware does not support where the number of rx and tx queues is\n+\t * not equal in hip08.\n+\t */\n+\tif (nb_rx_q != nb_tx_q) {\n+\t\thns3_err(hw,\n+\t\t\t \"nb_rx_queues(%u) not equal with nb_tx_queues(%u)! \"\n+\t\t\t \"Hardware does not support this configuration!\",\n+\t\t\t nb_rx_q, nb_tx_q);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (conf->link_speeds & ETH_LINK_SPEED_FIXED) {\n+\t\thns3_err(hw, \"setting link speed/duplex not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thw->adapter_state = HNS3_NIC_CONFIGURING;\n+\n+\t/* When RSS is not configured, redirect the packet queue 0 */\n+\tif ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {\n+\t\trss_conf = conf->rx_adv_conf.rss_conf;\n+\t\tif (rss_conf.rss_key == NULL) {\n+\t\t\trss_conf.rss_key = rss_cfg->key;\n+\t\t\trss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;\n+\t\t}\n+\n+\t\tret = hns3_dev_rss_hash_update(dev, &rss_conf);\n+\t\tif (ret)\n+\t\t\tgoto cfg_err;\n+\t}\n+\n+\t/*\n+\t * If jumbo frames are enabled, MTU needs to be refreshed\n+\t * according to the maximum RX packet length.\n+\t */\n+\tif (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {\n+\t\t/*\n+\t\t * Security of max_rx_pkt_len is guaranteed in dpdk frame.\n+\t\t * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it\n+\t\t * can safely assign to \"uint16_t\" type variable.\n+\t\t */\n+\t\tmtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);\n+\t\tret = hns3vf_dev_mtu_set(dev, mtu);\n+\t\tif (ret)\n+\t\t\tgoto cfg_err;\n+\t\tdev->data->mtu = mtu;\n+\t}\n+\n+\tret = hns3vf_dev_configure_vlan(dev);\n+\tif (ret)\n+\t\tgoto cfg_err;\n+\n+\thw->adapter_state = HNS3_NIC_CONFIGURED;\n+\treturn 0;\n+\n+cfg_err:\n+\thw->adapter_state = HNS3_NIC_INITIALIZED;\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)\n+{\n+\tint ret;\n+\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,\n+\t\t\t\tsizeof(mtu), true, NULL, 0);\n+\tif (ret)\n+\t\thns3_err(hw, \"Failed to set mtu (%u) for vf: %d\", mtu, ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n+{\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;\n+\tint ret;\n+\n+\tif (mtu < RTE_ETHER_MIN_MTU || frame_size > HNS3_MAX_FRAME_LEN) {\n+\t\thns3_err(hw, \"Failed to set mtu, mtu(%u) invalid. valid \"\n+\t\t\t \"range: %d~%d\", mtu, RTE_ETHER_MIN_MTU, HNS3_MAX_MTU);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (dev->data->dev_started) {\n+\t\thns3_err(hw, \"Failed to set mtu, port %u must be stopped \"\n+\t\t\t \"before configuration\", dev->data->port_id);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\trte_spinlock_lock(&hw->lock);\n+\tret = hns3vf_config_mtu(hw, mtu);\n+\tif (ret) {\n+\t\trte_spinlock_unlock(&hw->lock);\n+\t\treturn ret;\n+\t}\n+\tif (frame_size > RTE_ETHER_MAX_LEN)\n+\t\tdev->data->dev_conf.rxmode.offloads |=\n+\t\t\t\t\t\tDEV_RX_OFFLOAD_JUMBO_FRAME;\n+\telse\n+\t\tdev->data->dev_conf.rxmode.offloads &=\n+\t\t\t\t\t\t~DEV_RX_OFFLOAD_JUMBO_FRAME;\n+\tdev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;\n+\trte_spinlock_unlock(&hw->lock);\n+\n+\treturn 0;\n+}\n+\n+static void\n+hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)\n+{\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\tinfo->max_rx_queues = hw->tqps_num;\n+\tinfo->max_tx_queues = hw->tqps_num;\n+\tinfo->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */\n+\tinfo->min_rx_bufsize = hw->rx_buf_len;\n+\tinfo->max_mac_addrs = HNS3_UC_MACADDR_NUM;\n+\tinfo->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;\n+\tinfo->min_mtu = RTE_ETHER_MIN_MTU;\n+\n+\tinfo->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\t DEV_RX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\t DEV_RX_OFFLOAD_TCP_CKSUM |\n+\t\t\t\t DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |\n+\t\t\t\t DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |\n+\t\t\t\t DEV_RX_OFFLOAD_KEEP_CRC |\n+\t\t\t\t DEV_RX_OFFLOAD_SCATTER |\n+\t\t\t\t DEV_RX_OFFLOAD_VLAN_STRIP |\n+\t\t\t\t DEV_RX_OFFLOAD_QINQ_STRIP |\n+\t\t\t\t DEV_RX_OFFLOAD_VLAN_FILTER |\n+\t\t\t\t DEV_RX_OFFLOAD_JUMBO_FRAME);\n+\tinfo->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;\n+\tinfo->tx_offload_capa = (DEV_TX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\t DEV_TX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\t DEV_TX_OFFLOAD_TCP_CKSUM |\n+\t\t\t\t DEV_TX_OFFLOAD_VLAN_INSERT |\n+\t\t\t\t DEV_TX_OFFLOAD_QINQ_INSERT |\n+\t\t\t\t DEV_TX_OFFLOAD_MULTI_SEGS |\n+\t\t\t\t info->tx_queue_offload_capa);\n+\n+\tinfo->rx_desc_lim = (struct rte_eth_desc_lim) {\n+\t\t.nb_max = HNS3_MAX_RING_DESC,\n+\t\t.nb_min = HNS3_MIN_RING_DESC,\n+\t\t.nb_align = HNS3_ALIGN_RING_DESC,\n+\t};\n+\n+\tinfo->tx_desc_lim = (struct rte_eth_desc_lim) {\n+\t\t.nb_max = HNS3_MAX_RING_DESC,\n+\t\t.nb_min = HNS3_MIN_RING_DESC,\n+\t\t.nb_align = HNS3_ALIGN_RING_DESC,\n+\t};\n+\n+\tinfo->vmdq_queue_num = 0;\n+\n+\tinfo->reta_size = HNS3_RSS_IND_TBL_SIZE;\n+\tinfo->hash_key_size = HNS3_RSS_KEY_SIZE;\n+\tinfo->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;\n+\tinfo->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;\n+\tinfo->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;\n+}\n+\n+static void\n+hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)\n+{\n+\thns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);\n+}\n+\n+static void\n+hns3vf_disable_irq0(struct hns3_hw *hw)\n+{\n+\thns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);\n+}\n+\n+static void\n+hns3vf_enable_irq0(struct hns3_hw *hw)\n+{\n+\thns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);\n+}\n+\n+static enum hns3vf_evt_cause\n+hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tenum hns3vf_evt_cause ret;\n+\tuint32_t cmdq_stat_reg;\n+\tuint32_t rst_ing_reg;\n+\tuint32_t val;\n+\n+\t/* Fetch the events from their corresponding regs */\n+\tcmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);\n+\n+\t/* Check for vector0 mailbox(=CMDQ RX) event source */\n+\tif (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {\n+\t\tval = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);\n+\t\tret = HNS3VF_VECTOR0_EVENT_MBX;\n+\t\tgoto out;\n+\t}\n+\n+\tval = 0;\n+\tret = HNS3VF_VECTOR0_EVENT_OTHER;\n+out:\n+\tif (clearval)\n+\t\t*clearval = val;\n+\treturn ret;\n+}\n+\n+static void\n+hns3vf_interrupt_handler(void *param)\n+{\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n+\tstruct hns3_adapter *hns = dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tenum hns3vf_evt_cause event_cause;\n+\tuint32_t clearval;\n+\n+\t/* Disable interrupt */\n+\thns3vf_disable_irq0(hw);\n+\n+\t/* Read out interrupt causes */\n+\tevent_cause = hns3vf_check_event_cause(hns, &clearval);\n+\n+\tswitch (event_cause) {\n+\tcase HNS3VF_VECTOR0_EVENT_MBX:\n+\t\thns3_dev_handle_mbx_msg(hw);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t/* Clear interrupt causes */\n+\thns3vf_clear_event_cause(hw, clearval);\n+\n+\t/* Enable interrupt */\n+\thns3vf_enable_irq0(hw);\n+}\n+\n+static int\n+hns3vf_check_tqp_info(struct hns3_hw *hw)\n+{\n+\tuint16_t tqps_num;\n+\n+\ttqps_num = hw->tqps_num;\n+\tif (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Get invalid tqps_num(%u) from PF. valid \"\n+\t\t\t\t  \"range: 1~%d\",\n+\t\t\t     tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (hw->rx_buf_len == 0)\n+\t\thw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;\n+\thw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3vf_get_queue_info(struct hns3_hw *hw)\n+{\n+#define HNS3VF_TQPS_RSS_INFO_LEN\t6\n+\tuint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];\n+\tint ret;\n+\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,\n+\t\t\t\tresp_msg, HNS3VF_TQPS_RSS_INFO_LEN);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to get tqp info from PF: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tmemcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));\n+\tmemcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));\n+\tmemcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));\n+\n+\treturn hns3vf_check_tqp_info(hw);\n+}\n+\n+static int\n+hns3vf_get_queue_depth(struct hns3_hw *hw)\n+{\n+#define HNS3VF_TQPS_DEPTH_INFO_LEN\t4\n+\tuint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];\n+\tint ret;\n+\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,\n+\t\t\t\tresp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to get tqp depth info from PF: %d\",\n+\t\t\t     ret);\n+\t\treturn ret;\n+\t}\n+\n+\tmemcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));\n+\tmemcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3vf_get_tc_info(struct hns3_hw *hw)\n+{\n+\tuint8_t resp_msg;\n+\tint ret;\n+\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,\n+\t\t\t\ttrue, &resp_msg, sizeof(resp_msg));\n+\tif (ret) {\n+\t\thns3_err(hw, \"VF request to get TC info from PF failed %d\",\n+\t\t\t ret);\n+\t\treturn ret;\n+\t}\n+\n+\thw->hw_tc_map = resp_msg;\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3vf_get_configuration(struct hns3_hw *hw)\n+{\n+\tint ret;\n+\n+\thw->mac.media_type = HNS3_MEDIA_TYPE_NONE;\n+\n+\t/* Get queue configuration from PF */\n+\tret = hns3vf_get_queue_info(hw);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Get queue depth info from PF */\n+\tret = hns3vf_get_queue_depth(hw);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Get tc configuration from PF */\n+\treturn hns3vf_get_tc_info(hw);\n+}\n+\n+static void\n+hns3vf_set_tc_info(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tuint16_t nb_rx_q = hw->data->nb_rx_queues;\n+\tuint16_t new_tqps;\n+\tuint8_t i;\n+\n+\thw->num_tc = 0;\n+\tfor (i = 0; i < HNS3_MAX_TC_NUM; i++)\n+\t\tif (hw->hw_tc_map & BIT(i))\n+\t\t\thw->num_tc++;\n+\n+\tnew_tqps = RTE_MIN(hw->tqps_num, nb_rx_q);\n+\thw->alloc_rss_size = RTE_MIN(hw->rss_size_max, new_tqps / hw->num_tc);\n+\thw->alloc_tqps = hw->alloc_rss_size * hw->num_tc;\n+\n+\thns3_tc_queue_mapping_cfg(hw);\n+}\n+\n+static void\n+hns3vf_request_link_info(struct hns3_hw *hw)\n+{\n+\tuint8_t resp_msg;\n+\tint ret;\n+\n+\tif (rte_atomic16_read(&hw->reset.resetting))\n+\t\treturn;\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,\n+\t\t\t\t&resp_msg, sizeof(resp_msg));\n+\tif (ret)\n+\t\thns3_err(hw, \"Failed to fetch link status from PF: %d\", ret);\n+}\n+\n+static int\n+hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)\n+{\n+#define HNS3VF_VLAN_MBX_MSG_LEN 5\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tuint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];\n+\tuint16_t proto = htons(RTE_ETHER_TYPE_VLAN);\n+\tuint8_t is_kill = on ? 0 : 1;\n+\n+\tmsg_data[0] = is_kill;\n+\tmemcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));\n+\tmemcpy(&msg_data[3], &proto, sizeof(proto));\n+\n+\treturn hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,\n+\t\t\t\t msg_data, HNS3VF_VLAN_MBX_MSG_LEN, false, NULL,\n+\t\t\t\t 0);\n+}\n+\n+static int\n+hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n+{\n+\tstruct hns3_adapter *hns = dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\trte_spinlock_lock(&hw->lock);\n+\tret = hns3vf_vlan_filter_configure(hns, vlan_id, on);\n+\trte_spinlock_unlock(&hw->lock);\n+\tif (ret)\n+\t\thns3_err(hw, \"vf set vlan id failed, vlan_id =%u, ret =%d\",\n+\t\t\t vlan_id, ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)\n+{\n+\tuint8_t msg_data;\n+\tint ret;\n+\n+\tmsg_data = enable ? 1 : 0;\n+\tret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,\n+\t\t\t\t&msg_data, sizeof(msg_data), false, NULL, 0);\n+\tif (ret)\n+\t\thns3_err(hw, \"vf enable strip failed, ret =%d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n+{\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct rte_eth_conf *dev_conf = &dev->data->dev_conf;\n+\tunsigned int tmp_mask;\n+\n+\ttmp_mask = (unsigned int)mask;\n+\t/* Vlan stripping setting */\n+\tif (tmp_mask & ETH_VLAN_STRIP_MASK) {\n+\t\trte_spinlock_lock(&hw->lock);\n+\t\t/* Enable or disable VLAN stripping */\n+\t\tif (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)\n+\t\t\thns3vf_en_hw_strip_rxvtag(hw, true);\n+\t\telse\n+\t\t\thns3vf_en_hw_strip_rxvtag(hw, false);\n+\t\trte_spinlock_unlock(&hw->lock);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)\n+{\n+\tstruct hns3_adapter *hns = dev->data->dev_private;\n+\tstruct rte_eth_dev_data *data = dev->data;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tif (data->dev_conf.txmode.hw_vlan_reject_tagged ||\n+\t    data->dev_conf.txmode.hw_vlan_reject_untagged ||\n+\t    data->dev_conf.txmode.hw_vlan_insert_pvid) {\n+\t\thns3_warn(hw, \"hw_vlan_reject_tagged, hw_vlan_reject_untagged \"\n+\t\t\t      \"or hw_vlan_insert_pvid is not support!\");\n+\t}\n+\n+\t/* Apply vlan offload setting */\n+\tret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);\n+\tif (ret)\n+\t\thns3_err(hw, \"dev config vlan offload failed, ret =%d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_set_alive(struct hns3_hw *hw, bool alive)\n+{\n+\tuint8_t msg_data;\n+\n+\tmsg_data = alive ? 1 : 0;\n+\treturn hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,\n+\t\t\t\t sizeof(msg_data), false, NULL, 0);\n+}\n+\n+static void\n+hns3vf_keep_alive_handler(void *param)\n+{\n+\tstruct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tuint8_t respmsg;\n+\tint ret;\n+\n+\tif (!hns3vf_is_reset_pending(hns)) {\n+\t\tret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,\n+\t\t\t\t\tfalse, &respmsg, sizeof(uint8_t));\n+\t\tif (ret)\n+\t\t\thns3_err(hw, \"VF sends keeping alive cmd failed(=%d)\",\n+\t\t\t\t ret);\n+\t} else\n+\t\thns3_warn(hw, \"Cancel keeping alive when reset is pending\");\n+\n+\trte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,\n+\t\t\t  eth_dev);\n+}\n+\n+static void\n+hns3vf_service_handler(void *param)\n+{\n+\tstruct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\t/*\n+\t * The query link status and reset processing are executed in the\n+\t * interrupt thread.When the IMP reset occurs, IMP will not respond,\n+\t * and the query operation will time out after 30ms. In the case of\n+\t * multiple PF/VFs, each query failure timeout causes the IMP reset\n+\t * interrupt to fail to respond within 100ms.\n+\t * Before querying the link status, check whether there is a reset\n+\t * pending, and if so, abandon the query.\n+\t */\n+\tif (!hns3vf_is_reset_pending(hns))\n+\t\thns3vf_request_link_info(hw);\n+\telse\n+\t\thns3_warn(hw, \"Cancel the query when reset is pending\");\n+\n+\trte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,\n+\t\t\t  eth_dev);\n+}\n+\n+static int\n+hns3vf_init_hardware(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tuint16_t mtu = hw->data->mtu;\n+\tint ret;\n+\n+\tret = hns3vf_set_promisc_mode(hw, true);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = hns3vf_config_mtu(hw, mtu);\n+\tif (ret)\n+\t\tgoto err_init_hardware;\n+\n+\tret = hns3vf_vlan_filter_configure(hns, 0, 1);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to initialize VLAN config: %d\", ret);\n+\t\tgoto err_init_hardware;\n+\t}\n+\n+\tret = hns3_config_gro(hw, false);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to config gro: %d\", ret);\n+\t\tgoto err_init_hardware;\n+\t}\n+\n+\tret = hns3vf_set_alive(hw, true);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to VF send alive to PF: %d\", ret);\n+\t\tgoto err_init_hardware;\n+\t}\n+\n+\thns3vf_request_link_info(hw);\n+\treturn 0;\n+\n+err_init_hardware:\n+\t(void)hns3vf_set_promisc_mode(hw, false);\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_init_vf(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Get hardware io base address from pcie BAR2 IO space */\n+\thw->io_base = pci_dev->mem_resource[2].addr;\n+\n+\t/* Firmware command queue initialize */\n+\tret = hns3_cmd_init_queue(hw);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init cmd queue: %d\", ret);\n+\t\tgoto err_cmd_init_queue;\n+\t}\n+\n+\t/* Firmware command initialize */\n+\tret = hns3_cmd_init(hw);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init cmd: %d\", ret);\n+\t\tgoto err_cmd_init;\n+\t}\n+\n+\trte_spinlock_init(&hw->mbx_resp.lock);\n+\n+\thns3vf_clear_event_cause(hw, 0);\n+\n+\tret = rte_intr_callback_register(&pci_dev->intr_handle,\n+\t\t\t\t\t hns3vf_interrupt_handler, eth_dev);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to register intr: %d\", ret);\n+\t\tgoto err_intr_callback_register;\n+\t}\n+\n+\t/* Enable interrupt */\n+\trte_intr_enable(&pci_dev->intr_handle);\n+\thns3vf_enable_irq0(hw);\n+\n+\t/* Get configuration from PF */\n+\tret = hns3vf_get_configuration(hw);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to fetch configuration: %d\", ret);\n+\t\tgoto err_get_config;\n+\t}\n+\n+\trte_eth_random_addr(hw->mac.mac_addr); /* Generate a random mac addr */\n+\n+\tret = hns3vf_init_hardware(hns);\n+\tif (ret)\n+\t\tgoto err_get_config;\n+\n+\thns3_set_default_rss_args(hw);\n+\n+\thns3_stats_reset(eth_dev);\n+\treturn 0;\n+\n+err_get_config:\n+\thns3vf_disable_irq0(hw);\n+\trte_intr_disable(&pci_dev->intr_handle);\n+\thns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,\n+\t\t\t     eth_dev);\n+err_intr_callback_register:\n+\thns3_cmd_uninit(hw);\n+\n+err_cmd_init:\n+\thns3_cmd_destroy_queue(hw);\n+\n+err_cmd_init_queue:\n+\thw->io_base = NULL;\n+\n+\treturn ret;\n+}\n+\n+static void\n+hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\thns3_rss_uninit(hns);\n+\t(void)hns3vf_set_alive(hw, false);\n+\t(void)hns3vf_set_promisc_mode(hw, false);\n+\thns3vf_disable_irq0(hw);\n+\trte_intr_disable(&pci_dev->intr_handle);\n+\thns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,\n+\t\t\t     eth_dev);\n+\thns3_cmd_uninit(hw);\n+\thns3_cmd_destroy_queue(hw);\n+\thw->io_base = NULL;\n+}\n+\n+static int\n+hns3vf_do_stop(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tbool reset_queue;\n+\n+\thw->mac.link_status = ETH_LINK_DOWN;\n+\n+\thns3vf_configure_mac_addr(hns, true);\n+\treset_queue = true;\n+\treturn hns3_stop_queues(hns, reset_queue);\n+}\n+\n+static void\n+hns3vf_dev_stop(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\thw->adapter_state = HNS3_NIC_STOPPING;\n+\thns3_set_rxtx_function(eth_dev);\n+\trte_wmb();\n+\t/* Disable datapath on secondary process. */\n+\thns3_mp_req_stop_rxtx(eth_dev);\n+\t/* Prevent crashes when queues are still in use. */\n+\trte_delay_ms(hw->tqps_num);\n+\n+\trte_spinlock_lock(&hw->lock);\n+\thns3vf_do_stop(hns);\n+\thns3_dev_release_mbufs(hns);\n+\thw->adapter_state = HNS3_NIC_CONFIGURED;\n+\trte_spinlock_unlock(&hw->lock);\n+}\n+\n+static void\n+hns3vf_dev_close(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\tif (hw->adapter_state == HNS3_NIC_STARTED)\n+\t\thns3vf_dev_stop(eth_dev);\n+\n+\thw->adapter_state = HNS3_NIC_CLOSING;\n+\trte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);\n+\trte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);\n+\thns3vf_configure_all_mc_mac_addr(hns, true);\n+\thns3vf_uninit_vf(eth_dev);\n+\thns3_free_all_queues(eth_dev);\n+\thw->adapter_state = HNS3_NIC_CLOSED;\n+}\n+\n+static int\n+hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n+\t\t       __rte_unused int wait_to_complete)\n+{\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_mac *mac = &hw->mac;\n+\tstruct rte_eth_link new_link;\n+\n+\thns3vf_request_link_info(hw);\n+\n+\tmemset(&new_link, 0, sizeof(new_link));\n+\tswitch (mac->link_speed) {\n+\tcase ETH_SPEED_NUM_10M:\n+\tcase ETH_SPEED_NUM_100M:\n+\tcase ETH_SPEED_NUM_1G:\n+\tcase ETH_SPEED_NUM_10G:\n+\tcase ETH_SPEED_NUM_25G:\n+\tcase ETH_SPEED_NUM_40G:\n+\tcase ETH_SPEED_NUM_50G:\n+\tcase ETH_SPEED_NUM_100G:\n+\t\tnew_link.link_speed = mac->link_speed;\n+\t\tbreak;\n+\tdefault:\n+\t\tnew_link.link_speed = ETH_SPEED_NUM_100M;\n+\t\tbreak;\n+\t}\n+\n+\tnew_link.link_duplex = mac->link_duplex;\n+\tnew_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;\n+\tnew_link.link_autoneg =\n+\t    !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);\n+\n+\treturn rte_eth_linkstatus_set(eth_dev, &new_link);\n+}\n+\n+static int\n+hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\thns3vf_set_tc_info(hns);\n+\n+\tret = hns3_start_queues(hns, reset_queue);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Failed to start queues: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3vf_dev_start(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\trte_spinlock_lock(&hw->lock);\n+\thw->adapter_state = HNS3_NIC_STARTING;\n+\tret = hns3vf_do_start(hns, true);\n+\tif (ret) {\n+\t\thw->adapter_state = HNS3_NIC_CONFIGURED;\n+\t\trte_spinlock_unlock(&hw->lock);\n+\t\treturn ret;\n+\t}\n+\thw->adapter_state = HNS3_NIC_STARTED;\n+\trte_spinlock_unlock(&hw->lock);\n+\treturn 0;\n+}\n+\n+static const struct eth_dev_ops hns3vf_eth_dev_ops = {\n+\t.dev_start          = hns3vf_dev_start,\n+\t.dev_stop           = hns3vf_dev_stop,\n+\t.dev_close          = hns3vf_dev_close,\n+\t.mtu_set            = hns3vf_dev_mtu_set,\n+\t.dev_infos_get      = hns3vf_dev_infos_get,\n+\t.dev_configure      = hns3vf_dev_configure,\n+\t.mac_addr_add       = hns3vf_add_mac_addr,\n+\t.mac_addr_remove    = hns3vf_remove_mac_addr,\n+\t.mac_addr_set       = hns3vf_set_default_mac_addr,\n+\t.set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,\n+\t.link_update        = hns3vf_dev_link_update,\n+\t.rss_hash_update    = hns3_dev_rss_hash_update,\n+\t.rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,\n+\t.reta_update        = hns3_dev_rss_reta_update,\n+\t.reta_query         = hns3_dev_rss_reta_query,\n+\t.filter_ctrl        = hns3_dev_filter_ctrl,\n+\t.vlan_filter_set    = hns3vf_vlan_filter_set,\n+\t.vlan_offload_set   = hns3vf_vlan_offload_set,\n+};\n+\n+static int\n+hns3vf_dev_init(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\teth_dev->process_private = (struct hns3_process_private *)\n+\t    rte_zmalloc_socket(\"hns3_filter_list\",\n+\t\t\t       sizeof(struct hns3_process_private),\n+\t\t\t       RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);\n+\tif (eth_dev->process_private == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to alloc memory for process private\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* initialize flow filter lists */\n+\thns3_filterlist_init(eth_dev);\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\teth_dev->dev_ops = &hns3vf_eth_dev_ops;\n+\n+\thw->adapter_state = HNS3_NIC_UNINITIALIZED;\n+\trte_eth_copy_pci_info(eth_dev, pci_dev);\n+\thns->is_vf = true;\n+\thw->data = eth_dev->data;\n+\n+\tret = hns3vf_init_vf(eth_dev);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init vf: %d\", ret);\n+\t\tgoto err_init_vf;\n+\t}\n+\n+\t/* Allocate memory for storing MAC addresses */\n+\teth_dev->data->mac_addrs = rte_zmalloc(\"hns3vf-mac\",\n+\t\t\t\t\t       sizeof(struct rte_ether_addr) *\n+\t\t\t\t\t       HNS3_UC_MACADDR_NUM, 0);\n+\tif (eth_dev->data->mac_addrs == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %ld bytes needed to \"\n+\t\t\t     \"store MAC addresses\",\n+\t\t\t     sizeof(struct rte_ether_addr) *\n+\t\t\t     HNS3_UC_MACADDR_NUM);\n+\t\tret = -ENOMEM;\n+\t\tgoto err_rte_zmalloc;\n+\t}\n+\n+\trte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,\n+\t\t\t    &eth_dev->data->mac_addrs[0]);\n+\thw->adapter_state = HNS3_NIC_INITIALIZED;\n+\trte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,\n+\t\t\t  eth_dev);\n+\trte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,\n+\t\t\t  eth_dev);\n+\treturn 0;\n+\n+err_rte_zmalloc:\n+\thns3vf_uninit_vf(eth_dev);\n+\n+err_init_vf:\n+\teth_dev->dev_ops = NULL;\n+\teth_dev->rx_pkt_burst = NULL;\n+\teth_dev->tx_pkt_burst = NULL;\n+\trte_free(eth_dev->process_private);\n+\teth_dev->process_private = NULL;\n+\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn -EPERM;\n+\n+\teth_dev->dev_ops = NULL;\n+\teth_dev->rx_pkt_burst = NULL;\n+\teth_dev->tx_pkt_burst = NULL;\n+\n+\tif (hw->adapter_state < HNS3_NIC_CLOSING)\n+\t\thns3vf_dev_close(eth_dev);\n+\n+\trte_free(eth_dev->process_private);\n+\teth_dev->process_private = NULL;\n+\thw->adapter_state = HNS3_NIC_REMOVED;\n+\treturn 0;\n+}\n+\n+static int\n+eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\t\t     struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_eth_dev_pci_generic_probe(pci_dev,\n+\t\t\t\t\t     sizeof(struct hns3_adapter),\n+\t\t\t\t\t     hns3vf_dev_init);\n+}\n+\n+static int\n+eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);\n+}\n+\n+static const struct rte_pci_id pci_id_hns3vf_map[] = {\n+\t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },\n+\t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },\n+\t{ .vendor_id = 0, /* sentinel */ },\n+};\n+\n+static struct rte_pci_driver rte_hns3vf_pmd = {\n+\t.id_table = pci_id_hns3vf_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = eth_hns3vf_pci_probe,\n+\t.remove = eth_hns3vf_pci_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);\n+RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, \"* igb_uio | vfio-pci\");\n",
    "prefixes": [
        "14/22"
    ]
}