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{
    "id": 5731,
    "url": "https://patches.dpdk.org/api/patches/5731/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1435116386-12010-19-git-send-email-wenzhuo.lu@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1435116386-12010-19-git-send-email-wenzhuo.lu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1435116386-12010-19-git-send-email-wenzhuo.lu@intel.com",
    "date": "2015-06-24T03:26:07",
    "name": "[dpdk-dev,18/37] ixgbe/base: check for functional ucode",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "73b00881eb49655cc340e6d1a57d6f6abbe7c988",
    "submitter": {
        "id": 258,
        "url": "https://patches.dpdk.org/api/people/258/?format=api",
        "name": "Wenzhuo Lu",
        "email": "wenzhuo.lu@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1435116386-12010-19-git-send-email-wenzhuo.lu@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/5731/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/5731/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 0D6ACC980;\n\tWed, 24 Jun 2015 05:27:18 +0200 (CEST)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id C4C74C97C\n\tfor <dev@dpdk.org>; Wed, 24 Jun 2015 05:27:15 +0200 (CEST)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga101.jf.intel.com with ESMTP; 23 Jun 2015 20:27:14 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga002.fm.intel.com with ESMTP; 23 Jun 2015 20:27:15 -0700",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t5O3RCjF020443;\n\tWed, 24 Jun 2015 11:27:12 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t5O3R9B4012173; Wed, 24 Jun 2015 11:27:11 +0800",
            "(from wenzhuol@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t5O3R9ul012169; \n\tWed, 24 Jun 2015 11:27:09 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.13,669,1427785200\"; d=\"scan'208\";a=\"749302568\"",
        "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Wed, 24 Jun 2015 11:26:07 +0800",
        "Message-Id": "<1435116386-12010-19-git-send-email-wenzhuo.lu@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1435116386-12010-1-git-send-email-wenzhuo.lu@intel.com>",
        "References": "<1435116386-12010-1-git-send-email-wenzhuo.lu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 18/37] ixgbe/base: check for functional ucode",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "During init, check the ucode running in the CS4227. If\nit is not responding correctly, reset the part. This is\na global reset so it must only be done the first time a\ndriver loads after power-on.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_x550.c | 78 +++++++++++++++++++++++++++++++++++--\n 1 file changed, 75 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c\nindex 3e8ea74..e4e8cff 100644\n--- a/drivers/net/ixgbe/base/ixgbe_x550.c\n+++ b/drivers/net/ixgbe/base/ixgbe_x550.c\n@@ -118,6 +118,7 @@ STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)\n {\n \ts32 status;\n \tu16 value = 0;\n+\tu16 reg_slice, reg_val;\n \tu8 retry;\n \n \tfor (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {\n@@ -132,6 +133,77 @@ STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)\n \tif (value != IXGBE_CS4227_GLOBAL_ID_VALUE)\n \t\treturn IXGBE_ERR_PHY;\n \n+\tstatus = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* If this is the first time after power-on, check the ucode.\n+\t * Otherwise, this will disrupt link on all ports. Because we\n+\t * can only do this the first time, we must check all ports,\n+\t * not just our own.\n+\t */\n+\tif (value != IXGBE_CS4227_SCRATCH_VALUE) {\n+\t\treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;\n+\t\treg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;\n+\t\tstatus = ixgbe_write_cs4227(hw, reg_slice, reg_val);\n+\t\tif (status != IXGBE_SUCCESS)\n+\t\t\treturn status;\n+\n+\t\treg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;\n+\t\treg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;\n+\t\tstatus = ixgbe_write_cs4227(hw, reg_slice, reg_val);\n+\t\tif (status != IXGBE_SUCCESS)\n+\t\t\treturn status;\n+\n+\t\treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);\n+\t\treg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;\n+\t\tstatus = ixgbe_write_cs4227(hw, reg_slice, reg_val);\n+\t\tif (status != IXGBE_SUCCESS)\n+\t\t\treturn status;\n+\n+\t\treg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);\n+\t\treg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;\n+\t\tstatus = ixgbe_write_cs4227(hw, reg_slice, reg_val);\n+\t\tif (status != IXGBE_SUCCESS)\n+\t\t\treturn status;\n+\n+\t\tmsec_delay(10);\n+\t}\n+\n+\t/* Verify that the ucode is operational on all ports. */\n+\treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;\n+\treg_val = 0xFFFF;\n+\tstatus = ixgbe_read_cs4227(hw, reg_slice, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\tif (reg_val != 0)\n+\t\treturn IXGBE_ERR_PHY;\n+\n+\treg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;\n+\treg_val = 0xFFFF;\n+\tstatus = ixgbe_read_cs4227(hw, reg_slice, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\tif (reg_val != 0)\n+\t\treturn IXGBE_ERR_PHY;\n+\n+\treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);\n+\treg_val = 0xFFFF;\n+\tstatus = ixgbe_read_cs4227(hw, reg_slice, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\tif (reg_val != 0)\n+\t\treturn IXGBE_ERR_PHY;\n+\n+\treg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);\n+\treg_val = 0xFFFF;\n+\tstatus = ixgbe_read_cs4227(hw, reg_slice, &reg_val);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\tif (reg_val != 0)\n+\t\treturn IXGBE_ERR_PHY;\n+\n+\t/* Set scratch indicating that the diagnostic was successful. */\n \tstatus = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,\n \t\t\t\t    IXGBE_CS4227_SCRATCH_VALUE);\n \tif (status != IXGBE_SUCCESS)\n@@ -141,6 +213,7 @@ STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)\n \t\treturn status;\n \tif (value != IXGBE_CS4227_SCRATCH_VALUE)\n \t\treturn IXGBE_ERR_PHY;\n+\n \treturn IXGBE_SUCCESS;\n }\n \n@@ -1771,13 +1844,12 @@ s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,\n \tif (ret_val != IXGBE_SUCCESS)\n \t\treturn ret_val;\n \n-\t/* Configure CS4227 for connection rate. */\n+\t/* Configure CS4227 for LINE connection rate then type. */\n \treg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);\n \treg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;\n \tret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,\n \t\t\t\t\t   reg_val);\n \n-\t/* Configure CS4227 for connection type. */\n \treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);\n \tif (setup_linear)\n \t\treg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;\n@@ -1786,12 +1858,12 @@ s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,\n \tret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,\n \t\t\t\t\t   reg_val);\n \n+\t/* Configure CS4227 for HOST connection rate then type. */\n \treg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);\n \treg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000;\n \tret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,\n \t\t\t\t\t   reg_val);\n \n-\t/* Configure CS4227 for connection type. */\n \treg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);\n \tif (setup_linear)\n \t\treg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;\n",
    "prefixes": [
        "dpdk-dev",
        "18/37"
    ]
}