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GET /api/patches/48987/?format=api
{ "id": 48987, "url": "https://patches.dpdk.org/api/patches/48987/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-20-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1545032259-77179-20-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1545032259-77179-20-git-send-email-wenzhuo.lu@intel.com", "date": "2018-12-17T07:37:27", "name": "[v5,19/31] net/ice: support link update", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "356a9d469d703f7792fbf1ba26b3707bf1570256", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-20-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 2824, "url": "https://patches.dpdk.org/api/series/2824/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2824", "date": "2018-12-17T07:37:08", "name": "A new net PMD - ICE", "version": 5, "mbox": "https://patches.dpdk.org/series/2824/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/48987/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/48987/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EA8731B9F2;\n\tMon, 17 Dec 2018 08:33:31 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 27EA31B5FE\n\tfor <dev@dpdk.org>; Mon, 17 Dec 2018 08:33:18 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Dec 2018 23:33:17 -0800", "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby orsmga002.jf.intel.com with ESMTP; 16 Dec 2018 23:33:16 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,364,1539673200\"; d=\"scan'208\";a=\"118899279\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>, Qiming Yang <qiming.yang@intel.com>, \n\tXiaoyun Li <xiaoyun.li@intel.com>, Jingjing Wu <jingjing.wu@intel.com>", "Date": "Mon, 17 Dec 2018 15:37:27 +0800", "Message-Id": "<1545032259-77179-20-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 19/31] net/ice: support link update", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add ops link_update.\nLSC interrupt is also enabled in this patch.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\nSigned-off-by: Xiaoyun Li <xiaoyun.li@intel.com>\nSigned-off-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n doc/guides/nics/features/ice.ini | 2 +\n drivers/net/ice/ice_ethdev.c | 332 +++++++++++++++++++++++++++++++++++++++\n 2 files changed, 334 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/ice.ini b/doc/guides/nics/features/ice.ini\nindex af8f0d3..eb852ff 100644\n--- a/doc/guides/nics/features/ice.ini\n+++ b/doc/guides/nics/features/ice.ini\n@@ -5,6 +5,8 @@\n ;\n [Features]\n Speed capabilities = Y\n+Link status = Y\n+Link status event = Y\n Queue start/stop = Y\n BSD nic_uio = Y\n Linux UIO = Y\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex c916bf2..3118b05 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -21,6 +21,8 @@\n static int ice_dev_reset(struct rte_eth_dev *dev);\n static void ice_dev_info_get(struct rte_eth_dev *dev,\n \t\t\t struct rte_eth_dev_info *dev_info);\n+static int ice_link_update(struct rte_eth_dev *dev,\n+\t\t\t int wait_to_complete);\n \n static const struct rte_pci_id pci_id_ice_map[] = {\n \t{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },\n@@ -45,6 +47,7 @@ static void ice_dev_info_get(struct rte_eth_dev *dev,\n \t.tx_queue_release = ice_tx_queue_release,\n \t.dev_infos_get = ice_dev_info_get,\n \t.dev_supported_ptypes_get = ice_dev_supported_ptypes_get,\n+\t.link_update = ice_link_update,\n };\n \n static void\n@@ -331,6 +334,187 @@ static void ice_dev_info_get(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+/* Enable IRQ0 */\n+static void\n+ice_pf_enable_irq0(struct ice_hw *hw)\n+{\n+\t/* reset the registers */\n+\tICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);\n+\tICE_READ_REG(hw, PFINT_OICR);\n+\n+#ifdef ICE_LSE_SPT\n+\tICE_WRITE_REG(hw, PFINT_OICR_ENA,\n+\t\t (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &\n+\t\t\t\t (~PFINT_OICR_LINK_STAT_CHANGE_M)));\n+\n+\tICE_WRITE_REG(hw, PFINT_OICR_CTL,\n+\t\t (0 & PFINT_OICR_CTL_MSIX_INDX_M) |\n+\t\t ((0 << PFINT_OICR_CTL_ITR_INDX_S) &\n+\t\t PFINT_OICR_CTL_ITR_INDX_M) |\n+\t\t PFINT_OICR_CTL_CAUSE_ENA_M);\n+\n+\tICE_WRITE_REG(hw, PFINT_FW_CTL,\n+\t\t (0 & PFINT_FW_CTL_MSIX_INDX_M) |\n+\t\t ((0 << PFINT_FW_CTL_ITR_INDX_S) &\n+\t\t PFINT_FW_CTL_ITR_INDX_M) |\n+\t\t PFINT_FW_CTL_CAUSE_ENA_M);\n+#else\n+\tICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);\n+#endif\n+\n+\tICE_WRITE_REG(hw, GLINT_DYN_CTL(0),\n+\t\t GLINT_DYN_CTL_INTENA_M |\n+\t\t GLINT_DYN_CTL_CLEARPBA_M |\n+\t\t GLINT_DYN_CTL_ITR_INDX_M);\n+\n+\tice_flush(hw);\n+}\n+\n+/* Disable IRQ0 */\n+static void\n+ice_pf_disable_irq0(struct ice_hw *hw)\n+{\n+\t/* Disable all interrupt types */\n+\tICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);\n+\tice_flush(hw);\n+}\n+\n+#ifdef ICE_LSE_SPT\n+static void\n+ice_handle_aq_msg(struct rte_eth_dev *dev)\n+{\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ice_ctl_q_info *cq = &hw->adminq;\n+\tstruct ice_rq_event_info event;\n+\tuint16_t pending, opcode;\n+\tint ret;\n+\n+\tevent.buf_len = ICE_AQ_MAX_BUF_LEN;\n+\tevent.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);\n+\tif (!event.msg_buf) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate mem\");\n+\t\treturn;\n+\t}\n+\n+\tpending = 1;\n+\twhile (pending) {\n+\t\tret = ice_clean_rq_elem(hw, cq, &event, &pending);\n+\n+\t\tif (ret != ICE_SUCCESS) {\n+\t\t\tPMD_DRV_LOG(INFO,\n+\t\t\t\t \"Failed to read msg from AdminQ, \"\n+\t\t\t\t \"adminq_err: %u\",\n+\t\t\t\t hw->adminq.sq_last_status);\n+\t\t\tbreak;\n+\t\t}\n+\t\topcode = rte_le_to_cpu_16(event.desc.opcode);\n+\n+\t\tswitch (opcode) {\n+\t\tcase ice_aqc_opc_get_link_status:\n+\t\t\tret = ice_link_update(dev, 0);\n+\t\t\tif (!ret)\n+\t\t\t\t_rte_eth_dev_callback_process\n+\t\t\t\t\t(dev, RTE_ETH_EVENT_INTR_LSC, NULL);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Request %u is not supported yet\",\n+\t\t\t\t opcode);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\trte_free(event.msg_buf);\n+}\n+#endif\n+\n+/**\n+ * Interrupt handler triggered by NIC for handling\n+ * specific interrupt.\n+ *\n+ * @param handle\n+ * Pointer to interrupt handle.\n+ * @param param\n+ * The address of parameter (struct rte_eth_dev *) regsitered before.\n+ *\n+ * @return\n+ * void\n+ */\n+static void\n+ice_interrupt_handler(void *param)\n+{\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t oicr;\n+\tuint32_t reg;\n+\tuint8_t pf_num;\n+\tuint8_t event;\n+\tuint16_t queue;\n+#ifdef ICE_LSE_SPT\n+\tuint32_t int_fw_ctl;\n+#endif\n+\n+\t/* Disable interrupt */\n+\tice_pf_disable_irq0(hw);\n+\n+\t/* read out interrupt causes */\n+\toicr = ICE_READ_REG(hw, PFINT_OICR);\n+#ifdef ICE_LSE_SPT\n+\tint_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);\n+#endif\n+\n+\t/* No interrupt event indicated */\n+\tif (!(oicr & PFINT_OICR_INTEVENT_M)) {\n+\t\tPMD_DRV_LOG(INFO, \"No interrupt event\");\n+\t\tgoto done;\n+\t}\n+\n+#ifdef ICE_LSE_SPT\n+\tif (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {\n+\t\tPMD_DRV_LOG(INFO, \"FW_CTL: link state change event\");\n+\t\tice_handle_aq_msg(dev);\n+\t}\n+#else\n+\tif (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {\n+\t\tPMD_DRV_LOG(INFO, \"OICR: link state change event\");\n+\t\tice_link_update(dev, 0);\n+\t}\n+#endif\n+\n+\tif (oicr & PFINT_OICR_MAL_DETECT_M) {\n+\t\tPMD_DRV_LOG(WARNING, \"OICR: MDD event\");\n+\t\treg = ICE_READ_REG(hw, GL_MDET_TX_PQM);\n+\t\tif (reg & GL_MDET_TX_PQM_VALID_M) {\n+\t\t\tpf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>\n+\t\t\t\t GL_MDET_TX_PQM_PF_NUM_S;\n+\t\t\tevent = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>\n+\t\t\t\tGL_MDET_TX_PQM_MAL_TYPE_S;\n+\t\t\tqueue = (reg & GL_MDET_TX_PQM_QNUM_M) >>\n+\t\t\t\tGL_MDET_TX_PQM_QNUM_S;\n+\n+\t\t\tPMD_DRV_LOG(WARNING, \"Malicious Driver Detection event \"\n+\t\t\t\t \"%d by PQM on TX queue %d PF# %d\",\n+\t\t\t\t event, queue, pf_num);\n+\t\t}\n+\n+\t\treg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);\n+\t\tif (reg & GL_MDET_TX_TCLAN_VALID_M) {\n+\t\t\tpf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>\n+\t\t\t\t GL_MDET_TX_TCLAN_PF_NUM_S;\n+\t\t\tevent = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>\n+\t\t\t\tGL_MDET_TX_TCLAN_MAL_TYPE_S;\n+\t\t\tqueue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>\n+\t\t\t\tGL_MDET_TX_TCLAN_QNUM_S;\n+\n+\t\t\tPMD_DRV_LOG(WARNING, \"Malicious Driver Detection event \"\n+\t\t\t\t \"%d by TCLAN on TX queue %d PF# %d\",\n+\t\t\t\t event, queue, pf_num);\n+\t\t}\n+\t}\n+done:\n+\t/* Enable interrupt */\n+\tice_pf_enable_irq0(hw);\n+\trte_intr_enable(dev->intr_handle);\n+}\n+\n /* Initialize SW parameters of PF */\n static int\n ice_pf_sw_init(struct rte_eth_dev *dev)\n@@ -488,6 +672,7 @@ static void ice_dev_info_get(struct rte_eth_dev *dev,\n ice_dev_init(struct rte_eth_dev *dev)\n {\n \tstruct rte_pci_device *pci_dev;\n+\tstruct rte_intr_handle *intr_handle;\n \tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tint ret;\n@@ -496,6 +681,7 @@ static void ice_dev_info_get(struct rte_eth_dev *dev,\n \n \tice_set_default_ptype_table(dev);\n \tpci_dev = RTE_DEV_TO_PCI(dev->device);\n+\tintr_handle = &pci_dev->intr_handle;\n \n \tpf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tpf->adapter->eth_dev = dev;\n@@ -541,6 +727,15 @@ static void ice_dev_info_get(struct rte_eth_dev *dev,\n \t\tgoto err_pf_setup;\n \t}\n \n+\t/* register callback func to eal lib */\n+\trte_intr_callback_register(intr_handle,\n+\t\t\t\t ice_interrupt_handler, dev);\n+\n+\tice_pf_enable_irq0(hw);\n+\n+\t/* enable uio intr after callback register */\n+\trte_intr_enable(intr_handle);\n+\n \treturn 0;\n \n err_pf_setup:\n@@ -587,6 +782,8 @@ static void ice_dev_info_get(struct rte_eth_dev *dev,\n {\n \tstruct rte_eth_dev_data *data = dev->data;\n \tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tuint16_t i;\n \n \t/* avoid stopping again */\n@@ -604,6 +801,13 @@ static void ice_dev_info_get(struct rte_eth_dev *dev,\n \t/* Clear all queues and release mbufs */\n \tice_clear_queues(dev);\n \n+\t/* Clean datapath event and queue/vec mapping */\n+\trte_intr_efd_disable(intr_handle);\n+\tif (intr_handle->intr_vec) {\n+\t\trte_free(intr_handle->intr_vec);\n+\t\tintr_handle->intr_vec = NULL;\n+\t}\n+\n \tpf->adapter_stopped = true;\n }\n \n@@ -629,6 +833,8 @@ static void ice_dev_info_get(struct rte_eth_dev *dev,\n {\n \tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \n \tice_dev_close(dev);\n \n@@ -639,6 +845,13 @@ static void ice_dev_info_get(struct rte_eth_dev *dev,\n \trte_free(dev->data->mac_addrs);\n \tdev->data->mac_addrs = NULL;\n \n+\t/* disable uio intr before callback unregister */\n+\trte_intr_disable(intr_handle);\n+\n+\t/* register callback func to eal lib */\n+\trte_intr_callback_unregister(intr_handle,\n+\t\t\t\t ice_interrupt_handler, dev);\n+\n \tice_release_vsi(pf->main_vsi);\n \tice_sched_cleanup_all(hw);\n \trte_free(hw->port_info);\n@@ -757,6 +970,9 @@ static int ice_init_rss(struct ice_pf *pf)\n \tif (ret != ICE_SUCCESS)\n \t\tPMD_DRV_LOG(WARNING, \"Fail to set phy mask\");\n \n+\t/* Call get_link_info aq commond to enable/disable LSE */\n+\tice_link_update(dev, 0);\n+\n \tpf->adapter_stopped = false;\n \n \treturn 0;\n@@ -895,6 +1111,122 @@ static int ice_init_rss(struct ice_pf *pf)\n \tdev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;\n }\n \n+static inline int\n+ice_atomic_read_link_status(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_link *link)\n+{\n+\tstruct rte_eth_link *dst = link;\n+\tstruct rte_eth_link *src = &dev->data->dev_link;\n+\n+\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n+\t\t\t\t*(uint64_t *)src) == 0)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+static inline int\n+ice_atomic_write_link_status(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_link *link)\n+{\n+\tstruct rte_eth_link *dst = &dev->data->dev_link;\n+\tstruct rte_eth_link *src = link;\n+\n+\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n+\t\t\t\t*(uint64_t *)src) == 0)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)\n+{\n+#define CHECK_INTERVAL 100 /* 100ms */\n+#define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ice_link_status link_status;\n+\tstruct rte_eth_link link, old;\n+\tint status;\n+\tunsigned int rep_cnt = MAX_REPEAT_TIME;\n+\tbool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;\n+\n+\tmemset(&link, 0, sizeof(link));\n+\tmemset(&old, 0, sizeof(old));\n+\tmemset(&link_status, 0, sizeof(link_status));\n+\tice_atomic_read_link_status(dev, &old);\n+\n+\tdo {\n+\t\t/* Get link status information from hardware */\n+\t\tstatus = ice_aq_get_link_info(hw->port_info, enable_lse,\n+\t\t\t\t\t &link_status, NULL);\n+\t\tif (status != ICE_SUCCESS) {\n+\t\t\tlink.link_speed = ETH_SPEED_NUM_100M;\n+\t\t\tlink.link_duplex = ETH_LINK_FULL_DUPLEX;\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to get link info\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tlink.link_status = link_status.link_info & ICE_AQ_LINK_UP;\n+\t\tif (!wait_to_complete || link.link_status)\n+\t\t\tbreak;\n+\n+\t\trte_delay_ms(CHECK_INTERVAL);\n+\t} while (--rep_cnt);\n+\n+\tif (!link.link_status)\n+\t\tgoto out;\n+\n+\t/* Full-duplex operation at all supported speeds */\n+\tlink.link_duplex = ETH_LINK_FULL_DUPLEX;\n+\n+\t/* Parse the link status */\n+\tswitch (link_status.link_speed) {\n+\tcase ICE_AQ_LINK_SPEED_10MB:\n+\t\tlink.link_speed = ETH_SPEED_NUM_10M;\n+\t\tbreak;\n+\tcase ICE_AQ_LINK_SPEED_100MB:\n+\t\tlink.link_speed = ETH_SPEED_NUM_100M;\n+\t\tbreak;\n+\tcase ICE_AQ_LINK_SPEED_1000MB:\n+\t\tlink.link_speed = ETH_SPEED_NUM_1G;\n+\t\tbreak;\n+\tcase ICE_AQ_LINK_SPEED_2500MB:\n+\t\tlink.link_speed = ETH_SPEED_NUM_2_5G;\n+\t\tbreak;\n+\tcase ICE_AQ_LINK_SPEED_5GB:\n+\t\tlink.link_speed = ETH_SPEED_NUM_5G;\n+\t\tbreak;\n+\tcase ICE_AQ_LINK_SPEED_10GB:\n+\t\tlink.link_speed = ETH_SPEED_NUM_10G;\n+\t\tbreak;\n+\tcase ICE_AQ_LINK_SPEED_20GB:\n+\t\tlink.link_speed = ETH_SPEED_NUM_20G;\n+\t\tbreak;\n+\tcase ICE_AQ_LINK_SPEED_25GB:\n+\t\tlink.link_speed = ETH_SPEED_NUM_25G;\n+\t\tbreak;\n+\tcase ICE_AQ_LINK_SPEED_40GB:\n+\t\tlink.link_speed = ETH_SPEED_NUM_40G;\n+\t\tbreak;\n+\tcase ICE_AQ_LINK_SPEED_UNKNOWN:\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Unknown link speed\");\n+\t\tlink.link_speed = ETH_SPEED_NUM_NONE;\n+\t\tbreak;\n+\t}\n+\n+\tlink.link_autoneg = !(dev->data->dev_conf.link_speeds &\n+\t\t\t ETH_LINK_SPEED_FIXED);\n+\n+out:\n+\tice_atomic_write_link_status(dev, &link);\n+\tif (link.link_status == old.link_status)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n static int\n ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t struct rte_pci_device *pci_dev)\n", "prefixes": [ "v5", "19/31" ] }