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GET /api/patches/48982/?format=api
{ "id": 48982, "url": "https://patches.dpdk.org/api/patches/48982/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-15-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1545032259-77179-15-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1545032259-77179-15-git-send-email-wenzhuo.lu@intel.com", "date": "2018-12-17T07:37:22", "name": "[v5,14/31] net/ice/base: add OS specific implementation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2369ab419e20f278d184b75e05c47e07dd482f4c", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-15-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 2824, "url": "https://patches.dpdk.org/api/series/2824/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2824", "date": "2018-12-17T07:37:08", "name": "A new net PMD - ICE", "version": 5, "mbox": "https://patches.dpdk.org/series/2824/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/48982/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/48982/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 563A21B8BE;\n\tMon, 17 Dec 2018 08:33:22 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 4E5131B5D1\n\tfor <dev@dpdk.org>; Mon, 17 Dec 2018 08:33:12 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Dec 2018 23:33:10 -0800", "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby orsmga002.jf.intel.com with ESMTP; 16 Dec 2018 23:33:10 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,364,1539673200\"; d=\"scan'208\";a=\"118899228\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "Date": "Mon, 17 Dec 2018 15:37:22 +0800", "Message-Id": "<1545032259-77179-15-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v5 14/31] net/ice/base: add OS specific\n\timplementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add some MACRO defination and small functions which\nare specific for DPDK.\nAdd readme too.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/ice/base/README | 22 ++\n drivers/net/ice/base/ice_osdep.h | 524 +++++++++++++++++++++++++++++++++++++++\n 2 files changed, 546 insertions(+)\n create mode 100644 drivers/net/ice/base/README\n create mode 100644 drivers/net/ice/base/ice_osdep.h", "diff": "diff --git a/drivers/net/ice/base/README b/drivers/net/ice/base/README\nnew file mode 100644\nindex 0000000..708f607\n--- /dev/null\n+++ b/drivers/net/ice/base/README\n@@ -0,0 +1,22 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n+ */\n+\n+Intel® ICE driver\n+==================\n+\n+This directory contains source code of FreeBSD ice driver of version\n+2018.12.11 released by the team which develops\n+basic drivers for any ice NIC. The directory of base/ contains the\n+original source package.\n+This driver is valid for the product(s) listed below\n+\n+* Intel® Ethernet Network Adapters E810\n+\n+Updating the driver\n+===================\n+\n+NOTE: The source code in this directory should not be modified apart from\n+the following file(s):\n+\n+ ice_osdep.h\ndiff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h\nnew file mode 100644\nindex 0000000..dd25b75\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_osdep.h\n@@ -0,0 +1,524 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n+ */\n+\n+#ifndef _ICE_OSDEP_H_\n+#define _ICE_OSDEP_H_\n+\n+#include <string.h>\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <stdarg.h>\n+#include <inttypes.h>\n+#include <sys/queue.h>\n+#include <stdbool.h>\n+\n+#include <rte_common.h>\n+#include <rte_memcpy.h>\n+#include <rte_malloc.h>\n+#include <rte_memzone.h>\n+#include <rte_byteorder.h>\n+#include <rte_cycles.h>\n+#include <rte_spinlock.h>\n+#include <rte_log.h>\n+#include <rte_random.h>\n+#include <rte_io.h>\n+\n+#include \"../ice_logs.h\"\n+\n+#define INLINE inline\n+#define STATIC static\n+\n+typedef uint8_t u8;\n+typedef int8_t s8;\n+typedef uint16_t u16;\n+typedef int16_t s16;\n+typedef uint32_t u32;\n+typedef int32_t s32;\n+typedef uint64_t u64;\n+typedef uint64_t s64;\n+\n+#define __iomem\n+#define hw_dbg(hw, S, A...) do {} while (0)\n+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))\n+#define lower_32_bits(n) ((u32)(n))\n+#define low_16_bits(x) ((x) & 0xFFFF)\n+#define high_16_bits(x) (((x) & 0xFFFF0000) >> 16)\n+\n+#ifndef ETH_ADDR_LEN\n+#define ETH_ADDR_LEN 6\n+#endif\n+\n+#ifndef __le16\n+#define __le16 uint16_t\n+#endif\n+#ifndef __le32\n+#define __le32 uint32_t\n+#endif\n+#ifndef __le64\n+#define __le64 uint64_t\n+#endif\n+#ifndef __be16\n+#define __be16 uint16_t\n+#endif\n+#ifndef __be32\n+#define __be32 uint32_t\n+#endif\n+#ifndef __be64\n+#define __be64 uint64_t\n+#endif\n+\n+#ifndef __always_unused\n+#define __always_unused __attribute__((unused))\n+#endif\n+#ifndef __maybe_unused\n+#define __maybe_unused __attribute__((unused))\n+#endif\n+#ifndef __packed\n+#define __packed __attribute__((packed))\n+#endif\n+\n+#ifndef BIT_ULL\n+#define BIT_ULL(a) (1ULL << (a))\n+#endif\n+\n+#define FALSE 0\n+#define TRUE 1\n+#define false 0\n+#define true 1\n+\n+#define min(a, b) RTE_MIN(a, b)\n+#define max(a, b) RTE_MAX(a, b)\n+\n+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0]))\n+#define FIELD_SIZEOF(t, f) (sizeof(((t *)0)->f))\n+#define MAKEMASK(m, s) ((m) << (s))\n+\n+#define DEBUGOUT(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A)\n+#define DEBUGFUNC(F) PMD_DRV_LOG_RAW(DEBUG, F)\n+\n+#define ice_debug(h, m, s, ...)\t\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\\\n+\tif (((m) & (h)->debug_mask))\t\t\t\t\\\n+\t\tPMD_DRV_LOG_RAW(DEBUG, \"ice %02x.%x \" s,\t\\\n+\t\t\t(h)->bus.device, (h)->bus.func,\t\t\\\n+\t\t\t\t\t##__VA_ARGS__);\t\t\\\n+} while (0)\n+\n+#define ice_info(hw, fmt, args...) ice_debug(hw, ICE_DBG_ALL, fmt, ##args)\n+#define ice_warn(hw, fmt, args...) ice_debug(hw, ICE_DBG_ALL, fmt, ##args)\n+#define ice_debug_array(hw, type, rowsize, groupsize, buf, len)\t\t\\\n+do {\t\t\t\t\t\t\t\t\t\\\n+\tstruct ice_hw *hw_l = hw;\t\t\t\t\t\\\n+\t\tu16 len_l = len;\t\t\t\t\t\\\n+\t\tu8 *buf_l = buf;\t\t\t\t\t\\\n+\t\tint i;\t\t\t\t\t\t\t\\\n+\t\tfor (i = 0; i < len_l; i += 8)\t\t\t\t\\\n+\t\t\tice_debug(hw_l, type,\t\t\t\t\\\n+\t\t\t\t \"0x%04X 0x%016\"PRIx64\"\\n\",\t\t\\\n+\t\t\t\t i, *((u64 *)((buf_l) + i)));\t\t\\\n+} while (0)\n+#define ice_snprintf snprintf\n+#ifndef SNPRINTF\n+#define SNPRINTF ice_snprintf\n+#endif\n+\n+#define ICE_PCI_REG(reg) rte_read32(reg)\n+#define ICE_PCI_REG_ADDR(a, reg) \\\n+\t((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))\n+static inline uint32_t ice_read_addr(volatile void *addr)\n+{\n+\treturn rte_le_to_cpu_32(ICE_PCI_REG(addr));\n+}\n+\n+#define ICE_PCI_REG_WRITE(reg, value) \\\n+\trte_write32((rte_cpu_to_le_32(value)), reg)\n+\n+#define ice_flush(a) ICE_READ_REG((a), GLGEN_STAT)\n+#define icevf_flush(a) ICE_READ_REG((a), VFGEN_RSTAT)\n+#define ICE_READ_REG(hw, reg) ice_read_addr(ICE_PCI_REG_ADDR((hw), (reg)))\n+#define ICE_WRITE_REG(hw, reg, value) \\\n+\tICE_PCI_REG_WRITE(ICE_PCI_REG_ADDR((hw), (reg)), (value))\n+\n+#define rd32(a, reg) ice_read_addr(ICE_PCI_REG_ADDR((a), (reg)))\n+#define wr32(a, reg, value) \\\n+\tICE_PCI_REG_WRITE(ICE_PCI_REG_ADDR((a), (reg)), (value))\n+#define flush(a) ice_read_addr(ICE_PCI_REG_ADDR((a), (GLGEN_STAT)))\n+#define div64_long(n, d) ((n) / (d))\n+\n+#define BITS_PER_BYTE 8\n+typedef u32 ice_bitmap_t;\n+#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n+#define BITS_TO_CHUNKS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(ice_bitmap_t))\n+#define ice_declare_bitmap(name, bits) \\\n+\tice_bitmap_t name[BITS_TO_CHUNKS(bits)]\n+\n+#define BITS_CHUNK_MASK(nr)\t(((ice_bitmap_t)~0) >>\t\t\t\\\n+\t\t((BITS_PER_BYTE * sizeof(ice_bitmap_t)) -\t\t\\\n+\t\t(((nr) - 1) % (BITS_PER_BYTE * sizeof(ice_bitmap_t))\t\\\n+\t\t + 1)))\n+#define BITS_PER_CHUNK (BITS_PER_BYTE * sizeof(ice_bitmap_t))\n+#define BIT_CHUNK(nr) ((nr) / BITS_PER_CHUNK)\n+#define BIT_IN_CHUNK(nr) BIT((nr) % BITS_PER_CHUNK)\n+\n+static inline bool ice_is_bit_set(const ice_bitmap_t *bitmap, u16 nr)\n+{\n+ return !!(bitmap[BIT_CHUNK(nr)] & BIT_IN_CHUNK(nr));\n+}\n+\n+#define ice_and_bitmap(d, b1, b2, sz) \\\n+\tice_intersect_bitmaps((u8 *)d, (u8 *)b1, (const u8 *)b2, (u16)sz)\n+static inline int\n+ice_intersect_bitmaps(u8 *dst, const u8 *bmp1, const u8 *bmp2, u16 sz)\n+{\n+\tu32 res = 0;\n+\tint cnt;\n+\tu16 i;\n+\n+\t/* Utilize 32-bit operations */\n+\tcnt = (sz % BITS_PER_BYTE) ?\n+\t\t(sz / BITS_PER_BYTE) + 1 : sz / BITS_PER_BYTE;\n+\tfor (i = 0; i < cnt / 4; i++) {\n+\t\t((u32 *)dst)[i] = ((const u32 *)bmp1)[i] &\n+\t\t((const u32 *)bmp2)[i];\n+\t\tres |= ((u32 *)dst)[i];\n+\t}\n+\n+\tfor (i *= 4; i < cnt; i++) {\n+\t\tif ((sz % 8 == 0) || (i + 1 < cnt)) {\n+\t\t\tdst[i] = bmp1[i] & bmp2[i];\n+\t\t} else {\n+\t\t\t/* Remaining bits that do not occupy the whole byte */\n+\t\t\tu8 mask = ~0u >> (8 - (sz % 8));\n+\n+\t\t\tdst[i] = bmp1[i] & bmp2[i] & mask;\n+\t\t}\n+\n+\t\tres |= dst[i];\n+\t}\n+\n+\treturn res != 0;\n+}\n+\n+static inline int ice_find_first_bit(ice_bitmap_t *name, u16 size)\n+{\n+\tu16 i;\n+\n+\tfor (i = 0; i < BITS_PER_BYTE * (size / BITS_PER_BYTE); i++)\n+\t\tif (ice_is_bit_set(name, i))\n+\t\t\treturn i;\n+\treturn size;\n+}\n+\n+static inline int ice_find_next_bit(ice_bitmap_t *name, u16 size, u16 bits)\n+{\n+\tu16 i;\n+\n+\tfor (i = bits; i < BITS_PER_BYTE * (size / BITS_PER_BYTE); i++)\n+\t\tif (ice_is_bit_set(name, i))\n+\t\t\treturn i;\n+\treturn bits;\n+}\n+\n+#define for_each_set_bit(bit, addr, size)\t\t\t\t\\\n+\tfor ((bit) = ice_find_first_bit((addr), (size));\t\t\\\n+\t(bit) < (size);\t\t\t\t\t\t\t\\\n+\t(bit) = ice_find_next_bit((addr), (size), (bit) + 1))\n+\n+static inline bool ice_is_any_bit_set(ice_bitmap_t *bitmap, u32 bits)\n+{\n+\tu32 max_index = BITS_TO_CHUNKS(bits);\n+\tu32 i;\n+\n+\tfor (i = 0; i < max_index; i++) {\n+\t\tif (bitmap[i])\n+\t\t\treturn true;\n+\t}\n+\treturn false;\n+}\n+\n+/* memory allocation tracking */\n+struct ice_dma_mem {\n+\tvoid *va;\n+\tu64 pa;\n+\tu32 size;\n+\tconst void *zone;\n+} __attribute__((packed));\n+\n+struct ice_virt_mem {\n+\tvoid *va;\n+\tu32 size;\n+} __attribute__((packed));\n+\n+#define ice_malloc(h, s) rte_zmalloc(NULL, s, 0)\n+#define ice_calloc(h, c, s) rte_zmalloc(NULL, c * s, 0)\n+#define ice_free(h, m) rte_free(m)\n+\n+#define ice_memset(a, b, c, d) memset((a), (b), (c))\n+#define ice_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))\n+#define ice_memdup(a, b, c, d) rte_memcpy(ice_malloc(a, c), b, c)\n+\n+#define CPU_TO_BE16(o) rte_cpu_to_be_16(o)\n+#define CPU_TO_BE32(o) rte_cpu_to_be_32(o)\n+#define CPU_TO_BE64(o) rte_cpu_to_be_64(o)\n+#define CPU_TO_LE16(o) rte_cpu_to_le_16(o)\n+#define CPU_TO_LE32(s) rte_cpu_to_le_32(s)\n+#define CPU_TO_LE64(h) rte_cpu_to_le_64(h)\n+#define LE16_TO_CPU(a) rte_le_to_cpu_16(a)\n+#define LE32_TO_CPU(c) rte_le_to_cpu_32(c)\n+#define LE64_TO_CPU(k) rte_le_to_cpu_64(k)\n+\n+#define NTOHS(a) rte_be_to_cpu_16(a)\n+#define NTOHL(a) rte_be_to_cpu_32(a)\n+#define HTONS(a) rte_cpu_to_be_16(a)\n+#define HTONL(a) rte_cpu_to_be_32(a)\n+\n+static inline void\n+ice_set_bit(unsigned int nr, volatile ice_bitmap_t *addr)\n+{\n+\t__sync_fetch_and_or(addr, (1UL << nr));\n+}\n+\n+static inline void\n+ice_clear_bit(unsigned int nr, volatile ice_bitmap_t *addr)\n+{\n+\t__sync_fetch_and_and(addr, (0UL << nr));\n+}\n+\n+static inline void\n+ice_zero_bitmap(ice_bitmap_t *bmp, u16 size)\n+{\n+\tunsigned long mask;\n+\tu16 i;\n+\n+\tfor (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)\n+\t\tbmp[i] = 0;\n+\tmask = BITS_CHUNK_MASK(size);\n+\tbmp[i] &= ~mask;\n+}\n+\n+static inline void\n+ice_or_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,\n+\t const ice_bitmap_t *bmp2, u16 size)\n+{\n+\tunsigned long mask;\n+\tu16 i;\n+\n+\t/* Handle all but last chunk*/\n+\tfor (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)\n+\t\tdst[i] = bmp1[i] | bmp2[i];\n+\n+\t/* We want to only OR bits within the size. Furthermore, we also do\n+\t * not want to modify destination bits which are beyond the specified\n+\t * size. Use a bitmask to ensure that we only modify the bits that are\n+\t * within the specified size.\n+\t */\n+\tmask = BITS_CHUNK_MASK(size);\n+\tdst[i] &= ~mask;\n+\tdst[i] |= (bmp1[i] | bmp2[i]) & mask;\n+}\n+\n+static inline void ice_cp_bitmap(ice_bitmap_t *dst, ice_bitmap_t *src, u16 size)\n+{\n+ ice_bitmap_t mask;\n+ u16 i;\n+\n+ /* Handle all but last chunk*/\n+ for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)\n+ dst[i] = src[i];\n+\n+ /* We want to only copy bits within the size.*/\n+ mask = BITS_CHUNK_MASK(size);\n+ dst[i] &= ~mask;\n+ dst[i] |= src[i] & mask;\n+}\n+\n+static inline bool\n+ice_cmp_bitmap(ice_bitmap_t *bmp1, ice_bitmap_t *bmp2, u16 size)\n+{\n+ ice_bitmap_t mask;\n+ u16 i;\n+\n+ /* Handle all but last chunk*/\n+ for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)\n+ if (bmp1[i] != bmp2[i])\n+ return false;\n+\n+ /* We want to only compare bits within the size.*/\n+ mask = BITS_CHUNK_MASK(size);\n+ if ((bmp1[i] & mask) != (bmp2[i] & mask))\n+ return false;\n+\n+ return true;\n+}\n+\n+/* SW spinlock */\n+struct ice_lock {\n+\trte_spinlock_t spinlock;\n+};\n+\n+static inline void\n+ice_init_lock(struct ice_lock *sp)\n+{\n+\trte_spinlock_init(&sp->spinlock);\n+}\n+\n+static inline void\n+ice_acquire_lock(struct ice_lock *sp)\n+{\n+\trte_spinlock_lock(&sp->spinlock);\n+}\n+\n+static inline void\n+ice_release_lock(struct ice_lock *sp)\n+{\n+\trte_spinlock_unlock(&sp->spinlock);\n+}\n+\n+static inline void\n+ice_destroy_lock(__attribute__((unused)) struct ice_lock *sp)\n+{\n+}\n+\n+struct ice_hw;\n+\n+static inline void *\n+ice_alloc_dma_mem(__attribute__((unused)) struct ice_hw *hw,\n+\t\t struct ice_dma_mem *mem, u64 size)\n+{\n+\tconst struct rte_memzone *mz = NULL;\n+\tchar z_name[RTE_MEMZONE_NAMESIZE];\n+\n+\tif (!mem)\n+\t\treturn NULL;\n+\n+\tsnprintf(z_name, sizeof(z_name), \"ice_dma_%\"PRIu64, rte_rand());\n+\tmz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,\n+\t\t\t\t\t 0, RTE_PGSIZE_2M);\n+\tif (!mz)\n+\t\treturn NULL;\n+\n+\tmem->size = size;\n+\tmem->va = mz->addr;\n+\tmem->pa = mz->phys_addr;\n+\tmem->zone = (const void *)mz;\n+\tPMD_DRV_LOG(DEBUG, \"memzone %s allocated with physical address: \"\n+\t\t \"%\"PRIu64, mz->name, mem->pa);\n+\n+\treturn mem->va;\n+}\n+\n+static inline void\n+ice_free_dma_mem(__attribute__((unused)) struct ice_hw *hw,\n+\t\t struct ice_dma_mem *mem)\n+{\n+\tPMD_DRV_LOG(DEBUG, \"memzone %s to be freed with physical address: \"\n+\t\t \"%\"PRIu64, ((const struct rte_memzone *)mem->zone)->name,\n+\t\t mem->pa);\n+\trte_memzone_free((const struct rte_memzone *)mem->zone);\n+\tmem->zone = NULL;\n+\tmem->va = NULL;\n+\tmem->pa = (u64)0;\n+}\n+\n+static inline u8\n+ice_hweight8(u32 num)\n+{\n+\tu8 bits = 0;\n+\tu32 i;\n+\n+\tfor (i = 0; i < 8; i++) {\n+\t\tbits += (u8)(num & 0x1);\n+\t\tnum >>= 1;\n+\t}\n+\n+\treturn bits;\n+}\n+\n+#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n+#define DELAY(x) rte_delay_us(x)\n+#define ice_usec_delay(x) rte_delay_us(x)\n+#define ice_msec_delay(x, y) rte_delay_us(1000 * (x))\n+#define udelay(x) DELAY(x)\n+#define msleep(x) DELAY(1000 * (x))\n+#define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))\n+\n+struct ice_list_entry {\n+\tLIST_ENTRY(ice_list_entry) next;\n+};\n+\n+LIST_HEAD(ice_list_head, ice_list_entry);\n+\n+#define LIST_ENTRY_TYPE ice_list_entry\n+#define LIST_HEAD_TYPE ice_list_head\n+#define INIT_LIST_HEAD(list_head) LIST_INIT(list_head)\n+#define LIST_DEL(entry) LIST_REMOVE(entry, next)\n+/* LIST_EMPTY(list_head)) the same in sys/queue.h */\n+\n+/*Note parameters are swapped*/\n+#define LIST_FIRST_ENTRY(head, type, field) (type *)((head)->lh_first)\n+#define LIST_ADD(entry, list_head) LIST_INSERT_HEAD(list_head, entry, next)\n+#define LIST_ADD_AFTER(entry, list_entry) \\\n+\tLIST_INSERT_AFTER(list_entry, entry, next)\n+#define LIST_FOR_EACH_ENTRY(pos, head, type, member)\t\t\t \\\n+\tfor ((pos) = (head)->lh_first ?\t\t\t\t\t \\\n+\t\t container_of((head)->lh_first, struct type, member) : \\\n+\t\t 0;\t\t\t\t\t\t\t \\\n+\t (pos);\t\t\t\t\t\t\t \\\n+\t (pos) = (pos)->member.next.le_next ?\t\t\t \\\n+\t\t container_of((pos)->member.next.le_next, struct type, \\\n+\t\t\t\t member) :\t\t\t\t \\\n+\t\t 0)\n+\n+#define LIST_REPLACE_INIT(list_head, head) do {\t\t\t\t\\\n+\t(head)->lh_first = (list_head)->lh_first;\t\t\t\\\n+\tINIT_LIST_HEAD(list_head);\t\t\t\t\t\\\n+} while (0)\n+\n+#define HLIST_NODE_TYPE LIST_ENTRY_TYPE\n+#define HLIST_HEAD_TYPE LIST_HEAD_TYPE\n+#define INIT_HLIST_HEAD(list_head) INIT_LIST_HEAD(list_head)\n+#define HLIST_ADD_HEAD(entry, list_head) LIST_ADD(entry, list_head)\n+#define HLIST_EMPTY(list_head) LIST_EMPTY(list_head)\n+#define HLIST_DEL(entry) LIST_DEL(entry)\n+#define HLIST_FOR_EACH_ENTRY(pos, head, type, member) \\\n+\tLIST_FOR_EACH_ENTRY(pos, head, type, member)\n+#define LIST_FOR_EACH_ENTRY_SAFE(pos, tmp, head, type, member) \\\n+\tLIST_FOR_EACH_ENTRY(pos, head, type, member)\n+\n+#ifndef ICE_DBG_TRACE\n+#define ICE_DBG_TRACE\t\tBIT_ULL(0)\n+#endif\n+\n+#ifndef DIVIDE_AND_ROUND_UP\n+#define DIVIDE_AND_ROUND_UP(a, b) (((a) + (b) - 1) / (b))\n+#endif\n+\n+#ifndef ICE_INTEL_VENDOR_ID\n+#define ICE_INTEL_VENDOR_ID\t\t0x8086\n+#endif\n+\n+#ifndef IS_UNICAST_ETHER_ADDR\n+#define IS_UNICAST_ETHER_ADDR(addr) \\\n+\t((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0))\n+#endif\n+\n+#ifndef IS_MULTICAST_ETHER_ADDR\n+#define IS_MULTICAST_ETHER_ADDR(addr) \\\n+\t((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1))\n+#endif\n+\n+#ifndef IS_BROADCAST_ETHER_ADDR\n+/* Check whether an address is broadcast. */\n+#define IS_BROADCAST_ETHER_ADDR(addr)\t\\\n+\t((bool)((((u16 *)(addr))[0] == ((u16)0xffff))))\n+#endif\n+\n+#ifndef IS_ZERO_ETHER_ADDR\n+#define IS_ZERO_ETHER_ADDR(addr) \\\n+\t(((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \\\n+\t ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \\\n+\t ((bool)((((u16 *)(addr))[2] == ((u16)0x0)))))\n+#endif\n+\n+#endif /* _ICE_OSDEP_H_ */\n", "prefixes": [ "v5", "14/31" ] }