Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 48981,
    "url": "https://patches.dpdk.org/api/patches/48981/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-14-git-send-email-wenzhuo.lu@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1545032259-77179-14-git-send-email-wenzhuo.lu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1545032259-77179-14-git-send-email-wenzhuo.lu@intel.com",
    "date": "2018-12-17T07:37:21",
    "name": "[v5,13/31] net/ice/base: add structures for RX/TX queues",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "84625b085297aea7fb0c6ba9a1db4d7e678a5e45",
    "submitter": {
        "id": 258,
        "url": "https://patches.dpdk.org/api/people/258/?format=api",
        "name": "Wenzhuo Lu",
        "email": "wenzhuo.lu@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "https://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-14-git-send-email-wenzhuo.lu@intel.com/mbox/",
    "series": [
        {
            "id": 2824,
            "url": "https://patches.dpdk.org/api/series/2824/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2824",
            "date": "2018-12-17T07:37:08",
            "name": "A new net PMD - ICE",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/2824/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/48981/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/48981/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 24EB01B8B6;\n\tMon, 17 Dec 2018 08:33:21 +0100 (CET)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 0CD181B5FE\n\tfor <dev@dpdk.org>; Mon, 17 Dec 2018 08:33:10 +0100 (CET)",
            "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Dec 2018 23:33:09 -0800",
            "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby orsmga002.jf.intel.com with ESMTP; 16 Dec 2018 23:33:08 -0800"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.56,364,1539673200\"; d=\"scan'208\";a=\"118899219\"",
        "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>",
        "Date": "Mon, 17 Dec 2018 15:37:21 +0800",
        "Message-Id": "<1545032259-77179-14-git-send-email-wenzhuo.lu@intel.com>",
        "X-Mailer": "git-send-email 1.9.3",
        "In-Reply-To": "<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>",
        "References": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v5 13/31] net/ice/base: add structures for RX/TX\n\tqueues",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n\nAdd the structures that define how the RX/TX queues\nare used.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n---\n drivers/net/ice/base/ice_lan_tx_rx.h | 2291 ++++++++++++++++++++++++++++++++++\n 1 file changed, 2291 insertions(+)\n create mode 100644 drivers/net/ice/base/ice_lan_tx_rx.h",
    "diff": "diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h\nnew file mode 100644\nindex 0000000..d27045f\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_lan_tx_rx.h\n@@ -0,0 +1,2291 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_LAN_TX_RX_H_\n+#define _ICE_LAN_TX_RX_H_\n+#include \"ice_osdep.h\"\n+\n+/* RX Descriptors */\n+union ice_16byte_rx_desc {\n+\tstruct {\n+\t\t__le64 pkt_addr; /* Packet buffer address */\n+\t\t__le64 hdr_addr; /* Header buffer address */\n+\t} read;\n+\tstruct {\n+\t\tstruct {\n+\t\t\tstruct {\n+\t\t\t\t__le16 mirroring_status;\n+\t\t\t\t__le16 l2tag1;\n+\t\t\t} lo_dword;\n+\t\t\tunion {\n+\t\t\t\t__le32 rss; /* RSS Hash */\n+\t\t\t\t__le32 fd_id; /* Flow Director filter id */\n+\t\t\t} hi_dword;\n+\t\t} qword0;\n+\t\tstruct {\n+\t\t\t/* ext status/error/PTYPE/length */\n+\t\t\t__le64 status_error_len;\n+\t\t} qword1;\n+\t} wb;  /* writeback */\n+};\n+\n+union ice_32byte_rx_desc {\n+\tstruct {\n+\t\t__le64 pkt_addr; /* Packet buffer address */\n+\t\t__le64 hdr_addr; /* Header buffer address */\n+\t\t\t/* bit 0 of hdr_addr is DD bit */\n+\t\t__le64 rsvd1;\n+\t\t__le64 rsvd2;\n+\t} read;\n+\tstruct {\n+\t\tstruct {\n+\t\t\tstruct {\n+\t\t\t\t__le16 mirroring_status;\n+\t\t\t\t__le16 l2tag1;\n+\t\t\t} lo_dword;\n+\t\t\tunion {\n+\t\t\t\t__le32 rss; /* RSS Hash */\n+\t\t\t\t__le32 fd_id; /* Flow Director filter id */\n+\t\t\t} hi_dword;\n+\t\t} qword0;\n+\t\tstruct {\n+\t\t\t/* status/error/PTYPE/length */\n+\t\t\t__le64 status_error_len;\n+\t\t} qword1;\n+\t\tstruct {\n+\t\t\t__le16 ext_status; /* extended status */\n+\t\t\t__le16 rsvd;\n+\t\t\t__le16 l2tag2_1;\n+\t\t\t__le16 l2tag2_2;\n+\t\t} qword2;\n+\t\tstruct {\n+\t\t\t__le32 reserved;\n+\t\t\t__le32 fd_id;\n+\t\t} qword3;\n+\t} wb; /* writeback */\n+};\n+\n+struct ice_fltr_desc {\n+\t__le64 qidx_compq_space_stat;\n+\t__le64 dtype_cmd_vsi_fdid;\n+};\n+\n+#define ICE_FXD_FLTR_QW0_QINDEX_S\t0\n+#define ICE_FXD_FLTR_QW0_QINDEX_M\t(0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S)\n+#define ICE_FXD_FLTR_QW0_COMP_Q_S\t11\n+#define ICE_FXD_FLTR_QW0_COMP_Q_M\tBIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S)\n+#define ICE_FXD_FLTR_QW0_COMP_Q_ZERO\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_COMP_Q_QINDX\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW0_COMP_REPORT_S\t12\n+#define ICE_FXD_FLTR_QW0_COMP_REPORT_M\t\\\n+\t\t\t\t(0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S)\n+#define ICE_FXD_FLTR_QW0_COMP_REPORT_NONE\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL\t0x1ULL\n+#define ICE_FXD_FLTR_QW0_COMP_REPORT_SW\t\t0x2ULL\n+\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_S\t14\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_M\t(0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S)\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR\t\t\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_BEST_EFFORT\t\t0x1ULL\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST\t\t0x2ULL\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_BEST_GUAR\t\t0x3ULL\n+\n+#define ICE_FXD_FLTR_QW0_STAT_CNT_S\t16\n+#define ICE_FXD_FLTR_QW0_STAT_CNT_M\t\\\n+\t\t\t\t(0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S)\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_S\t29\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_M\t(0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S)\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_NONE\t\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS\t\t0x1ULL\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_BYTES\t\t0x2ULL\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS_BYTES\t0x3ULL\n+\n+#define ICE_FXD_FLTR_QW0_EVICT_ENA_S\t31\n+#define ICE_FXD_FLTR_QW0_EVICT_ENA_M\tBIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S)\n+#define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE\t\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW0_TO_Q_S\t\t32\n+#define ICE_FXD_FLTR_QW0_TO_Q_M\t\t(0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S)\n+#define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW0_TO_Q_PRI_S\t35\n+#define ICE_FXD_FLTR_QW0_TO_Q_PRI_M\t(0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S)\n+#define ICE_FXD_FLTR_QW0_TO_Q_PRIO1\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW0_DPU_RECIPE_S\t38\n+#define ICE_FXD_FLTR_QW0_DPU_RECIPE_M\t\\\n+\t\t\t(0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S)\n+#define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW0_DROP_S\t\t40\n+#define ICE_FXD_FLTR_QW0_DROP_M\t\tBIT_ULL(ICE_FXD_FLTR_QW0_DROP_S)\n+#define ICE_FXD_FLTR_QW0_DROP_NO\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_DROP_YES\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW0_FLEX_PRI_S\t41\n+#define ICE_FXD_FLTR_QW0_FLEX_PRI_M\t(0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S)\n+#define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW0_FLEX_MDID_S\t44\n+#define ICE_FXD_FLTR_QW0_FLEX_MDID_M\t(0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S)\n+#define ICE_FXD_FLTR_QW0_FLEX_MDID0\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW0_FLEX_VAL_S\t48\n+#define ICE_FXD_FLTR_QW0_FLEX_VAL_M\t\\\n+\t\t\t\t(0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S)\n+#define ICE_FXD_FLTR_QW0_FLEX_VAL0\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW1_DTYPE_S\t0\n+#define ICE_FXD_FLTR_QW1_DTYPE_M\t(0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S)\n+#define ICE_FXD_FLTR_QW1_PCMD_S\t\t4\n+#define ICE_FXD_FLTR_QW1_PCMD_M\t\tBIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S)\n+#define ICE_FXD_FLTR_QW1_PCMD_ADD\t0x0ULL\n+#define ICE_FXD_FLTR_QW1_PCMD_REMOVE\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW1_PROF_PRI_S\t5\n+#define ICE_FXD_FLTR_QW1_PROF_PRI_M\t(0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S)\n+#define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW1_PROF_S\t\t8\n+#define ICE_FXD_FLTR_QW1_PROF_M\t\t(0x3FULL << ICE_FXD_FLTR_QW1_PROF_S)\n+#define ICE_FXD_FLTR_QW1_PROF_ZERO\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW1_FD_VSI_S\t14\n+#define ICE_FXD_FLTR_QW1_FD_VSI_M\t(0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S)\n+#define ICE_FXD_FLTR_QW1_SWAP_S\t\t24\n+#define ICE_FXD_FLTR_QW1_SWAP_M\t\tBIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S)\n+#define ICE_FXD_FLTR_QW1_SWAP_NOT_SET\t0x0ULL\n+#define ICE_FXD_FLTR_QW1_SWAP_SET\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW1_FDID_PRI_S\t25\n+#define ICE_FXD_FLTR_QW1_FDID_PRI_M\t(0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)\n+#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW1_FDID_MDID_S\t28\n+#define ICE_FXD_FLTR_QW1_FDID_MDID_M\t(0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S)\n+#define ICE_FXD_FLTR_QW1_FDID_MDID_FD\t0x05ULL\n+\n+#define ICE_FXD_FLTR_QW1_FDID_S\t\t32\n+#define ICE_FXD_FLTR_QW1_FDID_M\t\t\\\n+\t\t\t(0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)\n+#define ICE_FXD_FLTR_QW1_FDID_ZERO\t0x0ULL\n+\n+\n+enum ice_rx_desc_status_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_DESC_STATUS_DD_S\t\t\t= 0,\n+\tICE_RX_DESC_STATUS_EOF_S\t\t= 1,\n+\tICE_RX_DESC_STATUS_L2TAG1P_S\t\t= 2,\n+\tICE_RX_DESC_STATUS_L3L4P_S\t\t= 3,\n+\tICE_RX_DESC_STATUS_CRCP_S\t\t= 4,\n+\tICE_RX_DESC_STATUS_TSYNINDX_S\t\t= 5, /* 2 BITS */\n+\tICE_RX_DESC_STATUS_TSYNVALID_S\t\t= 7,\n+\tICE_RX_DESC_STATUS_EXT_UDP_0_S\t\t= 8,\n+\tICE_RX_DESC_STATUS_UMBCAST_S\t\t= 9, /* 2 BITS */\n+\tICE_RX_DESC_STATUS_FLM_S\t\t= 11,\n+\tICE_RX_DESC_STATUS_FLTSTAT_S\t\t= 12, /* 2 BITS */\n+\tICE_RX_DESC_STATUS_LPBK_S\t\t= 14,\n+\tICE_RX_DESC_STATUS_IPV6EXADD_S\t\t= 15,\n+\tICE_RX_DESC_STATUS_RESERVED2_S\t\t= 16, /* 2 BITS */\n+\tICE_RX_DESC_STATUS_INT_UDP_0_S\t\t= 18,\n+\tICE_RX_DESC_STATUS_LAST /* this entry must be last!!! */\n+};\n+\n+#define ICE_RXD_QW1_STATUS_S\t0\n+#define ICE_RXD_QW1_STATUS_M\t((BIT(ICE_RX_DESC_STATUS_LAST) - 1) << \\\n+\t\t\t\t ICE_RXD_QW1_STATUS_S)\n+\n+#define ICE_RXD_QW1_STATUS_TSYNINDX_S ICE_RX_DESC_STATUS_TSYNINDX_S\n+#define ICE_RXD_QW1_STATUS_TSYNINDX_M (0x3UL << ICE_RXD_QW1_STATUS_TSYNINDX_S)\n+\n+#define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S\n+#define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S)\n+\n+\n+enum ice_rx_desc_fltstat_values {\n+\tICE_RX_DESC_FLTSTAT_NO_DATA\t= 0,\n+\tICE_RX_DESC_FLTSTAT_RSV_FD_ID\t= 1, /* 16byte desc? FD_ID : RSV */\n+\tICE_RX_DESC_FLTSTAT_RSV\t\t= 2,\n+\tICE_RX_DESC_FLTSTAT_RSS_HASH\t= 3,\n+};\n+\n+\n+#define ICE_RXD_QW1_ERROR_S\t19\n+#define ICE_RXD_QW1_ERROR_M\t\t(0xFFUL << ICE_RXD_QW1_ERROR_S)\n+\n+enum ice_rx_desc_error_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_DESC_ERROR_RXE_S\t\t\t= 0,\n+\tICE_RX_DESC_ERROR_RECIPE_S\t\t= 1,\n+\tICE_RX_DESC_ERROR_HBO_S\t\t\t= 2,\n+\tICE_RX_DESC_ERROR_L3L4E_S\t\t= 3, /* 3 BITS */\n+\tICE_RX_DESC_ERROR_IPE_S\t\t\t= 3,\n+\tICE_RX_DESC_ERROR_L4E_S\t\t\t= 4,\n+\tICE_RX_DESC_ERROR_EIPE_S\t\t= 5,\n+\tICE_RX_DESC_ERROR_OVERSIZE_S\t\t= 6,\n+\tICE_RX_DESC_ERROR_PPRS_S\t\t= 7\n+};\n+\n+enum ice_rx_desc_error_l3l4e_masks {\n+\tICE_RX_DESC_ERROR_L3L4E_NONE\t\t= 0,\n+\tICE_RX_DESC_ERROR_L3L4E_PROT\t\t= 1,\n+};\n+\n+#define ICE_RXD_QW1_PTYPE_S\t30\n+#define ICE_RXD_QW1_PTYPE_M\t(0xFFULL << ICE_RXD_QW1_PTYPE_S)\n+\n+/* Packet type non-ip values */\n+enum ice_rx_l2_ptype {\n+\tICE_RX_PTYPE_L2_RESERVED\t= 0,\n+\tICE_RX_PTYPE_L2_MAC_PAY2\t= 1,\n+\tICE_RX_PTYPE_L2_FIP_PAY2\t= 3,\n+\tICE_RX_PTYPE_L2_OUI_PAY2\t= 4,\n+\tICE_RX_PTYPE_L2_MACCNTRL_PAY2\t= 5,\n+\tICE_RX_PTYPE_L2_LLDP_PAY2\t= 6,\n+\tICE_RX_PTYPE_L2_ECP_PAY2\t= 7,\n+\tICE_RX_PTYPE_L2_EVB_PAY2\t= 8,\n+\tICE_RX_PTYPE_L2_QCN_PAY2\t= 9,\n+\tICE_RX_PTYPE_L2_EAPOL_PAY2\t= 10,\n+\tICE_RX_PTYPE_L2_ARP\t\t= 11,\n+};\n+\n+struct ice_rx_ptype_decoded {\n+\tu32 ptype:10;\n+\tu32 known:1;\n+\tu32 outer_ip:1;\n+\tu32 outer_ip_ver:2;\n+\tu32 outer_frag:1;\n+\tu32 tunnel_type:3;\n+\tu32 tunnel_end_prot:2;\n+\tu32 tunnel_end_frag:1;\n+\tu32 inner_prot:4;\n+\tu32 payload_layer:3;\n+};\n+\n+enum ice_rx_ptype_outer_ip {\n+\tICE_RX_PTYPE_OUTER_L2\t= 0,\n+\tICE_RX_PTYPE_OUTER_IP\t= 1,\n+};\n+\n+enum ice_rx_ptype_outer_ip_ver {\n+\tICE_RX_PTYPE_OUTER_NONE\t= 0,\n+\tICE_RX_PTYPE_OUTER_IPV4\t= 1,\n+\tICE_RX_PTYPE_OUTER_IPV6\t= 2,\n+};\n+\n+enum ice_rx_ptype_outer_fragmented {\n+\tICE_RX_PTYPE_NOT_FRAG\t= 0,\n+\tICE_RX_PTYPE_FRAG\t= 1,\n+};\n+\n+enum ice_rx_ptype_tunnel_type {\n+\tICE_RX_PTYPE_TUNNEL_NONE\t\t= 0,\n+\tICE_RX_PTYPE_TUNNEL_IP_IP\t\t= 1,\n+\tICE_RX_PTYPE_TUNNEL_IP_GRENAT\t\t= 2,\n+\tICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC\t= 3,\n+\tICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN\t= 4,\n+};\n+\n+enum ice_rx_ptype_tunnel_end_prot {\n+\tICE_RX_PTYPE_TUNNEL_END_NONE\t= 0,\n+\tICE_RX_PTYPE_TUNNEL_END_IPV4\t= 1,\n+\tICE_RX_PTYPE_TUNNEL_END_IPV6\t= 2,\n+};\n+\n+enum ice_rx_ptype_inner_prot {\n+\tICE_RX_PTYPE_INNER_PROT_NONE\t\t= 0,\n+\tICE_RX_PTYPE_INNER_PROT_UDP\t\t= 1,\n+\tICE_RX_PTYPE_INNER_PROT_TCP\t\t= 2,\n+\tICE_RX_PTYPE_INNER_PROT_SCTP\t\t= 3,\n+\tICE_RX_PTYPE_INNER_PROT_ICMP\t\t= 4,\n+};\n+\n+enum ice_rx_ptype_payload_layer {\n+\tICE_RX_PTYPE_PAYLOAD_LAYER_NONE\t= 0,\n+\tICE_RX_PTYPE_PAYLOAD_LAYER_PAY2\t= 1,\n+\tICE_RX_PTYPE_PAYLOAD_LAYER_PAY3\t= 2,\n+\tICE_RX_PTYPE_PAYLOAD_LAYER_PAY4\t= 3,\n+};\n+\n+\n+#define ICE_RXD_QW1_LEN_PBUF_S\t38\n+#define ICE_RXD_QW1_LEN_PBUF_M\t(0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S)\n+\n+#define ICE_RXD_QW1_LEN_HBUF_S\t52\n+#define ICE_RXD_QW1_LEN_HBUF_M\t(0x7FFULL << ICE_RXD_QW1_LEN_HBUF_S)\n+\n+#define ICE_RXD_QW1_LEN_SPH_S\t63\n+#define ICE_RXD_QW1_LEN_SPH_M\tBIT_ULL(ICE_RXD_QW1_LEN_SPH_S)\n+\n+\n+enum ice_rx_desc_ext_status_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_DESC_EXT_STATUS_L2TAG2P_S\t= 0,\n+\tICE_RX_DESC_EXT_STATUS_L2TAG3P_S\t= 1,\n+\tICE_RX_DESC_EXT_STATUS_FLEXBL_S\t\t= 2, /* 2 BITS */\n+\tICE_RX_DESC_EXT_STATUS_FLEXBH_S\t\t= 4, /* 2 BITS */\n+\tICE_RX_DESC_EXT_STATUS_FDLONGB_S\t= 9,\n+\tICE_RX_DESC_EXT_STATUS_PELONGB_S\t= 11,\n+};\n+\n+\n+enum ice_rx_desc_pe_status_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_DESC_PE_STATUS_QPID_S\t\t= 0, /* 18 BITS */\n+\tICE_RX_DESC_PE_STATUS_L4PORT_S\t\t= 0, /* 16 BITS */\n+\tICE_RX_DESC_PE_STATUS_IPINDEX_S\t\t= 16, /* 8 BITS */\n+\tICE_RX_DESC_PE_STATUS_QPIDHIT_S\t\t= 24,\n+\tICE_RX_DESC_PE_STATUS_APBVTHIT_S\t= 25,\n+\tICE_RX_DESC_PE_STATUS_PORTV_S\t\t= 26,\n+\tICE_RX_DESC_PE_STATUS_URG_S\t\t= 27,\n+\tICE_RX_DESC_PE_STATUS_IPFRAG_S\t\t= 28,\n+\tICE_RX_DESC_PE_STATUS_IPOPT_S\t\t= 29\n+};\n+\n+#define ICE_RX_PROG_STATUS_DESC_LEN_S\t38\n+#define ICE_RX_PROG_STATUS_DESC_LEN\t0x2000000\n+\n+#define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S\t2\n+#define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M\t\\\n+\t\t\t(0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S)\n+\n+\n+#define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S\t19\n+#define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M\t\\\n+\t\t\t(0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S)\n+\n+enum ice_rx_prog_status_desc_status_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_PROG_STATUS_DESC_DD_S\t\t= 0,\n+\tICE_RX_PROG_STATUS_DESC_PROG_ID_S\t= 2 /* 3 BITS */\n+};\n+\n+enum ice_rx_prog_status_desc_prog_id_masks {\n+\tICE_RX_PROG_STATUS_DESC_FD_FLTR_STATUS\t= 1,\n+};\n+\n+enum ice_rx_prog_status_desc_error_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_PROG_STATUS_DESC_FD_TBL_FULL_S\t= 0,\n+\tICE_RX_PROG_STATUS_DESC_NO_FD_ENTRY_S\t= 1,\n+};\n+\n+/* RX Flex Descriptor\n+ * This descriptor is used instead of the legacy version descriptor when\n+ * ice_rlan_ctx.adv_desc is set\n+ */\n+union ice_32b_rx_flex_desc {\n+\tstruct {\n+\t\t__le64 pkt_addr; /* Packet buffer address */\n+\t\t__le64 hdr_addr; /* Header buffer address */\n+\t\t\t\t /* bit 0 of hdr_addr is DD bit */\n+\t\t__le64 rsvd1;\n+\t\t__le64 rsvd2;\n+\t} read;\n+\tstruct {\n+\t\t/* Qword 0 */\n+\t\tu8 rxdid; /* descriptor builder profile id */\n+\t\tu8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */\n+\t\t__le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */\n+\t\t__le16 pkt_len; /* [15:14] are reserved */\n+\t\t__le16 hdr_len_sph_flex_flags1; /* header=[10:0] */\n+\t\t\t\t\t\t/* sph=[11:11] */\n+\t\t\t\t\t\t/* ff1/ext=[15:12] */\n+\n+\t\t/* Qword 1 */\n+\t\t__le16 status_error0;\n+\t\t__le16 l2tag1;\n+\t\t__le16 flex_meta0;\n+\t\t__le16 flex_meta1;\n+\n+\t\t/* Qword 2 */\n+\t\t__le16 status_error1;\n+\t\tu8 flex_flags2;\n+\t\tu8 time_stamp_low;\n+\t\t__le16 l2tag2_1st;\n+\t\t__le16 l2tag2_2nd;\n+\n+\t\t/* Qword 3 */\n+\t\t__le16 flex_meta2;\n+\t\t__le16 flex_meta3;\n+\t\tunion {\n+\t\t\tstruct {\n+\t\t\t\t__le16 flex_meta4;\n+\t\t\t\t__le16 flex_meta5;\n+\t\t\t} flex;\n+\t\t\t__le32 ts_high;\n+\t\t} flex_ts;\n+\t} wb; /* writeback */\n+};\n+\n+/* Rx Flex Descriptor NIC Profile\n+ * RxDID Profile Id 2\n+ * Flex-field 0: RSS hash lower 16-bits\n+ * Flex-field 1: RSS hash upper 16-bits\n+ * Flex-field 2: Flow Id lower 16-bits\n+ * Flex-field 3: Flow Id higher 16-bits\n+ * Flex-field 4: reserved, Vlan id taken from L2Tag\n+ */\n+struct ice_32b_rx_flex_desc_nic {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le32 rss_hash;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flexi_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le32 flow_id;\n+\tunion {\n+\t\tstruct {\n+\t\t\t__le16 rsvd;\n+\t\t\t__le16 flow_id_ipv6;\n+\t\t} flex;\n+\t\t__le32 ts_high;\n+\t} flex_ts;\n+};\n+\n+/* Rx Flex Descriptor Switch Profile\n+ * RxDID Profile Id 3\n+ * Flex-field 0: Source Vsi\n+ */\n+struct ice_32b_rx_flex_desc_sw {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le16 src_vsi; /* [10:15] are reserved */\n+\t__le16 flex_md1_rsvd;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flex_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le32 rsvd; /* flex words 2-3 are reserved */\n+\t__le32 ts_high;\n+};\n+\n+/* Rx Flex Descriptor NIC VEB Profile\n+ * RxDID Profile Id 4\n+ * Flex-field 0: Destination Vsi\n+ */\n+struct ice_32b_rx_flex_desc_nic_veb_dbg {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le16 dst_vsi; /* [0:12]: destination vsi */\n+\t\t\t/* 13: vsi valid bit */\n+\t\t\t/* [14:15] are reserved */\n+\t__le16 flex_field_1;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flex_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le32 rsvd; /* flex words 2-3 are reserved */\n+\t__le32 ts_high;\n+};\n+\n+/* Rx Flex Descriptor NIC ACL Profile\n+ * RxDID Profile Id 5\n+ * Flex-field 0: ACL Counter 0\n+ * Flex-field 1: ACL Counter 1\n+ * Flex-field 2: ACL Counter 2\n+ */\n+struct ice_32b_rx_flex_desc_nic_acl_dbg {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le16 acl_ctr0;\n+\t__le16 acl_ctr1;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flex_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le16 acl_ctr2;\n+\t__le16 rsvd; /* flex words 2-3 are reserved */\n+\t__le32 ts_high;\n+};\n+\n+/* Rx Flex Descriptor NIC Profile\n+ * RxDID Profile Id 6\n+ * Flex-field 0: RSS hash lower 16-bits\n+ * Flex-field 1: RSS hash upper 16-bits\n+ * Flex-field 2: Flow Id lower 16-bits\n+ * Flex-field 3: Source Vsi\n+ * Flex-field 4: reserved, Vlan id taken from L2Tag\n+ */\n+struct ice_32b_rx_flex_desc_nic_2 {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le32 rss_hash;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flexi_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le16 flow_id;\n+\t__le16 src_vsi;\n+\tunion {\n+\t\tstruct {\n+\t\t\t__le16 rsvd;\n+\t\t\t__le16 flow_id_ipv6;\n+\t\t} flex;\n+\t\t__le32 ts_high;\n+\t} flex_ts;\n+};\n+\n+/* Receive Flex Descriptor profile IDs: There are a total\n+ * of 64 profiles where profile IDs 0/1 are for legacy; and\n+ * profiles 2-63 are flex profiles that can be programmed\n+ * with a specific metadata (profile 7 reserved for HW)\n+ */\n+enum ice_rxdid {\n+\tICE_RXDID_LEGACY_0\t\t= 0,\n+\tICE_RXDID_LEGACY_1\t\t= 1,\n+\tICE_RXDID_FLEX_NIC\t\t= 2,\n+\tICE_RXDID_FLEX_NIC_2\t\t= 6,\n+\tICE_RXDID_HW\t\t\t= 7,\n+\tICE_RXDID_LAST\t\t\t= 63,\n+};\n+\n+/* Recceive Flex descriptor Dword Index */\n+enum ice_flex_word {\n+\tICE_RX_FLEX_DWORD_0 = 0,\n+\tICE_RX_FLEX_DWORD_1,\n+\tICE_RX_FLEX_DWORD_2,\n+\tICE_RX_FLEX_DWORD_3,\n+\tICE_RX_FLEX_DWORD_4,\n+\tICE_RX_FLEX_DWORD_5\n+};\n+\n+/* Receive Flex Descriptor Rx opcode values */\n+enum ice_flex_opcode {\n+\tICE_RX_OPC_DEBUG = 0,\n+\tICE_RX_OPC_MDID,\n+\tICE_RX_OPC_EXTRACT,\n+\tICE_RX_OPC_PROTID\n+};\n+\n+/* Receive Descriptor MDID values */\n+enum ice_flex_rx_mdid {\n+\tICE_RX_MDID_FLOW_ID_LOWER\t= 5,\n+\tICE_RX_MDID_FLOW_ID_HIGH,\n+\tICE_RX_MDID_DST_VSI\t\t= 13,\n+\tICE_RX_MDID_SRC_VSI\t\t= 19,\n+\tICE_RX_MDID_HASH_LOW\t\t= 56,\n+\tICE_RX_MDID_HASH_HIGH,\n+\tICE_RX_MDID_ACL_CTR0\t\t= ICE_RX_MDID_HASH_LOW,\n+\tICE_RX_MDID_ACL_CTR1\t\t= ICE_RX_MDID_HASH_HIGH,\n+\tICE_RX_MDID_ACL_CTR2\t\t= 59\n+};\n+\n+/* for ice_32byte_rx_flex_desc.mir_id_umb_cast member */\n+#define ICE_RX_FLEX_DESC_MIRROR_M\t(0x3F) /* 6-bits */\n+\n+/* Rx Flag64 packet flag bits */\n+enum ice_rx_flg64_bits {\n+\tICE_RXFLG_PKT_DSI\t= 0,\n+\tICE_RXFLG_EVLAN_x8100\t= 15,\n+\tICE_RXFLG_EVLAN_x9100,\n+\tICE_RXFLG_VLAN_x8100,\n+\tICE_RXFLG_TNL_MAC\t= 22,\n+\tICE_RXFLG_TNL_VLAN,\n+\tICE_RXFLG_PKT_FRG,\n+\tICE_RXFLG_FIN\t\t= 32,\n+\tICE_RXFLG_SYN,\n+\tICE_RXFLG_RST,\n+\tICE_RXFLG_TNL0\t\t= 38,\n+\tICE_RXFLG_TNL1,\n+\tICE_RXFLG_TNL2,\n+\tICE_RXFLG_UDP_GRE,\n+\tICE_RXFLG_RSVD\t\t= 63\n+};\n+\n+enum ice_rx_flex_desc_umb_cast_bits { /* field is 2 bits long */\n+\tICE_RX_FLEX_DESC_UMB_CAST_S = 6,\n+\tICE_RX_FLEX_DESC_UMB_CAST_LAST /* this entry must be last!!! */\n+};\n+\n+enum ice_umbcast_dest_addr_types {\n+\tICE_DEST_UNICAST = 0,\n+\tICE_DEST_MULTICAST,\n+\tICE_DEST_BROADCAST,\n+\tICE_DEST_MIRRORED,\n+};\n+\n+/* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */\n+#define ICE_RX_FLEX_DESC_PTYPE_M\t(0x3FF) /* 10-bits */\n+\n+enum ice_rx_flex_desc_flexi_flags0_bits { /* field is 6 bits long */\n+\tICE_RX_FLEX_DESC_FLEXI_FLAGS0_S = 10,\n+\tICE_RX_FLEX_DESC_FLEXI_FLAGS0_LAST /* this entry must be last!!! */\n+};\n+\n+/* for ice_32byte_rx_flex_desc.pkt_length member */\n+#define ICE_RX_FLX_DESC_PKT_LEN_M\t(0x3FFF) /* 14-bits */\n+\n+/* for ice_32byte_rx_flex_desc.header_length_sph_flexi_flags1 member */\n+#define ICE_RX_FLEX_DESC_HEADER_LEN_M\t(0x7FF) /* 11-bits */\n+\n+enum ice_rx_flex_desc_sph_bits { /* field is 1 bit long */\n+\tICE_RX_FLEX_DESC_SPH_S = 11,\n+\tICE_RX_FLEX_DESC_SPH_LAST /* this entry must be last!!! */\n+};\n+\n+enum ice_rx_flex_desc_flexi_flags1_bits { /* field is 4 bits long */\n+\tICE_RX_FLEX_DESC_FLEXI_FLAGS1_S = 12,\n+\tICE_RX_FLEX_DESC_FLEXI_FLAGS1_LAST /* this entry must be last!!! */\n+};\n+\n+enum ice_rx_flex_desc_ext_status_bits { /* field is 4 bits long */\n+\tICE_RX_FLEX_DESC_EXT_STATUS_EXT_UDP_S = 12,\n+\tICE_RX_FLEX_DESC_EXT_STATUS_INT_UDP_S = 13,\n+\tICE_RX_FLEX_DESC_EXT_STATUS_RECIPE_S = 14,\n+\tICE_RX_FLEX_DESC_EXT_STATUS_OVERSIZE_S = 15,\n+\tICE_RX_FLEX_DESC_EXT_STATUS_LAST /* entry must be last!!! */\n+};\n+\n+enum ice_rx_flex_desc_status_error_0_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_FLEX_DESC_STATUS0_DD_S = 0,\n+\tICE_RX_FLEX_DESC_STATUS0_EOF_S,\n+\tICE_RX_FLEX_DESC_STATUS0_HBO_S,\n+\tICE_RX_FLEX_DESC_STATUS0_L3L4P_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,\n+\tICE_RX_FLEX_DESC_STATUS0_LPBK_S,\n+\tICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,\n+\tICE_RX_FLEX_DESC_STATUS0_RXE_S,\n+\tICE_RX_FLEX_DESC_STATUS0_CRCP_S,\n+\tICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S,\n+\tICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,\n+\tICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */\n+};\n+\n+enum ice_rx_flex_desc_status_error_1_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_FLEX_DESC_STATUS1_CPM_S = 0, /* 4 bits */\n+\tICE_RX_FLEX_DESC_STATUS1_NAT_S = 4,\n+\tICE_RX_FLEX_DESC_STATUS1_CRYPTO_S = 5,\n+\t/* [10:6] reserved */\n+\tICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,\n+\tICE_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,\n+\tICE_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,\n+\tICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,\n+\tICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,\n+\tICE_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */\n+};\n+\n+enum ice_rx_flex_desc_exstat_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_FLEX_DESC_EXSTAT_EXTUDP_S = 0,\n+\tICE_RX_FLEX_DESC_EXSTAT_INTUDP_S = 1,\n+\tICE_RX_FLEX_DESC_EXSTAT_RECIPE_S = 2,\n+\tICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3,\n+};\n+\n+\n+#define ICE_RXQ_CTX_SIZE_DWORDS\t\t8\n+#define ICE_RXQ_CTX_SZ\t\t\t(ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))\n+#define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS\t22\n+#define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS\t5\n+#define GLTCLAN_CQ_CNTX(i, CQ)\t\t(GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))\n+\n+/* RLAN Rx queue context data\n+ *\n+ * The sizes of the variables may be larger than needed due to crossing byte\n+ * boundaries. If we do not have the width of the variable set to the correct\n+ * size then we could end up shifting bits off the top of the variable when the\n+ * variable is at the top of a byte and crosses over into the next byte.\n+ */\n+struct ice_rlan_ctx {\n+\tu16 head;\n+\tu16 cpuid; /* bigger than needed, see above for reason */\n+#define ICE_RLAN_BASE_S 7\n+\tu64 base;\n+\tu16 qlen;\n+#define ICE_RLAN_CTX_DBUF_S 7\n+\tu16 dbuf; /* bigger than needed, see above for reason */\n+#define ICE_RLAN_CTX_HBUF_S 6\n+\tu16 hbuf; /* bigger than needed, see above for reason */\n+\tu8 dtype;\n+\tu8 dsize;\n+\tu8 crcstrip;\n+\tu8 l2tsel;\n+\tu8 hsplit_0;\n+\tu8 hsplit_1;\n+\tu8 showiv;\n+\tu32 rxmax; /* bigger than needed, see above for reason */\n+\tu8 tphrdesc_ena;\n+\tu8 tphwdesc_ena;\n+\tu8 tphdata_ena;\n+\tu8 tphhead_ena;\n+\tu16 lrxqthresh; /* bigger than needed, see above for reason */\n+};\n+\n+struct ice_ctx_ele {\n+\tu16 offset;\n+\tu16 size_of;\n+\tu16 width;\n+\tu16 lsb;\n+};\n+\n+#define ICE_CTX_STORE(_struct, _ele, _width, _lsb) {\t\\\n+\t.offset = offsetof(struct _struct, _ele),\t\\\n+\t.size_of = FIELD_SIZEOF(struct _struct, _ele),\t\\\n+\t.width = _width,\t\t\t\t\\\n+\t.lsb = _lsb,\t\t\t\t\t\\\n+}\n+\n+/* for hsplit_0 field of Rx RLAN context */\n+enum ice_rlan_ctx_rx_hsplit_0 {\n+\tICE_RLAN_RX_HSPLIT_0_NO_SPLIT\t\t= 0,\n+\tICE_RLAN_RX_HSPLIT_0_SPLIT_L2\t\t= 1,\n+\tICE_RLAN_RX_HSPLIT_0_SPLIT_IP\t\t= 2,\n+\tICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP\t= 4,\n+\tICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP\t\t= 8,\n+};\n+\n+/* for hsplit_1 field of Rx RLAN context */\n+enum ice_rlan_ctx_rx_hsplit_1 {\n+\tICE_RLAN_RX_HSPLIT_1_NO_SPLIT\t\t= 0,\n+\tICE_RLAN_RX_HSPLIT_1_SPLIT_L2\t\t= 1,\n+\tICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS\t= 2,\n+};\n+\n+/* TX Descriptor */\n+struct ice_tx_desc {\n+\t__le64 buf_addr; /* Address of descriptor's data buf */\n+\t__le64 cmd_type_offset_bsz;\n+};\n+\n+#define ICE_TXD_QW1_DTYPE_S\t0\n+#define ICE_TXD_QW1_DTYPE_M\t(0xFUL << ICE_TXD_QW1_DTYPE_S)\n+\n+enum ice_tx_desc_dtype_value {\n+\tICE_TX_DESC_DTYPE_DATA\t\t= 0x0,\n+\tICE_TX_DESC_DTYPE_CTX\t\t= 0x1,\n+\tICE_TX_DESC_DTYPE_IPSEC\t\t= 0x3,\n+\tICE_TX_DESC_DTYPE_FLTR_PROG\t= 0x8,\n+\tICE_TX_DESC_DTYPE_HLP_META\t= 0x9,\n+\t/* DESC_DONE - HW has completed write-back of descriptor */\n+\tICE_TX_DESC_DTYPE_DESC_DONE\t= 0xF,\n+};\n+\n+#define ICE_TXD_QW1_CMD_S\t4\n+#define ICE_TXD_QW1_CMD_M\t(0xFFFUL << ICE_TXD_QW1_CMD_S)\n+\n+enum ice_tx_desc_cmd_bits {\n+\tICE_TX_DESC_CMD_EOP\t\t\t= 0x0001,\n+\tICE_TX_DESC_CMD_RS\t\t\t= 0x0002,\n+\tICE_TX_DESC_CMD_RSVD\t\t\t= 0x0004,\n+\tICE_TX_DESC_CMD_IL2TAG1\t\t\t= 0x0008,\n+\tICE_TX_DESC_CMD_DUMMY\t\t\t= 0x0010,\n+\tICE_TX_DESC_CMD_IIPT_NONIP\t\t= 0x0000, /* 2 BITS */\n+\tICE_TX_DESC_CMD_IIPT_IPV6\t\t= 0x0020, /* 2 BITS */\n+\tICE_TX_DESC_CMD_IIPT_IPV4\t\t= 0x0040, /* 2 BITS */\n+\tICE_TX_DESC_CMD_IIPT_IPV4_CSUM\t\t= 0x0060, /* 2 BITS */\n+\tICE_TX_DESC_CMD_RSVD2\t\t\t= 0x0080,\n+\tICE_TX_DESC_CMD_L4T_EOFT_UNK\t\t= 0x0000, /* 2 BITS */\n+\tICE_TX_DESC_CMD_L4T_EOFT_TCP\t\t= 0x0100, /* 2 BITS */\n+\tICE_TX_DESC_CMD_L4T_EOFT_SCTP\t\t= 0x0200, /* 2 BITS */\n+\tICE_TX_DESC_CMD_L4T_EOFT_UDP\t\t= 0x0300, /* 2 BITS */\n+\tICE_TX_DESC_CMD_RE\t\t\t= 0x0400,\n+\tICE_TX_DESC_CMD_RSVD3\t\t\t= 0x0800,\n+};\n+\n+#define ICE_TXD_QW1_OFFSET_S\t16\n+#define ICE_TXD_QW1_OFFSET_M\t(0x3FFFFULL << ICE_TXD_QW1_OFFSET_S)\n+\n+enum ice_tx_desc_len_fields {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_TX_DESC_LEN_MACLEN_S\t= 0, /* 7 BITS */\n+\tICE_TX_DESC_LEN_IPLEN_S\t= 7, /* 7 BITS */\n+\tICE_TX_DESC_LEN_L4_LEN_S\t= 14 /* 4 BITS */\n+};\n+\n+#define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S)\n+#define ICE_TXD_QW1_IPLEN_M  (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S)\n+#define ICE_TXD_QW1_L4LEN_M  (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S)\n+\n+/* Tx descriptor field limits in bytes */\n+#define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \\\n+\t\t\t     ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD)\n+#define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \\\n+\t\t\t    ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD)\n+#define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \\\n+\t\t\t    ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD)\n+\n+#define ICE_TXD_QW1_TX_BUF_SZ_S\t34\n+#define ICE_TXD_QW1_TX_BUF_SZ_M\t(0x3FFFULL << ICE_TXD_QW1_TX_BUF_SZ_S)\n+\n+#define ICE_TXD_QW1_L2TAG1_S\t48\n+#define ICE_TXD_QW1_L2TAG1_M\t(0xFFFFULL << ICE_TXD_QW1_L2TAG1_S)\n+\n+/* Context descriptors */\n+struct ice_tx_ctx_desc {\n+\t__le32 tunneling_params;\n+\t__le16 l2tag2;\n+\t__le16 rsvd;\n+\t__le64 qw1;\n+};\n+\n+#define ICE_TXD_CTX_QW1_DTYPE_S\t0\n+#define ICE_TXD_CTX_QW1_DTYPE_M\t(0xFUL << ICE_TXD_CTX_QW1_DTYPE_S)\n+\n+#define ICE_TXD_CTX_QW1_CMD_S\t4\n+#define ICE_TXD_CTX_QW1_CMD_M\t(0x7FUL << ICE_TXD_CTX_QW1_CMD_S)\n+\n+#define ICE_TXD_CTX_QW1_IPSEC_S\t11\n+#define ICE_TXD_CTX_QW1_IPSEC_M\t(0x7FUL << ICE_TXD_CTX_QW1_IPSEC_S)\n+\n+#define ICE_TXD_CTX_QW1_TSO_LEN_S\t30\n+#define ICE_TXD_CTX_QW1_TSO_LEN_M\t\\\n+\t\t\t(0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S)\n+\n+#define ICE_TXD_CTX_QW1_TSYN_S\tICE_TXD_CTX_QW1_TSO_LEN_S\n+#define ICE_TXD_CTX_QW1_TSYN_M\tICE_TXD_CTX_QW1_TSO_LEN_M\n+\n+#define ICE_TXD_CTX_QW1_MSS_S\t50\n+#define ICE_TXD_CTX_QW1_MSS_M\t(0x3FFFULL << ICE_TXD_CTX_QW1_MSS_S)\n+#define ICE_TXD_CTX_MIN_MSS\t64\n+#define ICE_TXD_CTX_MAX_MSS\t9668\n+\n+#define ICE_TXD_CTX_QW1_VSI_S\t50\n+#define ICE_TXD_CTX_QW1_VSI_M\t(0x3FFULL << ICE_TXD_CTX_QW1_VSI_S)\n+\n+enum ice_tx_ctx_desc_cmd_bits {\n+\tICE_TX_CTX_DESC_TSO\t\t= 0x01,\n+\tICE_TX_CTX_DESC_TSYN\t\t= 0x02,\n+\tICE_TX_CTX_DESC_IL2TAG2\t\t= 0x04,\n+\tICE_TX_CTX_DESC_IL2TAG2_IL2H\t= 0x08,\n+\tICE_TX_CTX_DESC_SWTCH_NOTAG\t= 0x00,\n+\tICE_TX_CTX_DESC_SWTCH_UPLINK\t= 0x10,\n+\tICE_TX_CTX_DESC_SWTCH_LOCAL\t= 0x20,\n+\tICE_TX_CTX_DESC_SWTCH_VSI\t= 0x30,\n+\tICE_TX_CTX_DESC_RESERVED\t= 0x40\n+};\n+\n+enum ice_tx_ctx_desc_eipt_offload {\n+\tICE_TX_CTX_EIPT_NONE\t\t= 0x0,\n+\tICE_TX_CTX_EIPT_IPV6\t\t= 0x1,\n+\tICE_TX_CTX_EIPT_IPV4_NO_CSUM\t= 0x2,\n+\tICE_TX_CTX_EIPT_IPV4\t\t= 0x3\n+};\n+\n+#define ICE_TXD_CTX_QW0_EIPT_S\t0\n+#define ICE_TXD_CTX_QW0_EIPT_M\t(0x3ULL << ICE_TXD_CTX_QW0_EIPT_S)\n+\n+#define ICE_TXD_CTX_QW0_EIPLEN_S\t2\n+#define ICE_TXD_CTX_QW0_EIPLEN_M\t(0x7FUL << ICE_TXD_CTX_QW0_EIPLEN_S)\n+\n+#define ICE_TXD_CTX_QW0_L4TUNT_S\t9\n+#define ICE_TXD_CTX_QW0_L4TUNT_M\t(0x3ULL << ICE_TXD_CTX_QW0_L4TUNT_S)\n+\n+#define ICE_TXD_CTX_UDP_TUNNELING\tBIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S)\n+#define ICE_TXD_CTX_GRE_TUNNELING\t(0x2ULL << ICE_TXD_CTX_QW0_L4TUNT_S)\n+\n+#define ICE_TXD_CTX_QW0_EIP_NOINC_S\t11\n+#define ICE_TXD_CTX_QW0_EIP_NOINC_M\tBIT_ULL(ICE_TXD_CTX_QW0_EIP_NOINC_S)\n+\n+#define ICE_TXD_CTX_EIP_NOINC_IPID_CONST\tICE_TXD_CTX_QW0_EIP_NOINC_M\n+\n+#define ICE_TXD_CTX_QW0_NATLEN_S\t12\n+#define ICE_TXD_CTX_QW0_NATLEN_M\t(0X7FULL << ICE_TXD_CTX_QW0_NATLEN_S)\n+\n+#define ICE_TXD_CTX_QW0_DECTTL_S\t19\n+#define ICE_TXD_CTX_QW0_DECTTL_M\t(0xFULL << ICE_TXD_CTX_QW0_DECTTL_S)\n+\n+#define ICE_TXD_CTX_QW0_L4T_CS_S\t23\n+#define ICE_TXD_CTX_QW0_L4T_CS_M\tBIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)\n+\n+\n+#define ICE_LAN_TXQ_MAX_QGRPS\t127\n+#define ICE_LAN_TXQ_MAX_QDIS\t1023\n+\n+/* Tx queue context data\n+ *\n+ * The sizes of the variables may be larger than needed due to crossing byte\n+ * boundaries. If we do not have the width of the variable set to the correct\n+ * size then we could end up shifting bits off the top of the variable when the\n+ * variable is at the top of a byte and crosses over into the next byte.\n+ */\n+struct ice_tlan_ctx {\n+#define ICE_TLAN_CTX_BASE_S\t7\n+\tu64 base;\t\t/* base is defined in 128-byte units */\n+\tu8 port_num;\n+\tu16 cgd_num;\t\t/* bigger than needed, see above for reason */\n+\tu8 pf_num;\n+\tu16 vmvf_num;\n+\tu8 vmvf_type;\n+#define ICE_TLAN_CTX_VMVF_TYPE_VMQ\t1\n+#define ICE_TLAN_CTX_VMVF_TYPE_PF\t2\n+\tu16 src_vsi;\n+\tu8 tsyn_ena;\n+\tu8 alt_vlan;\n+\tu16 cpuid;\t\t/* bigger than needed, see above for reason */\n+\tu8 wb_mode;\n+\tu8 tphrd_desc;\n+\tu8 tphrd;\n+\tu8 tphwr_desc;\n+\tu16 cmpq_id;\n+\tu16 qnum_in_func;\n+\tu8 itr_notification_mode;\n+\tu8 adjust_prof_id;\n+\tu32 qlen;\t\t/* bigger than needed, see above for reason */\n+\tu8 quanta_prof_idx;\n+\tu8 tso_ena;\n+\tu16 tso_qnum;\n+\tu8 legacy_int;\n+\tu8 drop_ena;\n+\tu8 cache_prof_idx;\n+\tu8 pkt_shaper_prof_idx;\n+\tu8 int_q_state;\t/* width not needed - internal do not write */\n+};\n+\n+/* LAN Tx Completion Queue data */\n+#pragma pack(1)\n+struct ice_tx_cmpltnq {\n+\tu16 txq_id;\n+\tu8 generation;\n+\tu16 tx_head;\n+\tu8 cmpl_type;\n+};\n+#pragma pack()\n+\n+\n+/* LAN Tx Completion Queue Context */\n+#pragma pack(1)\n+struct ice_tx_cmpltnq_ctx {\n+\tu64 base;\n+\tu32 q_len;\n+#define ICE_TX_CMPLTNQ_CTX_Q_LEN_S\t4\n+\tu8 generation;\n+\tu32 wrt_ptr;\n+\tu8 pf_num;\n+\tu16 vmvf_num;\n+\tu8 vmvf_type;\n+\tu8 tph_desc_wr;\n+\tu8 cpuid;\n+\tu32 cmpltn_cache[16];\n+};\n+#pragma pack()\n+\n+/* LAN Tx Doorbell Descriptor Format */\n+struct ice_tx_drbell_fmt {\n+\tu16 txq_id;\n+\tu8 dd;\n+\tu8 rs;\n+\tu32 db;\n+};\n+\n+\n+/* LAN Tx Doorbell Queue Context */\n+#pragma pack(1)\n+struct ice_tx_drbell_q_ctx {\n+\tu64 base;\n+\tu16 ring_len;\n+\tu8 pf_num;\n+\tu16 vf_num;\n+\tu8 vmvf_type;\n+\tu8 cpuid;\n+\tu8 tph_desc_rd;\n+\tu8 tph_desc_wr;\n+\tu8 db_q_en;\n+\tu16 rd_head;\n+\tu16 rd_tail;\n+};\n+#pragma pack()\n+\n+/* The ice_ptype_lkup table is used to convert from the 10-bit ptype in the\n+ * hardware to a bit-field that can be used by SW to more easily determine the\n+ * packet type.\n+ *\n+ * Macros are used to shorten the table lines and make this table human\n+ * readable.\n+ *\n+ * We store the PTYPE in the top byte of the bit field - this is just so that\n+ * we can check that the table doesn't have a row missing, as the index into\n+ * the table should be the PTYPE.\n+ *\n+ * Typical work flow:\n+ *\n+ * IF NOT ice_ptype_lkup[ptype].known\n+ * THEN\n+ *      Packet is unknown\n+ * ELSE IF ice_ptype_lkup[ptype].outer_ip == ICE_RX_PTYPE_OUTER_IP\n+ *      Use the rest of the fields to look at the tunnels, inner protocols, etc\n+ * ELSE\n+ *      Use the enum ice_rx_l2_ptype to decode the packet type\n+ * ENDIF\n+ */\n+\n+/* macro to make the table lines short */\n+#define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\\\n+\t{\tPTYPE, \\\n+\t\t1, \\\n+\t\tICE_RX_PTYPE_OUTER_##OUTER_IP, \\\n+\t\tICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \\\n+\t\tICE_RX_PTYPE_##OUTER_FRAG, \\\n+\t\tICE_RX_PTYPE_TUNNEL_##T, \\\n+\t\tICE_RX_PTYPE_TUNNEL_END_##TE, \\\n+\t\tICE_RX_PTYPE_##TEF, \\\n+\t\tICE_RX_PTYPE_INNER_PROT_##I, \\\n+\t\tICE_RX_PTYPE_PAYLOAD_LAYER_##PL }\n+\n+#define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }\n+\n+/* shorter macros makes the table fit but are terse */\n+#define ICE_RX_PTYPE_NOF\t\tICE_RX_PTYPE_NOT_FRAG\n+#define ICE_RX_PTYPE_FRG\t\tICE_RX_PTYPE_FRAG\n+\n+/* Lookup table mapping the HW PTYPE to the bit field for decoding */\n+static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = {\n+\t/* L2 Packet types */\n+\tICE_PTT_UNUSED_ENTRY(0),\n+\tICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),\n+\tICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n+\tICE_PTT_UNUSED_ENTRY(3),\n+\tICE_PTT_UNUSED_ENTRY(4),\n+\tICE_PTT_UNUSED_ENTRY(5),\n+\tICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n+\tICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n+\tICE_PTT_UNUSED_ENTRY(8),\n+\tICE_PTT_UNUSED_ENTRY(9),\n+\tICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n+\tICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n+\tICE_PTT_UNUSED_ENTRY(12),\n+\tICE_PTT_UNUSED_ENTRY(13),\n+\tICE_PTT_UNUSED_ENTRY(14),\n+\tICE_PTT_UNUSED_ENTRY(15),\n+\tICE_PTT_UNUSED_ENTRY(16),\n+\tICE_PTT_UNUSED_ENTRY(17),\n+\tICE_PTT_UNUSED_ENTRY(18),\n+\tICE_PTT_UNUSED_ENTRY(19),\n+\tICE_PTT_UNUSED_ENTRY(20),\n+\tICE_PTT_UNUSED_ENTRY(21),\n+\n+\t/* Non Tunneled IPv4 */\n+\tICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),\n+\tICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),\n+\tICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(25),\n+\tICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),\n+\tICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),\n+\tICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> IPv4 */\n+\tICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(32),\n+\tICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> IPv6 */\n+\tICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(39),\n+\tICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> GRE/NAT */\n+\tICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv4 --> GRE/NAT --> IPv4 */\n+\tICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(47),\n+\tICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> GRE/NAT --> IPv6 */\n+\tICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(54),\n+\tICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> GRE/NAT --> MAC */\n+\tICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv4 --> GRE/NAT --> MAC --> IPv4 */\n+\tICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(62),\n+\tICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> GRE/NAT -> MAC --> IPv6 */\n+\tICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(69),\n+\tICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> GRE/NAT --> MAC/VLAN */\n+\tICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */\n+\tICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(77),\n+\tICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */\n+\tICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(84),\n+\tICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* Non Tunneled IPv6 */\n+\tICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),\n+\tICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),\n+\tICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),\n+\tICE_PTT_UNUSED_ENTRY(91),\n+\tICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),\n+\tICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),\n+\tICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> IPv4 */\n+\tICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(98),\n+\tICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> IPv6 */\n+\tICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(105),\n+\tICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT */\n+\tICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv6 --> GRE/NAT -> IPv4 */\n+\tICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(113),\n+\tICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT -> IPv6 */\n+\tICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(120),\n+\tICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC */\n+\tICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC -> IPv4 */\n+\tICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(128),\n+\tICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC -> IPv6 */\n+\tICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(135),\n+\tICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC/VLAN */\n+\tICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */\n+\tICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(143),\n+\tICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */\n+\tICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(150),\n+\tICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* unused entries */\n+\tICE_PTT_UNUSED_ENTRY(154),\n+\tICE_PTT_UNUSED_ENTRY(155),\n+\tICE_PTT_UNUSED_ENTRY(156),\n+\tICE_PTT_UNUSED_ENTRY(157),\n+\tICE_PTT_UNUSED_ENTRY(158),\n+\tICE_PTT_UNUSED_ENTRY(159),\n+\n+\tICE_PTT_UNUSED_ENTRY(160),\n+\tICE_PTT_UNUSED_ENTRY(161),\n+\tICE_PTT_UNUSED_ENTRY(162),\n+\tICE_PTT_UNUSED_ENTRY(163),\n+\tICE_PTT_UNUSED_ENTRY(164),\n+\tICE_PTT_UNUSED_ENTRY(165),\n+\tICE_PTT_UNUSED_ENTRY(166),\n+\tICE_PTT_UNUSED_ENTRY(167),\n+\tICE_PTT_UNUSED_ENTRY(168),\n+\tICE_PTT_UNUSED_ENTRY(169),\n+\n+\tICE_PTT_UNUSED_ENTRY(170),\n+\tICE_PTT_UNUSED_ENTRY(171),\n+\tICE_PTT_UNUSED_ENTRY(172),\n+\tICE_PTT_UNUSED_ENTRY(173),\n+\tICE_PTT_UNUSED_ENTRY(174),\n+\tICE_PTT_UNUSED_ENTRY(175),\n+\tICE_PTT_UNUSED_ENTRY(176),\n+\tICE_PTT_UNUSED_ENTRY(177),\n+\tICE_PTT_UNUSED_ENTRY(178),\n+\tICE_PTT_UNUSED_ENTRY(179),\n+\n+\tICE_PTT_UNUSED_ENTRY(180),\n+\tICE_PTT_UNUSED_ENTRY(181),\n+\tICE_PTT_UNUSED_ENTRY(182),\n+\tICE_PTT_UNUSED_ENTRY(183),\n+\tICE_PTT_UNUSED_ENTRY(184),\n+\tICE_PTT_UNUSED_ENTRY(185),\n+\tICE_PTT_UNUSED_ENTRY(186),\n+\tICE_PTT_UNUSED_ENTRY(187),\n+\tICE_PTT_UNUSED_ENTRY(188),\n+\tICE_PTT_UNUSED_ENTRY(189),\n+\n+\tICE_PTT_UNUSED_ENTRY(190),\n+\tICE_PTT_UNUSED_ENTRY(191),\n+\tICE_PTT_UNUSED_ENTRY(192),\n+\tICE_PTT_UNUSED_ENTRY(193),\n+\tICE_PTT_UNUSED_ENTRY(194),\n+\tICE_PTT_UNUSED_ENTRY(195),\n+\tICE_PTT_UNUSED_ENTRY(196),\n+\tICE_PTT_UNUSED_ENTRY(197),\n+\tICE_PTT_UNUSED_ENTRY(198),\n+\tICE_PTT_UNUSED_ENTRY(199),\n+\n+\tICE_PTT_UNUSED_ENTRY(200),\n+\tICE_PTT_UNUSED_ENTRY(201),\n+\tICE_PTT_UNUSED_ENTRY(202),\n+\tICE_PTT_UNUSED_ENTRY(203),\n+\tICE_PTT_UNUSED_ENTRY(204),\n+\tICE_PTT_UNUSED_ENTRY(205),\n+\tICE_PTT_UNUSED_ENTRY(206),\n+\tICE_PTT_UNUSED_ENTRY(207),\n+\tICE_PTT_UNUSED_ENTRY(208),\n+\tICE_PTT_UNUSED_ENTRY(209),\n+\n+\tICE_PTT_UNUSED_ENTRY(210),\n+\tICE_PTT_UNUSED_ENTRY(211),\n+\tICE_PTT_UNUSED_ENTRY(212),\n+\tICE_PTT_UNUSED_ENTRY(213),\n+\tICE_PTT_UNUSED_ENTRY(214),\n+\tICE_PTT_UNUSED_ENTRY(215),\n+\tICE_PTT_UNUSED_ENTRY(216),\n+\tICE_PTT_UNUSED_ENTRY(217),\n+\tICE_PTT_UNUSED_ENTRY(218),\n+\tICE_PTT_UNUSED_ENTRY(219),\n+\n+\tICE_PTT_UNUSED_ENTRY(220),\n+\tICE_PTT_UNUSED_ENTRY(221),\n+\tICE_PTT_UNUSED_ENTRY(222),\n+\tICE_PTT_UNUSED_ENTRY(223),\n+\tICE_PTT_UNUSED_ENTRY(224),\n+\tICE_PTT_UNUSED_ENTRY(225),\n+\tICE_PTT_UNUSED_ENTRY(226),\n+\tICE_PTT_UNUSED_ENTRY(227),\n+\tICE_PTT_UNUSED_ENTRY(228),\n+\tICE_PTT_UNUSED_ENTRY(229),\n+\n+\tICE_PTT_UNUSED_ENTRY(230),\n+\tICE_PTT_UNUSED_ENTRY(231),\n+\tICE_PTT_UNUSED_ENTRY(232),\n+\tICE_PTT_UNUSED_ENTRY(233),\n+\tICE_PTT_UNUSED_ENTRY(234),\n+\tICE_PTT_UNUSED_ENTRY(235),\n+\tICE_PTT_UNUSED_ENTRY(236),\n+\tICE_PTT_UNUSED_ENTRY(237),\n+\tICE_PTT_UNUSED_ENTRY(238),\n+\tICE_PTT_UNUSED_ENTRY(239),\n+\n+\tICE_PTT_UNUSED_ENTRY(240),\n+\tICE_PTT_UNUSED_ENTRY(241),\n+\tICE_PTT_UNUSED_ENTRY(242),\n+\tICE_PTT_UNUSED_ENTRY(243),\n+\tICE_PTT_UNUSED_ENTRY(244),\n+\tICE_PTT_UNUSED_ENTRY(245),\n+\tICE_PTT_UNUSED_ENTRY(246),\n+\tICE_PTT_UNUSED_ENTRY(247),\n+\tICE_PTT_UNUSED_ENTRY(248),\n+\tICE_PTT_UNUSED_ENTRY(249),\n+\n+\tICE_PTT_UNUSED_ENTRY(250),\n+\tICE_PTT_UNUSED_ENTRY(251),\n+\tICE_PTT_UNUSED_ENTRY(252),\n+\tICE_PTT_UNUSED_ENTRY(253),\n+\tICE_PTT_UNUSED_ENTRY(254),\n+\tICE_PTT_UNUSED_ENTRY(255),\n+\tICE_PTT_UNUSED_ENTRY(256),\n+\tICE_PTT_UNUSED_ENTRY(257),\n+\tICE_PTT_UNUSED_ENTRY(258),\n+\tICE_PTT_UNUSED_ENTRY(259),\n+\n+\tICE_PTT_UNUSED_ENTRY(260),\n+\tICE_PTT_UNUSED_ENTRY(261),\n+\tICE_PTT_UNUSED_ENTRY(262),\n+\tICE_PTT_UNUSED_ENTRY(263),\n+\tICE_PTT_UNUSED_ENTRY(264),\n+\tICE_PTT_UNUSED_ENTRY(265),\n+\tICE_PTT_UNUSED_ENTRY(266),\n+\tICE_PTT_UNUSED_ENTRY(267),\n+\tICE_PTT_UNUSED_ENTRY(268),\n+\tICE_PTT_UNUSED_ENTRY(269),\n+\n+\tICE_PTT_UNUSED_ENTRY(270),\n+\tICE_PTT_UNUSED_ENTRY(271),\n+\tICE_PTT_UNUSED_ENTRY(272),\n+\tICE_PTT_UNUSED_ENTRY(273),\n+\tICE_PTT_UNUSED_ENTRY(274),\n+\tICE_PTT_UNUSED_ENTRY(275),\n+\tICE_PTT_UNUSED_ENTRY(276),\n+\tICE_PTT_UNUSED_ENTRY(277),\n+\tICE_PTT_UNUSED_ENTRY(278),\n+\tICE_PTT_UNUSED_ENTRY(279),\n+\n+\tICE_PTT_UNUSED_ENTRY(280),\n+\tICE_PTT_UNUSED_ENTRY(281),\n+\tICE_PTT_UNUSED_ENTRY(282),\n+\tICE_PTT_UNUSED_ENTRY(283),\n+\tICE_PTT_UNUSED_ENTRY(284),\n+\tICE_PTT_UNUSED_ENTRY(285),\n+\tICE_PTT_UNUSED_ENTRY(286),\n+\tICE_PTT_UNUSED_ENTRY(287),\n+\tICE_PTT_UNUSED_ENTRY(288),\n+\tICE_PTT_UNUSED_ENTRY(289),\n+\n+\tICE_PTT_UNUSED_ENTRY(290),\n+\tICE_PTT_UNUSED_ENTRY(291),\n+\tICE_PTT_UNUSED_ENTRY(292),\n+\tICE_PTT_UNUSED_ENTRY(293),\n+\tICE_PTT_UNUSED_ENTRY(294),\n+\tICE_PTT_UNUSED_ENTRY(295),\n+\tICE_PTT_UNUSED_ENTRY(296),\n+\tICE_PTT_UNUSED_ENTRY(297),\n+\tICE_PTT_UNUSED_ENTRY(298),\n+\tICE_PTT_UNUSED_ENTRY(299),\n+\n+\tICE_PTT_UNUSED_ENTRY(300),\n+\tICE_PTT_UNUSED_ENTRY(301),\n+\tICE_PTT_UNUSED_ENTRY(302),\n+\tICE_PTT_UNUSED_ENTRY(303),\n+\tICE_PTT_UNUSED_ENTRY(304),\n+\tICE_PTT_UNUSED_ENTRY(305),\n+\tICE_PTT_UNUSED_ENTRY(306),\n+\tICE_PTT_UNUSED_ENTRY(307),\n+\tICE_PTT_UNUSED_ENTRY(308),\n+\tICE_PTT_UNUSED_ENTRY(309),\n+\n+\tICE_PTT_UNUSED_ENTRY(310),\n+\tICE_PTT_UNUSED_ENTRY(311),\n+\tICE_PTT_UNUSED_ENTRY(312),\n+\tICE_PTT_UNUSED_ENTRY(313),\n+\tICE_PTT_UNUSED_ENTRY(314),\n+\tICE_PTT_UNUSED_ENTRY(315),\n+\tICE_PTT_UNUSED_ENTRY(316),\n+\tICE_PTT_UNUSED_ENTRY(317),\n+\tICE_PTT_UNUSED_ENTRY(318),\n+\tICE_PTT_UNUSED_ENTRY(319),\n+\n+\tICE_PTT_UNUSED_ENTRY(320),\n+\tICE_PTT_UNUSED_ENTRY(321),\n+\tICE_PTT_UNUSED_ENTRY(322),\n+\tICE_PTT_UNUSED_ENTRY(323),\n+\tICE_PTT_UNUSED_ENTRY(324),\n+\tICE_PTT_UNUSED_ENTRY(325),\n+\tICE_PTT_UNUSED_ENTRY(326),\n+\tICE_PTT_UNUSED_ENTRY(327),\n+\tICE_PTT_UNUSED_ENTRY(328),\n+\tICE_PTT_UNUSED_ENTRY(329),\n+\n+\tICE_PTT_UNUSED_ENTRY(330),\n+\tICE_PTT_UNUSED_ENTRY(331),\n+\tICE_PTT_UNUSED_ENTRY(332),\n+\tICE_PTT_UNUSED_ENTRY(333),\n+\tICE_PTT_UNUSED_ENTRY(334),\n+\tICE_PTT_UNUSED_ENTRY(335),\n+\tICE_PTT_UNUSED_ENTRY(336),\n+\tICE_PTT_UNUSED_ENTRY(337),\n+\tICE_PTT_UNUSED_ENTRY(338),\n+\tICE_PTT_UNUSED_ENTRY(339),\n+\n+\tICE_PTT_UNUSED_ENTRY(340),\n+\tICE_PTT_UNUSED_ENTRY(341),\n+\tICE_PTT_UNUSED_ENTRY(342),\n+\tICE_PTT_UNUSED_ENTRY(343),\n+\tICE_PTT_UNUSED_ENTRY(344),\n+\tICE_PTT_UNUSED_ENTRY(345),\n+\tICE_PTT_UNUSED_ENTRY(346),\n+\tICE_PTT_UNUSED_ENTRY(347),\n+\tICE_PTT_UNUSED_ENTRY(348),\n+\tICE_PTT_UNUSED_ENTRY(349),\n+\n+\tICE_PTT_UNUSED_ENTRY(350),\n+\tICE_PTT_UNUSED_ENTRY(351),\n+\tICE_PTT_UNUSED_ENTRY(352),\n+\tICE_PTT_UNUSED_ENTRY(353),\n+\tICE_PTT_UNUSED_ENTRY(354),\n+\tICE_PTT_UNUSED_ENTRY(355),\n+\tICE_PTT_UNUSED_ENTRY(356),\n+\tICE_PTT_UNUSED_ENTRY(357),\n+\tICE_PTT_UNUSED_ENTRY(358),\n+\tICE_PTT_UNUSED_ENTRY(359),\n+\n+\tICE_PTT_UNUSED_ENTRY(360),\n+\tICE_PTT_UNUSED_ENTRY(361),\n+\tICE_PTT_UNUSED_ENTRY(362),\n+\tICE_PTT_UNUSED_ENTRY(363),\n+\tICE_PTT_UNUSED_ENTRY(364),\n+\tICE_PTT_UNUSED_ENTRY(365),\n+\tICE_PTT_UNUSED_ENTRY(366),\n+\tICE_PTT_UNUSED_ENTRY(367),\n+\tICE_PTT_UNUSED_ENTRY(368),\n+\tICE_PTT_UNUSED_ENTRY(369),\n+\n+\tICE_PTT_UNUSED_ENTRY(370),\n+\tICE_PTT_UNUSED_ENTRY(371),\n+\tICE_PTT_UNUSED_ENTRY(372),\n+\tICE_PTT_UNUSED_ENTRY(373),\n+\tICE_PTT_UNUSED_ENTRY(374),\n+\tICE_PTT_UNUSED_ENTRY(375),\n+\tICE_PTT_UNUSED_ENTRY(376),\n+\tICE_PTT_UNUSED_ENTRY(377),\n+\tICE_PTT_UNUSED_ENTRY(378),\n+\tICE_PTT_UNUSED_ENTRY(379),\n+\n+\tICE_PTT_UNUSED_ENTRY(380),\n+\tICE_PTT_UNUSED_ENTRY(381),\n+\tICE_PTT_UNUSED_ENTRY(382),\n+\tICE_PTT_UNUSED_ENTRY(383),\n+\tICE_PTT_UNUSED_ENTRY(384),\n+\tICE_PTT_UNUSED_ENTRY(385),\n+\tICE_PTT_UNUSED_ENTRY(386),\n+\tICE_PTT_UNUSED_ENTRY(387),\n+\tICE_PTT_UNUSED_ENTRY(388),\n+\tICE_PTT_UNUSED_ENTRY(389),\n+\n+\tICE_PTT_UNUSED_ENTRY(390),\n+\tICE_PTT_UNUSED_ENTRY(391),\n+\tICE_PTT_UNUSED_ENTRY(392),\n+\tICE_PTT_UNUSED_ENTRY(393),\n+\tICE_PTT_UNUSED_ENTRY(394),\n+\tICE_PTT_UNUSED_ENTRY(395),\n+\tICE_PTT_UNUSED_ENTRY(396),\n+\tICE_PTT_UNUSED_ENTRY(397),\n+\tICE_PTT_UNUSED_ENTRY(398),\n+\tICE_PTT_UNUSED_ENTRY(399),\n+\n+\tICE_PTT_UNUSED_ENTRY(400),\n+\tICE_PTT_UNUSED_ENTRY(401),\n+\tICE_PTT_UNUSED_ENTRY(402),\n+\tICE_PTT_UNUSED_ENTRY(403),\n+\tICE_PTT_UNUSED_ENTRY(404),\n+\tICE_PTT_UNUSED_ENTRY(405),\n+\tICE_PTT_UNUSED_ENTRY(406),\n+\tICE_PTT_UNUSED_ENTRY(407),\n+\tICE_PTT_UNUSED_ENTRY(408),\n+\tICE_PTT_UNUSED_ENTRY(409),\n+\n+\tICE_PTT_UNUSED_ENTRY(410),\n+\tICE_PTT_UNUSED_ENTRY(411),\n+\tICE_PTT_UNUSED_ENTRY(412),\n+\tICE_PTT_UNUSED_ENTRY(413),\n+\tICE_PTT_UNUSED_ENTRY(414),\n+\tICE_PTT_UNUSED_ENTRY(415),\n+\tICE_PTT_UNUSED_ENTRY(416),\n+\tICE_PTT_UNUSED_ENTRY(417),\n+\tICE_PTT_UNUSED_ENTRY(418),\n+\tICE_PTT_UNUSED_ENTRY(419),\n+\n+\tICE_PTT_UNUSED_ENTRY(420),\n+\tICE_PTT_UNUSED_ENTRY(421),\n+\tICE_PTT_UNUSED_ENTRY(422),\n+\tICE_PTT_UNUSED_ENTRY(423),\n+\tICE_PTT_UNUSED_ENTRY(424),\n+\tICE_PTT_UNUSED_ENTRY(425),\n+\tICE_PTT_UNUSED_ENTRY(426),\n+\tICE_PTT_UNUSED_ENTRY(427),\n+\tICE_PTT_UNUSED_ENTRY(428),\n+\tICE_PTT_UNUSED_ENTRY(429),\n+\n+\tICE_PTT_UNUSED_ENTRY(430),\n+\tICE_PTT_UNUSED_ENTRY(431),\n+\tICE_PTT_UNUSED_ENTRY(432),\n+\tICE_PTT_UNUSED_ENTRY(433),\n+\tICE_PTT_UNUSED_ENTRY(434),\n+\tICE_PTT_UNUSED_ENTRY(435),\n+\tICE_PTT_UNUSED_ENTRY(436),\n+\tICE_PTT_UNUSED_ENTRY(437),\n+\tICE_PTT_UNUSED_ENTRY(438),\n+\tICE_PTT_UNUSED_ENTRY(439),\n+\n+\tICE_PTT_UNUSED_ENTRY(440),\n+\tICE_PTT_UNUSED_ENTRY(441),\n+\tICE_PTT_UNUSED_ENTRY(442),\n+\tICE_PTT_UNUSED_ENTRY(443),\n+\tICE_PTT_UNUSED_ENTRY(444),\n+\tICE_PTT_UNUSED_ENTRY(445),\n+\tICE_PTT_UNUSED_ENTRY(446),\n+\tICE_PTT_UNUSED_ENTRY(447),\n+\tICE_PTT_UNUSED_ENTRY(448),\n+\tICE_PTT_UNUSED_ENTRY(449),\n+\n+\tICE_PTT_UNUSED_ENTRY(450),\n+\tICE_PTT_UNUSED_ENTRY(451),\n+\tICE_PTT_UNUSED_ENTRY(452),\n+\tICE_PTT_UNUSED_ENTRY(453),\n+\tICE_PTT_UNUSED_ENTRY(454),\n+\tICE_PTT_UNUSED_ENTRY(455),\n+\tICE_PTT_UNUSED_ENTRY(456),\n+\tICE_PTT_UNUSED_ENTRY(457),\n+\tICE_PTT_UNUSED_ENTRY(458),\n+\tICE_PTT_UNUSED_ENTRY(459),\n+\n+\tICE_PTT_UNUSED_ENTRY(460),\n+\tICE_PTT_UNUSED_ENTRY(461),\n+\tICE_PTT_UNUSED_ENTRY(462),\n+\tICE_PTT_UNUSED_ENTRY(463),\n+\tICE_PTT_UNUSED_ENTRY(464),\n+\tICE_PTT_UNUSED_ENTRY(465),\n+\tICE_PTT_UNUSED_ENTRY(466),\n+\tICE_PTT_UNUSED_ENTRY(467),\n+\tICE_PTT_UNUSED_ENTRY(468),\n+\tICE_PTT_UNUSED_ENTRY(469),\n+\n+\tICE_PTT_UNUSED_ENTRY(470),\n+\tICE_PTT_UNUSED_ENTRY(471),\n+\tICE_PTT_UNUSED_ENTRY(472),\n+\tICE_PTT_UNUSED_ENTRY(473),\n+\tICE_PTT_UNUSED_ENTRY(474),\n+\tICE_PTT_UNUSED_ENTRY(475),\n+\tICE_PTT_UNUSED_ENTRY(476),\n+\tICE_PTT_UNUSED_ENTRY(477),\n+\tICE_PTT_UNUSED_ENTRY(478),\n+\tICE_PTT_UNUSED_ENTRY(479),\n+\n+\tICE_PTT_UNUSED_ENTRY(480),\n+\tICE_PTT_UNUSED_ENTRY(481),\n+\tICE_PTT_UNUSED_ENTRY(482),\n+\tICE_PTT_UNUSED_ENTRY(483),\n+\tICE_PTT_UNUSED_ENTRY(484),\n+\tICE_PTT_UNUSED_ENTRY(485),\n+\tICE_PTT_UNUSED_ENTRY(486),\n+\tICE_PTT_UNUSED_ENTRY(487),\n+\tICE_PTT_UNUSED_ENTRY(488),\n+\tICE_PTT_UNUSED_ENTRY(489),\n+\n+\tICE_PTT_UNUSED_ENTRY(490),\n+\tICE_PTT_UNUSED_ENTRY(491),\n+\tICE_PTT_UNUSED_ENTRY(492),\n+\tICE_PTT_UNUSED_ENTRY(493),\n+\tICE_PTT_UNUSED_ENTRY(494),\n+\tICE_PTT_UNUSED_ENTRY(495),\n+\tICE_PTT_UNUSED_ENTRY(496),\n+\tICE_PTT_UNUSED_ENTRY(497),\n+\tICE_PTT_UNUSED_ENTRY(498),\n+\tICE_PTT_UNUSED_ENTRY(499),\n+\n+\tICE_PTT_UNUSED_ENTRY(500),\n+\tICE_PTT_UNUSED_ENTRY(501),\n+\tICE_PTT_UNUSED_ENTRY(502),\n+\tICE_PTT_UNUSED_ENTRY(503),\n+\tICE_PTT_UNUSED_ENTRY(504),\n+\tICE_PTT_UNUSED_ENTRY(505),\n+\tICE_PTT_UNUSED_ENTRY(506),\n+\tICE_PTT_UNUSED_ENTRY(507),\n+\tICE_PTT_UNUSED_ENTRY(508),\n+\tICE_PTT_UNUSED_ENTRY(509),\n+\n+\tICE_PTT_UNUSED_ENTRY(510),\n+\tICE_PTT_UNUSED_ENTRY(511),\n+\tICE_PTT_UNUSED_ENTRY(512),\n+\tICE_PTT_UNUSED_ENTRY(513),\n+\tICE_PTT_UNUSED_ENTRY(514),\n+\tICE_PTT_UNUSED_ENTRY(515),\n+\tICE_PTT_UNUSED_ENTRY(516),\n+\tICE_PTT_UNUSED_ENTRY(517),\n+\tICE_PTT_UNUSED_ENTRY(518),\n+\tICE_PTT_UNUSED_ENTRY(519),\n+\n+\tICE_PTT_UNUSED_ENTRY(520),\n+\tICE_PTT_UNUSED_ENTRY(521),\n+\tICE_PTT_UNUSED_ENTRY(522),\n+\tICE_PTT_UNUSED_ENTRY(523),\n+\tICE_PTT_UNUSED_ENTRY(524),\n+\tICE_PTT_UNUSED_ENTRY(525),\n+\tICE_PTT_UNUSED_ENTRY(526),\n+\tICE_PTT_UNUSED_ENTRY(527),\n+\tICE_PTT_UNUSED_ENTRY(528),\n+\tICE_PTT_UNUSED_ENTRY(529),\n+\n+\tICE_PTT_UNUSED_ENTRY(530),\n+\tICE_PTT_UNUSED_ENTRY(531),\n+\tICE_PTT_UNUSED_ENTRY(532),\n+\tICE_PTT_UNUSED_ENTRY(533),\n+\tICE_PTT_UNUSED_ENTRY(534),\n+\tICE_PTT_UNUSED_ENTRY(535),\n+\tICE_PTT_UNUSED_ENTRY(536),\n+\tICE_PTT_UNUSED_ENTRY(537),\n+\tICE_PTT_UNUSED_ENTRY(538),\n+\tICE_PTT_UNUSED_ENTRY(539),\n+\n+\tICE_PTT_UNUSED_ENTRY(540),\n+\tICE_PTT_UNUSED_ENTRY(541),\n+\tICE_PTT_UNUSED_ENTRY(542),\n+\tICE_PTT_UNUSED_ENTRY(543),\n+\tICE_PTT_UNUSED_ENTRY(544),\n+\tICE_PTT_UNUSED_ENTRY(545),\n+\tICE_PTT_UNUSED_ENTRY(546),\n+\tICE_PTT_UNUSED_ENTRY(547),\n+\tICE_PTT_UNUSED_ENTRY(548),\n+\tICE_PTT_UNUSED_ENTRY(549),\n+\n+\tICE_PTT_UNUSED_ENTRY(550),\n+\tICE_PTT_UNUSED_ENTRY(551),\n+\tICE_PTT_UNUSED_ENTRY(552),\n+\tICE_PTT_UNUSED_ENTRY(553),\n+\tICE_PTT_UNUSED_ENTRY(554),\n+\tICE_PTT_UNUSED_ENTRY(555),\n+\tICE_PTT_UNUSED_ENTRY(556),\n+\tICE_PTT_UNUSED_ENTRY(557),\n+\tICE_PTT_UNUSED_ENTRY(558),\n+\tICE_PTT_UNUSED_ENTRY(559),\n+\n+\tICE_PTT_UNUSED_ENTRY(560),\n+\tICE_PTT_UNUSED_ENTRY(561),\n+\tICE_PTT_UNUSED_ENTRY(562),\n+\tICE_PTT_UNUSED_ENTRY(563),\n+\tICE_PTT_UNUSED_ENTRY(564),\n+\tICE_PTT_UNUSED_ENTRY(565),\n+\tICE_PTT_UNUSED_ENTRY(566),\n+\tICE_PTT_UNUSED_ENTRY(567),\n+\tICE_PTT_UNUSED_ENTRY(568),\n+\tICE_PTT_UNUSED_ENTRY(569),\n+\n+\tICE_PTT_UNUSED_ENTRY(570),\n+\tICE_PTT_UNUSED_ENTRY(571),\n+\tICE_PTT_UNUSED_ENTRY(572),\n+\tICE_PTT_UNUSED_ENTRY(573),\n+\tICE_PTT_UNUSED_ENTRY(574),\n+\tICE_PTT_UNUSED_ENTRY(575),\n+\tICE_PTT_UNUSED_ENTRY(576),\n+\tICE_PTT_UNUSED_ENTRY(577),\n+\tICE_PTT_UNUSED_ENTRY(578),\n+\tICE_PTT_UNUSED_ENTRY(579),\n+\n+\tICE_PTT_UNUSED_ENTRY(580),\n+\tICE_PTT_UNUSED_ENTRY(581),\n+\tICE_PTT_UNUSED_ENTRY(582),\n+\tICE_PTT_UNUSED_ENTRY(583),\n+\tICE_PTT_UNUSED_ENTRY(584),\n+\tICE_PTT_UNUSED_ENTRY(585),\n+\tICE_PTT_UNUSED_ENTRY(586),\n+\tICE_PTT_UNUSED_ENTRY(587),\n+\tICE_PTT_UNUSED_ENTRY(588),\n+\tICE_PTT_UNUSED_ENTRY(589),\n+\n+\tICE_PTT_UNUSED_ENTRY(590),\n+\tICE_PTT_UNUSED_ENTRY(591),\n+\tICE_PTT_UNUSED_ENTRY(592),\n+\tICE_PTT_UNUSED_ENTRY(593),\n+\tICE_PTT_UNUSED_ENTRY(594),\n+\tICE_PTT_UNUSED_ENTRY(595),\n+\tICE_PTT_UNUSED_ENTRY(596),\n+\tICE_PTT_UNUSED_ENTRY(597),\n+\tICE_PTT_UNUSED_ENTRY(598),\n+\tICE_PTT_UNUSED_ENTRY(599),\n+\n+\tICE_PTT_UNUSED_ENTRY(600),\n+\tICE_PTT_UNUSED_ENTRY(601),\n+\tICE_PTT_UNUSED_ENTRY(602),\n+\tICE_PTT_UNUSED_ENTRY(603),\n+\tICE_PTT_UNUSED_ENTRY(604),\n+\tICE_PTT_UNUSED_ENTRY(605),\n+\tICE_PTT_UNUSED_ENTRY(606),\n+\tICE_PTT_UNUSED_ENTRY(607),\n+\tICE_PTT_UNUSED_ENTRY(608),\n+\tICE_PTT_UNUSED_ENTRY(609),\n+\n+\tICE_PTT_UNUSED_ENTRY(610),\n+\tICE_PTT_UNUSED_ENTRY(611),\n+\tICE_PTT_UNUSED_ENTRY(612),\n+\tICE_PTT_UNUSED_ENTRY(613),\n+\tICE_PTT_UNUSED_ENTRY(614),\n+\tICE_PTT_UNUSED_ENTRY(615),\n+\tICE_PTT_UNUSED_ENTRY(616),\n+\tICE_PTT_UNUSED_ENTRY(617),\n+\tICE_PTT_UNUSED_ENTRY(618),\n+\tICE_PTT_UNUSED_ENTRY(619),\n+\n+\tICE_PTT_UNUSED_ENTRY(620),\n+\tICE_PTT_UNUSED_ENTRY(621),\n+\tICE_PTT_UNUSED_ENTRY(622),\n+\tICE_PTT_UNUSED_ENTRY(623),\n+\tICE_PTT_UNUSED_ENTRY(624),\n+\tICE_PTT_UNUSED_ENTRY(625),\n+\tICE_PTT_UNUSED_ENTRY(626),\n+\tICE_PTT_UNUSED_ENTRY(627),\n+\tICE_PTT_UNUSED_ENTRY(628),\n+\tICE_PTT_UNUSED_ENTRY(629),\n+\n+\tICE_PTT_UNUSED_ENTRY(630),\n+\tICE_PTT_UNUSED_ENTRY(631),\n+\tICE_PTT_UNUSED_ENTRY(632),\n+\tICE_PTT_UNUSED_ENTRY(633),\n+\tICE_PTT_UNUSED_ENTRY(634),\n+\tICE_PTT_UNUSED_ENTRY(635),\n+\tICE_PTT_UNUSED_ENTRY(636),\n+\tICE_PTT_UNUSED_ENTRY(637),\n+\tICE_PTT_UNUSED_ENTRY(638),\n+\tICE_PTT_UNUSED_ENTRY(639),\n+\n+\tICE_PTT_UNUSED_ENTRY(640),\n+\tICE_PTT_UNUSED_ENTRY(641),\n+\tICE_PTT_UNUSED_ENTRY(642),\n+\tICE_PTT_UNUSED_ENTRY(643),\n+\tICE_PTT_UNUSED_ENTRY(644),\n+\tICE_PTT_UNUSED_ENTRY(645),\n+\tICE_PTT_UNUSED_ENTRY(646),\n+\tICE_PTT_UNUSED_ENTRY(647),\n+\tICE_PTT_UNUSED_ENTRY(648),\n+\tICE_PTT_UNUSED_ENTRY(649),\n+\n+\tICE_PTT_UNUSED_ENTRY(650),\n+\tICE_PTT_UNUSED_ENTRY(651),\n+\tICE_PTT_UNUSED_ENTRY(652),\n+\tICE_PTT_UNUSED_ENTRY(653),\n+\tICE_PTT_UNUSED_ENTRY(654),\n+\tICE_PTT_UNUSED_ENTRY(655),\n+\tICE_PTT_UNUSED_ENTRY(656),\n+\tICE_PTT_UNUSED_ENTRY(657),\n+\tICE_PTT_UNUSED_ENTRY(658),\n+\tICE_PTT_UNUSED_ENTRY(659),\n+\n+\tICE_PTT_UNUSED_ENTRY(660),\n+\tICE_PTT_UNUSED_ENTRY(661),\n+\tICE_PTT_UNUSED_ENTRY(662),\n+\tICE_PTT_UNUSED_ENTRY(663),\n+\tICE_PTT_UNUSED_ENTRY(664),\n+\tICE_PTT_UNUSED_ENTRY(665),\n+\tICE_PTT_UNUSED_ENTRY(666),\n+\tICE_PTT_UNUSED_ENTRY(667),\n+\tICE_PTT_UNUSED_ENTRY(668),\n+\tICE_PTT_UNUSED_ENTRY(669),\n+\n+\tICE_PTT_UNUSED_ENTRY(670),\n+\tICE_PTT_UNUSED_ENTRY(671),\n+\tICE_PTT_UNUSED_ENTRY(672),\n+\tICE_PTT_UNUSED_ENTRY(673),\n+\tICE_PTT_UNUSED_ENTRY(674),\n+\tICE_PTT_UNUSED_ENTRY(675),\n+\tICE_PTT_UNUSED_ENTRY(676),\n+\tICE_PTT_UNUSED_ENTRY(677),\n+\tICE_PTT_UNUSED_ENTRY(678),\n+\tICE_PTT_UNUSED_ENTRY(679),\n+\n+\tICE_PTT_UNUSED_ENTRY(680),\n+\tICE_PTT_UNUSED_ENTRY(681),\n+\tICE_PTT_UNUSED_ENTRY(682),\n+\tICE_PTT_UNUSED_ENTRY(683),\n+\tICE_PTT_UNUSED_ENTRY(684),\n+\tICE_PTT_UNUSED_ENTRY(685),\n+\tICE_PTT_UNUSED_ENTRY(686),\n+\tICE_PTT_UNUSED_ENTRY(687),\n+\tICE_PTT_UNUSED_ENTRY(688),\n+\tICE_PTT_UNUSED_ENTRY(689),\n+\n+\tICE_PTT_UNUSED_ENTRY(690),\n+\tICE_PTT_UNUSED_ENTRY(691),\n+\tICE_PTT_UNUSED_ENTRY(692),\n+\tICE_PTT_UNUSED_ENTRY(693),\n+\tICE_PTT_UNUSED_ENTRY(694),\n+\tICE_PTT_UNUSED_ENTRY(695),\n+\tICE_PTT_UNUSED_ENTRY(696),\n+\tICE_PTT_UNUSED_ENTRY(697),\n+\tICE_PTT_UNUSED_ENTRY(698),\n+\tICE_PTT_UNUSED_ENTRY(699),\n+\n+\tICE_PTT_UNUSED_ENTRY(700),\n+\tICE_PTT_UNUSED_ENTRY(701),\n+\tICE_PTT_UNUSED_ENTRY(702),\n+\tICE_PTT_UNUSED_ENTRY(703),\n+\tICE_PTT_UNUSED_ENTRY(704),\n+\tICE_PTT_UNUSED_ENTRY(705),\n+\tICE_PTT_UNUSED_ENTRY(706),\n+\tICE_PTT_UNUSED_ENTRY(707),\n+\tICE_PTT_UNUSED_ENTRY(708),\n+\tICE_PTT_UNUSED_ENTRY(709),\n+\n+\tICE_PTT_UNUSED_ENTRY(710),\n+\tICE_PTT_UNUSED_ENTRY(711),\n+\tICE_PTT_UNUSED_ENTRY(712),\n+\tICE_PTT_UNUSED_ENTRY(713),\n+\tICE_PTT_UNUSED_ENTRY(714),\n+\tICE_PTT_UNUSED_ENTRY(715),\n+\tICE_PTT_UNUSED_ENTRY(716),\n+\tICE_PTT_UNUSED_ENTRY(717),\n+\tICE_PTT_UNUSED_ENTRY(718),\n+\tICE_PTT_UNUSED_ENTRY(719),\n+\n+\tICE_PTT_UNUSED_ENTRY(720),\n+\tICE_PTT_UNUSED_ENTRY(721),\n+\tICE_PTT_UNUSED_ENTRY(722),\n+\tICE_PTT_UNUSED_ENTRY(723),\n+\tICE_PTT_UNUSED_ENTRY(724),\n+\tICE_PTT_UNUSED_ENTRY(725),\n+\tICE_PTT_UNUSED_ENTRY(726),\n+\tICE_PTT_UNUSED_ENTRY(727),\n+\tICE_PTT_UNUSED_ENTRY(728),\n+\tICE_PTT_UNUSED_ENTRY(729),\n+\n+\tICE_PTT_UNUSED_ENTRY(730),\n+\tICE_PTT_UNUSED_ENTRY(731),\n+\tICE_PTT_UNUSED_ENTRY(732),\n+\tICE_PTT_UNUSED_ENTRY(733),\n+\tICE_PTT_UNUSED_ENTRY(734),\n+\tICE_PTT_UNUSED_ENTRY(735),\n+\tICE_PTT_UNUSED_ENTRY(736),\n+\tICE_PTT_UNUSED_ENTRY(737),\n+\tICE_PTT_UNUSED_ENTRY(738),\n+\tICE_PTT_UNUSED_ENTRY(739),\n+\n+\tICE_PTT_UNUSED_ENTRY(740),\n+\tICE_PTT_UNUSED_ENTRY(741),\n+\tICE_PTT_UNUSED_ENTRY(742),\n+\tICE_PTT_UNUSED_ENTRY(743),\n+\tICE_PTT_UNUSED_ENTRY(744),\n+\tICE_PTT_UNUSED_ENTRY(745),\n+\tICE_PTT_UNUSED_ENTRY(746),\n+\tICE_PTT_UNUSED_ENTRY(747),\n+\tICE_PTT_UNUSED_ENTRY(748),\n+\tICE_PTT_UNUSED_ENTRY(749),\n+\n+\tICE_PTT_UNUSED_ENTRY(750),\n+\tICE_PTT_UNUSED_ENTRY(751),\n+\tICE_PTT_UNUSED_ENTRY(752),\n+\tICE_PTT_UNUSED_ENTRY(753),\n+\tICE_PTT_UNUSED_ENTRY(754),\n+\tICE_PTT_UNUSED_ENTRY(755),\n+\tICE_PTT_UNUSED_ENTRY(756),\n+\tICE_PTT_UNUSED_ENTRY(757),\n+\tICE_PTT_UNUSED_ENTRY(758),\n+\tICE_PTT_UNUSED_ENTRY(759),\n+\n+\tICE_PTT_UNUSED_ENTRY(760),\n+\tICE_PTT_UNUSED_ENTRY(761),\n+\tICE_PTT_UNUSED_ENTRY(762),\n+\tICE_PTT_UNUSED_ENTRY(763),\n+\tICE_PTT_UNUSED_ENTRY(764),\n+\tICE_PTT_UNUSED_ENTRY(765),\n+\tICE_PTT_UNUSED_ENTRY(766),\n+\tICE_PTT_UNUSED_ENTRY(767),\n+\tICE_PTT_UNUSED_ENTRY(768),\n+\tICE_PTT_UNUSED_ENTRY(769),\n+\n+\tICE_PTT_UNUSED_ENTRY(770),\n+\tICE_PTT_UNUSED_ENTRY(771),\n+\tICE_PTT_UNUSED_ENTRY(772),\n+\tICE_PTT_UNUSED_ENTRY(773),\n+\tICE_PTT_UNUSED_ENTRY(774),\n+\tICE_PTT_UNUSED_ENTRY(775),\n+\tICE_PTT_UNUSED_ENTRY(776),\n+\tICE_PTT_UNUSED_ENTRY(777),\n+\tICE_PTT_UNUSED_ENTRY(778),\n+\tICE_PTT_UNUSED_ENTRY(779),\n+\n+\tICE_PTT_UNUSED_ENTRY(780),\n+\tICE_PTT_UNUSED_ENTRY(781),\n+\tICE_PTT_UNUSED_ENTRY(782),\n+\tICE_PTT_UNUSED_ENTRY(783),\n+\tICE_PTT_UNUSED_ENTRY(784),\n+\tICE_PTT_UNUSED_ENTRY(785),\n+\tICE_PTT_UNUSED_ENTRY(786),\n+\tICE_PTT_UNUSED_ENTRY(787),\n+\tICE_PTT_UNUSED_ENTRY(788),\n+\tICE_PTT_UNUSED_ENTRY(789),\n+\n+\tICE_PTT_UNUSED_ENTRY(790),\n+\tICE_PTT_UNUSED_ENTRY(791),\n+\tICE_PTT_UNUSED_ENTRY(792),\n+\tICE_PTT_UNUSED_ENTRY(793),\n+\tICE_PTT_UNUSED_ENTRY(794),\n+\tICE_PTT_UNUSED_ENTRY(795),\n+\tICE_PTT_UNUSED_ENTRY(796),\n+\tICE_PTT_UNUSED_ENTRY(797),\n+\tICE_PTT_UNUSED_ENTRY(798),\n+\tICE_PTT_UNUSED_ENTRY(799),\n+\n+\tICE_PTT_UNUSED_ENTRY(800),\n+\tICE_PTT_UNUSED_ENTRY(801),\n+\tICE_PTT_UNUSED_ENTRY(802),\n+\tICE_PTT_UNUSED_ENTRY(803),\n+\tICE_PTT_UNUSED_ENTRY(804),\n+\tICE_PTT_UNUSED_ENTRY(805),\n+\tICE_PTT_UNUSED_ENTRY(806),\n+\tICE_PTT_UNUSED_ENTRY(807),\n+\tICE_PTT_UNUSED_ENTRY(808),\n+\tICE_PTT_UNUSED_ENTRY(809),\n+\n+\tICE_PTT_UNUSED_ENTRY(810),\n+\tICE_PTT_UNUSED_ENTRY(811),\n+\tICE_PTT_UNUSED_ENTRY(812),\n+\tICE_PTT_UNUSED_ENTRY(813),\n+\tICE_PTT_UNUSED_ENTRY(814),\n+\tICE_PTT_UNUSED_ENTRY(815),\n+\tICE_PTT_UNUSED_ENTRY(816),\n+\tICE_PTT_UNUSED_ENTRY(817),\n+\tICE_PTT_UNUSED_ENTRY(818),\n+\tICE_PTT_UNUSED_ENTRY(819),\n+\n+\tICE_PTT_UNUSED_ENTRY(820),\n+\tICE_PTT_UNUSED_ENTRY(821),\n+\tICE_PTT_UNUSED_ENTRY(822),\n+\tICE_PTT_UNUSED_ENTRY(823),\n+\tICE_PTT_UNUSED_ENTRY(824),\n+\tICE_PTT_UNUSED_ENTRY(825),\n+\tICE_PTT_UNUSED_ENTRY(826),\n+\tICE_PTT_UNUSED_ENTRY(827),\n+\tICE_PTT_UNUSED_ENTRY(828),\n+\tICE_PTT_UNUSED_ENTRY(829),\n+\n+\tICE_PTT_UNUSED_ENTRY(830),\n+\tICE_PTT_UNUSED_ENTRY(831),\n+\tICE_PTT_UNUSED_ENTRY(832),\n+\tICE_PTT_UNUSED_ENTRY(833),\n+\tICE_PTT_UNUSED_ENTRY(834),\n+\tICE_PTT_UNUSED_ENTRY(835),\n+\tICE_PTT_UNUSED_ENTRY(836),\n+\tICE_PTT_UNUSED_ENTRY(837),\n+\tICE_PTT_UNUSED_ENTRY(838),\n+\tICE_PTT_UNUSED_ENTRY(839),\n+\n+\tICE_PTT_UNUSED_ENTRY(840),\n+\tICE_PTT_UNUSED_ENTRY(841),\n+\tICE_PTT_UNUSED_ENTRY(842),\n+\tICE_PTT_UNUSED_ENTRY(843),\n+\tICE_PTT_UNUSED_ENTRY(844),\n+\tICE_PTT_UNUSED_ENTRY(845),\n+\tICE_PTT_UNUSED_ENTRY(846),\n+\tICE_PTT_UNUSED_ENTRY(847),\n+\tICE_PTT_UNUSED_ENTRY(848),\n+\tICE_PTT_UNUSED_ENTRY(849),\n+\n+\tICE_PTT_UNUSED_ENTRY(850),\n+\tICE_PTT_UNUSED_ENTRY(851),\n+\tICE_PTT_UNUSED_ENTRY(852),\n+\tICE_PTT_UNUSED_ENTRY(853),\n+\tICE_PTT_UNUSED_ENTRY(854),\n+\tICE_PTT_UNUSED_ENTRY(855),\n+\tICE_PTT_UNUSED_ENTRY(856),\n+\tICE_PTT_UNUSED_ENTRY(857),\n+\tICE_PTT_UNUSED_ENTRY(858),\n+\tICE_PTT_UNUSED_ENTRY(859),\n+\n+\tICE_PTT_UNUSED_ENTRY(860),\n+\tICE_PTT_UNUSED_ENTRY(861),\n+\tICE_PTT_UNUSED_ENTRY(862),\n+\tICE_PTT_UNUSED_ENTRY(863),\n+\tICE_PTT_UNUSED_ENTRY(864),\n+\tICE_PTT_UNUSED_ENTRY(865),\n+\tICE_PTT_UNUSED_ENTRY(866),\n+\tICE_PTT_UNUSED_ENTRY(867),\n+\tICE_PTT_UNUSED_ENTRY(868),\n+\tICE_PTT_UNUSED_ENTRY(869),\n+\n+\tICE_PTT_UNUSED_ENTRY(870),\n+\tICE_PTT_UNUSED_ENTRY(871),\n+\tICE_PTT_UNUSED_ENTRY(872),\n+\tICE_PTT_UNUSED_ENTRY(873),\n+\tICE_PTT_UNUSED_ENTRY(874),\n+\tICE_PTT_UNUSED_ENTRY(875),\n+\tICE_PTT_UNUSED_ENTRY(876),\n+\tICE_PTT_UNUSED_ENTRY(877),\n+\tICE_PTT_UNUSED_ENTRY(878),\n+\tICE_PTT_UNUSED_ENTRY(879),\n+\n+\tICE_PTT_UNUSED_ENTRY(880),\n+\tICE_PTT_UNUSED_ENTRY(881),\n+\tICE_PTT_UNUSED_ENTRY(882),\n+\tICE_PTT_UNUSED_ENTRY(883),\n+\tICE_PTT_UNUSED_ENTRY(884),\n+\tICE_PTT_UNUSED_ENTRY(885),\n+\tICE_PTT_UNUSED_ENTRY(886),\n+\tICE_PTT_UNUSED_ENTRY(887),\n+\tICE_PTT_UNUSED_ENTRY(888),\n+\tICE_PTT_UNUSED_ENTRY(889),\n+\n+\tICE_PTT_UNUSED_ENTRY(890),\n+\tICE_PTT_UNUSED_ENTRY(891),\n+\tICE_PTT_UNUSED_ENTRY(892),\n+\tICE_PTT_UNUSED_ENTRY(893),\n+\tICE_PTT_UNUSED_ENTRY(894),\n+\tICE_PTT_UNUSED_ENTRY(895),\n+\tICE_PTT_UNUSED_ENTRY(896),\n+\tICE_PTT_UNUSED_ENTRY(897),\n+\tICE_PTT_UNUSED_ENTRY(898),\n+\tICE_PTT_UNUSED_ENTRY(899),\n+\n+\tICE_PTT_UNUSED_ENTRY(900),\n+\tICE_PTT_UNUSED_ENTRY(901),\n+\tICE_PTT_UNUSED_ENTRY(902),\n+\tICE_PTT_UNUSED_ENTRY(903),\n+\tICE_PTT_UNUSED_ENTRY(904),\n+\tICE_PTT_UNUSED_ENTRY(905),\n+\tICE_PTT_UNUSED_ENTRY(906),\n+\tICE_PTT_UNUSED_ENTRY(907),\n+\tICE_PTT_UNUSED_ENTRY(908),\n+\tICE_PTT_UNUSED_ENTRY(909),\n+\n+\tICE_PTT_UNUSED_ENTRY(910),\n+\tICE_PTT_UNUSED_ENTRY(911),\n+\tICE_PTT_UNUSED_ENTRY(912),\n+\tICE_PTT_UNUSED_ENTRY(913),\n+\tICE_PTT_UNUSED_ENTRY(914),\n+\tICE_PTT_UNUSED_ENTRY(915),\n+\tICE_PTT_UNUSED_ENTRY(916),\n+\tICE_PTT_UNUSED_ENTRY(917),\n+\tICE_PTT_UNUSED_ENTRY(918),\n+\tICE_PTT_UNUSED_ENTRY(919),\n+\n+\tICE_PTT_UNUSED_ENTRY(920),\n+\tICE_PTT_UNUSED_ENTRY(921),\n+\tICE_PTT_UNUSED_ENTRY(922),\n+\tICE_PTT_UNUSED_ENTRY(923),\n+\tICE_PTT_UNUSED_ENTRY(924),\n+\tICE_PTT_UNUSED_ENTRY(925),\n+\tICE_PTT_UNUSED_ENTRY(926),\n+\tICE_PTT_UNUSED_ENTRY(927),\n+\tICE_PTT_UNUSED_ENTRY(928),\n+\tICE_PTT_UNUSED_ENTRY(929),\n+\n+\tICE_PTT_UNUSED_ENTRY(930),\n+\tICE_PTT_UNUSED_ENTRY(931),\n+\tICE_PTT_UNUSED_ENTRY(932),\n+\tICE_PTT_UNUSED_ENTRY(933),\n+\tICE_PTT_UNUSED_ENTRY(934),\n+\tICE_PTT_UNUSED_ENTRY(935),\n+\tICE_PTT_UNUSED_ENTRY(936),\n+\tICE_PTT_UNUSED_ENTRY(937),\n+\tICE_PTT_UNUSED_ENTRY(938),\n+\tICE_PTT_UNUSED_ENTRY(939),\n+\n+\tICE_PTT_UNUSED_ENTRY(940),\n+\tICE_PTT_UNUSED_ENTRY(941),\n+\tICE_PTT_UNUSED_ENTRY(942),\n+\tICE_PTT_UNUSED_ENTRY(943),\n+\tICE_PTT_UNUSED_ENTRY(944),\n+\tICE_PTT_UNUSED_ENTRY(945),\n+\tICE_PTT_UNUSED_ENTRY(946),\n+\tICE_PTT_UNUSED_ENTRY(947),\n+\tICE_PTT_UNUSED_ENTRY(948),\n+\tICE_PTT_UNUSED_ENTRY(949),\n+\n+\tICE_PTT_UNUSED_ENTRY(950),\n+\tICE_PTT_UNUSED_ENTRY(951),\n+\tICE_PTT_UNUSED_ENTRY(952),\n+\tICE_PTT_UNUSED_ENTRY(953),\n+\tICE_PTT_UNUSED_ENTRY(954),\n+\tICE_PTT_UNUSED_ENTRY(955),\n+\tICE_PTT_UNUSED_ENTRY(956),\n+\tICE_PTT_UNUSED_ENTRY(957),\n+\tICE_PTT_UNUSED_ENTRY(958),\n+\tICE_PTT_UNUSED_ENTRY(959),\n+\n+\tICE_PTT_UNUSED_ENTRY(960),\n+\tICE_PTT_UNUSED_ENTRY(961),\n+\tICE_PTT_UNUSED_ENTRY(962),\n+\tICE_PTT_UNUSED_ENTRY(963),\n+\tICE_PTT_UNUSED_ENTRY(964),\n+\tICE_PTT_UNUSED_ENTRY(965),\n+\tICE_PTT_UNUSED_ENTRY(966),\n+\tICE_PTT_UNUSED_ENTRY(967),\n+\tICE_PTT_UNUSED_ENTRY(968),\n+\tICE_PTT_UNUSED_ENTRY(969),\n+\n+\tICE_PTT_UNUSED_ENTRY(970),\n+\tICE_PTT_UNUSED_ENTRY(971),\n+\tICE_PTT_UNUSED_ENTRY(972),\n+\tICE_PTT_UNUSED_ENTRY(973),\n+\tICE_PTT_UNUSED_ENTRY(974),\n+\tICE_PTT_UNUSED_ENTRY(975),\n+\tICE_PTT_UNUSED_ENTRY(976),\n+\tICE_PTT_UNUSED_ENTRY(977),\n+\tICE_PTT_UNUSED_ENTRY(978),\n+\tICE_PTT_UNUSED_ENTRY(979),\n+\n+\tICE_PTT_UNUSED_ENTRY(980),\n+\tICE_PTT_UNUSED_ENTRY(981),\n+\tICE_PTT_UNUSED_ENTRY(982),\n+\tICE_PTT_UNUSED_ENTRY(983),\n+\tICE_PTT_UNUSED_ENTRY(984),\n+\tICE_PTT_UNUSED_ENTRY(985),\n+\tICE_PTT_UNUSED_ENTRY(986),\n+\tICE_PTT_UNUSED_ENTRY(987),\n+\tICE_PTT_UNUSED_ENTRY(988),\n+\tICE_PTT_UNUSED_ENTRY(989),\n+\n+\tICE_PTT_UNUSED_ENTRY(990),\n+\tICE_PTT_UNUSED_ENTRY(991),\n+\tICE_PTT_UNUSED_ENTRY(992),\n+\tICE_PTT_UNUSED_ENTRY(993),\n+\tICE_PTT_UNUSED_ENTRY(994),\n+\tICE_PTT_UNUSED_ENTRY(995),\n+\tICE_PTT_UNUSED_ENTRY(996),\n+\tICE_PTT_UNUSED_ENTRY(997),\n+\tICE_PTT_UNUSED_ENTRY(998),\n+\tICE_PTT_UNUSED_ENTRY(999),\n+\n+\tICE_PTT_UNUSED_ENTRY(1000),\n+\tICE_PTT_UNUSED_ENTRY(1001),\n+\tICE_PTT_UNUSED_ENTRY(1002),\n+\tICE_PTT_UNUSED_ENTRY(1003),\n+\tICE_PTT_UNUSED_ENTRY(1004),\n+\tICE_PTT_UNUSED_ENTRY(1005),\n+\tICE_PTT_UNUSED_ENTRY(1006),\n+\tICE_PTT_UNUSED_ENTRY(1007),\n+\tICE_PTT_UNUSED_ENTRY(1008),\n+\tICE_PTT_UNUSED_ENTRY(1009),\n+\n+\tICE_PTT_UNUSED_ENTRY(1010),\n+\tICE_PTT_UNUSED_ENTRY(1011),\n+\tICE_PTT_UNUSED_ENTRY(1012),\n+\tICE_PTT_UNUSED_ENTRY(1013),\n+\tICE_PTT_UNUSED_ENTRY(1014),\n+\tICE_PTT_UNUSED_ENTRY(1015),\n+\tICE_PTT_UNUSED_ENTRY(1016),\n+\tICE_PTT_UNUSED_ENTRY(1017),\n+\tICE_PTT_UNUSED_ENTRY(1018),\n+\tICE_PTT_UNUSED_ENTRY(1019),\n+\n+\tICE_PTT_UNUSED_ENTRY(1020),\n+\tICE_PTT_UNUSED_ENTRY(1021),\n+\tICE_PTT_UNUSED_ENTRY(1022),\n+\tICE_PTT_UNUSED_ENTRY(1023),\n+};\n+\n+static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype)\n+{\n+\treturn ice_ptype_lkup[ptype];\n+}\n+\n+#define ICE_LINK_SPEED_UNKNOWN\t\t0\n+#define ICE_LINK_SPEED_10MBPS\t\t10\n+#define ICE_LINK_SPEED_100MBPS\t\t100\n+#define ICE_LINK_SPEED_1000MBPS\t\t1000\n+#define ICE_LINK_SPEED_2500MBPS\t\t2500\n+#define ICE_LINK_SPEED_5000MBPS\t\t5000\n+#define ICE_LINK_SPEED_10000MBPS\t10000\n+#define ICE_LINK_SPEED_20000MBPS\t20000\n+#define ICE_LINK_SPEED_25000MBPS\t25000\n+#define ICE_LINK_SPEED_40000MBPS\t40000\n+#define ICE_LINK_SPEED_50000MBPS\t50000\n+#define ICE_LINK_SPEED_100000MBPS\t100000\n+\n+#endif /* _ICE_LAN_TX_RX_H_ */\n",
    "prefixes": [
        "v5",
        "13/31"
    ]
}