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{
    "id": 48978,
    "url": "https://patches.dpdk.org/api/patches/48978/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-11-git-send-email-wenzhuo.lu@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1545032259-77179-11-git-send-email-wenzhuo.lu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1545032259-77179-11-git-send-email-wenzhuo.lu@intel.com",
    "date": "2018-12-17T07:37:18",
    "name": "[v5,10/31] net/ice/base: add common functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "ad6a6f9fc9e36281c4890c605efab5fdc3fd7128",
    "submitter": {
        "id": 258,
        "url": "https://patches.dpdk.org/api/people/258/?format=api",
        "name": "Wenzhuo Lu",
        "email": "wenzhuo.lu@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "https://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-11-git-send-email-wenzhuo.lu@intel.com/mbox/",
    "series": [
        {
            "id": 2824,
            "url": "https://patches.dpdk.org/api/series/2824/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2824",
            "date": "2018-12-17T07:37:08",
            "name": "A new net PMD - ICE",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/2824/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/48978/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/48978/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BA89B1B857;\n\tMon, 17 Dec 2018 08:33:15 +0100 (CET)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 119291B5AC\n\tfor <dev@dpdk.org>; Mon, 17 Dec 2018 08:33:07 +0100 (CET)",
            "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Dec 2018 23:33:06 -0800",
            "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby orsmga002.jf.intel.com with ESMTP; 16 Dec 2018 23:33:05 -0800"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.56,364,1539673200\"; d=\"scan'208\";a=\"118899169\"",
        "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>",
        "Date": "Mon, 17 Dec 2018 15:37:18 +0800",
        "Message-Id": "<1545032259-77179-11-git-send-email-wenzhuo.lu@intel.com>",
        "X-Mailer": "git-send-email 1.9.3",
        "In-Reply-To": "<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>",
        "References": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v5 10/31] net/ice/base: add common functions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n\nAdd code that multiple other features use.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 3521 +++++++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_common.h |  186 ++\n 2 files changed, 3707 insertions(+)\n create mode 100644 drivers/net/ice/base/ice_common.c\n create mode 100644 drivers/net/ice/base/ice_common.h",
    "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nnew file mode 100644\nindex 0000000..d49264d\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -0,0 +1,3521 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#include \"ice_common.h\"\n+#include \"ice_sched.h\"\n+#include \"ice_adminq_cmd.h\"\n+\n+#include \"ice_flow.h\"\n+#include \"ice_switch.h\"\n+\n+#define ICE_PF_RESET_WAIT_COUNT\t200\n+\n+#define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \\\n+\twr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \\\n+\t     ((ICE_RX_OPC_MDID << \\\n+\t       GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \\\n+\t      GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \\\n+\t     (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \\\n+\t      GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))\n+\n+#define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \\\n+\twr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \\\n+\t     (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \\\n+\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \\\n+\t     (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \\\n+\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \\\n+\t     (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \\\n+\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \\\n+\t     (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \\\n+\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))\n+\n+\n+/**\n+ * ice_set_mac_type - Sets MAC type\n+ * @hw: pointer to the HW structure\n+ *\n+ * This function sets the MAC type of the adapter based on the\n+ * vendor ID and device ID stored in the hw structure.\n+ */\n+static enum ice_status ice_set_mac_type(struct ice_hw *hw)\n+{\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_set_mac_type\\n\");\n+\n+\tif (hw->vendor_id == ICE_INTEL_VENDOR_ID) {\n+\t\tswitch (hw->device_id) {\n+\t\tdefault:\n+\t\t\thw->mac_type = ICE_MAC_GENERIC;\n+\t\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\tstatus = ICE_ERR_DEVICE_NOT_SUPPORTED;\n+\t}\n+\n+\tice_debug(hw, ICE_DBG_INIT, \"found mac_type: %d, status: %d\\n\",\n+\t\t  hw->mac_type, status);\n+\n+\treturn status;\n+}\n+\n+#if defined(FPGA_SUPPORT) || defined(CVL_A0_SUPPORT)\n+void ice_dev_onetime_setup(struct ice_hw *hw)\n+{\n+\t/* configure Rx - set non pxe mode */\n+\twr32(hw, GLLAN_RCTL_0, 0x1);\n+\n+\n+\n+}\n+#endif /* FPGA_SUPPORT || CVL_A0_SUPPORT */\n+\n+/**\n+ * ice_clear_pf_cfg - Clear PF configuration\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port\n+ * configuration, flow director filters, etc.).\n+ */\n+enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+}\n+\n+/**\n+ * ice_aq_manage_mac_read - manage MAC address read command\n+ * @hw: pointer to the hw struct\n+ * @buf: a virtual buffer to hold the manage MAC read response\n+ * @buf_size: Size of the virtual buffer\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function is used to return per PF station MAC address (0x0107).\n+ * NOTE: Upon successful completion of this command, MAC address information\n+ * is returned in user specified buffer. Please interpret user specified\n+ * buffer as \"manage_mac_read\" response.\n+ * Response such as various MAC addresses are stored in HW struct (port.mac)\n+ * ice_aq_discover_caps is expected to be called before this function is called.\n+ */\n+static enum ice_status\n+ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,\n+\t\t       struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_manage_mac_read_resp *resp;\n+\tstruct ice_aqc_manage_mac_read *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\tu16 flags;\n+\tu8 i;\n+\n+\tcmd = &desc.params.mac_read;\n+\n+\tif (buf_size < sizeof(*resp))\n+\t\treturn ICE_ERR_BUF_TOO_SHORT;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (status)\n+\t\treturn status;\n+\n+\tresp = (struct ice_aqc_manage_mac_read_resp *)buf;\n+\tflags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;\n+\n+\tif (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {\n+\t\tice_debug(hw, ICE_DBG_LAN, \"got invalid MAC address\\n\");\n+\t\treturn ICE_ERR_CFG;\n+\t}\n+\n+\t/* A single port can report up to two (LAN and WoL) addresses */\n+\tfor (i = 0; i < cmd->num_addr; i++)\n+\t\tif (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {\n+\t\t\tice_memcpy(hw->port_info->mac.lan_addr,\n+\t\t\t\t   resp[i].mac_addr, ETH_ALEN,\n+\t\t\t\t   ICE_DMA_TO_NONDMA);\n+\t\t\tice_memcpy(hw->port_info->mac.perm_addr,\n+\t\t\t\t   resp[i].mac_addr,\n+\t\t\t\t   ETH_ALEN, ICE_DMA_TO_NONDMA);\n+\t\t\tbreak;\n+\t\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_aq_get_phy_caps - returns PHY capabilities\n+ * @pi: port information structure\n+ * @qual_mods: report qualified modules\n+ * @report_mode: report mode capabilities\n+ * @pcaps: structure for PHY capabilities to be filled\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Returns the various PHY capabilities supported on the Port (0x0600)\n+ */\n+enum ice_status\n+ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,\n+\t\t    struct ice_aqc_get_phy_caps_data *pcaps,\n+\t\t    struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_get_phy_caps *cmd;\n+\tu16 pcaps_size = sizeof(*pcaps);\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.get_phy;\n+\n+\tif (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);\n+\n+\tif (qual_mods)\n+\t\tcmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);\n+\n+\tcmd->param0 |= CPU_TO_LE16(report_mode);\n+\tstatus = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);\n+\n+\tif (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {\n+\t\tpi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);\n+\t\tpi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_get_media_type - Gets media type\n+ * @pi: port information structure\n+ */\n+static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n+{\n+\tstruct ice_link_status *hw_link_info;\n+\n+\tif (!pi)\n+\t\treturn ICE_MEDIA_UNKNOWN;\n+\n+\thw_link_info = &pi->phy.link_info;\n+\tif (hw_link_info->phy_type_low && hw_link_info->phy_type_high)\n+\t\t/* If more than one media type is selected, report unknown */\n+\t\treturn ICE_MEDIA_UNKNOWN;\n+\n+\tif (hw_link_info->phy_type_low) {\n+\t\tswitch (hw_link_info->phy_type_low) {\n+\t\tcase ICE_PHY_TYPE_LOW_1000BASE_SX:\n+\t\tcase ICE_PHY_TYPE_LOW_1000BASE_LX:\n+\t\tcase ICE_PHY_TYPE_LOW_10GBASE_SR:\n+\t\tcase ICE_PHY_TYPE_LOW_10GBASE_LR:\n+\t\tcase ICE_PHY_TYPE_LOW_10G_SFI_C2C:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_SR:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_LR:\n+\t\tcase ICE_PHY_TYPE_LOW_25G_AUI_C2C:\n+\t\tcase ICE_PHY_TYPE_LOW_40GBASE_SR4:\n+\t\tcase ICE_PHY_TYPE_LOW_40GBASE_LR4:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_SR2:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_LR2:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_SR:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_FR:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_LR:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_SR4:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_LR4:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_SR2:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_DR:\n+\t\t\treturn ICE_MEDIA_FIBER;\n+\t\tcase ICE_PHY_TYPE_LOW_100BASE_TX:\n+\t\tcase ICE_PHY_TYPE_LOW_1000BASE_T:\n+\t\tcase ICE_PHY_TYPE_LOW_2500BASE_T:\n+\t\tcase ICE_PHY_TYPE_LOW_5GBASE_T:\n+\t\tcase ICE_PHY_TYPE_LOW_10GBASE_T:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_T:\n+\t\t\treturn ICE_MEDIA_BASET;\n+\t\tcase ICE_PHY_TYPE_LOW_10G_SFI_DA:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR_S:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR1:\n+\t\tcase ICE_PHY_TYPE_LOW_40GBASE_CR4:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_CR2:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_CP:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_CR4:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_CP2:\n+\t\t\treturn ICE_MEDIA_DA;\n+\t\tcase ICE_PHY_TYPE_LOW_1000BASE_KX:\n+\t\tcase ICE_PHY_TYPE_LOW_2500BASE_KX:\n+\t\tcase ICE_PHY_TYPE_LOW_2500BASE_X:\n+\t\tcase ICE_PHY_TYPE_LOW_5GBASE_KR:\n+\t\tcase ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR1:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR_S:\n+\t\tcase ICE_PHY_TYPE_LOW_40GBASE_KR4:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:\n+\t\tcase ICE_PHY_TYPE_LOW_50GBASE_KR2:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_KR4:\n+\t\tcase ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:\n+\t\t\treturn ICE_MEDIA_BACKPLANE;\n+\t\t}\n+\t} else {\n+\t\tswitch (hw_link_info->phy_type_high) {\n+\t\tcase ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:\n+\t\t\treturn ICE_MEDIA_BACKPLANE;\n+\t\t}\n+\t}\n+\treturn ICE_MEDIA_UNKNOWN;\n+}\n+\n+/**\n+ * ice_aq_get_link_info\n+ * @pi: port information structure\n+ * @ena_lse: enable/disable LinkStatusEvent reporting\n+ * @link: pointer to link status structure - optional\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Get Link Status (0x607). Returns the link status of the adapter.\n+ */\n+enum ice_status\n+ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n+\t\t     struct ice_link_status *link, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_link_status *hw_link_info_old, *hw_link_info;\n+\tstruct ice_aqc_get_link_status_data link_data = { 0 };\n+\tstruct ice_aqc_get_link_status *resp;\n+\tenum ice_media_type *hw_media_type;\n+\tstruct ice_fc_info *hw_fc_info;\n+\tbool tx_pause, rx_pause;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\tu16 cmd_flags;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\thw_link_info_old = &pi->phy.link_info_old;\n+\thw_media_type = &pi->phy.media_type;\n+\thw_link_info = &pi->phy.link_info;\n+\thw_fc_info = &pi->fc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);\n+\tcmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;\n+\tresp = &desc.params.get_link_status;\n+\tresp->cmd_flags = CPU_TO_LE16(cmd_flags);\n+\tresp->lport_num = pi->lport;\n+\n+\tstatus = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data),\n+\t\t\t\t cd);\n+\n+\tif (status != ICE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* save off old link status information */\n+\t*hw_link_info_old = *hw_link_info;\n+\n+\t/* update current link status information */\n+\thw_link_info->link_speed = LE16_TO_CPU(link_data.link_speed);\n+\thw_link_info->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);\n+\thw_link_info->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);\n+\t*hw_media_type = ice_get_media_type(pi);\n+\thw_link_info->link_info = link_data.link_info;\n+\thw_link_info->an_info = link_data.an_info;\n+\thw_link_info->ext_info = link_data.ext_info;\n+\thw_link_info->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);\n+\thw_link_info->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;\n+\thw_link_info->topo_media_conflict = link_data.topo_media_conflict;\n+\thw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M;\n+\n+\t/* update fc info */\n+\ttx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);\n+\trx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);\n+\tif (tx_pause && rx_pause)\n+\t\thw_fc_info->current_mode = ICE_FC_FULL;\n+\telse if (tx_pause)\n+\t\thw_fc_info->current_mode = ICE_FC_TX_PAUSE;\n+\telse if (rx_pause)\n+\t\thw_fc_info->current_mode = ICE_FC_RX_PAUSE;\n+\telse\n+\t\thw_fc_info->current_mode = ICE_FC_NONE;\n+\n+\thw_link_info->lse_ena =\n+\t\t!!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));\n+\n+\n+\t/* save link status information */\n+\tif (link)\n+\t\t*link = *hw_link_info;\n+\n+\t/* flag cleared so calling functions don't call AQ again */\n+\tpi->phy.get_link_info = false;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_init_flex_flags\n+ * @hw: pointer to the hardware structure\n+ * @prof_id: Rx Descriptor Builder profile ID\n+ *\n+ * Function to initialize Rx flex flags\n+ */\n+static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)\n+{\n+\tu8 idx = 0;\n+\n+\t/* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:\n+\t * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE\n+\t * flexiflags1[3:0] - Not used for flag programming\n+\t * flexiflags2[7:0] - Tunnel and VLAN types\n+\t * 2 invalid fields in last index\n+\t */\n+\tswitch (prof_id) {\n+\t/* Rx flex flags are currently programmed for the NIC profiles only.\n+\t * Different flag bit programming configurations can be added per\n+\t * profile as needed.\n+\t */\n+\tcase ICE_RXDID_FLEX_NIC:\n+\tcase ICE_RXDID_FLEX_NIC_2:\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_FRG,\n+\t\t\t\t   ICE_RXFLG_UDP_GRE, ICE_RXFLG_PKT_DSI,\n+\t\t\t\t   ICE_RXFLG_FIN, idx++);\n+\t\t/* flex flag 1 is not used for flexi-flag programming, skipping\n+\t\t * these four FLG64 bits.\n+\t\t */\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_SYN, ICE_RXFLG_RST,\n+\t\t\t\t   ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_DSI,\n+\t\t\t\t   ICE_RXFLG_PKT_DSI, ICE_RXFLG_EVLAN_x8100,\n+\t\t\t\t   ICE_RXFLG_EVLAN_x9100, idx++);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_VLAN_x8100,\n+\t\t\t\t   ICE_RXFLG_TNL_VLAN, ICE_RXFLG_TNL_MAC,\n+\t\t\t\t   ICE_RXFLG_TNL0, idx++);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2,\n+\t\t\t\t   ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Flag programming for profile ID %d not supported\\n\",\n+\t\t\t  prof_id);\n+\t}\n+}\n+\n+/**\n+ * ice_init_flex_flds\n+ * @hw: pointer to the hardware structure\n+ * @prof_id: Rx Descriptor Builder profile ID\n+ *\n+ * Function to initialize flex descriptors\n+ */\n+static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)\n+{\n+\tenum ice_flex_rx_mdid mdid;\n+\n+\tswitch (prof_id) {\n+\tcase ICE_RXDID_FLEX_NIC:\n+\tcase ICE_RXDID_FLEX_NIC_2:\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0);\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1);\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2);\n+\n+\t\tmdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?\n+\t\t\tICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH;\n+\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);\n+\n+\t\tice_init_flex_flags(hw, prof_id);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Field init for profile ID %d not supported\\n\",\n+\t\t\t  prof_id);\n+\t}\n+}\n+\n+\n+/**\n+ * ice_init_fltr_mgmt_struct - initializes filter management list and locks\n+ * @hw: pointer to the hw struct\n+ */\n+static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)\n+{\n+\tstruct ice_switch_info *sw;\n+\n+\thw->switch_info = (struct ice_switch_info *)\n+\t\t\t  ice_malloc(hw, sizeof(*hw->switch_info));\n+\tsw = hw->switch_info;\n+\n+\tif (!sw)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tINIT_LIST_HEAD(&sw->vsi_list_map_head);\n+\n+\treturn ice_init_def_sw_recp(hw);\n+}\n+\n+/**\n+ * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks\n+ * @hw: pointer to the hw struct\n+ */\n+static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tstruct ice_vsi_list_map_info *v_pos_map;\n+\tstruct ice_vsi_list_map_info *v_tmp_map;\n+\tstruct ice_sw_recipe *recps;\n+\tu8 i;\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,\n+\t\t\t\t ice_vsi_list_map_info, list_entry) {\n+\t\tLIST_DEL(&v_pos_map->list_entry);\n+\t\tice_free(hw, v_pos_map);\n+\t}\n+\trecps = hw->switch_info->recp_list;\n+\tfor (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {\n+\t\trecps[i].root_rid = i;\n+\n+\t\tif (recps[i].adv_rule) {\n+\t\t\tstruct ice_adv_fltr_mgmt_list_entry *tmp_entry;\n+\t\t\tstruct ice_adv_fltr_mgmt_list_entry *lst_itr;\n+\n+\t\t\tice_destroy_lock(&recps[i].filt_rule_lock);\n+\t\t\tLIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,\n+\t\t\t\t\t\t &recps[i].filt_rules,\n+\t\t\t\t\t\t ice_adv_fltr_mgmt_list_entry,\n+\t\t\t\t\t\t list_entry) {\n+\t\t\t\tLIST_DEL(&lst_itr->list_entry);\n+\t\t\t\tice_free(hw, lst_itr->lkups);\n+\t\t\t\tice_free(hw, lst_itr);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tstruct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;\n+\n+\t\t\tice_destroy_lock(&recps[i].filt_rule_lock);\n+\t\t\tLIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,\n+\t\t\t\t\t\t &recps[i].filt_rules,\n+\t\t\t\t\t\t ice_fltr_mgmt_list_entry,\n+\t\t\t\t\t\t list_entry) {\n+\t\t\t\tLIST_DEL(&lst_itr->list_entry);\n+\t\t\t\tice_free(hw, lst_itr);\n+\t\t\t}\n+\t\t}\n+\t}\n+\tice_rm_all_sw_replay_rule_info(hw);\n+\tice_free(hw, sw->recp_list);\n+\tice_free(hw, sw);\n+}\n+\n+#define ICE_FW_LOG_DESC_SIZE(n)\t(sizeof(struct ice_aqc_fw_logging_data) + \\\n+\t(((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))\n+#define ICE_FW_LOG_DESC_SIZE_MAX\t\\\n+\tICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)\n+\n+/**\n+ * ice_cfg_fw_log - configure FW logging\n+ * @hw: pointer to the hw struct\n+ * @enable: enable certain FW logging events if true, disable all if false\n+ *\n+ * This function enables/disables the FW logging via Rx CQ events and a UART\n+ * port based on predetermined configurations. FW logging via the Rx CQ can be\n+ * enabled/disabled for individual PF's. However, FW logging via the UART can\n+ * only be enabled/disabled for all PFs on the same device.\n+ *\n+ * To enable overall FW logging, the \"cq_en\" and \"uart_en\" enable bits in\n+ * hw->fw_log need to be set accordingly, e.g. based on user-provided input,\n+ * before initializing the device.\n+ *\n+ * When re/configuring FW logging, callers need to update the \"cfg\" elements of\n+ * the hw->fw_log.evnts array with the desired logging event configurations for\n+ * modules of interest. When disabling FW logging completely, the callers can\n+ * just pass false in the \"enable\" parameter. On completion, the function will\n+ * update the \"cur\" element of the hw->fw_log.evnts array with the resulting\n+ * logging event configurations of the modules that are being re/configured. FW\n+ * logging modules that are not part of a reconfiguration operation retain their\n+ * previous states.\n+ *\n+ * Before resetting the device, it is recommended that the driver disables FW\n+ * logging before shutting down the control queue. When disabling FW logging\n+ * (\"enable\" = false), the latest configurations of FW logging events stored in\n+ * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after\n+ * a device reset.\n+ *\n+ * When enabling FW logging to emit log messages via the Rx CQ during the\n+ * device's initialization phase, a mechanism alternative to interrupt handlers\n+ * needs to be used to extract FW log messages from the Rx CQ periodically and\n+ * to prevent the Rx CQ from being full and stalling other types of control\n+ * messages from FW to SW. Interrupts are typically disabled during the device's\n+ * initialization phase.\n+ */\n+static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)\n+{\n+\tstruct ice_aqc_fw_logging_data *data = NULL;\n+\tstruct ice_aqc_fw_logging *cmd;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu16 i, chgs = 0, len = 0;\n+\tstruct ice_aq_desc desc;\n+\tu8 actv_evnts = 0;\n+\tvoid *buf = NULL;\n+\n+\tif (!hw->fw_log.cq_en && !hw->fw_log.uart_en)\n+\t\treturn ICE_SUCCESS;\n+\n+\t/* Disable FW logging only when the control queue is still responsive */\n+\tif (!enable &&\n+\t    (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))\n+\t\treturn ICE_SUCCESS;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);\n+\tcmd = &desc.params.fw_logging;\n+\n+\t/* Indicate which controls are valid */\n+\tif (hw->fw_log.cq_en)\n+\t\tcmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;\n+\n+\tif (hw->fw_log.uart_en)\n+\t\tcmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;\n+\n+\tif (enable) {\n+\t\t/* Fill in an array of entries with FW logging modules and\n+\t\t * logging events being reconfigured.\n+\t\t */\n+\t\tfor (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {\n+\t\t\tu16 val;\n+\n+\t\t\t/* Keep track of enabled event types */\n+\t\t\tactv_evnts |= hw->fw_log.evnts[i].cfg;\n+\n+\t\t\tif (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (!data) {\n+\t\t\t\tdata = (struct ice_aqc_fw_logging_data *)\n+\t\t\t\t\tice_malloc(hw,\n+\t\t\t\t\t\t   ICE_FW_LOG_DESC_SIZE_MAX);\n+\t\t\t\tif (!data)\n+\t\t\t\t\treturn ICE_ERR_NO_MEMORY;\n+\t\t\t}\n+\n+\t\t\tval = i << ICE_AQC_FW_LOG_ID_S;\n+\t\t\tval |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;\n+\t\t\tdata->entry[chgs++] = CPU_TO_LE16(val);\n+\t\t}\n+\n+\t\t/* Only enable FW logging if at least one module is specified.\n+\t\t * If FW logging is currently enabled but all modules are not\n+\t\t * enabled to emit log messages, disable FW logging altogether.\n+\t\t */\n+\t\tif (actv_evnts) {\n+\t\t\t/* Leave if there is effectively no change */\n+\t\t\tif (!chgs)\n+\t\t\t\tgoto out;\n+\n+\t\t\tif (hw->fw_log.cq_en)\n+\t\t\t\tcmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;\n+\n+\t\t\tif (hw->fw_log.uart_en)\n+\t\t\t\tcmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;\n+\n+\t\t\tbuf = data;\n+\t\t\tlen = ICE_FW_LOG_DESC_SIZE(chgs);\n+\t\t\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\t\t}\n+\t}\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, len, NULL);\n+\tif (!status) {\n+\t\t/* Update the current configuration to reflect events enabled.\n+\t\t * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW\n+\t\t * logging mode is enabled for the device. They do not reflect\n+\t\t * actual modules being enabled to emit log messages. So, their\n+\t\t * values remain unchanged even when all modules are disabled.\n+\t\t */\n+\t\tu16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;\n+\n+\t\thw->fw_log.actv_evnts = actv_evnts;\n+\t\tfor (i = 0; i < cnt; i++) {\n+\t\t\tu16 v, m;\n+\n+\t\t\tif (!enable) {\n+\t\t\t\t/* When disabling all FW logging events as part\n+\t\t\t\t * of device's de-initialization, the original\n+\t\t\t\t * configurations are retained, and can be used\n+\t\t\t\t * to reconfigure FW logging later if the device\n+\t\t\t\t * is re-initialized.\n+\t\t\t\t */\n+\t\t\t\thw->fw_log.evnts[i].cur = 0;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tv = LE16_TO_CPU(data->entry[i]);\n+\t\t\tm = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;\n+\t\t\thw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;\n+\t\t}\n+\t}\n+\n+out:\n+\tif (data)\n+\t\tice_free(hw, data);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_output_fw_log\n+ * @hw: pointer to the hw struct\n+ * @desc: pointer to the AQ message descriptor\n+ * @buf: pointer to the buffer accompanying the AQ message\n+ *\n+ * Formats a FW Log message and outputs it via the standard driver logs.\n+ */\n+void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)\n+{\n+\tice_debug(hw, ICE_DBG_AQ_MSG, \"[ FW Log Msg Start ]\\n\");\n+\tice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf,\n+\t\t\tLE16_TO_CPU(desc->datalen));\n+\tice_debug(hw, ICE_DBG_AQ_MSG, \"[ FW Log Msg End ]\\n\");\n+}\n+\n+/**\n+ * ice_get_itr_intrl_gran - determine int/intrl granularity\n+ * @hw: pointer to the hw struct\n+ *\n+ * Determines the itr/intrl granularities based on the maximum aggregate\n+ * bandwidth according to the device's configuration during power-on.\n+ */\n+static enum ice_status ice_get_itr_intrl_gran(struct ice_hw *hw)\n+{\n+\tu8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &\n+\t\t\t GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>\n+\t\t\tGL_PWR_MODE_CTL_CAR_MAX_BW_S;\n+\n+\tswitch (max_agg_bw) {\n+\tcase ICE_MAX_AGG_BW_200G:\n+\tcase ICE_MAX_AGG_BW_100G:\n+\tcase ICE_MAX_AGG_BW_50G:\n+\t\thw->itr_gran = ICE_ITR_GRAN_ABOVE_25;\n+\t\thw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;\n+\t\tbreak;\n+\tcase ICE_MAX_AGG_BW_25G:\n+\t\thw->itr_gran = ICE_ITR_GRAN_MAX_25;\n+\t\thw->intrl_gran = ICE_INTRL_GRAN_MAX_25;\n+\t\tbreak;\n+\tdefault:\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Failed to determine itr/intrl granularity\\n\");\n+\t\treturn ICE_ERR_CFG;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_init_hw - main hardware initialization routine\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_init_hw(struct ice_hw *hw)\n+{\n+\tstruct ice_aqc_get_phy_caps_data *pcaps;\n+\tenum ice_status status;\n+\tu16 mac_buf_len;\n+\tvoid *mac_buf;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_init_hw\");\n+\n+\n+\t/* Set MAC type based on DeviceID */\n+\tstatus = ice_set_mac_type(hw);\n+\tif (status)\n+\t\treturn status;\n+\n+\thw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &\n+\t\t\t PF_FUNC_RID_FUNCTION_NUMBER_M) >>\n+\t\tPF_FUNC_RID_FUNCTION_NUMBER_S;\n+\n+\n+\tstatus = ice_reset(hw, ICE_RESET_PFR);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_get_itr_intrl_gran(hw);\n+\tif (status)\n+\t\treturn status;\n+\n+\n+\tstatus = ice_init_all_ctrlq(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\t/* Enable FW logging. Not fatal if this fails. */\n+\tstatus = ice_cfg_fw_log(hw, true);\n+\tif (status)\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to enable FW logging.\\n\");\n+\n+\tstatus = ice_clear_pf_cfg(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\n+\tice_clear_pxe_mode(hw);\n+\n+\tstatus = ice_init_nvm(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\tstatus = ice_get_caps(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\thw->port_info = (struct ice_port_info *)\n+\t\t\tice_malloc(hw, sizeof(*hw->port_info));\n+\tif (!hw->port_info) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto err_unroll_cqinit;\n+\t}\n+\n+\t/* set the back pointer to hw */\n+\thw->port_info->hw = hw;\n+\n+\t/* Initialize port_info struct with switch configuration data */\n+\tstatus = ice_get_initial_sw_cfg(hw);\n+\tif (status)\n+\t\tgoto err_unroll_alloc;\n+\n+\thw->evb_veb = true;\n+\n+\t/* Query the allocated resources for Tx scheduler */\n+\tstatus = ice_sched_query_res_alloc(hw);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t  \"Failed to get scheduler allocated resources\\n\");\n+\t\tgoto err_unroll_alloc;\n+\t}\n+\n+\n+\t/* Initialize port_info struct with scheduler data */\n+\tstatus = ice_sched_init_port(hw->port_info);\n+\tif (status)\n+\t\tgoto err_unroll_sched;\n+\n+\tpcaps = (struct ice_aqc_get_phy_caps_data *)\n+\t\tice_malloc(hw, sizeof(*pcaps));\n+\tif (!pcaps) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto err_unroll_sched;\n+\t}\n+\n+\t/* Initialize port_info struct with PHY capabilities */\n+\tstatus = ice_aq_get_phy_caps(hw->port_info, false,\n+\t\t\t\t     ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);\n+\tice_free(hw, pcaps);\n+\tif (status)\n+\t\tgoto err_unroll_sched;\n+\n+\t/* Initialize port_info struct with link information */\n+\tstatus = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);\n+\tif (status)\n+\t\tgoto err_unroll_sched;\n+\t/* need a valid SW entry point to build a Tx tree */\n+\tif (!hw->sw_entry_point_layer) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"invalid sw entry point\\n\");\n+\t\tstatus = ICE_ERR_CFG;\n+\t\tgoto err_unroll_sched;\n+\t}\n+\tINIT_LIST_HEAD(&hw->agg_list);\n+\t/* Initialize max burst size */\n+\tif (!hw->max_burst_size)\n+\t\tice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);\n+\n+\tstatus = ice_init_fltr_mgmt_struct(hw);\n+\tif (status)\n+\t\tgoto err_unroll_sched;\n+\n+#if defined(FPGA_SUPPORT) || defined(CVL_A0_SUPPORT)\n+\t/* some of the register write workarounds to get Rx working */\n+\tice_dev_onetime_setup(hw);\n+#endif /* FPGA_SUPPORT || CVL_A0_SUPPORT */\n+\n+\t/* Get MAC information */\n+\t/* A single port can report up to two (LAN and WoL) addresses */\n+\tmac_buf = ice_calloc(hw, 2,\n+\t\t\t     sizeof(struct ice_aqc_manage_mac_read_resp));\n+\tmac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);\n+\n+\tif (!mac_buf) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto err_unroll_fltr_mgmt_struct;\n+\t}\n+\n+\tstatus = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);\n+\tice_free(hw, mac_buf);\n+\n+\tif (status)\n+\t\tgoto err_unroll_fltr_mgmt_struct;\n+\n+\tice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);\n+\tice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);\n+\n+\n+\treturn ICE_SUCCESS;\n+\n+err_unroll_fltr_mgmt_struct:\n+\tice_cleanup_fltr_mgmt_struct(hw);\n+err_unroll_sched:\n+\tice_sched_cleanup_all(hw);\n+err_unroll_alloc:\n+\tice_free(hw, hw->port_info);\n+\thw->port_info = NULL;\n+err_unroll_cqinit:\n+\tice_shutdown_all_ctrlq(hw);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_deinit_hw - unroll initialization operations done by ice_init_hw\n+ * @hw: pointer to the hardware structure\n+ *\n+ * This should be called only during nominal operation, not as a result of\n+ * ice_init_hw() failing since ice_init_hw() will take care of unrolling\n+ * applicable initializations if it fails for any reason.\n+ */\n+void ice_deinit_hw(struct ice_hw *hw)\n+{\n+\tice_cleanup_fltr_mgmt_struct(hw);\n+\n+\tice_sched_cleanup_all(hw);\n+\tice_sched_clear_agg(hw);\n+\n+\tif (hw->port_info) {\n+\t\tice_free(hw, hw->port_info);\n+\t\thw->port_info = NULL;\n+\t}\n+\n+\t/* Attempt to disable FW logging before shutting down control queues */\n+\tice_cfg_fw_log(hw, false);\n+\tice_shutdown_all_ctrlq(hw);\n+\n+\t/* Clear VSI contexts if not already cleared */\n+\tice_clear_all_vsi_ctx(hw);\n+}\n+\n+/**\n+ * ice_check_reset - Check to see if a global reset is complete\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_check_reset(struct ice_hw *hw)\n+{\n+\tu32 cnt, reg = 0, grst_delay;\n+\n+\t/* Poll for Device Active state in case a recent CORER, GLOBR,\n+\t * or EMPR has occurred. The grst delay value is in 100ms units.\n+\t * Add 1sec for outstanding AQ commands that can take a long time.\n+\t */\n+#define GLGEN_RSTCTL\t\t0x000B8180 /* Reset Source: POR */\n+#define GLGEN_RSTCTL_GRSTDEL_S\t0\n+#define GLGEN_RSTCTL_GRSTDEL_M\tMAKEMASK(0x3F, GLGEN_RSTCTL_GRSTDEL_S)\n+\tgrst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>\n+\t\t      GLGEN_RSTCTL_GRSTDEL_S) + 10;\n+\n+\tfor (cnt = 0; cnt < grst_delay; cnt++) {\n+\t\tice_msec_delay(100, true);\n+\t\treg = rd32(hw, GLGEN_RSTAT);\n+\t\tif (!(reg & GLGEN_RSTAT_DEVSTATE_M))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (cnt == grst_delay) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Global reset polling failed to complete.\\n\");\n+\t\treturn ICE_ERR_RESET_FAILED;\n+\t}\n+\n+#define ICE_RESET_DONE_MASK\t(GLNVM_ULD_CORER_DONE_M | \\\n+\t\t\t\t GLNVM_ULD_GLOBR_DONE_M)\n+\n+\t/* Device is Active; check Global Reset processes are done */\n+\tfor (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {\n+\t\treg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;\n+\t\tif (reg == ICE_RESET_DONE_MASK) {\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"Global reset processes done. %d\\n\", cnt);\n+\t\t\tbreak;\n+\t\t}\n+\t\tice_msec_delay(10, true);\n+\t}\n+\n+\tif (cnt == ICE_PF_RESET_WAIT_COUNT) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Wait for Reset Done timed out. GLNVM_ULD = 0x%x\\n\",\n+\t\t\t  reg);\n+\t\treturn ICE_ERR_RESET_FAILED;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_pf_reset - Reset the PF\n+ * @hw: pointer to the hardware structure\n+ *\n+ * If a global reset has been triggered, this function checks\n+ * for its completion and then issues the PF reset\n+ */\n+static enum ice_status ice_pf_reset(struct ice_hw *hw)\n+{\n+\tu32 cnt, reg;\n+\n+\t/* If at function entry a global reset was already in progress, i.e.\n+\t * state is not 'device active' or any of the reset done bits are not\n+\t * set in GLNVM_ULD, there is no need for a PF Reset; poll until the\n+\t * global reset is done.\n+\t */\n+\tif ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||\n+\t    (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {\n+\t\t/* poll on global reset currently in progress until done */\n+\t\tif (ice_check_reset(hw))\n+\t\t\treturn ICE_ERR_RESET_FAILED;\n+\n+\t\treturn ICE_SUCCESS;\n+\t}\n+\n+\t/* Reset the PF */\n+\treg = rd32(hw, PFGEN_CTRL);\n+\n+\twr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));\n+\n+\tfor (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {\n+\t\treg = rd32(hw, PFGEN_CTRL);\n+\t\tif (!(reg & PFGEN_CTRL_PFSWR_M))\n+\t\t\tbreak;\n+\n+\t\tice_msec_delay(1, true);\n+\t}\n+\n+\tif (cnt == ICE_PF_RESET_WAIT_COUNT) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"PF reset polling failed to complete.\\n\");\n+\t\treturn ICE_ERR_RESET_FAILED;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_reset - Perform different types of reset\n+ * @hw: pointer to the hardware structure\n+ * @req: reset request\n+ *\n+ * This function triggers a reset as specified by the req parameter.\n+ *\n+ * Note:\n+ * If anything other than a PF reset is triggered, PXE mode is restored.\n+ * This has to be cleared using ice_clear_pxe_mode again, once the AQ\n+ * interface has been restored in the rebuild flow.\n+ */\n+enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)\n+{\n+\tu32 val = 0;\n+\n+\tswitch (req) {\n+\tcase ICE_RESET_PFR:\n+\t\treturn ice_pf_reset(hw);\n+\tcase ICE_RESET_CORER:\n+\t\tice_debug(hw, ICE_DBG_INIT, \"CoreR requested\\n\");\n+\t\tval = GLGEN_RTRIG_CORER_M;\n+\t\tbreak;\n+\tcase ICE_RESET_GLOBR:\n+\t\tice_debug(hw, ICE_DBG_INIT, \"GlobalR requested\\n\");\n+\t\tval = GLGEN_RTRIG_GLOBR_M;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tval |= rd32(hw, GLGEN_RTRIG);\n+\twr32(hw, GLGEN_RTRIG, val);\n+\tice_flush(hw);\n+\n+\n+\t/* wait for the FW to be ready */\n+\treturn ice_check_reset(hw);\n+}\n+\n+\n+\n+/**\n+ * ice_copy_rxq_ctx_to_hw\n+ * @hw: pointer to the hardware structure\n+ * @ice_rxq_ctx: pointer to the rxq context\n+ * @rxq_index: the index of the Rx queue\n+ *\n+ * Copies rxq context from dense structure to hw register space\n+ */\n+static enum ice_status\n+ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)\n+{\n+\tu8 i;\n+\n+\tif (!ice_rxq_ctx)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\tif (rxq_index > QRX_CTRL_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Copy each dword separately to hw */\n+\tfor (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {\n+\t\twr32(hw, QRX_CONTEXT(i, rxq_index),\n+\t\t     *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));\n+\n+\t\tice_debug(hw, ICE_DBG_QCTX, \"qrxdata[%d]: %08X\\n\", i,\n+\t\t\t  *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/* LAN Rx Queue Context */\n+static const struct ice_ctx_ele ice_rlan_ctx_info[] = {\n+\t/* Field\t\tWidth\tLSB */\n+\tICE_CTX_STORE(ice_rlan_ctx, head,\t\t13,\t0),\n+\tICE_CTX_STORE(ice_rlan_ctx, cpuid,\t\t8,\t13),\n+\tICE_CTX_STORE(ice_rlan_ctx, base,\t\t57,\t32),\n+\tICE_CTX_STORE(ice_rlan_ctx, qlen,\t\t13,\t89),\n+\tICE_CTX_STORE(ice_rlan_ctx, dbuf,\t\t7,\t102),\n+\tICE_CTX_STORE(ice_rlan_ctx, hbuf,\t\t5,\t109),\n+\tICE_CTX_STORE(ice_rlan_ctx, dtype,\t\t2,\t114),\n+\tICE_CTX_STORE(ice_rlan_ctx, dsize,\t\t1,\t116),\n+\tICE_CTX_STORE(ice_rlan_ctx, crcstrip,\t\t1,\t117),\n+\tICE_CTX_STORE(ice_rlan_ctx, l2tsel,\t\t1,\t119),\n+\tICE_CTX_STORE(ice_rlan_ctx, hsplit_0,\t\t4,\t120),\n+\tICE_CTX_STORE(ice_rlan_ctx, hsplit_1,\t\t2,\t124),\n+\tICE_CTX_STORE(ice_rlan_ctx, showiv,\t\t1,\t127),\n+\tICE_CTX_STORE(ice_rlan_ctx, rxmax,\t\t14,\t174),\n+\tICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena,\t1,\t193),\n+\tICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena,\t1,\t194),\n+\tICE_CTX_STORE(ice_rlan_ctx, tphdata_ena,\t1,\t195),\n+\tICE_CTX_STORE(ice_rlan_ctx, tphhead_ena,\t1,\t196),\n+\tICE_CTX_STORE(ice_rlan_ctx, lrxqthresh,\t\t3,\t198),\n+\t{ 0 }\n+};\n+\n+/**\n+ * ice_write_rxq_ctx\n+ * @hw: pointer to the hardware structure\n+ * @rlan_ctx: pointer to the rxq context\n+ * @rxq_index: the index of the Rx queue\n+ *\n+ * Converts rxq context from sparse to dense structure and then writes\n+ * it to hw register space\n+ */\n+enum ice_status\n+ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n+\t\t  u32 rxq_index)\n+{\n+\tu8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };\n+\n+\tice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);\n+\treturn ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);\n+}\n+\n+#if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)\n+/**\n+ * ice_clear_rxq_ctx\n+ * @hw: pointer to the hardware structure\n+ * @rxq_index: the index of the Rx queue to clear\n+ *\n+ * Clears rxq context in hw register space\n+ */\n+enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)\n+{\n+\tu8 i;\n+\n+\tif (rxq_index > QRX_CTRL_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Clear each dword register separately */\n+\tfor (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)\n+\t\twr32(hw, QRX_CONTEXT(i, rxq_index), 0);\n+\n+\treturn ICE_SUCCESS;\n+}\n+#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */\n+\n+/* LAN Tx Queue Context */\n+const struct ice_ctx_ele ice_tlan_ctx_info[] = {\n+\t\t\t\t    /* Field\t\t\tWidth\tLSB */\n+\tICE_CTX_STORE(ice_tlan_ctx, base,\t\t\t57,\t0),\n+\tICE_CTX_STORE(ice_tlan_ctx, port_num,\t\t\t3,\t57),\n+\tICE_CTX_STORE(ice_tlan_ctx, cgd_num,\t\t\t5,\t60),\n+\tICE_CTX_STORE(ice_tlan_ctx, pf_num,\t\t\t3,\t65),\n+\tICE_CTX_STORE(ice_tlan_ctx, vmvf_num,\t\t\t10,\t68),\n+\tICE_CTX_STORE(ice_tlan_ctx, vmvf_type,\t\t\t2,\t78),\n+\tICE_CTX_STORE(ice_tlan_ctx, src_vsi,\t\t\t10,\t80),\n+\tICE_CTX_STORE(ice_tlan_ctx, tsyn_ena,\t\t\t1,\t90),\n+\tICE_CTX_STORE(ice_tlan_ctx, alt_vlan,\t\t\t1,\t92),\n+\tICE_CTX_STORE(ice_tlan_ctx, cpuid,\t\t\t8,\t93),\n+\tICE_CTX_STORE(ice_tlan_ctx, wb_mode,\t\t\t1,\t101),\n+\tICE_CTX_STORE(ice_tlan_ctx, tphrd_desc,\t\t\t1,\t102),\n+\tICE_CTX_STORE(ice_tlan_ctx, tphrd,\t\t\t1,\t103),\n+\tICE_CTX_STORE(ice_tlan_ctx, tphwr_desc,\t\t\t1,\t104),\n+\tICE_CTX_STORE(ice_tlan_ctx, cmpq_id,\t\t\t9,\t105),\n+\tICE_CTX_STORE(ice_tlan_ctx, qnum_in_func,\t\t14,\t114),\n+\tICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode,\t1,\t128),\n+\tICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id,\t\t6,\t129),\n+\tICE_CTX_STORE(ice_tlan_ctx, qlen,\t\t\t13,\t135),\n+\tICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx,\t\t4,\t148),\n+\tICE_CTX_STORE(ice_tlan_ctx, tso_ena,\t\t\t1,\t152),\n+\tICE_CTX_STORE(ice_tlan_ctx, tso_qnum,\t\t\t11,\t153),\n+\tICE_CTX_STORE(ice_tlan_ctx, legacy_int,\t\t\t1,\t164),\n+\tICE_CTX_STORE(ice_tlan_ctx, drop_ena,\t\t\t1,\t165),\n+\tICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx,\t\t2,\t166),\n+\tICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx,\t3,\t168),\n+\tICE_CTX_STORE(ice_tlan_ctx, int_q_state,\t\t110,\t171),\n+\t{ 0 }\n+};\n+\n+#if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)\n+/**\n+ * ice_copy_tx_cmpltnq_ctx_to_hw\n+ * @hw: pointer to the hardware structure\n+ * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context\n+ * @tx_cmpltnq_index: the index of the completion queue\n+ *\n+ * Copies Tx completion q context from dense structure to hw register space\n+ */\n+static enum ice_status\n+ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,\n+\t\t\t      u32 tx_cmpltnq_index)\n+{\n+\tu8 i;\n+\n+\tif (!ice_tx_cmpltnq_ctx)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\tif (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Copy each dword separately to hw */\n+\tfor (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {\n+\t\twr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),\n+\t\t     *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));\n+\n+\t\tice_debug(hw, ICE_DBG_QCTX, \"cmpltnqdata[%d]: %08X\\n\", i,\n+\t\t\t  *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/* LAN Tx Completion Queue Context */\n+static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {\n+\t\t\t\t       /* Field\t\t\tWidth   LSB */\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, base,\t\t\t57,\t0),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len,\t\t18,\t64),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation,\t\t1,\t96),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr,\t\t22,\t97),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num,\t\t3,\t128),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num,\t\t10,\t131),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type,\t\t2,\t141),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr,\t\t1,\t160),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid,\t\t8,\t161),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache,\t\t512,\t192),\n+\t{ 0 }\n+};\n+\n+/**\n+ * ice_write_tx_cmpltnq_ctx\n+ * @hw: pointer to the hardware structure\n+ * @tx_cmpltnq_ctx: pointer to the completion queue context\n+ * @tx_cmpltnq_index: the index of the completion queue\n+ *\n+ * Converts completion queue context from sparse to dense structure and then\n+ * writes it to hw register space\n+ */\n+enum ice_status\n+ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,\n+\t\t\t struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,\n+\t\t\t u32 tx_cmpltnq_index)\n+{\n+\tu8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };\n+\n+\tice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);\n+\treturn ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);\n+}\n+\n+/**\n+ * ice_clear_tx_cmpltnq_ctx\n+ * @hw: pointer to the hardware structure\n+ * @tx_cmpltnq_index: the index of the completion queue to clear\n+ *\n+ * Clears Tx completion queue context in hw register space\n+ */\n+enum ice_status\n+ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)\n+{\n+\tu8 i;\n+\n+\tif (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Clear each dword register separately */\n+\tfor (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)\n+\t\twr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_copy_tx_drbell_q_ctx_to_hw\n+ * @hw: pointer to the hardware structure\n+ * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context\n+ * @tx_drbell_q_index: the index of the doorbell queue\n+ *\n+ * Copies doorbell q context from dense structure to hw register space\n+ */\n+static enum ice_status\n+ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,\n+\t\t\t       u32 tx_drbell_q_index)\n+{\n+\tu8 i;\n+\n+\tif (!ice_tx_drbell_q_ctx)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\tif (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Copy each dword separately to hw */\n+\tfor (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {\n+\t\twr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),\n+\t\t     *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));\n+\n+\t\tice_debug(hw, ICE_DBG_QCTX, \"tx_drbell_qdata[%d]: %08X\\n\", i,\n+\t\t\t  *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/* LAN Tx Doorbell Queue Context info */\n+static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {\n+\t\t\t\t\t/* Field\t\tWidth   LSB */\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, base,\t\t57,\t0),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len,\t\t13,\t64),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num,\t\t3,\t80),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num,\t\t8,\t84),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type,\t\t2,\t94),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid,\t\t8,\t96),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd,\t\t1,\t104),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr,\t\t1,\t108),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en,\t\t1,\t112),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head,\t\t13,\t128),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail,\t\t13,\t144),\n+\t{ 0 }\n+};\n+\n+/**\n+ * ice_write_tx_drbell_q_ctx\n+ * @hw: pointer to the hardware structure\n+ * @tx_drbell_q_ctx: pointer to the doorbell queue context\n+ * @tx_drbell_q_index: the index of the doorbell queue\n+ *\n+ * Converts doorbell queue context from sparse to dense structure and then\n+ * writes it to hw register space\n+ */\n+enum ice_status\n+ice_write_tx_drbell_q_ctx(struct ice_hw *hw,\n+\t\t\t  struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,\n+\t\t\t  u32 tx_drbell_q_index)\n+{\n+\tu8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };\n+\n+\tice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);\n+\treturn ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);\n+}\n+\n+/**\n+ * ice_clear_tx_drbell_q_ctx\n+ * @hw: pointer to the hardware structure\n+ * @tx_drbell_q_index: the index of the doorbell queue to clear\n+ *\n+ * Clears doorbell queue context in hw register space\n+ */\n+enum ice_status\n+ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)\n+{\n+\tu8 i;\n+\n+\tif (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Clear each dword register separately */\n+\tfor (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)\n+\t\twr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);\n+\n+\treturn ICE_SUCCESS;\n+}\n+#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */\n+\n+/**\n+ * ice_debug_cq\n+ * @hw: pointer to the hardware structure\n+ * @mask: debug mask\n+ * @desc: pointer to control queue descriptor\n+ * @buf: pointer to command buffer\n+ * @buf_len: max length of buf\n+ *\n+ * Dumps debug log about control command with descriptor contents.\n+ */\n+void\n+ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len)\n+{\n+\tstruct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;\n+\tu16 len;\n+\n+\tif (!(mask & hw->debug_mask))\n+\t\treturn;\n+\n+\tif (!desc)\n+\t\treturn;\n+\n+\tlen = LE16_TO_CPU(cq_desc->datalen);\n+\n+\tice_debug(hw, mask,\n+\t\t  \"CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\\n\",\n+\t\t  LE16_TO_CPU(cq_desc->opcode),\n+\t\t  LE16_TO_CPU(cq_desc->flags),\n+\t\t  LE16_TO_CPU(cq_desc->datalen), LE16_TO_CPU(cq_desc->retval));\n+\tice_debug(hw, mask, \"\\tcookie (h,l) 0x%08X 0x%08X\\n\",\n+\t\t  LE32_TO_CPU(cq_desc->cookie_high),\n+\t\t  LE32_TO_CPU(cq_desc->cookie_low));\n+\tice_debug(hw, mask, \"\\tparam (0,1)  0x%08X 0x%08X\\n\",\n+\t\t  LE32_TO_CPU(cq_desc->params.generic.param0),\n+\t\t  LE32_TO_CPU(cq_desc->params.generic.param1));\n+\tice_debug(hw, mask, \"\\taddr (h,l)   0x%08X 0x%08X\\n\",\n+\t\t  LE32_TO_CPU(cq_desc->params.generic.addr_high),\n+\t\t  LE32_TO_CPU(cq_desc->params.generic.addr_low));\n+\tif (buf && cq_desc->datalen != 0) {\n+\t\tice_debug(hw, mask, \"Buffer:\\n\");\n+\t\tif (buf_len < len)\n+\t\t\tlen = buf_len;\n+\n+\t\tice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);\n+\t}\n+}\n+\n+\n+/* FW Admin Queue command wrappers */\n+\n+/**\n+ * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue\n+ * @hw: pointer to the hw struct\n+ * @desc: descriptor describing the command\n+ * @buf: buffer to use for indirect commands (NULL for direct commands)\n+ * @buf_size: size of buffer for indirect commands (0 for direct commands)\n+ * @cd: pointer to command details structure\n+ *\n+ * Helper function to send FW Admin Queue commands to the FW Admin Queue.\n+ */\n+enum ice_status\n+ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,\n+\t\tu16 buf_size, struct ice_sq_cd *cd)\n+{\n+\treturn ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);\n+}\n+\n+/**\n+ * ice_aq_get_fw_ver\n+ * @hw: pointer to the hw struct\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Get the firmware version (0x0001) from the admin queue commands\n+ */\n+enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_get_ver *resp;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tresp = &desc.params.get_ver;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+\n+\tif (!status) {\n+\t\thw->fw_branch = resp->fw_branch;\n+\t\thw->fw_maj_ver = resp->fw_major;\n+\t\thw->fw_min_ver = resp->fw_minor;\n+\t\thw->fw_patch = resp->fw_patch;\n+\t\thw->fw_build = LE32_TO_CPU(resp->fw_build);\n+\t\thw->api_branch = resp->api_branch;\n+\t\thw->api_maj_ver = resp->api_major;\n+\t\thw->api_min_ver = resp->api_minor;\n+\t\thw->api_patch = resp->api_patch;\n+\t}\n+\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_aq_q_shutdown\n+ * @hw: pointer to the hw struct\n+ * @unloading: is the driver unloading itself\n+ *\n+ * Tell the Firmware that we're shutting down the AdminQ and whether\n+ * or not the driver is unloading as well (0x0003).\n+ */\n+enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)\n+{\n+\tstruct ice_aqc_q_shutdown *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.q_shutdown;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);\n+\n+\tif (unloading)\n+\t\tcmd->driver_unloading = CPU_TO_LE32(ICE_AQC_DRIVER_UNLOADING);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+}\n+\n+/**\n+ * ice_aq_req_res\n+ * @hw: pointer to the hw struct\n+ * @res: resource id\n+ * @access: access type\n+ * @sdp_number: resource number\n+ * @timeout: the maximum time in ms that the driver may hold the resource\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Requests common resource using the admin queue commands (0x0008).\n+ * When attempting to acquire the Global Config Lock, the driver can\n+ * learn of three states:\n+ *  1) ICE_SUCCESS -        acquired lock, and can perform download package\n+ *  2) ICE_ERR_AQ_ERROR -   did not get lock, driver should fail to load\n+ *  3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has\n+ *                          successfully downloaded the package; the driver does\n+ *                          not have to download the package and can continue\n+ *                          loading\n+ *\n+ * Note that if the caller is in an acquire lock, perform action, release lock\n+ * phase of operation, it is possible that the FW may detect a timeout and issue\n+ * a CORER. In this case, the driver will receive a CORER interrupt and will\n+ * have to determine its cause. The calling thread that is handling this flow\n+ * will likely get an error propagated back to it indicating the Download\n+ * Package, Update Package or the Release Resource AQ commands timed out.\n+ */\n+static enum ice_status\n+ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,\n+\t       enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,\n+\t       struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_req_res *cmd_resp;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_req_res\");\n+\n+\tcmd_resp = &desc.params.res_owner;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);\n+\n+\tcmd_resp->res_id = CPU_TO_LE16(res);\n+\tcmd_resp->access_type = CPU_TO_LE16(access);\n+\tcmd_resp->res_number = CPU_TO_LE32(sdp_number);\n+\tcmd_resp->timeout = CPU_TO_LE32(*timeout);\n+\t*timeout = 0;\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+\n+\t/* The completion specifies the maximum time in ms that the driver\n+\t * may hold the resource in the Timeout field.\n+\t */\n+\n+\t/* Global config lock response utilizes an additional status field.\n+\t *\n+\t * If the Global config lock resource is held by some other driver, the\n+\t * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field\n+\t * and the timeout field indicates the maximum time the current owner\n+\t * of the resource has to free it.\n+\t */\n+\tif (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {\n+\t\tif (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {\n+\t\t\t*timeout = LE32_TO_CPU(cmd_resp->timeout);\n+\t\t\treturn ICE_SUCCESS;\n+\t\t} else if (LE16_TO_CPU(cmd_resp->status) ==\n+\t\t\t   ICE_AQ_RES_GLBL_IN_PROG) {\n+\t\t\t*timeout = LE32_TO_CPU(cmd_resp->timeout);\n+\t\t\treturn ICE_ERR_AQ_ERROR;\n+\t\t} else if (LE16_TO_CPU(cmd_resp->status) ==\n+\t\t\t   ICE_AQ_RES_GLBL_DONE) {\n+\t\t\treturn ICE_ERR_AQ_NO_WORK;\n+\t\t}\n+\n+\t\t/* invalid FW response, force a timeout immediately */\n+\t\t*timeout = 0;\n+\t\treturn ICE_ERR_AQ_ERROR;\n+\t}\n+\n+\t/* If the resource is held by some other driver, the command completes\n+\t * with a busy return value and the timeout field indicates the maximum\n+\t * time the current owner of the resource has to free it.\n+\t */\n+\tif (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)\n+\t\t*timeout = LE32_TO_CPU(cmd_resp->timeout);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_release_res\n+ * @hw: pointer to the hw struct\n+ * @res: resource id\n+ * @sdp_number: resource number\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * release common resource using the admin queue commands (0x0009)\n+ */\n+static enum ice_status\n+ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,\n+\t\t   struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_req_res *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_release_res\");\n+\n+\tcmd = &desc.params.res_owner;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);\n+\n+\tcmd->res_id = CPU_TO_LE16(res);\n+\tcmd->res_number = CPU_TO_LE32(sdp_number);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+/**\n+ * ice_acquire_res\n+ * @hw: pointer to the HW structure\n+ * @res: resource id\n+ * @access: access type (read or write)\n+ * @timeout: timeout in milliseconds\n+ *\n+ * This function will attempt to acquire the ownership of a resource.\n+ */\n+enum ice_status\n+ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,\n+\t\tenum ice_aq_res_access_type access, u32 timeout)\n+{\n+#define ICE_RES_POLLING_DELAY_MS\t10\n+\tu32 delay = ICE_RES_POLLING_DELAY_MS;\n+\tu32 time_left = timeout;\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_acquire_res\");\n+\n+\tstatus = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);\n+\n+\t/* A return code of ICE_ERR_AQ_NO_WORK means that another driver has\n+\t * previously acquired the resource and performed any necessary updates;\n+\t * in this case the caller does not obtain the resource and has no\n+\t * further work to do.\n+\t */\n+\tif (status == ICE_ERR_AQ_NO_WORK)\n+\t\tgoto ice_acquire_res_exit;\n+\n+\tif (status)\n+\t\tice_debug(hw, ICE_DBG_RES,\n+\t\t\t  \"resource %d acquire type %d failed.\\n\", res, access);\n+\n+\t/* If necessary, poll until the current lock owner timeouts */\n+\ttimeout = time_left;\n+\twhile (status && timeout && time_left) {\n+\t\tice_msec_delay(delay, true);\n+\t\ttimeout = (timeout > delay) ? timeout - delay : 0;\n+\t\tstatus = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);\n+\n+\t\tif (status == ICE_ERR_AQ_NO_WORK)\n+\t\t\t/* lock free, but no work to do */\n+\t\t\tbreak;\n+\n+\t\tif (!status)\n+\t\t\t/* lock acquired */\n+\t\t\tbreak;\n+\t}\n+\tif (status && status != ICE_ERR_AQ_NO_WORK)\n+\t\tice_debug(hw, ICE_DBG_RES, \"resource acquire timed out.\\n\");\n+\n+ice_acquire_res_exit:\n+\tif (status == ICE_ERR_AQ_NO_WORK) {\n+\t\tif (access == ICE_RES_WRITE)\n+\t\t\tice_debug(hw, ICE_DBG_RES,\n+\t\t\t\t  \"resource indicates no work to do.\\n\");\n+\t\telse\n+\t\t\tice_debug(hw, ICE_DBG_RES,\n+\t\t\t\t  \"Warning: ICE_ERR_AQ_NO_WORK not expected\\n\");\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_release_res\n+ * @hw: pointer to the HW structure\n+ * @res: resource id\n+ *\n+ * This function will release a resource using the proper Admin Command.\n+ */\n+void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)\n+{\n+\tenum ice_status status;\n+\tu32 total_delay = 0;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_release_res\");\n+\n+\tstatus = ice_aq_release_res(hw, res, 0, NULL);\n+\n+\t/* there are some rare cases when trying to release the resource\n+\t * results in an admin Q timeout, so handle them correctly\n+\t */\n+\twhile ((status == ICE_ERR_AQ_TIMEOUT) &&\n+\t       (total_delay < hw->adminq.sq_cmd_timeout)) {\n+\t\tice_msec_delay(1, true);\n+\t\tstatus = ice_aq_release_res(hw, res, 0, NULL);\n+\t\ttotal_delay++;\n+\t}\n+}\n+\n+/**\n+ * ice_aq_alloc_free_res - command to allocate/free resources\n+ * @hw: pointer to the hw struct\n+ * @num_entries: number of resource entries in buffer\n+ * @buf: Indirect buffer to hold data parameters and response\n+ * @buf_size: size of buffer for indirect commands\n+ * @opc: pass in the command opcode\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Helper function to allocate/free resources using the admin queue commands\n+ */\n+enum ice_status\n+ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,\n+\t\t      struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,\n+\t\t      enum ice_adminq_opc opc, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_alloc_free_res_cmd *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_alloc_free_res\");\n+\n+\tcmd = &desc.params.sw_res_ctrl;\n+\n+\tif (!buf)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (buf_size < (num_entries * sizeof(buf->elem[0])))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, opc);\n+\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\tcmd->num_entries = CPU_TO_LE16(num_entries);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+}\n+\n+\n+/**\n+ * ice_get_num_per_func - determine number of resources per PF\n+ * @hw: pointer to the hw structure\n+ * @max: value to be evenly split between each PF\n+ *\n+ * Determine the number of valid functions by going through the bitmap returned\n+ * from parsing capabilities and use this to calculate the number of resources\n+ * per PF based on the max value passed in.\n+ */\n+static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)\n+{\n+\tu8 funcs;\n+\n+#define ICE_CAPS_VALID_FUNCS_M\t0xFF\n+\tfuncs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &\n+\t\t\t     ICE_CAPS_VALID_FUNCS_M);\n+\n+\tif (!funcs)\n+\t\treturn 0;\n+\n+\treturn max / funcs;\n+}\n+\n+/**\n+ * ice_parse_caps - parse function/device capabilities\n+ * @hw: pointer to the hw struct\n+ * @buf: pointer to a buffer containing function/device capability records\n+ * @cap_count: number of capability records in the list\n+ * @opc: type of capabilities list to parse\n+ *\n+ * Helper function to parse function(0x000a)/device(0x000b) capabilities list.\n+ */\n+static void\n+ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n+\t       enum ice_adminq_opc opc)\n+{\n+\tstruct ice_aqc_list_caps_elem *cap_resp;\n+\tstruct ice_hw_func_caps *func_p = NULL;\n+\tstruct ice_hw_dev_caps *dev_p = NULL;\n+\tstruct ice_hw_common_caps *caps;\n+\tu32 i;\n+\n+\tif (!buf)\n+\t\treturn;\n+\n+\tcap_resp = (struct ice_aqc_list_caps_elem *)buf;\n+\n+\tif (opc == ice_aqc_opc_list_dev_caps) {\n+\t\tdev_p = &hw->dev_caps;\n+\t\tcaps = &dev_p->common_cap;\n+\t} else if (opc == ice_aqc_opc_list_func_caps) {\n+\t\tfunc_p = &hw->func_caps;\n+\t\tcaps = &func_p->common_cap;\n+\t} else {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"wrong opcode\\n\");\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; caps && i < cap_count; i++, cap_resp++) {\n+\t\tu32 logical_id = LE32_TO_CPU(cap_resp->logical_id);\n+\t\tu32 phys_id = LE32_TO_CPU(cap_resp->phys_id);\n+\t\tu32 number = LE32_TO_CPU(cap_resp->number);\n+\t\tu16 cap = LE16_TO_CPU(cap_resp->cap);\n+\n+\t\tswitch (cap) {\n+\t\tcase ICE_AQC_CAPS_VALID_FUNCTIONS:\n+\t\t\tcaps->valid_functions = number;\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Valid Functions = %d\\n\",\n+\t\t\t\t  caps->valid_functions);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_VSI:\n+\t\t\tif (dev_p) {\n+\t\t\t\tdev_p->num_vsi_allocd_to_host = number;\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: Dev.VSI cnt = %d\\n\",\n+\t\t\t\t\t  dev_p->num_vsi_allocd_to_host);\n+\t\t\t} else if (func_p) {\n+\t\t\t\tfunc_p->guar_num_vsi =\n+\t\t\t\t\tice_get_num_per_func(hw, ICE_MAX_VSI);\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: Func.VSI cnt = %d\\n\",\n+\t\t\t\t\t  number);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_RSS:\n+\t\t\tcaps->rss_table_size = number;\n+\t\t\tcaps->rss_table_entry_width = logical_id;\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: RSS table size = %d\\n\",\n+\t\t\t\t  caps->rss_table_size);\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: RSS table width = %d\\n\",\n+\t\t\t\t  caps->rss_table_entry_width);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_RXQS:\n+\t\t\tcaps->num_rxq = number;\n+\t\t\tcaps->rxq_first_id = phys_id;\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Num Rx Qs = %d\\n\", caps->num_rxq);\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Rx first queue ID = %d\\n\",\n+\t\t\t\t  caps->rxq_first_id);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_TXQS:\n+\t\t\tcaps->num_txq = number;\n+\t\t\tcaps->txq_first_id = phys_id;\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Num Tx Qs = %d\\n\", caps->num_txq);\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Tx first queue ID = %d\\n\",\n+\t\t\t\t  caps->txq_first_id);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_MSIX:\n+\t\t\tcaps->num_msix_vectors = number;\n+\t\t\tcaps->msix_vector_first_id = phys_id;\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: MSIX vector count = %d\\n\",\n+\t\t\t\t  caps->num_msix_vectors);\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: MSIX first vector index = %d\\n\",\n+\t\t\t\t  caps->msix_vector_first_id);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_MAX_MTU:\n+\t\t\tcaps->max_mtu = number;\n+\t\t\tif (dev_p)\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: Dev.MaxMTU = %d\\n\",\n+\t\t\t\t\t  caps->max_mtu);\n+\t\t\telse if (func_p)\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: func.MaxMTU = %d\\n\",\n+\t\t\t\t\t  caps->max_mtu);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Unknown capability[%d]: 0x%x\\n\", i,\n+\t\t\t\t  cap);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * ice_aq_discover_caps - query function/device capabilities\n+ * @hw: pointer to the hw struct\n+ * @buf: a virtual buffer to hold the capabilities\n+ * @buf_size: Size of the virtual buffer\n+ * @cap_count: cap count needed if AQ err==ENOMEM\n+ * @opc: capabilities type to discover - pass in the command opcode\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Get the function(0x000a)/device(0x000b) capabilities description from\n+ * the firmware.\n+ */\n+static enum ice_status\n+ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,\n+\t\t     enum ice_adminq_opc opc, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_list_caps *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.get_cap;\n+\n+\tif (opc != ice_aqc_opc_list_func_caps &&\n+\t    opc != ice_aqc_opc_list_dev_caps)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, opc);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (!status)\n+\t\tice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);\n+\telse if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)\n+\t\t*cap_count = LE32_TO_CPU(cmd->count);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_discover_caps - get info about the HW\n+ * @hw: pointer to the hardware structure\n+ * @opc: capabilities type to discover - pass in the command opcode\n+ */\n+static enum ice_status\n+ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)\n+{\n+\tenum ice_status status;\n+\tu32 cap_count;\n+\tu16 cbuf_len;\n+\tu8 retries;\n+\n+\t/* The driver doesn't know how many capabilities the device will return\n+\t * so the buffer size required isn't known ahead of time. The driver\n+\t * starts with cbuf_len and if this turns out to be insufficient, the\n+\t * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.\n+\t * The driver then allocates the buffer based on the count and retries\n+\t * the operation. So it follows that the retry count is 2.\n+\t */\n+#define ICE_GET_CAP_BUF_COUNT\t40\n+#define ICE_GET_CAP_RETRY_COUNT\t2\n+\n+\tcap_count = ICE_GET_CAP_BUF_COUNT;\n+\tretries = ICE_GET_CAP_RETRY_COUNT;\n+\n+\tdo {\n+\t\tvoid *cbuf;\n+\n+\t\tcbuf_len = (u16)(cap_count *\n+\t\t\t\t sizeof(struct ice_aqc_list_caps_elem));\n+\t\tcbuf = ice_malloc(hw, cbuf_len);\n+\t\tif (!cbuf)\n+\t\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\t\tstatus = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,\n+\t\t\t\t\t      opc, NULL);\n+\t\tice_free(hw, cbuf);\n+\n+\t\tif (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)\n+\t\t\tbreak;\n+\n+\t\t/* If ENOMEM is returned, try again with bigger buffer */\n+\t} while (--retries);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_get_caps - get info about the HW\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_get_caps(struct ice_hw *hw)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);\n+\tif (!status)\n+\t\tstatus = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_manage_mac_write - manage MAC address write command\n+ * @hw: pointer to the hw struct\n+ * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address\n+ * @flags: flags to control write behavior\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function is used to write MAC address to the NVM (0x0108).\n+ */\n+enum ice_status\n+ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,\n+\t\t\tstruct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_manage_mac_write *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.mac_write;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);\n+\n+\tcmd->flags = flags;\n+\n+\n+\t/* Prep values for flags, sah, sal */\n+\tcmd->sah = HTONS(*((const u16 *)mac_addr));\n+\tcmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+/**\n+ * ice_aq_clear_pxe_mode\n+ * @hw: pointer to the hw struct\n+ *\n+ * Tell the firmware that the driver is taking over from PXE (0x0110).\n+ */\n+static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);\n+\tdesc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+}\n+\n+/**\n+ * ice_clear_pxe_mode - clear pxe operations mode\n+ * @hw: pointer to the hw struct\n+ *\n+ * Make sure all PXE mode settings are cleared, including things\n+ * like descriptor fetch/write-back mode.\n+ */\n+void ice_clear_pxe_mode(struct ice_hw *hw)\n+{\n+\tif (ice_check_sq_alive(hw, &hw->adminq))\n+\t\tice_aq_clear_pxe_mode(hw);\n+}\n+\n+\n+/**\n+ * ice_get_link_speed_based_on_phy_type - returns link speed\n+ * @phy_type_low: lower part of phy_type\n+ * @phy_type_high: higher part of phy_type\n+ *\n+ * This helper function will convert an entry in phy type structure\n+ * [phy_type_low, phy_type_high] to its corresponding link speed.\n+ * Note: In the structure of [phy_type_low, phy_type_high], there should\n+ * be one bit set, as this function will convert one phy type to its\n+ * speed.\n+ * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned\n+ * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned\n+ */\n+static u16\n+ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)\n+{\n+\tu16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;\n+\tu16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;\n+\n+\tswitch (phy_type_low) {\n+\tcase ICE_PHY_TYPE_LOW_100BASE_TX:\n+\tcase ICE_PHY_TYPE_LOW_100M_SGMII:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_1000BASE_T:\n+\tcase ICE_PHY_TYPE_LOW_1000BASE_SX:\n+\tcase ICE_PHY_TYPE_LOW_1000BASE_LX:\n+\tcase ICE_PHY_TYPE_LOW_1000BASE_KX:\n+\tcase ICE_PHY_TYPE_LOW_1G_SGMII:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_2500BASE_T:\n+\tcase ICE_PHY_TYPE_LOW_2500BASE_X:\n+\tcase ICE_PHY_TYPE_LOW_2500BASE_KX:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_5GBASE_T:\n+\tcase ICE_PHY_TYPE_LOW_5GBASE_KR:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_10GBASE_T:\n+\tcase ICE_PHY_TYPE_LOW_10G_SFI_DA:\n+\tcase ICE_PHY_TYPE_LOW_10GBASE_SR:\n+\tcase ICE_PHY_TYPE_LOW_10GBASE_LR:\n+\tcase ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:\n+\tcase ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_10G_SFI_C2C:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_T:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_CR:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_CR_S:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_CR1:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_SR:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_LR:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_KR:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_KR_S:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_KR1:\n+\tcase ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_25G_AUI_C2C:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_40GBASE_CR4:\n+\tcase ICE_PHY_TYPE_LOW_40GBASE_SR4:\n+\tcase ICE_PHY_TYPE_LOW_40GBASE_LR4:\n+\tcase ICE_PHY_TYPE_LOW_40GBASE_KR4:\n+\tcase ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_40G_XLAUI:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_CR2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_SR2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_LR2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_KR2:\n+\tcase ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_50G_LAUI2:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI2:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_CP:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_SR:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_FR:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_LR:\n+\tcase ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_50G_AUI1:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_CR4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_SR4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_LR4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_KR4:\n+\tcase ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_100G_CAUI4:\n+\tcase ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_100G_AUI4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_CP2:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_SR2:\n+\tcase ICE_PHY_TYPE_LOW_100GBASE_DR:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;\n+\t\tbreak;\n+\tdefault:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;\n+\t\tbreak;\n+\t}\n+\n+\tswitch (phy_type_high) {\n+\tcase ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:\n+\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_HIGH_100G_CAUI2:\n+\tcase ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:\n+\tcase ICE_PHY_TYPE_HIGH_100G_AUI2:\n+\t\tspeed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;\n+\t\tbreak;\n+\tdefault:\n+\t\tspeed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;\n+\t\tbreak;\n+\t}\n+\n+\tif (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&\n+\t    speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)\n+\t\treturn ICE_AQ_LINK_SPEED_UNKNOWN;\n+\telse if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&\n+\t\t speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)\n+\t\treturn ICE_AQ_LINK_SPEED_UNKNOWN;\n+\telse if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&\n+\t\t speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)\n+\t\treturn speed_phy_type_low;\n+\telse\n+\t\treturn speed_phy_type_high;\n+}\n+\n+/**\n+ * ice_update_phy_type\n+ * @phy_type_low: pointer to the lower part of phy_type\n+ * @phy_type_high: pointer to the higher part of phy_type\n+ * @link_speeds_bitmap: targeted link speeds bitmap\n+ *\n+ * Note: For the link_speeds_bitmap structure, you can check it at\n+ * [ice_aqc_get_link_status->link_speed]. Caller can pass in\n+ * link_speeds_bitmap include multiple speeds.\n+ *\n+ * Each entry in this [phy_type_low, phy_type_high] structure will\n+ * present a certain link speed. This helper function will turn on bits\n+ * in [phy_type_low, phy_type_high] structure based on the value of\n+ * link_speeds_bitmap input parameter.\n+ */\n+void\n+ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,\n+\t\t    u16 link_speeds_bitmap)\n+{\n+\tu16 speed = ICE_AQ_LINK_SPEED_UNKNOWN;\n+\tu64 pt_high;\n+\tu64 pt_low;\n+\tint index;\n+\n+\t/* We first check with low part of phy_type */\n+\tfor (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {\n+\t\tpt_low = BIT_ULL(index);\n+\t\tspeed = ice_get_link_speed_based_on_phy_type(pt_low, 0);\n+\n+\t\tif (link_speeds_bitmap & speed)\n+\t\t\t*phy_type_low |= BIT_ULL(index);\n+\t}\n+\n+\t/* We then check with high part of phy_type */\n+\tfor (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {\n+\t\tpt_high = BIT_ULL(index);\n+\t\tspeed = ice_get_link_speed_based_on_phy_type(0, pt_high);\n+\n+\t\tif (link_speeds_bitmap & speed)\n+\t\t\t*phy_type_high |= BIT_ULL(index);\n+\t}\n+}\n+\n+/**\n+ * ice_aq_set_phy_cfg\n+ * @hw: pointer to the hw struct\n+ * @lport: logical port number\n+ * @cfg: structure with PHY configuration data to be set\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Set the various PHY configuration parameters supported on the Port.\n+ * One or more of the Set PHY config parameters may be ignored in an MFP\n+ * mode as the PF may not have the privilege to set some of the PHY Config\n+ * parameters. This status will be indicated by the command response (0x0601).\n+ */\n+enum ice_status\n+ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,\n+\t\t   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tif (!cfg)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);\n+\tdesc.params.set_phy.lport_num = lport;\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);\n+}\n+\n+/**\n+ * ice_update_link_info - update status of the HW network link\n+ * @pi: port info structure of the interested logical port\n+ */\n+enum ice_status ice_update_link_info(struct ice_port_info *pi)\n+{\n+\tstruct ice_aqc_get_phy_caps_data *pcaps;\n+\tstruct ice_phy_info *phy_info;\n+\tenum ice_status status;\n+\tstruct ice_hw *hw;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\thw = pi->hw;\n+\n+\tpcaps = (struct ice_aqc_get_phy_caps_data *)\n+\t\tice_malloc(hw, sizeof(*pcaps));\n+\tif (!pcaps)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tphy_info = &pi->phy;\n+\tstatus = ice_aq_get_link_info(pi, true, NULL, NULL);\n+\tif (status)\n+\t\tgoto out;\n+\n+\tif (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {\n+\t\tstatus = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG,\n+\t\t\t\t\t     pcaps, NULL);\n+\t\tif (status)\n+\t\t\tgoto out;\n+\n+\t\tice_memcpy(phy_info->link_info.module_type, &pcaps->module_type,\n+\t\t\t   sizeof(phy_info->link_info.module_type),\n+\t\t\t   ICE_NONDMA_TO_NONDMA);\n+\t}\n+out:\n+\tice_free(hw, pcaps);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_set_fc\n+ * @pi: port information structure\n+ * @aq_failures: pointer to status code, specific to ice_set_fc routine\n+ * @ena_auto_link_update: enable automatic link update\n+ *\n+ * Set the requested flow control mode.\n+ */\n+enum ice_status\n+ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n+{\n+\tstruct ice_aqc_set_phy_cfg_data cfg = { 0 };\n+\tstruct ice_aqc_get_phy_caps_data *pcaps;\n+\tenum ice_status status;\n+\tu8 pause_mask = 0x0;\n+\tstruct ice_hw *hw;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\thw = pi->hw;\n+\t*aq_failures = ICE_SET_FC_AQ_FAIL_NONE;\n+\n+\tswitch (pi->fc.req_mode) {\n+\tcase ICE_FC_FULL:\n+\t\tpause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;\n+\t\tpause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;\n+\t\tbreak;\n+\tcase ICE_FC_RX_PAUSE:\n+\t\tpause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;\n+\t\tbreak;\n+\tcase ICE_FC_TX_PAUSE:\n+\t\tpause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tpcaps = (struct ice_aqc_get_phy_caps_data *)\n+\t\tice_malloc(hw, sizeof(*pcaps));\n+\tif (!pcaps)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\t/* Get the current phy config */\n+\tstatus = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,\n+\t\t\t\t     NULL);\n+\tif (status) {\n+\t\t*aq_failures = ICE_SET_FC_AQ_FAIL_GET;\n+\t\tgoto out;\n+\t}\n+\n+\t/* clear the old pause settings */\n+\tcfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |\n+\t\t\t\t   ICE_AQC_PHY_EN_RX_LINK_PAUSE);\n+\t/* set the new capabilities */\n+\tcfg.caps |= pause_mask;\n+\t/* If the capabilities have changed, then set the new config */\n+\tif (cfg.caps != pcaps->caps) {\n+\t\tint retry_count, retry_max = 10;\n+\n+\t\t/* Auto restart link so settings take effect */\n+\t\tif (ena_auto_link_update)\n+\t\t\tcfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;\n+\t\t/* Copy over all the old settings */\n+\t\tcfg.phy_type_high = pcaps->phy_type_high;\n+\t\tcfg.phy_type_low = pcaps->phy_type_low;\n+\t\tcfg.low_power_ctrl = pcaps->low_power_ctrl;\n+\t\tcfg.eee_cap = pcaps->eee_cap;\n+\t\tcfg.eeer_value = pcaps->eeer_value;\n+\t\tcfg.link_fec_opt = pcaps->link_fec_options;\n+\n+\t\tstatus = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);\n+\t\tif (status) {\n+\t\t\t*aq_failures = ICE_SET_FC_AQ_FAIL_SET;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\t/* Update the link info\n+\t\t * It sometimes takes a really long time for link to\n+\t\t * come back from the atomic reset. Thus, we wait a\n+\t\t * little bit.\n+\t\t */\n+\t\tfor (retry_count = 0; retry_count < retry_max; retry_count++) {\n+\t\t\tstatus = ice_update_link_info(pi);\n+\n+\t\t\tif (status == ICE_SUCCESS)\n+\t\t\t\tbreak;\n+\n+\t\t\tice_msec_delay(100, true);\n+\t\t}\n+\n+\t\tif (status)\n+\t\t\t*aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;\n+\t}\n+\n+out:\n+\tice_free(hw, pcaps);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data\n+ * @caps: PHY ability structure to copy date from\n+ * @cfg: PHY configuration structure to copy data to\n+ *\n+ * Helper function to copy AQC PHY get ability data to PHY set configuration\n+ * data structure\n+ */\n+void\n+ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,\n+\t\t\t struct ice_aqc_set_phy_cfg_data *cfg)\n+{\n+\tif (!caps || !cfg)\n+\t\treturn;\n+\n+\tcfg->phy_type_low = caps->phy_type_low;\n+\tcfg->phy_type_high = caps->phy_type_high;\n+\tcfg->caps = caps->caps;\n+\tcfg->low_power_ctrl = caps->low_power_ctrl;\n+\tcfg->eee_cap = caps->eee_cap;\n+\tcfg->eeer_value = caps->eeer_value;\n+\tcfg->link_fec_opt = caps->link_fec_options;\n+}\n+\n+/**\n+ * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode\n+ * @cfg: PHY configuration data to set FEC mode\n+ * @fec: FEC mode to configure\n+ *\n+ * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC\n+ * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps\n+ * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.\n+ */\n+void\n+ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)\n+{\n+\tswitch (fec) {\n+\tcase ICE_FEC_BASER:\n+\t\t/* Clear auto FEC and RS bits, and AND BASE-R ability\n+\t\t * bits and OR request bits.\n+\t\t */\n+\t\tcfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;\n+\t\tcfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |\n+\t\t\t\t     ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;\n+\t\tcfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |\n+\t\t\t\t     ICE_AQC_PHY_FEC_25G_KR_REQ;\n+\t\tbreak;\n+\tcase ICE_FEC_RS:\n+\t\t/* Clear auto FEC and BASE-R bits, and AND RS ability\n+\t\t * bits and OR request bits.\n+\t\t */\n+\t\tcfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;\n+\t\tcfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;\n+\t\tcfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |\n+\t\t\t\t     ICE_AQC_PHY_FEC_25G_RS_544_REQ;\n+\t\tbreak;\n+\tcase ICE_FEC_NONE:\n+\t\t/* Clear auto FEC and all FEC option bits. */\n+\t\tcfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;\n+\t\tcfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;\n+\t\tbreak;\n+\tcase ICE_FEC_AUTO:\n+\t\t/* AND auto FEC bit, and all caps bits. */\n+\t\tcfg->caps &= ICE_AQC_PHY_CAPS_MASK;\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * ice_get_link_status - get status of the HW network link\n+ * @pi: port information structure\n+ * @link_up: pointer to bool (true/false = linkup/linkdown)\n+ *\n+ * Variable link_up is true if link is up, false if link is down.\n+ * The variable link_up is invalid if status is non zero. As a\n+ * result of this call, link status reporting becomes enabled\n+ */\n+enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)\n+{\n+\tstruct ice_phy_info *phy_info;\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\tif (!pi || !link_up)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tphy_info = &pi->phy;\n+\n+\tif (phy_info->get_link_info) {\n+\t\tstatus = ice_update_link_info(pi);\n+\n+\t\tif (status)\n+\t\t\tice_debug(pi->hw, ICE_DBG_LINK,\n+\t\t\t\t  \"get link status error, status = %d\\n\",\n+\t\t\t\t  status);\n+\t}\n+\n+\t*link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_set_link_restart_an\n+ * @pi: pointer to the port information structure\n+ * @ena_link: if true: enable link, if false: disable link\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Sets up the link and restarts the Auto-Negotiation over the link.\n+ */\n+enum ice_status\n+ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,\n+\t\t\t   struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_restart_an *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.restart_an;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);\n+\n+\tcmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;\n+\tcmd->lport_num = pi->lport;\n+\tif (ena_link)\n+\t\tcmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;\n+\telse\n+\t\tcmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;\n+\n+\treturn ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);\n+}\n+\n+/**\n+ * ice_aq_set_event_mask\n+ * @hw: pointer to the hw struct\n+ * @port_num: port number of the physical function\n+ * @mask: event mask to be set\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Set event mask (0x0613)\n+ */\n+enum ice_status\n+ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,\n+\t\t      struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_set_event_mask *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.set_event_mask;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);\n+\n+\tcmd->lport_num = port_num;\n+\n+\tcmd->event_mask = CPU_TO_LE16(mask);\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+/**\n+ * ice_aq_set_mac_loopback\n+ * @hw: pointer to the hw struct\n+ * @ena_lpbk: Enable or Disable loopback\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Enable/disable loopback on a given port\n+ */\n+enum ice_status\n+ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_set_mac_lb *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.set_mac_lb;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);\n+\tif (ena_lpbk)\n+\t\tcmd->lb_mode = ICE_AQ_MAC_LB_EN;\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+\n+/**\n+ * ice_aq_set_port_id_led\n+ * @pi: pointer to the port information\n+ * @is_orig_mode: is this LED set to original mode (by the net-list)\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Set LED value for the given port (0x06e9)\n+ */\n+enum ice_status\n+ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,\n+\t\t       struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_set_port_id_led *cmd;\n+\tstruct ice_hw *hw = pi->hw;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.set_port_id_led;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);\n+\n+\n+\tif (is_orig_mode)\n+\t\tcmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;\n+\telse\n+\t\tcmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+/**\n+ * __ice_aq_get_set_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_id: VSI FW index\n+ * @lut_type: LUT table type\n+ * @lut: pointer to the LUT buffer provided by the caller\n+ * @lut_size: size of the LUT buffer\n+ * @glob_lut_idx: global LUT index\n+ * @set: set true to set the table, false to get the table\n+ *\n+ * Internal function to get (0x0B05) or set (0x0B03) RSS look up table\n+ */\n+static enum ice_status\n+__ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,\n+\t\t\t u16 lut_size, u8 glob_lut_idx, bool set)\n+{\n+\tstruct ice_aqc_get_set_rss_lut *cmd_resp;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\tu16 flags = 0;\n+\n+\tcmd_resp = &desc.params.get_set_rss_lut;\n+\n+\tif (set) {\n+\t\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);\n+\t\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\t} else {\n+\t\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);\n+\t}\n+\n+\tcmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<\n+\t\t\t\t\t ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &\n+\t\t\t\t\tICE_AQC_GSET_RSS_LUT_VSI_ID_M) |\n+\t\t\t\t       ICE_AQC_GSET_RSS_LUT_VSI_VALID);\n+\n+\tswitch (lut_type) {\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:\n+\t\tflags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &\n+\t\t\t  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);\n+\t\tbreak;\n+\tdefault:\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto ice_aq_get_set_rss_lut_exit;\n+\t}\n+\n+\tif (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {\n+\t\tflags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &\n+\t\t\t  ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);\n+\n+\t\tif (!set)\n+\t\t\tgoto ice_aq_get_set_rss_lut_send;\n+\t} else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {\n+\t\tif (!set)\n+\t\t\tgoto ice_aq_get_set_rss_lut_send;\n+\t} else {\n+\t\tgoto ice_aq_get_set_rss_lut_send;\n+\t}\n+\n+\t/* LUT size is only valid for Global and PF table types */\n+\tswitch (lut_size) {\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:\n+\t\tflags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<\n+\t\t\t  ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &\n+\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;\n+\t\tbreak;\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:\n+\t\tflags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<\n+\t\t\t  ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &\n+\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;\n+\t\tbreak;\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:\n+\t\tif (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {\n+\t\t\tflags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<\n+\t\t\t\t  ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &\n+\t\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* fall-through */\n+\tdefault:\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto ice_aq_get_set_rss_lut_exit;\n+\t}\n+\n+ice_aq_get_set_rss_lut_send:\n+\tcmd_resp->flags = CPU_TO_LE16(flags);\n+\tstatus = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);\n+\n+ice_aq_get_set_rss_lut_exit:\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_get_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: software VSI handle\n+ * @lut_type: LUT table type\n+ * @lut: pointer to the LUT buffer provided by the caller\n+ * @lut_size: size of the LUT buffer\n+ *\n+ * get the RSS lookup table, PF or VSI type\n+ */\n+enum ice_status\n+ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,\n+\t\t   u8 *lut, u16 lut_size)\n+{\n+\tif (!ice_is_vsi_valid(hw, vsi_handle) || !lut)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\treturn __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),\n+\t\t\t\t\tlut_type, lut, lut_size, 0, false);\n+}\n+\n+/**\n+ * ice_aq_set_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: software VSI handle\n+ * @lut_type: LUT table type\n+ * @lut: pointer to the LUT buffer provided by the caller\n+ * @lut_size: size of the LUT buffer\n+ *\n+ * set the RSS lookup table, PF or VSI type\n+ */\n+enum ice_status\n+ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,\n+\t\t   u8 *lut, u16 lut_size)\n+{\n+\tif (!ice_is_vsi_valid(hw, vsi_handle) || !lut)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\treturn __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),\n+\t\t\t\t\tlut_type, lut, lut_size, 0, true);\n+}\n+\n+/**\n+ * __ice_aq_get_set_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_id: VSI FW index\n+ * @key: pointer to key info struct\n+ * @set: set true to set the key, false to get the key\n+ *\n+ * get (0x0B04) or set (0x0B02) the RSS key per VSI\n+ */\n+static enum\n+ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,\n+\t\t\t\t    struct ice_aqc_get_set_rss_keys *key,\n+\t\t\t\t    bool set)\n+{\n+\tstruct ice_aqc_get_set_rss_key *cmd_resp;\n+\tu16 key_size = sizeof(*key);\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd_resp = &desc.params.get_set_rss_key;\n+\n+\tif (set) {\n+\t\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);\n+\t\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\t} else {\n+\t\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);\n+\t}\n+\n+\tcmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<\n+\t\t\t\t\t ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &\n+\t\t\t\t\tICE_AQC_GSET_RSS_KEY_VSI_ID_M) |\n+\t\t\t\t       ICE_AQC_GSET_RSS_KEY_VSI_VALID);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, key, key_size, NULL);\n+}\n+\n+/**\n+ * ice_aq_get_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: software VSI handle\n+ * @key: pointer to key info struct\n+ *\n+ * get the RSS key per VSI\n+ */\n+enum ice_status\n+ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,\n+\t\t   struct ice_aqc_get_set_rss_keys *key)\n+{\n+\tif (!ice_is_vsi_valid(hw, vsi_handle) || !key)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\treturn __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),\n+\t\t\t\t\tkey, false);\n+}\n+\n+/**\n+ * ice_aq_set_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: software VSI handle\n+ * @keys: pointer to key info struct\n+ *\n+ * set the RSS key per VSI\n+ */\n+enum ice_status\n+ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,\n+\t\t   struct ice_aqc_get_set_rss_keys *keys)\n+{\n+\tif (!ice_is_vsi_valid(hw, vsi_handle) || !keys)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\treturn __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),\n+\t\t\t\t\tkeys, true);\n+}\n+\n+/**\n+ * ice_aq_add_lan_txq\n+ * @hw: pointer to the hardware structure\n+ * @num_qgrps: Number of added queue groups\n+ * @qg_list: list of queue groups to be added\n+ * @buf_size: size of buffer for indirect command\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Add Tx LAN queue (0x0C30)\n+ *\n+ * NOTE:\n+ * Prior to calling add Tx LAN queue:\n+ * Initialize the following as part of the Tx queue context:\n+ * Completion queue ID if the queue uses Completion queue, Quanta profile,\n+ * Cache profile and Packet shaper profile.\n+ *\n+ * After add Tx LAN queue AQ command is completed:\n+ * Interrupts should be associated with specific queues,\n+ * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue\n+ * flow.\n+ */\n+static enum ice_status\n+ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,\n+\t\t   struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,\n+\t\t   struct ice_sq_cd *cd)\n+{\n+\tu16 i, sum_header_size, sum_q_size = 0;\n+\tstruct ice_aqc_add_tx_qgrp *list;\n+\tstruct ice_aqc_add_txqs *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_add_lan_txq\");\n+\n+\tcmd = &desc.params.add_txqs;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);\n+\n+\tif (!qg_list)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tsum_header_size = num_qgrps *\n+\t\t(sizeof(*qg_list) - sizeof(*qg_list->txqs));\n+\n+\tlist = qg_list;\n+\tfor (i = 0; i < num_qgrps; i++) {\n+\t\tstruct ice_aqc_add_txqs_perq *q = list->txqs;\n+\n+\t\tsum_q_size += list->num_txqs * sizeof(*q);\n+\t\tlist = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);\n+\t}\n+\n+\tif (buf_size != (sum_header_size + sum_q_size))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\tcmd->num_qgrps = num_qgrps;\n+\n+\treturn ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);\n+}\n+\n+/**\n+ * ice_aq_dis_lan_txq\n+ * @hw: pointer to the hardware structure\n+ * @num_qgrps: number of groups in the list\n+ * @qg_list: the list of groups to disable\n+ * @buf_size: the total size of the qg_list buffer in bytes\n+ * @rst_src: if called due to reset, specifies the rst source\n+ * @vmvf_num: the relative vm or vf number that is undergoing the reset\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Disable LAN Tx queue (0x0C31)\n+ */\n+static enum ice_status\n+ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,\n+\t\t   struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,\n+\t\t   enum ice_disq_rst_src rst_src, u16 vmvf_num,\n+\t\t   struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_dis_txqs *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\tu16 i, sz = 0;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_dis_lan_txq\");\n+\tcmd = &desc.params.dis_txqs;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);\n+\n+\t/* qg_list can be NULL only in VM/VF reset flow */\n+\tif (!qg_list && !rst_src)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tcmd->num_entries = num_qgrps;\n+\n+\tcmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &\n+\t\t\t\t\t    ICE_AQC_Q_DIS_TIMEOUT_M);\n+\n+\tswitch (rst_src) {\n+\tcase ICE_VM_RESET:\n+\t\tcmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;\n+\t\tcmd->vmvf_and_timeout |=\n+\t\t\tCPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);\n+\t\tbreak;\n+\tcase ICE_NO_RESET:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t/* flush pipe on time out */\n+\tcmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;\n+\t/* If no queue group info, we are in a reset flow. Issue the AQ */\n+\tif (!qg_list)\n+\t\tgoto do_aq;\n+\n+\t/* set RD bit to indicate that command buffer is provided by the driver\n+\t * and it needs to be read by the firmware\n+\t */\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\tfor (i = 0; i < num_qgrps; ++i) {\n+\t\t/* Calculate the size taken up by the queue IDs in this group */\n+\t\tsz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);\n+\n+\t\t/* Add the size of the group header */\n+\t\tsz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);\n+\n+\t\t/* If the num of queues is even, add 2 bytes of padding */\n+\t\tif ((qg_list[i].num_qs % 2) == 0)\n+\t\t\tsz += 2;\n+\t}\n+\n+\tif (buf_size != sz)\n+\t\treturn ICE_ERR_PARAM;\n+\n+do_aq:\n+\tstatus = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);\n+\tif (status) {\n+\t\tif (!qg_list)\n+\t\t\tice_debug(hw, ICE_DBG_SCHED, \"VM%d disable failed %d\\n\",\n+\t\t\t\t  vmvf_num, hw->adminq.sq_last_status);\n+\t\telse\n+\t\t\tice_debug(hw, ICE_DBG_SCHED, \"disable Q %d failed %d\\n\",\n+\t\t\t\t  LE16_TO_CPU(qg_list[0].q_id[0]),\n+\t\t\t\t  hw->adminq.sq_last_status);\n+\t}\n+\treturn status;\n+}\n+\n+\n+/* End of FW Admin Queue command wrappers */\n+\n+/**\n+ * ice_write_byte - write a byte to a packed context structure\n+ * @src_ctx:  the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info:  a description of the struct to be filled\n+ */\n+static void\n+ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+{\n+\tu8 src_byte, dest_byte, mask;\n+\tu8 *from, *dest;\n+\tu16 shift_width;\n+\n+\t/* copy from the next struct field */\n+\tfrom = src_ctx + ce_info->offset;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\tmask = (u8)(BIT(ce_info->width) - 1);\n+\n+\tsrc_byte = *from;\n+\tsrc_byte &= mask;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\tsrc_byte <<= shift_width;\n+\n+\t/* get the current bits from the target bit string */\n+\tdest = dest_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);\n+\n+\tdest_byte &= ~mask;\t/* get the bits not changing */\n+\tdest_byte |= src_byte;\t/* add in the new bits */\n+\n+\t/* put it all back */\n+\tice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_write_word - write a word to a packed context structure\n+ * @src_ctx:  the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info:  a description of the struct to be filled\n+ */\n+static void\n+ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+{\n+\tu16 src_word, mask;\n+\t__le16 dest_word;\n+\tu8 *from, *dest;\n+\tu16 shift_width;\n+\n+\t/* copy from the next struct field */\n+\tfrom = src_ctx + ce_info->offset;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\tmask = BIT(ce_info->width) - 1;\n+\n+\t/* don't swizzle the bits until after the mask because the mask bits\n+\t * will be in a different bit position on big endian machines\n+\t */\n+\tsrc_word = *(u16 *)from;\n+\tsrc_word &= mask;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\tsrc_word <<= shift_width;\n+\n+\t/* get the current bits from the target bit string */\n+\tdest = dest_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);\n+\n+\tdest_word &= ~(CPU_TO_LE16(mask));\t/* get the bits not changing */\n+\tdest_word |= CPU_TO_LE16(src_word);\t/* add in the new bits */\n+\n+\t/* put it all back */\n+\tice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_write_dword - write a dword to a packed context structure\n+ * @src_ctx:  the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info:  a description of the struct to be filled\n+ */\n+static void\n+ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+{\n+\tu32 src_dword, mask;\n+\t__le32 dest_dword;\n+\tu8 *from, *dest;\n+\tu16 shift_width;\n+\n+\t/* copy from the next struct field */\n+\tfrom = src_ctx + ce_info->offset;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\n+\t/* if the field width is exactly 32 on an x86 machine, then the shift\n+\t * operation will not work because the SHL instructions count is masked\n+\t * to 5 bits so the shift will do nothing\n+\t */\n+\tif (ce_info->width < 32)\n+\t\tmask = BIT(ce_info->width) - 1;\n+\telse\n+\t\tmask = (u32)~0;\n+\n+\t/* don't swizzle the bits until after the mask because the mask bits\n+\t * will be in a different bit position on big endian machines\n+\t */\n+\tsrc_dword = *(u32 *)from;\n+\tsrc_dword &= mask;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\tsrc_dword <<= shift_width;\n+\n+\t/* get the current bits from the target bit string */\n+\tdest = dest_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);\n+\n+\tdest_dword &= ~(CPU_TO_LE32(mask));\t/* get the bits not changing */\n+\tdest_dword |= CPU_TO_LE32(src_dword);\t/* add in the new bits */\n+\n+\t/* put it all back */\n+\tice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_write_qword - write a qword to a packed context structure\n+ * @src_ctx:  the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info:  a description of the struct to be filled\n+ */\n+static void\n+ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+{\n+\tu64 src_qword, mask;\n+\t__le64 dest_qword;\n+\tu8 *from, *dest;\n+\tu16 shift_width;\n+\n+\t/* copy from the next struct field */\n+\tfrom = src_ctx + ce_info->offset;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\n+\t/* if the field width is exactly 64 on an x86 machine, then the shift\n+\t * operation will not work because the SHL instructions count is masked\n+\t * to 6 bits so the shift will do nothing\n+\t */\n+\tif (ce_info->width < 64)\n+\t\tmask = BIT_ULL(ce_info->width) - 1;\n+\telse\n+\t\tmask = (u64)~0;\n+\n+\t/* don't swizzle the bits until after the mask because the mask bits\n+\t * will be in a different bit position on big endian machines\n+\t */\n+\tsrc_qword = *(u64 *)from;\n+\tsrc_qword &= mask;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\tsrc_qword <<= shift_width;\n+\n+\t/* get the current bits from the target bit string */\n+\tdest = dest_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);\n+\n+\tdest_qword &= ~(CPU_TO_LE64(mask));\t/* get the bits not changing */\n+\tdest_qword |= CPU_TO_LE64(src_qword);\t/* add in the new bits */\n+\n+\t/* put it all back */\n+\tice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_set_ctx - set context bits in packed structure\n+ * @src_ctx:  pointer to a generic non-packed context structure\n+ * @dest_ctx: pointer to memory for the packed structure\n+ * @ce_info:  a description of the structure to be transformed\n+ */\n+enum ice_status\n+ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+{\n+\tint f;\n+\n+\tfor (f = 0; ce_info[f].width; f++) {\n+\t\t/* We have to deal with each element of the FW response\n+\t\t * using the correct size so that we are correct regardless\n+\t\t * of the endianness of the machine.\n+\t\t */\n+\t\tswitch (ce_info[f].size_of) {\n+\t\tcase sizeof(u8):\n+\t\t\tice_write_byte(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tcase sizeof(u16):\n+\t\t\tice_write_word(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tcase sizeof(u32):\n+\t\t\tice_write_dword(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tcase sizeof(u64):\n+\t\t\tice_write_qword(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn ICE_ERR_INVAL_SIZE;\n+\t\t}\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+\n+\n+\n+\n+/**\n+ * ice_ena_vsi_txq\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: tc number\n+ * @num_qgrps: Number of added queue groups\n+ * @buf: list of queue groups to be added\n+ * @buf_size: size of buffer for indirect command\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function adds one lan q\n+ */\n+enum ice_status\n+ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_qgrps,\n+\t\tstruct ice_aqc_add_tx_qgrp *buf, u16 buf_size,\n+\t\tstruct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_txsched_elem_data node = { 0 };\n+\tstruct ice_sched_node *parent;\n+\tenum ice_status status;\n+\tstruct ice_hw *hw;\n+\n+\tif (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tif (num_qgrps > 1 || buf->num_txqs > 1)\n+\t\treturn ICE_ERR_MAX_LIMIT;\n+\n+\thw = pi->hw;\n+\n+\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\t/* find a parent node */\n+\tparent = ice_sched_get_free_qparent(pi, vsi_handle, tc,\n+\t\t\t\t\t    ICE_SCHED_NODE_OWNER_LAN);\n+\tif (!parent) {\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto ena_txq_exit;\n+\t}\n+\n+\tbuf->parent_teid = parent->info.node_teid;\n+\tnode.parent_teid = parent->info.node_teid;\n+\t/* Mark that the values in the \"generic\" section as valid. The default\n+\t * value in the \"generic\" section is zero. This means that :\n+\t * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.\n+\t * - 0 priority among siblings, indicated by Bit 1-3.\n+\t * - WFQ, indicated by Bit 4.\n+\t * - 0 Adjustment value is used in PSM credit update flow, indicated by\n+\t * Bit 5-6.\n+\t * - Bit 7 is reserved.\n+\t * Without setting the generic section as valid in valid_sections, the\n+\t * Admin Q command will fail with error code ICE_AQ_RC_EINVAL.\n+\t */\n+\tbuf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;\n+\n+\t/* add the lan q */\n+\tstatus = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);\n+\tif (status != ICE_SUCCESS) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"enable Q %d failed %d\\n\",\n+\t\t\t  LE16_TO_CPU(buf->txqs[0].txq_id),\n+\t\t\t  hw->adminq.sq_last_status);\n+\t\tgoto ena_txq_exit;\n+\t}\n+\n+\tnode.node_teid = buf->txqs[0].q_teid;\n+\tnode.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;\n+\n+\t/* add a leaf node into schduler tree q layer */\n+\tstatus = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);\n+\n+ena_txq_exit:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_dis_vsi_txq\n+ * @pi: port information structure\n+ * @num_queues: number of queues\n+ * @q_ids: pointer to the q_id array\n+ * @q_teids: pointer to queue node teids\n+ * @rst_src: if called due to reset, specifies the rst source\n+ * @vmvf_num: the relative vm or vf number that is undergoing the reset\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function removes queues and their corresponding nodes in SW DB\n+ */\n+enum ice_status\n+ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,\n+\t\tu32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num,\n+\t\tstruct ice_sq_cd *cd)\n+{\n+\tenum ice_status status = ICE_ERR_DOES_NOT_EXIST;\n+\tstruct ice_aqc_dis_txq_item qg_list;\n+\tu16 i;\n+\n+\tif (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)\n+\t\treturn ICE_ERR_CFG;\n+\n+\t/* if queue is disabled already yet the disable queue command has to be\n+\t * sent to complete the VF reset, then call ice_aq_dis_lan_txq without\n+\t * any queue information\n+\t */\n+\n+\tif (!num_queues && rst_src)\n+\t\treturn ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, vmvf_num,\n+\t\t\t\t\t  NULL);\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\tfor (i = 0; i < num_queues; i++) {\n+\t\tstruct ice_sched_node *node;\n+\n+\t\tnode = ice_sched_find_node_by_teid(pi->root, q_teids[i]);\n+\t\tif (!node)\n+\t\t\tcontinue;\n+\t\tqg_list.parent_teid = node->info.parent_teid;\n+\t\tqg_list.num_qs = 1;\n+\t\tqg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);\n+\t\tstatus = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,\n+\t\t\t\t\t    sizeof(qg_list), rst_src, vmvf_num,\n+\t\t\t\t\t    cd);\n+\n+\t\tif (status != ICE_SUCCESS)\n+\t\t\tbreak;\n+\t\tice_free_sched_node(pi, node);\n+\t}\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_vsi_qs - configure the new/exisiting VSI queues\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc_bitmap: TC bitmap\n+ * @maxqs: max queues array per TC\n+ * @owner: lan or rdma\n+ *\n+ * This function adds/updates the VSI queues per TC.\n+ */\n+static enum ice_status\n+ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n+\t       u16 *maxqs, u8 owner)\n+{\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 i;\n+\n+\tif (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\tfor (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) {\n+\t\t/* configuration is possible only if TC node is present */\n+\t\tif (!ice_sched_get_tc_node(pi, i))\n+\t\t\tcontinue;\n+\n+\t\tstatus = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,\n+\t\t\t\t\t   ice_is_tc_ena(tc_bitmap, i));\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_vsi_lan - configure VSI lan queues\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc_bitmap: TC bitmap\n+ * @max_lanqs: max lan queues array per TC\n+ *\n+ * This function adds/updates the VSI lan queues per TC.\n+ */\n+enum ice_status\n+ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n+\t\tu16 *max_lanqs)\n+{\n+\treturn ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,\n+\t\t\t      ICE_SCHED_NODE_OWNER_LAN);\n+}\n+\n+\n+\n+/**\n+ * ice_replay_pre_init - replay pre initialization\n+ * @hw: pointer to the hw struct\n+ *\n+ * Initializes required config data for VSI, FD, ACL, and RSS before replay.\n+ */\n+static enum ice_status ice_replay_pre_init(struct ice_hw *hw)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tu8 i;\n+\n+\t/* Delete old entries from replay filter list head if there is any */\n+\tice_rm_all_sw_replay_rule_info(hw);\n+\t/* In start of replay, move entries into replay_rules list, it\n+\t * will allow adding rules entries back to filt_rules list,\n+\t * which is operational list.\n+\t */\n+\tfor (i = 0; i < ICE_MAX_NUM_RECIPES; i++)\n+\t\tLIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,\n+\t\t\t\t  &sw->recp_list[i].filt_replay_rules);\n+\tice_sched_replay_agg_vsi_preinit(hw);\n+\n+\treturn ice_sched_replay_tc_node_bw(hw);\n+}\n+\n+/**\n+ * ice_replay_vsi - replay vsi configuration\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: driver vsi handle\n+ *\n+ * Restore all VSI configuration after reset. It is required to call this\n+ * function with main VSI first.\n+ */\n+enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\tenum ice_status status;\n+\n+\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Replay pre-initialization if there is any */\n+\tif (vsi_handle == ICE_MAIN_VSI_HANDLE) {\n+\t\tstatus = ice_replay_pre_init(hw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\t/* Replay per VSI all filters */\n+\tstatus = ice_replay_vsi_all_fltr(hw, vsi_handle);\n+\tif (!status)\n+\t\tstatus = ice_replay_vsi_agg(hw, vsi_handle);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_replay_post - post replay configuration cleanup\n+ * @hw: pointer to the hw struct\n+ *\n+ * Post replay cleanup.\n+ */\n+void ice_replay_post(struct ice_hw *hw)\n+{\n+\t/* Delete old entries from replay filter list head */\n+\tice_rm_all_sw_replay_rule_info(hw);\n+\tice_sched_replay_agg(hw);\n+}\n+\n+/**\n+ * ice_stat_update40 - read 40 bit stat from the chip and update stat values\n+ * @hw: ptr to the hardware info\n+ * @hireg: high 32 bit HW register to read from\n+ * @loreg: low 32 bit HW register to read from\n+ * @prev_stat_loaded: bool to specify if previous stats are loaded\n+ * @prev_stat: ptr to previous loaded stat value\n+ * @cur_stat: ptr to current stat value\n+ */\n+void\n+ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,\n+\t\t  bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat)\n+{\n+\tu64 new_data;\n+\n+\tnew_data = rd32(hw, loreg);\n+\tnew_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;\n+\n+\t/* device stats are not reset at PFR, they likely will not be zeroed\n+\t * when the driver starts. So save the first values read and use them as\n+\t * offsets to be subtracted from the raw values in order to report stats\n+\t * that count from zero.\n+\t */\n+\tif (!prev_stat_loaded)\n+\t\t*prev_stat = new_data;\n+\tif (new_data >= *prev_stat)\n+\t\t*cur_stat = new_data - *prev_stat;\n+\telse\n+\t\t/* to manage the potential roll-over */\n+\t\t*cur_stat = (new_data + BIT_ULL(40)) - *prev_stat;\n+\t*cur_stat &= 0xFFFFFFFFFFULL;\n+}\n+\n+/**\n+ * ice_stat_update32 - read 32 bit stat from the chip and update stat values\n+ * @hw: ptr to the hardware info\n+ * @reg: HW register to read from\n+ * @prev_stat_loaded: bool to specify if previous stats are loaded\n+ * @prev_stat: ptr to previous loaded stat value\n+ * @cur_stat: ptr to current stat value\n+ */\n+void\n+ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,\n+\t\t  u64 *prev_stat, u64 *cur_stat)\n+{\n+\tu32 new_data;\n+\n+\tnew_data = rd32(hw, reg);\n+\n+\t/* device stats are not reset at PFR, they likely will not be zeroed\n+\t * when the driver starts. So save the first values read and use them as\n+\t * offsets to be subtracted from the raw values in order to report stats\n+\t * that count from zero.\n+\t */\n+\tif (!prev_stat_loaded)\n+\t\t*prev_stat = new_data;\n+\tif (new_data >= *prev_stat)\n+\t\t*cur_stat = new_data - *prev_stat;\n+\telse\n+\t\t/* to manage the potential roll-over */\n+\t\t*cur_stat = (new_data + BIT_ULL(32)) - *prev_stat;\n+}\n+\n+\n+/**\n+ * ice_sched_query_elem - query element information from hw\n+ * @hw: pointer to the hw struct\n+ * @node_teid: node teid to be queried\n+ * @buf: buffer to element information\n+ *\n+ * This function queries HW element information\n+ */\n+enum ice_status\n+ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,\n+\t\t     struct ice_aqc_get_elem *buf)\n+{\n+\tu16 buf_size, num_elem_ret = 0;\n+\tenum ice_status status;\n+\n+\tbuf_size = sizeof(*buf);\n+\tice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);\n+\tbuf->generic[0].node_teid = CPU_TO_LE32(node_teid);\n+\tstatus = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,\n+\t\t\t\t\t  NULL);\n+\tif (status != ICE_SUCCESS || num_elem_ret != 1)\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"query element failed\\n\");\n+\treturn status;\n+}\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nnew file mode 100644\nindex 0000000..082ae66\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -0,0 +1,186 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_COMMON_H_\n+#define _ICE_COMMON_H_\n+\n+#include \"ice_type.h\"\n+\n+#include \"ice_switch.h\"\n+\n+/* prototype for functions used for SW locks */\n+void ice_free_list(struct LIST_HEAD_TYPE *list);\n+void ice_init_lock(struct ice_lock *lock);\n+void ice_acquire_lock(struct ice_lock *lock);\n+void ice_release_lock(struct ice_lock *lock);\n+void ice_destroy_lock(struct ice_lock *lock);\n+\n+void *ice_alloc_dma_mem(struct ice_hw *hw, struct ice_dma_mem *m, u64 size);\n+void ice_free_dma_mem(struct ice_hw *hw, struct ice_dma_mem *m);\n+\n+bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq);\n+\n+enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);\n+\n+void\n+ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len);\n+enum ice_status ice_init_hw(struct ice_hw *hw);\n+void ice_deinit_hw(struct ice_hw *hw);\n+enum ice_status ice_check_reset(struct ice_hw *hw);\n+enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);\n+\n+enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);\n+void ice_shutdown_all_ctrlq(struct ice_hw *hw);\n+enum ice_status\n+ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n+\t\t  struct ice_rq_event_info *e, u16 *pending);\n+enum ice_status\n+ice_get_link_status(struct ice_port_info *pi, bool *link_up);\n+enum ice_status\n+ice_update_link_info(struct ice_port_info *pi);\n+enum ice_status\n+ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,\n+\t\tenum ice_aq_res_access_type access, u32 timeout);\n+void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);\n+enum ice_status\n+ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,\n+\t\t      struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,\n+\t\t      enum ice_adminq_opc opc, struct ice_sq_cd *cd);\n+enum ice_status ice_init_nvm(struct ice_hw *hw);\n+enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);\n+enum ice_status\n+ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);\n+enum ice_status\n+ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n+\t\tstruct ice_aq_desc *desc, void *buf, u16 buf_size,\n+\t\tstruct ice_sq_cd *cd);\n+void ice_clear_pxe_mode(struct ice_hw *hw);\n+\n+enum ice_status ice_get_caps(struct ice_hw *hw);\n+\n+\n+\n+#if defined(FPGA_SUPPORT) || defined(CVL_A0_SUPPORT)\n+void ice_dev_onetime_setup(struct ice_hw *hw);\n+#endif /* FPGA_SUPPORT || CVL_A0_SUPPORT */\n+\n+\n+enum ice_status\n+ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n+\t\t  u32 rxq_index);\n+#if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)\n+enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);\n+enum ice_status\n+ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);\n+enum ice_status\n+ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,\n+\t\t\t struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,\n+\t\t\t u32 tx_cmpltnq_index);\n+enum ice_status\n+ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index);\n+enum ice_status\n+ice_write_tx_drbell_q_ctx(struct ice_hw *hw,\n+\t\t\t  struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,\n+\t\t\t  u32 tx_drbell_q_index);\n+#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */\n+\n+enum ice_status\n+ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,\n+\t\t   u16 lut_size);\n+enum ice_status\n+ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,\n+\t\t   u16 lut_size);\n+enum ice_status\n+ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,\n+\t\t   struct ice_aqc_get_set_rss_keys *keys);\n+enum ice_status\n+ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,\n+\t\t   struct ice_aqc_get_set_rss_keys *keys);\n+\n+bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);\n+enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);\n+void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);\n+extern const struct ice_ctx_ele ice_tlan_ctx_info[];\n+enum ice_status\n+ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);\n+enum ice_status\n+ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,\n+\t\tvoid *buf, u16 buf_size, struct ice_sq_cd *cd);\n+enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);\n+\n+enum ice_status\n+ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,\n+\t\t    struct ice_aqc_get_phy_caps_data *caps,\n+\t\t    struct ice_sq_cd *cd);\n+void\n+ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,\n+\t\t    u16 link_speeds_bitmap);\n+enum ice_status\n+ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,\n+\t\t\tstruct ice_sq_cd *cd);\n+\n+enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);\n+enum ice_status\n+ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,\n+\t\t   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);\n+enum ice_status\n+ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,\n+\t   bool ena_auto_link_update);\n+void\n+ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);\n+void\n+ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,\n+\t\t\t struct ice_aqc_set_phy_cfg_data *cfg);\n+enum ice_status\n+ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,\n+\t\t\t   struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n+\t\t     struct ice_link_status *link, struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,\n+\t\t      struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);\n+\n+\n+enum ice_status\n+ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,\n+\t\t       struct ice_sq_cd *cd);\n+\n+\n+\n+\n+enum ice_status\n+ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,\n+\t\tu32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num,\n+\t\tstruct ice_sq_cd *cmd_details);\n+enum ice_status\n+ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n+\t\tu16 *max_lanqs);\n+enum ice_status\n+ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_qgrps,\n+\t\tstruct ice_aqc_add_tx_qgrp *buf, u16 buf_size,\n+\t\tstruct ice_sq_cd *cd);\n+enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);\n+void ice_replay_post(struct ice_hw *hw);\n+void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);\n+void ice_sched_replay_agg(struct ice_hw *hw);\n+enum ice_status ice_sched_replay_tc_node_bw(struct ice_hw *hw);\n+enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);\n+enum ice_status\n+ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,\n+\t\t\t enum ice_rl_type rl_type, u8 bw_alloc);\n+enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);\n+void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf);\n+void\n+ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,\n+\t\t  bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat);\n+void\n+ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,\n+\t\t  u64 *prev_stat, u64 *cur_stat);\n+enum ice_status\n+ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,\n+\t\t     struct ice_aqc_get_elem *buf);\n+#endif /* _ICE_COMMON_H_ */\n",
    "prefixes": [
        "v5",
        "10/31"
    ]
}