Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 48975,
    "url": "https://patches.dpdk.org/api/patches/48975/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-8-git-send-email-wenzhuo.lu@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1545032259-77179-8-git-send-email-wenzhuo.lu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1545032259-77179-8-git-send-email-wenzhuo.lu@intel.com",
    "date": "2018-12-17T07:37:15",
    "name": "[v5,07/31] net/ice/base: add basic transmit scheduler",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "cd8888dc67e8e7658b09069acbc5978bc7e9bf22",
    "submitter": {
        "id": 258,
        "url": "https://patches.dpdk.org/api/people/258/?format=api",
        "name": "Wenzhuo Lu",
        "email": "wenzhuo.lu@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "https://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-8-git-send-email-wenzhuo.lu@intel.com/mbox/",
    "series": [
        {
            "id": 2824,
            "url": "https://patches.dpdk.org/api/series/2824/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2824",
            "date": "2018-12-17T07:37:08",
            "name": "A new net PMD - ICE",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/2824/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/48975/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/48975/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7B6211B5EE;\n\tMon, 17 Dec 2018 08:33:08 +0100 (CET)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id DDAE91B5B8\n\tfor <dev@dpdk.org>; Mon, 17 Dec 2018 08:33:03 +0100 (CET)",
            "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Dec 2018 23:33:02 -0800",
            "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby orsmga002.jf.intel.com with ESMTP; 16 Dec 2018 23:33:00 -0800"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.56,364,1539673200\"; d=\"scan'208\";a=\"118899127\"",
        "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>",
        "Date": "Mon, 17 Dec 2018 15:37:15 +0800",
        "Message-Id": "<1545032259-77179-8-git-send-email-wenzhuo.lu@intel.com>",
        "X-Mailer": "git-send-email 1.9.3",
        "In-Reply-To": "<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>",
        "References": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v5 07/31] net/ice/base: add basic transmit\n\tscheduler",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n\nAdd code for the basic TX scheduler.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n---\n drivers/net/ice/base/ice_sched.c | 5380 ++++++++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_sched.h |  210 ++\n 2 files changed, 5590 insertions(+)\n create mode 100644 drivers/net/ice/base/ice_sched.c\n create mode 100644 drivers/net/ice/base/ice_sched.h",
    "diff": "diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nnew file mode 100644\nindex 0000000..7acbae6\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -0,0 +1,5380 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#include \"ice_sched.h\"\n+\n+\n+/**\n+ * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB\n+ * @pi: port information structure\n+ * @info: Scheduler element information from firmware\n+ *\n+ * This function inserts the root node of the scheduling tree topology\n+ * to the SW DB.\n+ */\n+static enum ice_status\n+ice_sched_add_root_node(struct ice_port_info *pi,\n+\t\t\tstruct ice_aqc_txsched_elem_data *info)\n+{\n+\tstruct ice_sched_node *root;\n+\tstruct ice_hw *hw;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\thw = pi->hw;\n+\n+\troot = (struct ice_sched_node *)ice_malloc(hw, sizeof(*root));\n+\tif (!root)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\t/* coverity[suspicious_sizeof] */\n+\troot->children = (struct ice_sched_node **)\n+\t\tice_calloc(hw, hw->max_children[0], sizeof(*root));\n+\tif (!root->children) {\n+\t\tice_free(hw, root);\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\t}\n+\n+\tice_memcpy(&root->info, info, sizeof(*info), ICE_DMA_TO_NONDMA);\n+\tpi->root = root;\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_find_node_by_teid - Find the Tx scheduler node in SW DB\n+ * @start_node: pointer to the starting ice_sched_node struct in a sub-tree\n+ * @teid: node teid to search\n+ *\n+ * This function searches for a node matching the teid in the scheduling tree\n+ * from the SW DB. The search is recursive and is restricted by the number of\n+ * layers it has searched through; stopping at the max supported layer.\n+ *\n+ * This function needs to be called when holding the port_info->sched_lock\n+ */\n+struct ice_sched_node *\n+ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid)\n+{\n+\tu16 i;\n+\n+\t/* The TEID is same as that of the start_node */\n+\tif (ICE_TXSCHED_GET_NODE_TEID(start_node) == teid)\n+\t\treturn start_node;\n+\n+\t/* The node has no children or is at the max layer */\n+\tif (!start_node->num_children ||\n+\t    start_node->tx_sched_layer >= ICE_AQC_TOPO_MAX_LEVEL_NUM ||\n+\t    start_node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF)\n+\t\treturn NULL;\n+\n+\t/* Check if teid matches to any of the children nodes */\n+\tfor (i = 0; i < start_node->num_children; i++)\n+\t\tif (ICE_TXSCHED_GET_NODE_TEID(start_node->children[i]) == teid)\n+\t\t\treturn start_node->children[i];\n+\n+\t/* Search within each child's sub-tree */\n+\tfor (i = 0; i < start_node->num_children; i++) {\n+\t\tstruct ice_sched_node *tmp;\n+\n+\t\ttmp = ice_sched_find_node_by_teid(start_node->children[i],\n+\t\t\t\t\t\t  teid);\n+\t\tif (tmp)\n+\t\t\treturn tmp;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_aqc_send_sched_elem_cmd - send scheduling elements cmd\n+ * @hw: pointer to the hw struct\n+ * @cmd_opc: cmd opcode\n+ * @elems_req: number of elements to request\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @elems_resp: returns total number of elements response\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function sends a scheduling elements cmd (cmd_opc)\n+ */\n+static enum ice_status\n+ice_aqc_send_sched_elem_cmd(struct ice_hw *hw, enum ice_adminq_opc cmd_opc,\n+\t\t\t    u16 elems_req, void *buf, u16 buf_size,\n+\t\t\t    u16 *elems_resp, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_sched_elem_cmd *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.sched_elem_cmd;\n+\tice_fill_dflt_direct_cmd_desc(&desc, cmd_opc);\n+\tcmd->num_elem_req = CPU_TO_LE16(elems_req);\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (!status && elems_resp)\n+\t\t*elems_resp = LE16_TO_CPU(cmd->num_elem_resp);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_query_sched_elems - query scheduler elements\n+ * @hw: pointer to the hw struct\n+ * @elems_req: number of elements to query\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @elems_ret: returns total number of elements returned\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Query scheduling elements (0x0404)\n+ */\n+enum ice_status\n+ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,\n+\t\t\t struct ice_aqc_get_elem *buf, u16 buf_size,\n+\t\t\t u16 *elems_ret, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_get_sched_elems,\n+\t\t\t\t\t   elems_req, (void *)buf, buf_size,\n+\t\t\t\t\t   elems_ret, cd);\n+}\n+\n+/**\n+ * ice_sched_add_node - Insert the Tx scheduler node in SW DB\n+ * @pi: port information structure\n+ * @layer: Scheduler layer of the node\n+ * @info: Scheduler element information from firmware\n+ *\n+ * This function inserts a scheduler node to the SW DB.\n+ */\n+enum ice_status\n+ice_sched_add_node(struct ice_port_info *pi, u8 layer,\n+\t\t   struct ice_aqc_txsched_elem_data *info)\n+{\n+\tstruct ice_sched_node *parent;\n+\tstruct ice_aqc_get_elem elem;\n+\tstruct ice_sched_node *node;\n+\tenum ice_status status;\n+\tstruct ice_hw *hw;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\thw = pi->hw;\n+\n+\t/* A valid parent node should be there */\n+\tparent = ice_sched_find_node_by_teid(pi->root,\n+\t\t\t\t\t     LE32_TO_CPU(info->parent_teid));\n+\tif (!parent) {\n+\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t  \"Parent Node not found for parent_teid=0x%x\\n\",\n+\t\t\t  LE32_TO_CPU(info->parent_teid));\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\t/* query the current node information from FW  before additing it\n+\t * to the SW DB\n+\t */\n+\tstatus = ice_sched_query_elem(hw, LE32_TO_CPU(info->node_teid), &elem);\n+\tif (status)\n+\t\treturn status;\n+\tnode = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node));\n+\tif (!node)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\tif (hw->max_children[layer]) {\n+\t\t/* coverity[suspicious_sizeof] */\n+\t\tnode->children = (struct ice_sched_node **)\n+\t\t\tice_calloc(hw, hw->max_children[layer], sizeof(*node));\n+\t\tif (!node->children) {\n+\t\t\tice_free(hw, node);\n+\t\t\treturn ICE_ERR_NO_MEMORY;\n+\t\t}\n+\t}\n+\n+\tnode->in_use = true;\n+\tnode->parent = parent;\n+\tnode->tx_sched_layer = layer;\n+\tparent->children[parent->num_children++] = node;\n+\tnode->info = elem.generic[0];\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_aq_delete_sched_elems - delete scheduler elements\n+ * @hw: pointer to the hw struct\n+ * @grps_req: number of groups to delete\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @grps_del: returns total number of elements deleted\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Delete scheduling elements (0x040F)\n+ */\n+static enum ice_status\n+ice_aq_delete_sched_elems(struct ice_hw *hw, u16 grps_req,\n+\t\t\t  struct ice_aqc_delete_elem *buf, u16 buf_size,\n+\t\t\t  u16 *grps_del, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_delete_sched_elems,\n+\t\t\t\t\t   grps_req, (void *)buf, buf_size,\n+\t\t\t\t\t   grps_del, cd);\n+}\n+\n+/**\n+ * ice_sched_remove_elems - remove nodes from hw\n+ * @hw: pointer to the hw struct\n+ * @parent: pointer to the parent node\n+ * @num_nodes: number of nodes\n+ * @node_teids: array of node teids to be deleted\n+ *\n+ * This function remove nodes from hw\n+ */\n+static enum ice_status\n+ice_sched_remove_elems(struct ice_hw *hw, struct ice_sched_node *parent,\n+\t\t       u16 num_nodes, u32 *node_teids)\n+{\n+\tstruct ice_aqc_delete_elem *buf;\n+\tu16 i, num_groups_removed = 0;\n+\tenum ice_status status;\n+\tu16 buf_size;\n+\n+\tbuf_size = sizeof(*buf) + sizeof(u32) * (num_nodes - 1);\n+\tbuf = (struct ice_aqc_delete_elem *)ice_malloc(hw, buf_size);\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tbuf->hdr.parent_teid = parent->info.node_teid;\n+\tbuf->hdr.num_elems = CPU_TO_LE16(num_nodes);\n+\tfor (i = 0; i < num_nodes; i++)\n+\t\tbuf->teid[i] = CPU_TO_LE32(node_teids[i]);\n+\n+\tstatus = ice_aq_delete_sched_elems(hw, 1, buf, buf_size,\n+\t\t\t\t\t   &num_groups_removed, NULL);\n+\tif (status != ICE_SUCCESS || num_groups_removed != 1)\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"remove node failed FW error %d\\n\",\n+\t\t\t  hw->adminq.sq_last_status);\n+\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_get_first_node - get the first node of the given layer\n+ * @hw: pointer to the hw struct\n+ * @parent: pointer the base node of the subtree\n+ * @layer: layer number\n+ *\n+ * This function retrieves the first node of the given layer from the subtree\n+ */\n+static struct ice_sched_node *\n+ice_sched_get_first_node(struct ice_hw *hw, struct ice_sched_node *parent,\n+\t\t\t u8 layer)\n+{\n+\tu8 i;\n+\n+\tif (layer < hw->sw_entry_point_layer)\n+\t\treturn NULL;\n+\tfor (i = 0; i < parent->num_children; i++) {\n+\t\tstruct ice_sched_node *node = parent->children[i];\n+\n+\t\tif (node) {\n+\t\t\tif (node->tx_sched_layer == layer)\n+\t\t\t\treturn node;\n+\t\t\t/* this recursion is intentional, and wouldn't\n+\t\t\t * go more than 9 calls\n+\t\t\t */\n+\t\t\treturn ice_sched_get_first_node(hw, node, layer);\n+\t\t}\n+\t}\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_sched_get_tc_node - get pointer to TC node\n+ * @pi: port information structure\n+ * @tc: TC number\n+ *\n+ * This function returns the TC node pointer\n+ */\n+struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc)\n+{\n+\tu8 i;\n+\n+\tif (!pi)\n+\t\treturn NULL;\n+\tfor (i = 0; i < pi->root->num_children; i++)\n+\t\tif (pi->root->children[i]->tc_num == tc)\n+\t\t\treturn pi->root->children[i];\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_free_sched_node - Free a Tx scheduler node from SW DB\n+ * @pi: port information structure\n+ * @node: pointer to the ice_sched_node struct\n+ *\n+ * This function frees up a node from SW DB as well as from HW\n+ *\n+ * This function needs to be called with the port_info->sched_lock held\n+ */\n+void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node)\n+{\n+\tstruct ice_sched_node *parent;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu8 i, j;\n+\n+\t/* Free the children before freeing up the parent node\n+\t * The parent array is updated below and that shifts the nodes\n+\t * in the array. So always pick the first child if num children > 0\n+\t */\n+\twhile (node->num_children)\n+\t\tice_free_sched_node(pi, node->children[0]);\n+\n+\t/* Leaf, TC and root nodes can't be deleted by SW */\n+\tif (node->tx_sched_layer >= hw->sw_entry_point_layer &&\n+\t    node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC &&\n+\t    node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT &&\n+\t    node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) {\n+\t\tu32 teid = LE32_TO_CPU(node->info.node_teid);\n+\n+\t\tice_sched_remove_elems(hw, node->parent, 1, &teid);\n+\t}\n+\tparent = node->parent;\n+\t/* root has no parent */\n+\tif (parent) {\n+\t\tstruct ice_sched_node *p, *tc_node;\n+\n+\t\t/* update the parent */\n+\t\tfor (i = 0; i < parent->num_children; i++)\n+\t\t\tif (parent->children[i] == node) {\n+\t\t\t\tfor (j = i + 1; j < parent->num_children; j++)\n+\t\t\t\t\tparent->children[j - 1] =\n+\t\t\t\t\t\tparent->children[j];\n+\t\t\t\tparent->num_children--;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t/* search for previous sibling that points to this node and\n+\t\t * remove the reference\n+\t\t */\n+\t\ttc_node = ice_sched_get_tc_node(pi, node->tc_num);\n+\t\tif (!tc_node) {\n+\t\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t\t  \"Invalid TC number %d\\n\", node->tc_num);\n+\t\t\tgoto err_exit;\n+\t\t}\n+\t\tp = ice_sched_get_first_node(hw, tc_node, node->tx_sched_layer);\n+\t\twhile (p) {\n+\t\t\tif (p->sibling == node) {\n+\t\t\t\tp->sibling = node->sibling;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tp = p->sibling;\n+\t\t}\n+\t}\n+err_exit:\n+\t/* leaf nodes have no children */\n+\tif (node->children)\n+\t\tice_free(hw, node->children);\n+\tice_free(hw, node);\n+}\n+\n+/**\n+ * ice_aq_get_dflt_topo - gets default scheduler topology\n+ * @hw: pointer to the hw struct\n+ * @lport: logical port number\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @num_branches: returns total number of queue to port branches\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Get default scheduler topology (0x400)\n+ */\n+static enum ice_status\n+ice_aq_get_dflt_topo(struct ice_hw *hw, u8 lport,\n+\t\t     struct ice_aqc_get_topo_elem *buf, u16 buf_size,\n+\t\t     u8 *num_branches, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_get_topo *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.get_topo;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_dflt_topo);\n+\tcmd->port_num = lport;\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (!status && num_branches)\n+\t\t*num_branches = cmd->num_branches;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_add_sched_elems - adds scheduling element\n+ * @hw: pointer to the hw struct\n+ * @grps_req: the number of groups that are requested to be added\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @grps_added: returns total number of groups added\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Add scheduling elements (0x0401)\n+ */\n+static enum ice_status\n+ice_aq_add_sched_elems(struct ice_hw *hw, u16 grps_req,\n+\t\t       struct ice_aqc_add_elem *buf, u16 buf_size,\n+\t\t       u16 *grps_added, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_add_sched_elems,\n+\t\t\t\t\t   grps_req, (void *)buf, buf_size,\n+\t\t\t\t\t   grps_added, cd);\n+}\n+\n+/**\n+ * ice_aq_cfg_sched_elems - configures scheduler elements\n+ * @hw: pointer to the hw struct\n+ * @elems_req: number of elements to configure\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @elems_cfgd: returns total number of elements configured\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Configure scheduling elements (0x0403)\n+ */\n+static enum ice_status\n+ice_aq_cfg_sched_elems(struct ice_hw *hw, u16 elems_req,\n+\t\t       struct ice_aqc_conf_elem *buf, u16 buf_size,\n+\t\t       u16 *elems_cfgd, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_cfg_sched_elems,\n+\t\t\t\t\t   elems_req, (void *)buf, buf_size,\n+\t\t\t\t\t   elems_cfgd, cd);\n+}\n+\n+/**\n+ * ice_aq_move_sched_elems - move scheduler elements\n+ * @hw: pointer to the hw struct\n+ * @grps_req: number of groups to move\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @grps_movd: returns total number of groups moved\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Move scheduling elements (0x0408)\n+ */\n+enum ice_status\n+ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req,\n+\t\t\tstruct ice_aqc_move_elem *buf, u16 buf_size,\n+\t\t\tu16 *grps_movd, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_move_sched_elems,\n+\t\t\t\t\t   grps_req, (void *)buf, buf_size,\n+\t\t\t\t\t   grps_movd, cd);\n+}\n+\n+/**\n+ * ice_aq_suspend_sched_elems - suspend scheduler elements\n+ * @hw: pointer to the hw struct\n+ * @elems_req: number of elements to suspend\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @elems_ret: returns total number of elements suspended\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Suspend scheduling elements (0x0409)\n+ */\n+static enum ice_status\n+ice_aq_suspend_sched_elems(struct ice_hw *hw, u16 elems_req,\n+\t\t\t   struct ice_aqc_suspend_resume_elem *buf,\n+\t\t\t   u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_suspend_sched_elems,\n+\t\t\t\t\t   elems_req, (void *)buf, buf_size,\n+\t\t\t\t\t   elems_ret, cd);\n+}\n+\n+/**\n+ * ice_aq_resume_sched_elems - resume scheduler elements\n+ * @hw: pointer to the hw struct\n+ * @elems_req: number of elements to resume\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @elems_ret: returns total number of elements resumed\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * resume scheduling elements (0x040A)\n+ */\n+static enum ice_status\n+ice_aq_resume_sched_elems(struct ice_hw *hw, u16 elems_req,\n+\t\t\t  struct ice_aqc_suspend_resume_elem *buf,\n+\t\t\t  u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_resume_sched_elems,\n+\t\t\t\t\t   elems_req, (void *)buf, buf_size,\n+\t\t\t\t\t   elems_ret, cd);\n+}\n+\n+/**\n+ * ice_aq_query_sched_res - query scheduler resource\n+ * @hw: pointer to the hw struct\n+ * @buf_size: buffer size in bytes\n+ * @buf: pointer to buffer\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Query scheduler resource allocation (0x0412)\n+ */\n+static enum ice_status\n+ice_aq_query_sched_res(struct ice_hw *hw, u16 buf_size,\n+\t\t       struct ice_aqc_query_txsched_res_resp *buf,\n+\t\t       struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_sched_res);\n+\treturn ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+}\n+\n+/**\n+ * ice_sched_suspend_resume_elems - suspend or resume hw nodes\n+ * @hw: pointer to the hw struct\n+ * @num_nodes: number of nodes\n+ * @node_teids: array of node teids to be suspended or resumed\n+ * @suspend: true means suspend / false means resume\n+ *\n+ * This function suspends or resumes hw nodes\n+ */\n+static enum ice_status\n+ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids,\n+\t\t\t       bool suspend)\n+{\n+\tstruct ice_aqc_suspend_resume_elem *buf;\n+\tu16 i, buf_size, num_elem_ret = 0;\n+\tenum ice_status status;\n+\n+\tbuf_size = sizeof(*buf) * num_nodes;\n+\tbuf = (struct ice_aqc_suspend_resume_elem *)\n+\t\tice_malloc(hw, buf_size);\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tfor (i = 0; i < num_nodes; i++)\n+\t\tbuf->teid[i] = CPU_TO_LE32(node_teids[i]);\n+\n+\tif (suspend)\n+\t\tstatus = ice_aq_suspend_sched_elems(hw, num_nodes, buf,\n+\t\t\t\t\t\t    buf_size, &num_elem_ret,\n+\t\t\t\t\t\t    NULL);\n+\telse\n+\t\tstatus = ice_aq_resume_sched_elems(hw, num_nodes, buf,\n+\t\t\t\t\t\t   buf_size, &num_elem_ret,\n+\t\t\t\t\t\t   NULL);\n+\tif (status != ICE_SUCCESS || num_elem_ret != num_nodes)\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"suspend/resume failed\\n\");\n+\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_rl_profile - performs a rate limiting task\n+ * @hw: pointer to the hw struct\n+ * @opcode:opcode for add, query, or remove profile(s)\n+ * @num_profiles: the number of profiles\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @num_processed: number of processed add or remove profile(s) to return\n+ * @cd: pointer to command details structure\n+ *\n+ * Rl profile function to add, query, or remove profile(s)\n+ */\n+static enum ice_status\n+ice_aq_rl_profile(struct ice_hw *hw, enum ice_adminq_opc opcode,\n+\t\t  u16 num_profiles, struct ice_aqc_rl_profile_generic_elem *buf,\n+\t\t  u16 buf_size, u16 *num_processed, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_rl_profile *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.rl_profile;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, opcode);\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\tcmd->num_profiles = CPU_TO_LE16(num_profiles);\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (!status && num_processed)\n+\t\t*num_processed = LE16_TO_CPU(cmd->num_processed);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_add_rl_profile - adds rate limiting profile(s)\n+ * @hw: pointer to the hw struct\n+ * @num_profiles: the number of profile(s) to be add\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @num_profiles_added: total number of profiles added to return\n+ * @cd: pointer to command details structure\n+ *\n+ * Add rl profile (0x0410)\n+ */\n+static enum ice_status\n+ice_aq_add_rl_profile(struct ice_hw *hw, u16 num_profiles,\n+\t\t      struct ice_aqc_rl_profile_generic_elem *buf,\n+\t\t      u16 buf_size, u16 *num_profiles_added,\n+\t\t      struct ice_sq_cd *cd)\n+{\n+\treturn ice_aq_rl_profile(hw, ice_aqc_opc_add_rl_profiles,\n+\t\t\t\t num_profiles, buf,\n+\t\t\t\t buf_size, num_profiles_added, cd);\n+}\n+\n+/**\n+ * ice_aq_query_rl_profile - query rate limiting profile(s)\n+ * @hw: pointer to the hw struct\n+ * @num_profiles: the number of profile(s) to query\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @cd: pointer to command details structure\n+ *\n+ * Query rl profile (0x0411)\n+ */\n+enum ice_status\n+ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles,\n+\t\t\tstruct ice_aqc_rl_profile_generic_elem *buf,\n+\t\t\tu16 buf_size, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aq_rl_profile(hw, ice_aqc_opc_query_rl_profiles,\n+\t\t\t\t num_profiles, buf, buf_size, NULL, cd);\n+}\n+\n+/**\n+ * ice_aq_remove_rl_profile - removes rl profile(s)\n+ * @hw: pointer to the hw struct\n+ * @num_profiles: the number of profile(s) to remove\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @num_profiles_removed: total number of profiles removed to return\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Remove rl profile (0x0415)\n+ */\n+static enum ice_status\n+ice_aq_remove_rl_profile(struct ice_hw *hw, u16 num_profiles,\n+\t\t\t struct ice_aqc_rl_profile_generic_elem *buf,\n+\t\t\t u16 buf_size, u16 *num_profiles_removed,\n+\t\t\t struct ice_sq_cd *cd)\n+{\n+\treturn ice_aq_rl_profile(hw, ice_aqc_opc_remove_rl_profiles,\n+\t\t\t\t num_profiles, buf,\n+\t\t\t\t buf_size, num_profiles_removed, cd);\n+}\n+\n+/**\n+ * ice_sched_clear_rl_prof - clears rl prof entries\n+ * @pi: port information structure\n+ *\n+ * This function removes all rl profile from hw as well as from SW DB.\n+ */\n+static void ice_sched_clear_rl_prof(struct ice_port_info *pi)\n+{\n+\tu8 ln;\n+\n+\tfor (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {\n+\t\tstruct ice_aqc_rl_profile_info *rl_prof_elem;\n+\t\tstruct ice_aqc_rl_profile_info *rl_prof_tmp;\n+\n+\t\tLIST_FOR_EACH_ENTRY_SAFE(rl_prof_elem, rl_prof_tmp,\n+\t\t\t\t\t &pi->rl_prof_list[ln],\n+\t\t\t\t\t ice_aqc_rl_profile_info, list_entry) {\n+\t\t\tstruct ice_hw *hw = pi->hw;\n+\t\t\tenum ice_status status;\n+\n+\t\t\trl_prof_elem->prof_id_ref = 0;\n+\t\t\tstatus = ice_sched_del_rl_profile(hw, rl_prof_elem);\n+\t\t\tif (status) {\n+\t\t\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t\t\t  \"Remove rl profile failed\\n\");\n+\t\t\t\t/* On error, free mem required */\n+\t\t\t\tLIST_DEL(&rl_prof_elem->list_entry);\n+\t\t\t\tice_free(hw, rl_prof_elem);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * ice_sched_clear_agg - clears the agg related information\n+ * @hw: pointer to the hardware structure\n+ *\n+ * This function removes agg list and free up agg related memory\n+ * previously allocated.\n+ */\n+void ice_sched_clear_agg(struct ice_hw *hw)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\tstruct ice_sched_agg_info *atmp;\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &hw->agg_list,\n+\t\t\t\t ice_sched_agg_info,\n+\t\t\t\t list_entry) {\n+\t\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\t\tstruct ice_sched_agg_vsi_info *vtmp;\n+\n+\t\tLIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, vtmp,\n+\t\t\t\t\t &agg_info->agg_vsi_list,\n+\t\t\t\t\t ice_sched_agg_vsi_info, list_entry) {\n+\t\t\tLIST_DEL(&agg_vsi_info->list_entry);\n+\t\t\tice_free(hw, agg_vsi_info);\n+\t\t}\n+\t\tLIST_DEL(&agg_info->list_entry);\n+\t\tice_free(hw, agg_info);\n+\t}\n+}\n+\n+/**\n+ * ice_sched_clear_tx_topo - clears the schduler tree nodes\n+ * @pi: port information structure\n+ *\n+ * This function removes all the nodes from HW as well as from SW DB.\n+ */\n+static void ice_sched_clear_tx_topo(struct ice_port_info *pi)\n+{\n+\tif (!pi)\n+\t\treturn;\n+\t/* remove rl profiles related lists */\n+\tice_sched_clear_rl_prof(pi);\n+\tif (pi->root) {\n+\t\tice_free_sched_node(pi, pi->root);\n+\t\tpi->root = NULL;\n+\t}\n+}\n+\n+/**\n+ * ice_sched_clear_port - clear the scheduler elements from SW DB for a port\n+ * @pi: port information structure\n+ *\n+ * Cleanup scheduling elements from SW DB\n+ */\n+void ice_sched_clear_port(struct ice_port_info *pi)\n+{\n+\tif (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)\n+\t\treturn;\n+\n+\tpi->port_state = ICE_SCHED_PORT_STATE_INIT;\n+\tice_acquire_lock(&pi->sched_lock);\n+\tice_sched_clear_tx_topo(pi);\n+\tice_release_lock(&pi->sched_lock);\n+\tice_destroy_lock(&pi->sched_lock);\n+}\n+\n+/**\n+ * ice_sched_cleanup_all - cleanup scheduler elements from SW DB for all ports\n+ * @hw: pointer to the hw struct\n+ *\n+ * Cleanup scheduling elements from SW DB for all the ports\n+ */\n+void ice_sched_cleanup_all(struct ice_hw *hw)\n+{\n+\tif (!hw)\n+\t\treturn;\n+\n+\tif (hw->layer_info) {\n+\t\tice_free(hw, hw->layer_info);\n+\t\thw->layer_info = NULL;\n+\t}\n+\n+\tif (hw->port_info)\n+\t\tice_sched_clear_port(hw->port_info);\n+\n+\thw->num_tx_sched_layers = 0;\n+\thw->num_tx_sched_phys_layers = 0;\n+\thw->flattened_layers = 0;\n+\thw->max_cgds = 0;\n+}\n+\n+/**\n+ * ice_aq_cfg_l2_node_cgd - configures L2 node to CGD mapping\n+ * @hw: pointer to the hw struct\n+ * @num_l2_nodes: the number of L2 nodes whose CGDs to configure\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Configure L2 Node CGD (0x0414)\n+ */\n+enum ice_status\n+ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_l2_nodes,\n+\t\t       struct ice_aqc_cfg_l2_node_cgd_data *buf,\n+\t\t       u16 buf_size, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_cfg_l2_node_cgd *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.cfg_l2_node_cgd;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_l2_node_cgd);\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\tcmd->num_l2_nodes = CPU_TO_LE16(num_l2_nodes);\n+\treturn ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+}\n+\n+\n+/**\n+ * ice_sched_add_elems - add nodes to hw and SW DB\n+ * @pi: port information structure\n+ * @tc_node: pointer to the branch node\n+ * @parent: pointer to the parent node\n+ * @layer: layer number to add nodes\n+ * @num_nodes: number of nodes\n+ * @num_nodes_added: pointer to num nodes added\n+ * @first_node_teid: if new nodes are added then return the teid of first node\n+ *\n+ * This function add nodes to hw as well as to SW DB for a given layer\n+ */\n+static enum ice_status\n+ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node,\n+\t\t    struct ice_sched_node *parent, u8 layer, u16 num_nodes,\n+\t\t    u16 *num_nodes_added, u32 *first_node_teid)\n+{\n+\tstruct ice_sched_node *prev, *new_node;\n+\tstruct ice_aqc_add_elem *buf;\n+\tu16 i, num_groups_added = 0;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu16 buf_size;\n+\tu32 teid;\n+\n+\tbuf_size = sizeof(*buf) + sizeof(*buf->generic) * (num_nodes - 1);\n+\tbuf = (struct ice_aqc_add_elem *)ice_malloc(hw, buf_size);\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tbuf->hdr.parent_teid = parent->info.node_teid;\n+\tbuf->hdr.num_elems = CPU_TO_LE16(num_nodes);\n+\tfor (i = 0; i < num_nodes; i++) {\n+\t\tbuf->generic[i].parent_teid = parent->info.node_teid;\n+\t\tbuf->generic[i].data.elem_type = ICE_AQC_ELEM_TYPE_SE_GENERIC;\n+\t\tbuf->generic[i].data.valid_sections =\n+\t\t\tICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |\n+\t\t\tICE_AQC_ELEM_VALID_EIR;\n+\t\tbuf->generic[i].data.generic = 0;\n+\t\tbuf->generic[i].data.cir_bw.bw_profile_idx =\n+\t\t\tCPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);\n+\t\tbuf->generic[i].data.cir_bw.bw_alloc =\n+\t\t\tCPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);\n+\t\tbuf->generic[i].data.eir_bw.bw_profile_idx =\n+\t\t\tCPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);\n+\t\tbuf->generic[i].data.eir_bw.bw_alloc =\n+\t\t\tCPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);\n+\t}\n+\n+\tstatus = ice_aq_add_sched_elems(hw, 1, buf, buf_size,\n+\t\t\t\t\t&num_groups_added, NULL);\n+\tif (status != ICE_SUCCESS || num_groups_added != 1) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"add node failed FW Error %d\\n\",\n+\t\t\t  hw->adminq.sq_last_status);\n+\t\tice_free(hw, buf);\n+\t\treturn ICE_ERR_CFG;\n+\t}\n+\n+\t*num_nodes_added = num_nodes;\n+\t/* add nodes to the SW DB */\n+\tfor (i = 0; i < num_nodes; i++) {\n+\t\tstatus = ice_sched_add_node(pi, layer, &buf->generic[i]);\n+\t\tif (status != ICE_SUCCESS) {\n+\t\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t\t  \"add nodes in SW DB failed status =%d\\n\",\n+\t\t\t\t  status);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tteid = LE32_TO_CPU(buf->generic[i].node_teid);\n+\t\tnew_node = ice_sched_find_node_by_teid(parent, teid);\n+\t\tif (!new_node) {\n+\t\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t\t  \"Node is missing for teid =%d\\n\", teid);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tnew_node->sibling = NULL;\n+\t\tnew_node->tc_num = tc_node->tc_num;\n+\n+\t\t/* add it to previous node sibling pointer */\n+\t\t/* Note: siblings are not linked across branches */\n+\t\tprev = ice_sched_get_first_node(hw, tc_node, layer);\n+\t\tif (prev && prev != new_node) {\n+\t\t\twhile (prev->sibling)\n+\t\t\t\tprev = prev->sibling;\n+\t\t\tprev->sibling = new_node;\n+\t\t}\n+\n+\t\tif (i == 0)\n+\t\t\t*first_node_teid = teid;\n+\t}\n+\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_add_nodes_to_layer - Add nodes to a given layer\n+ * @pi: port information structure\n+ * @tc_node: pointer to TC node\n+ * @parent: pointer to parent node\n+ * @layer: layer number to add nodes\n+ * @num_nodes: number of nodes to be added\n+ * @first_node_teid: pointer to the first node teid\n+ * @num_nodes_added: pointer to number of nodes added\n+ *\n+ * This function add nodes to a given layer.\n+ */\n+static enum ice_status\n+ice_sched_add_nodes_to_layer(struct ice_port_info *pi,\n+\t\t\t     struct ice_sched_node *tc_node,\n+\t\t\t     struct ice_sched_node *parent, u8 layer,\n+\t\t\t     u16 num_nodes, u32 *first_node_teid,\n+\t\t\t     u16 *num_nodes_added)\n+{\n+\tu32 *first_teid_ptr = first_node_teid;\n+\tu16 new_num_nodes, max_child_nodes;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu16 num_added = 0;\n+\tu32 temp;\n+\n+\t*num_nodes_added = 0;\n+\n+\tif (!num_nodes)\n+\t\treturn status;\n+\n+\tif (!parent || layer < hw->sw_entry_point_layer)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* max children per node per layer */\n+\tmax_child_nodes = hw->max_children[parent->tx_sched_layer];\n+\n+\t/* current number of children + required nodes exceed max children ? */\n+\tif ((parent->num_children + num_nodes) > max_child_nodes) {\n+\t\t/* Fail if the parent is a TC node */\n+\t\tif (parent == tc_node)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\t/* utilize all the spaces if the parent is not full */\n+\t\tif (parent->num_children < max_child_nodes) {\n+\t\t\tnew_num_nodes = max_child_nodes - parent->num_children;\n+\t\t\t/* this recursion is intentional, and wouldn't\n+\t\t\t * go more than 2 calls\n+\t\t\t */\n+\t\t\tstatus = ice_sched_add_nodes_to_layer(pi, tc_node,\n+\t\t\t\t\t\t\t      parent, layer,\n+\t\t\t\t\t\t\t      new_num_nodes,\n+\t\t\t\t\t\t\t      first_node_teid,\n+\t\t\t\t\t\t\t      &num_added);\n+\t\t\tif (status != ICE_SUCCESS)\n+\t\t\t\treturn status;\n+\n+\t\t\t*num_nodes_added += num_added;\n+\t\t}\n+\t\t/* Don't modify the first node teid memory if the first node was\n+\t\t * added already in the above call. Instead send some temp\n+\t\t * memory for all other recursive calls.\n+\t\t */\n+\t\tif (num_added)\n+\t\t\tfirst_teid_ptr = &temp;\n+\n+\t\tnew_num_nodes = num_nodes - num_added;\n+\n+\t\t/* This parent is full, try the next sibling */\n+\t\tparent = parent->sibling;\n+\n+\t\t/* this recursion is intentional, for 1024 queues\n+\t\t * per VSI, it goes max of 16 iterations.\n+\t\t * 1024 / 8 = 128 layer 8 nodes\n+\t\t * 128 /8 = 16 (add 8 nodes per iteration)\n+\t\t */\n+\t\tstatus = ice_sched_add_nodes_to_layer(pi, tc_node, parent,\n+\t\t\t\t\t\t      layer, new_num_nodes,\n+\t\t\t\t\t\t      first_teid_ptr,\n+\t\t\t\t\t\t      &num_added);\n+\t\t*num_nodes_added += num_added;\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes,\n+\t\t\t\t     num_nodes_added, first_node_teid);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_get_qgrp_layer - get the current queue group layer number\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function returns the current queue group layer number\n+ */\n+static u8 ice_sched_get_qgrp_layer(struct ice_hw *hw)\n+{\n+\t/* It's always total layers - 1, the array is 0 relative so -2 */\n+\treturn hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET;\n+}\n+\n+/**\n+ * ice_sched_get_vsi_layer - get the current VSI layer number\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function returns the current VSI layer number\n+ */\n+static u8 ice_sched_get_vsi_layer(struct ice_hw *hw)\n+{\n+\t/* Num Layers       VSI layer\n+\t *     9               6\n+\t *     7               4\n+\t *     5 or less       sw_entry_point_layer\n+\t */\n+\t/* calculate the vsi layer based on number of layers. */\n+\tif (hw->num_tx_sched_layers > ICE_VSI_LAYER_OFFSET + 1) {\n+\t\tu8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET;\n+\n+\t\tif (layer > hw->sw_entry_point_layer)\n+\t\t\treturn layer;\n+\t}\n+\treturn hw->sw_entry_point_layer;\n+}\n+\n+/**\n+ * ice_sched_get_agg_layer - get the current aggregator layer number\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function returns the current aggregator layer number\n+ */\n+static u8 ice_sched_get_agg_layer(struct ice_hw *hw)\n+{\n+\t/* Num Layers       agg layer\n+\t *     9               4\n+\t *     7 or less       sw_entry_point_layer\n+\t */\n+\t/* calculate the agg layer based on number of layers. */\n+\tif (hw->num_tx_sched_layers > ICE_AGG_LAYER_OFFSET + 1) {\n+\t\tu8 layer = hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET;\n+\n+\t\tif (layer > hw->sw_entry_point_layer)\n+\t\t\treturn layer;\n+\t}\n+\treturn hw->sw_entry_point_layer;\n+}\n+\n+/**\n+ * ice_rm_dflt_leaf_node - remove the default leaf node in the tree\n+ * @pi: port information structure\n+ *\n+ * This function removes the leaf node that was created by the FW\n+ * during initialization\n+ */\n+static void ice_rm_dflt_leaf_node(struct ice_port_info *pi)\n+{\n+\tstruct ice_sched_node *node;\n+\n+\tnode = pi->root;\n+\twhile (node) {\n+\t\tif (!node->num_children)\n+\t\t\tbreak;\n+\t\tnode = node->children[0];\n+\t}\n+\tif (node && node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) {\n+\t\tu32 teid = LE32_TO_CPU(node->info.node_teid);\n+\t\tenum ice_status status;\n+\n+\t\t/* remove the default leaf node */\n+\t\tstatus = ice_sched_remove_elems(pi->hw, node->parent, 1, &teid);\n+\t\tif (!status)\n+\t\t\tice_free_sched_node(pi, node);\n+\t}\n+}\n+\n+/**\n+ * ice_sched_rm_dflt_nodes - free the default nodes in the tree\n+ * @pi: port information structure\n+ *\n+ * This function frees all the nodes except root and TC that were created by\n+ * the FW during initialization\n+ */\n+static void ice_sched_rm_dflt_nodes(struct ice_port_info *pi)\n+{\n+\tstruct ice_sched_node *node;\n+\n+\tice_rm_dflt_leaf_node(pi);\n+\n+\t/* remove the default nodes except TC and root nodes */\n+\tnode = pi->root;\n+\twhile (node) {\n+\t\tif (node->tx_sched_layer >= pi->hw->sw_entry_point_layer &&\n+\t\t    node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC &&\n+\t\t    node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT) {\n+\t\t\tice_free_sched_node(pi, node);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (!node->num_children)\n+\t\t\tbreak;\n+\t\tnode = node->children[0];\n+\t}\n+}\n+\n+/**\n+ * ice_sched_init_port - Initialize scheduler by querying information from FW\n+ * @pi: port info structure for the tree to cleanup\n+ *\n+ * This function is the initial call to find the total number of Tx scheduler\n+ * resources, default topology created by firmware and storing the information\n+ * in SW DB.\n+ */\n+enum ice_status ice_sched_init_port(struct ice_port_info *pi)\n+{\n+\tstruct ice_aqc_get_topo_elem *buf;\n+\tenum ice_status status;\n+\tstruct ice_hw *hw;\n+\tu8 num_branches;\n+\tu16 num_elems;\n+\tu8 i, j;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\thw = pi->hw;\n+\n+\t/* Query the Default Topology from FW */\n+\tbuf = (struct ice_aqc_get_topo_elem *)ice_malloc(hw,\n+\t\t\t\t\t\t\t ICE_AQ_MAX_BUF_LEN);\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\t/* Query default scheduling tree topology */\n+\tstatus = ice_aq_get_dflt_topo(hw, pi->lport, buf, ICE_AQ_MAX_BUF_LEN,\n+\t\t\t\t      &num_branches, NULL);\n+\tif (status)\n+\t\tgoto err_init_port;\n+\n+\t/* num_branches should be between 1-8 */\n+\tif (num_branches < 1 || num_branches > ICE_TXSCHED_MAX_BRANCHES) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"num_branches unexpected %d\\n\",\n+\t\t\t  num_branches);\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto err_init_port;\n+\t}\n+\n+\t/* get the number of elements on the default/first branch */\n+\tnum_elems = LE16_TO_CPU(buf[0].hdr.num_elems);\n+\n+\t/* num_elems should always be between 1-9 */\n+\tif (num_elems < 1 || num_elems > ICE_AQC_TOPO_MAX_LEVEL_NUM) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"num_elems unexpected %d\\n\",\n+\t\t\t  num_elems);\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto err_init_port;\n+\t}\n+\n+\t/* If the last node is a leaf node then the index of the Q group\n+\t * layer is two less than the number of elements.\n+\t */\n+\tif (num_elems > 2 && buf[0].generic[num_elems - 1].data.elem_type ==\n+\t    ICE_AQC_ELEM_TYPE_LEAF)\n+\t\tpi->last_node_teid =\n+\t\t\tLE32_TO_CPU(buf[0].generic[num_elems - 2].node_teid);\n+\telse\n+\t\tpi->last_node_teid =\n+\t\t\tLE32_TO_CPU(buf[0].generic[num_elems - 1].node_teid);\n+\n+\t/* Insert the Tx Sched root node */\n+\tstatus = ice_sched_add_root_node(pi, &buf[0].generic[0]);\n+\tif (status)\n+\t\tgoto err_init_port;\n+\n+\t/* Parse the default tree and cache the information */\n+\tfor (i = 0; i < num_branches; i++) {\n+\t\tnum_elems = LE16_TO_CPU(buf[i].hdr.num_elems);\n+\n+\t\t/* Skip root element as already inserted */\n+\t\tfor (j = 1; j < num_elems; j++) {\n+\t\t\t/* update the sw entry point */\n+\t\t\tif (buf[0].generic[j].data.elem_type ==\n+\t\t\t    ICE_AQC_ELEM_TYPE_ENTRY_POINT)\n+\t\t\t\thw->sw_entry_point_layer = j;\n+\n+\t\t\tstatus = ice_sched_add_node(pi, j, &buf[i].generic[j]);\n+\t\t\tif (status)\n+\t\t\t\tgoto err_init_port;\n+\t\t}\n+\t}\n+\n+\t/* Remove the default nodes. */\n+\tif (pi->root)\n+\t\tice_sched_rm_dflt_nodes(pi);\n+\n+\t/* initialize the port for handling the scheduler tree */\n+\tpi->port_state = ICE_SCHED_PORT_STATE_READY;\n+\tice_init_lock(&pi->sched_lock);\n+\tfor (i = 0; i < ICE_AQC_TOPO_MAX_LEVEL_NUM; i++)\n+\t\tINIT_LIST_HEAD(&pi->rl_prof_list[i]);\n+\n+err_init_port:\n+\tif (status && pi->root) {\n+\t\tice_free_sched_node(pi, pi->root);\n+\t\tpi->root = NULL;\n+\t}\n+\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_get_node - Get the struct ice_sched_node for given teid\n+ * @pi: port information structure\n+ * @teid: Scheduler node TEID\n+ *\n+ * This function retrieves the ice_sched_node struct for given teid from\n+ * the SW DB and returns it to the caller.\n+ */\n+struct ice_sched_node *ice_sched_get_node(struct ice_port_info *pi, u32 teid)\n+{\n+\tstruct ice_sched_node *node;\n+\n+\tif (!pi)\n+\t\treturn NULL;\n+\n+\t/* Find the node starting from root */\n+\tice_acquire_lock(&pi->sched_lock);\n+\tnode = ice_sched_find_node_by_teid(pi->root, teid);\n+\tice_release_lock(&pi->sched_lock);\n+\n+\tif (!node)\n+\t\tice_debug(pi->hw, ICE_DBG_SCHED,\n+\t\t\t  \"Node not found for teid=0x%x\\n\", teid);\n+\n+\treturn node;\n+}\n+\n+/**\n+ * ice_sched_query_res_alloc - query the FW for num of logical sched layers\n+ * @hw: pointer to the HW struct\n+ *\n+ * query FW for allocated scheduler resources and store in HW struct\n+ */\n+enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw)\n+{\n+\tstruct ice_aqc_query_txsched_res_resp *buf;\n+\tenum ice_status status = ICE_SUCCESS;\n+\t__le16 max_sibl;\n+\tu8 i;\n+\n+\tif (hw->layer_info)\n+\t\treturn status;\n+\n+\tbuf = (struct ice_aqc_query_txsched_res_resp *)\n+\t\tice_malloc(hw, sizeof(*buf));\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tstatus = ice_aq_query_sched_res(hw, sizeof(*buf), buf, NULL);\n+\tif (status)\n+\t\tgoto sched_query_out;\n+\n+\thw->num_tx_sched_layers = LE16_TO_CPU(buf->sched_props.logical_levels);\n+\thw->num_tx_sched_phys_layers =\n+\t\tLE16_TO_CPU(buf->sched_props.phys_levels);\n+\thw->flattened_layers = buf->sched_props.flattening_bitmap;\n+\thw->max_cgds = buf->sched_props.max_pf_cgds;\n+\n+\t/* max sibling group size of current layer refers to the max children\n+\t * of the below layer node.\n+\t * layer 1 node max children will be layer 2 max sibling group size\n+\t * layer 2 node max children will be layer 3 max sibling group size\n+\t * and so on. This array will be populated from root (index 0) to\n+\t * qgroup layer 7. Leaf node has no children.\n+\t */\n+\tfor (i = 0; i < hw->num_tx_sched_layers - 1; i++) {\n+\t\tmax_sibl = buf->layer_props[i + 1].max_sibl_grp_sz;\n+\t\thw->max_children[i] = LE16_TO_CPU(max_sibl);\n+\t}\n+\n+\thw->layer_info = (struct ice_aqc_layer_props *)\n+\t\t\t ice_memdup(hw, buf->layer_props,\n+\t\t\t\t    (hw->num_tx_sched_layers *\n+\t\t\t\t     sizeof(*hw->layer_info)),\n+\t\t\t\t    ICE_DMA_TO_DMA);\n+\tif (!hw->layer_info) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto sched_query_out;\n+\t}\n+\n+\n+sched_query_out:\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_find_node_in_subtree - Find node in part of base node subtree\n+ * @hw: pointer to the hw struct\n+ * @base: pointer to the base node\n+ * @node: pointer to the node to search\n+ *\n+ * This function checks whether a given node is part of the base node\n+ * subtree or not\n+ */\n+bool\n+ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base,\n+\t\t\t       struct ice_sched_node *node)\n+{\n+\tu8 i;\n+\n+\tfor (i = 0; i < base->num_children; i++) {\n+\t\tstruct ice_sched_node *child = base->children[i];\n+\n+\t\tif (node == child)\n+\t\t\treturn true;\n+\n+\t\tif (child->tx_sched_layer > node->tx_sched_layer)\n+\t\t\treturn false;\n+\n+\t\t/* this recursion is intentional, and wouldn't\n+\t\t * go more than 8 calls\n+\t\t */\n+\t\tif (ice_sched_find_node_in_subtree(hw, child, node))\n+\t\t\treturn true;\n+\t}\n+\treturn false;\n+}\n+\n+/**\n+ * ice_sched_get_free_qparent - Get a free lan or rdma q group node\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: branch number\n+ * @owner: lan or rdma\n+ *\n+ * This function retrieves a free lan or rdma q group node\n+ */\n+struct ice_sched_node *\n+ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t\t   u8 owner)\n+{\n+\tstruct ice_sched_node *vsi_node, *qgrp_node = NULL;\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\tu16 max_children;\n+\tu8 qgrp_layer;\n+\n+\tqgrp_layer = ice_sched_get_qgrp_layer(pi->hw);\n+\tmax_children = pi->hw->max_children[qgrp_layer];\n+\n+\tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn NULL;\n+\tvsi_node = vsi_ctx->sched.vsi_node[tc];\n+\t/* validate invalid VSI id */\n+\tif (!vsi_node)\n+\t\tgoto lan_q_exit;\n+\n+\t/* get the first q group node from VSI sub-tree */\n+\tqgrp_node = ice_sched_get_first_node(pi->hw, vsi_node, qgrp_layer);\n+\twhile (qgrp_node) {\n+\t\t/* make sure the qgroup node is part of the VSI subtree */\n+\t\tif (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node))\n+\t\t\tif (qgrp_node->num_children < max_children &&\n+\t\t\t    qgrp_node->owner == owner)\n+\t\t\t\tbreak;\n+\t\tqgrp_node = qgrp_node->sibling;\n+\t}\n+\n+lan_q_exit:\n+\treturn qgrp_node;\n+}\n+\n+/**\n+ * ice_sched_get_vsi_node - Get a VSI node based on VSI id\n+ * @hw: pointer to the hw struct\n+ * @tc_node: pointer to the TC node\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function retrieves a VSI node for a given VSI id from a given\n+ * TC branch\n+ */\n+struct ice_sched_node *\n+ice_sched_get_vsi_node(struct ice_hw *hw, struct ice_sched_node *tc_node,\n+\t\t       u16 vsi_handle)\n+{\n+\tstruct ice_sched_node *node;\n+\tu8 vsi_layer;\n+\n+\tvsi_layer = ice_sched_get_vsi_layer(hw);\n+\tnode = ice_sched_get_first_node(hw, tc_node, vsi_layer);\n+\n+\t/* Check whether it already exists */\n+\twhile (node) {\n+\t\tif (node->vsi_handle == vsi_handle)\n+\t\t\treturn node;\n+\t\tnode = node->sibling;\n+\t}\n+\n+\treturn node;\n+}\n+\n+/**\n+ * ice_sched_get_agg_node - Get an aggregator node based on agg id\n+ * @hw: pointer to the hw struct\n+ * @tc_node: pointer to the TC node\n+ * @agg_id: aggregator id\n+ *\n+ * This function retrieves an aggregator node for a given agg id from a given\n+ * TC branch\n+ */\n+struct ice_sched_node *\n+ice_sched_get_agg_node(struct ice_hw *hw, struct ice_sched_node *tc_node,\n+\t\t       u32 agg_id)\n+{\n+\tstruct ice_sched_node *node;\n+\tu8 agg_layer;\n+\n+\tagg_layer = ice_sched_get_agg_layer(hw);\n+\tnode = ice_sched_get_first_node(hw, tc_node, agg_layer);\n+\n+\t/* Check whether it already exists */\n+\twhile (node) {\n+\t\tif (node->agg_id == agg_id)\n+\t\t\treturn node;\n+\t\tnode = node->sibling;\n+\t}\n+\n+\treturn node;\n+}\n+\n+/**\n+ * ice_sched_check_node - Compare node parameters between SW DB and HW DB\n+ * @hw: pointer to the hw struct\n+ * @node: pointer to the ice_sched_node struct\n+ *\n+ * This function queries and compares the HW element with SW DB node parameters\n+ */\n+static bool ice_sched_check_node(struct ice_hw *hw, struct ice_sched_node *node)\n+{\n+\tstruct ice_aqc_get_elem buf;\n+\tenum ice_status status;\n+\tu32 node_teid;\n+\n+\tnode_teid = LE32_TO_CPU(node->info.node_teid);\n+\tstatus = ice_sched_query_elem(hw, node_teid, &buf);\n+\tif (status != ICE_SUCCESS)\n+\t\treturn false;\n+\n+\tif (memcmp(buf.generic, &node->info, sizeof(*buf.generic))) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"Node mismatch for teid=0x%x\\n\",\n+\t\t\t  node_teid);\n+\t\treturn false;\n+\t}\n+\n+\treturn true;\n+}\n+\n+/**\n+ * ice_sched_calc_vsi_child_nodes - calculate number of VSI child nodes\n+ * @hw: pointer to the hw struct\n+ * @num_qs: number of queues\n+ * @num_nodes: num nodes array\n+ *\n+ * This function calculates the number of VSI child nodes based on the\n+ * number of queues.\n+ */\n+static void\n+ice_sched_calc_vsi_child_nodes(struct ice_hw *hw, u16 num_qs, u16 *num_nodes)\n+{\n+\tu16 num = num_qs;\n+\tu8 i, qgl, vsil;\n+\n+\tqgl = ice_sched_get_qgrp_layer(hw);\n+\tvsil = ice_sched_get_vsi_layer(hw);\n+\n+\t/* calculate num nodes from q group to VSI layer */\n+\tfor (i = qgl; i > vsil; i--) {\n+\t\t/* round to the next integer if there is a remainder */\n+\t\tnum = DIVIDE_AND_ROUND_UP(num, hw->max_children[i]);\n+\n+\t\t/* need at least one node */\n+\t\tnum_nodes[i] = num ? num : 1;\n+\t}\n+}\n+\n+/**\n+ * ice_sched_add_vsi_child_nodes - add VSI child nodes to tree\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc_node: pointer to the TC node\n+ * @num_nodes: pointer to the num nodes that needs to be added per layer\n+ * @owner: node owner (lan or rdma)\n+ *\n+ * This function adds the VSI child nodes to tree. It gets called for\n+ * lan and rdma separately.\n+ */\n+static enum ice_status\n+ice_sched_add_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle,\n+\t\t\t      struct ice_sched_node *tc_node, u16 *num_nodes,\n+\t\t\t      u8 owner)\n+{\n+\tstruct ice_sched_node *parent, *node;\n+\tstruct ice_hw *hw = pi->hw;\n+\tenum ice_status status;\n+\tu32 first_node_teid;\n+\tu16 num_added = 0;\n+\tu8 i, qgl, vsil;\n+\n+\tqgl = ice_sched_get_qgrp_layer(hw);\n+\tvsil = ice_sched_get_vsi_layer(hw);\n+\tparent = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);\n+\tfor (i = vsil + 1; i <= qgl; i++) {\n+\t\tif (!parent)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\tstatus = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i,\n+\t\t\t\t\t\t      num_nodes[i],\n+\t\t\t\t\t\t      &first_node_teid,\n+\t\t\t\t\t\t      &num_added);\n+\t\tif (status != ICE_SUCCESS || num_nodes[i] != num_added)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\t/* The newly added node can be a new parent for the next\n+\t\t * layer nodes\n+\t\t */\n+\t\tif (num_added) {\n+\t\t\tparent = ice_sched_find_node_by_teid(tc_node,\n+\t\t\t\t\t\t\t     first_node_teid);\n+\t\t\tnode = parent;\n+\t\t\twhile (node) {\n+\t\t\t\tnode->owner = owner;\n+\t\t\t\tnode = node->sibling;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tparent = parent->children[0];\n+\t\t}\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_calc_vsi_support_nodes - calculate number of VSI support nodes\n+ * @hw: pointer to the hw struct\n+ * @tc_node: pointer to TC node\n+ * @num_nodes: pointer to num nodes array\n+ *\n+ * This function calculates the number of supported nodes needed to add this\n+ * VSI into Tx tree including the VSI, parent and intermediate nodes in below\n+ * layers\n+ */\n+static void\n+ice_sched_calc_vsi_support_nodes(struct ice_hw *hw,\n+\t\t\t\t struct ice_sched_node *tc_node, u16 *num_nodes)\n+{\n+\tstruct ice_sched_node *node;\n+\tu8 vsil;\n+\tint i;\n+\n+\tvsil = ice_sched_get_vsi_layer(hw);\n+\tfor (i = vsil; i >= hw->sw_entry_point_layer; i--)\n+\t\t/* Add intermediate nodes if TC has no children and\n+\t\t * need at least one node for VSI\n+\t\t */\n+\t\tif (!tc_node->num_children || i == vsil) {\n+\t\t\tnum_nodes[i]++;\n+\t\t} else {\n+\t\t\t/* If intermediate nodes are reached max children\n+\t\t\t * then add a new one.\n+\t\t\t */\n+\t\t\tnode = ice_sched_get_first_node(hw, tc_node, (u8)i);\n+\t\t\t/* scan all the siblings */\n+\t\t\twhile (node) {\n+\t\t\t\tif (node->num_children < hw->max_children[i])\n+\t\t\t\t\tbreak;\n+\t\t\t\tnode = node->sibling;\n+\t\t\t}\n+\n+\t\t\t/* tree has one intermediate node to add this new VSI.\n+\t\t\t * So no need to calculate supported nodes for below\n+\t\t\t * layers.\n+\t\t\t */\n+\t\t\tif (node)\n+\t\t\t\tbreak;\n+\t\t\t/* all the nodes are full, allocate a new one */\n+\t\t\tnum_nodes[i]++;\n+\t\t}\n+}\n+\n+/**\n+ * ice_sched_add_vsi_support_nodes - add VSI supported nodes into Tx tree\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc_node: pointer to TC node\n+ * @num_nodes: pointer to num nodes array\n+ *\n+ * This function adds the VSI supported nodes into Tx tree including the\n+ * VSI, its parent and intermediate nodes in below layers\n+ */\n+static enum ice_status\n+ice_sched_add_vsi_support_nodes(struct ice_port_info *pi, u16 vsi_handle,\n+\t\t\t\tstruct ice_sched_node *tc_node, u16 *num_nodes)\n+{\n+\tstruct ice_sched_node *parent = tc_node;\n+\tenum ice_status status;\n+\tu32 first_node_teid;\n+\tu16 num_added = 0;\n+\tu8 i, vsil;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tvsil = ice_sched_get_vsi_layer(pi->hw);\n+\tfor (i = pi->hw->sw_entry_point_layer; i <= vsil; i++) {\n+\t\tstatus = ice_sched_add_nodes_to_layer(pi, tc_node, parent,\n+\t\t\t\t\t\t      i, num_nodes[i],\n+\t\t\t\t\t\t      &first_node_teid,\n+\t\t\t\t\t\t      &num_added);\n+\t\tif (status != ICE_SUCCESS || num_nodes[i] != num_added)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\t/* The newly added node can be a new parent for the next\n+\t\t * layer nodes\n+\t\t */\n+\t\tif (num_added)\n+\t\t\tparent = ice_sched_find_node_by_teid(tc_node,\n+\t\t\t\t\t\t\t     first_node_teid);\n+\t\telse\n+\t\t\tparent = parent->children[0];\n+\n+\t\tif (!parent)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\tif (i == vsil)\n+\t\t\tparent->vsi_handle = vsi_handle;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_add_vsi_to_topo - add a new VSI into tree\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: TC number\n+ *\n+ * This function adds a new VSI into scheduler tree\n+ */\n+static enum ice_status\n+ice_sched_add_vsi_to_topo(struct ice_port_info *pi, u16 vsi_handle, u8 tc)\n+{\n+\tu16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };\n+\tstruct ice_sched_node *tc_node;\n+\tstruct ice_hw *hw = pi->hw;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* calculate number of supported nodes needed for this VSI */\n+\tice_sched_calc_vsi_support_nodes(hw, tc_node, num_nodes);\n+\n+\t/* add vsi supported nodes to tc subtree */\n+\treturn ice_sched_add_vsi_support_nodes(pi, vsi_handle, tc_node,\n+\t\t\t\t\t       num_nodes);\n+}\n+\n+/**\n+ * ice_sched_update_vsi_child_nodes - update VSI child nodes\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: TC number\n+ * @new_numqs: new number of max queues\n+ * @owner: owner of this subtree\n+ *\n+ * This function updates the VSI child nodes based on the number of queues\n+ */\n+static enum ice_status\n+ice_sched_update_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle,\n+\t\t\t\t u8 tc, u16 new_numqs, u8 owner)\n+{\n+\tu16 new_num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };\n+\tstruct ice_sched_node *vsi_node;\n+\tstruct ice_sched_node *tc_node;\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu16 prev_numqs;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tvsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);\n+\tif (!vsi_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tvsi_ctx = ice_get_vsi_ctx(hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (owner == ICE_SCHED_NODE_OWNER_LAN)\n+\t\tprev_numqs = vsi_ctx->sched.max_lanq[tc];\n+\telse\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* num queues are not changed or less than the previous number */\n+\tif (new_numqs <= prev_numqs)\n+\t\treturn status;\n+\tif (new_numqs)\n+\t\tice_sched_calc_vsi_child_nodes(hw, new_numqs, new_num_nodes);\n+\t/* Keep the max number of queue configuration all the time. Update the\n+\t * tree only if number of queues > previous number of queues. This may\n+\t * leave some extra nodes in the tree if number of queues < previous\n+\t * number but that wouldn't harm anything. Removing those extra nodes\n+\t * may complicate the code if those nodes are part of SRL or\n+\t * individually rate limited.\n+\t */\n+\tstatus = ice_sched_add_vsi_child_nodes(pi, vsi_handle, tc_node,\n+\t\t\t\t\t       new_num_nodes, owner);\n+\tif (status)\n+\t\treturn status;\n+\tvsi_ctx->sched.max_lanq[tc] = new_numqs;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_cfg_vsi - configure the new/existing VSI\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: TC number\n+ * @maxqs: max number of queues\n+ * @owner: lan or rdma\n+ * @enable: TC enabled or disabled\n+ *\n+ * This function adds/updates VSI nodes based on the number of queues. If TC is\n+ * enabled and VSI is in suspended state then resume the VSI back. If TC is\n+ * disabled then suspend the VSI if it is not already.\n+ */\n+enum ice_status\n+ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,\n+\t\t  u8 owner, bool enable)\n+{\n+\tstruct ice_sched_node *vsi_node, *tc_node;\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\n+\tice_debug(pi->hw, ICE_DBG_SCHED, \"add/config VSI %d\\n\", vsi_handle);\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_PARAM;\n+\tvsi_ctx = ice_get_vsi_ctx(hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn ICE_ERR_PARAM;\n+\tvsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);\n+\n+\t/* suspend the VSI if tc is not enabled */\n+\tif (!enable) {\n+\t\tif (vsi_node && vsi_node->in_use) {\n+\t\t\tu32 teid = LE32_TO_CPU(vsi_node->info.node_teid);\n+\n+\t\t\tstatus = ice_sched_suspend_resume_elems(hw, 1, &teid,\n+\t\t\t\t\t\t\t\ttrue);\n+\t\t\tif (!status)\n+\t\t\t\tvsi_node->in_use = false;\n+\t\t}\n+\t\treturn status;\n+\t}\n+\n+\t/* TC is enabled, if it is a new VSI then add it to the tree */\n+\tif (!vsi_node) {\n+\t\tstatus = ice_sched_add_vsi_to_topo(pi, vsi_handle, tc);\n+\t\tif (status)\n+\t\t\treturn status;\n+\n+\t\tvsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);\n+\t\tif (!vsi_node)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\tvsi_ctx->sched.vsi_node[tc] = vsi_node;\n+\t\tvsi_node->in_use = true;\n+\t\t/* invalidate the max queues whenever VSI gets added first time\n+\t\t * into the scheduler tree (boot or after reset). We need to\n+\t\t * recreate the child nodes all the time in these cases.\n+\t\t */\n+\t\tvsi_ctx->sched.max_lanq[tc] = 0;\n+\t}\n+\n+\t/* update the VSI child nodes */\n+\tstatus = ice_sched_update_vsi_child_nodes(pi, vsi_handle, tc, maxqs,\n+\t\t\t\t\t\t  owner);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* TC is enabled, resume the VSI if it is in the suspend state */\n+\tif (!vsi_node->in_use) {\n+\t\tu32 teid = LE32_TO_CPU(vsi_node->info.node_teid);\n+\n+\t\tstatus = ice_sched_suspend_resume_elems(hw, 1, &teid, false);\n+\t\tif (!status)\n+\t\t\tvsi_node->in_use = true;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_rm_agg_vsi_entry - remove agg related vsi info entry\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function removes single aggregator vsi info entry from\n+ * aggregator list.\n+ */\n+static void\n+ice_sched_rm_agg_vsi_info(struct ice_port_info *pi, u16 vsi_handle)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\tstruct ice_sched_agg_info *atmp;\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &pi->hw->agg_list,\n+\t\t\t\t ice_sched_agg_info,\n+\t\t\t\t list_entry) {\n+\t\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\t\tstruct ice_sched_agg_vsi_info *vtmp;\n+\n+\t\tLIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, vtmp,\n+\t\t\t\t\t &agg_info->agg_vsi_list,\n+\t\t\t\t\t ice_sched_agg_vsi_info, list_entry)\n+\t\t\tif (agg_vsi_info->vsi_handle == vsi_handle) {\n+\t\t\t\tLIST_DEL(&agg_vsi_info->list_entry);\n+\t\t\t\tice_free(pi->hw, agg_vsi_info);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t}\n+}\n+\n+/**\n+ * ice_sched_is_leaf_node_present - check for a leaf node in the sub-tree\n+ * @node: pointer to the sub-tree node\n+ *\n+ * This function checks for a leaf node presence in a given sub-tree node.\n+ */\n+static bool ice_sched_is_leaf_node_present(struct ice_sched_node *node)\n+{\n+\tu8 i;\n+\n+\tfor (i = 0; i < node->num_children; i++)\n+\t\tif (ice_sched_is_leaf_node_present(node->children[i]))\n+\t\t\treturn true;\n+\t/* check for a leaf node */\n+\treturn (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF);\n+}\n+\n+/**\n+ * ice_sched_rm_vsi_cfg - remove the VSI and its children nodes\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @owner: lan or rdma\n+ *\n+ * This function removes the VSI and its lan or rdma children nodes from the\n+ * scheduler tree.\n+ */\n+static enum ice_status\n+ice_sched_rm_vsi_cfg(struct ice_port_info *pi, u16 vsi_handle, u8 owner)\n+{\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\tu8 i;\n+\n+\tice_debug(pi->hw, ICE_DBG_SCHED, \"removing VSI %d\\n\", vsi_handle);\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn status;\n+\tice_acquire_lock(&pi->sched_lock);\n+\tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\tgoto exit_sched_rm_vsi_cfg;\n+\n+\tfor (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) {\n+\t\tstruct ice_sched_node *vsi_node, *tc_node;\n+\t\tu8 j = 0;\n+\n+\t\ttc_node = ice_sched_get_tc_node(pi, i);\n+\t\tif (!tc_node)\n+\t\t\tcontinue;\n+\n+\t\tvsi_node = ice_sched_get_vsi_node(pi->hw, tc_node, vsi_handle);\n+\t\tif (!vsi_node)\n+\t\t\tcontinue;\n+\n+\t\tif (ice_sched_is_leaf_node_present(vsi_node)) {\n+\t\t\tice_debug(pi->hw, ICE_DBG_SCHED,\n+\t\t\t\t  \"VSI has leaf nodes in TC %d\\n\", i);\n+\t\t\tstatus = ICE_ERR_IN_USE;\n+\t\t\tgoto exit_sched_rm_vsi_cfg;\n+\t\t}\n+\t\twhile (j < vsi_node->num_children) {\n+\t\t\tif (vsi_node->children[j]->owner == owner) {\n+\t\t\t\tice_free_sched_node(pi, vsi_node->children[j]);\n+\n+\t\t\t\t/* reset the counter again since the num\n+\t\t\t\t * children will be updated after node removal\n+\t\t\t\t */\n+\t\t\t\tj = 0;\n+\t\t\t} else {\n+\t\t\t\tj++;\n+\t\t\t}\n+\t\t}\n+\t\t/* remove the VSI if it has no children */\n+\t\tif (!vsi_node->num_children) {\n+\t\t\tice_free_sched_node(pi, vsi_node);\n+\t\t\tvsi_ctx->sched.vsi_node[i] = NULL;\n+\n+\t\t\t/* clean up agg related vsi info if any */\n+\t\t\tice_sched_rm_agg_vsi_info(pi, vsi_handle);\n+\t\t}\n+\t\tif (owner == ICE_SCHED_NODE_OWNER_LAN)\n+\t\t\tvsi_ctx->sched.max_lanq[i] = 0;\n+\t}\n+\tstatus = ICE_SUCCESS;\n+\n+exit_sched_rm_vsi_cfg:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_rm_vsi_lan_cfg - remove VSI and its lan children nodes\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function clears the VSI and its lan children nodes from scheduler tree\n+ * for all TCs.\n+ */\n+enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle)\n+{\n+\treturn ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_LAN);\n+}\n+\n+\n+/**\n+ * ice_sched_is_tree_balanced - Check tree nodes are identical or not\n+ * @hw: pointer to the hw struct\n+ * @node: pointer to the ice_sched_node struct\n+ *\n+ * This function compares all the nodes for a given tree against HW DB nodes\n+ * This function needs to be called with the port_info->sched_lock held\n+ */\n+bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node)\n+{\n+\tu8 i;\n+\n+\t/* start from the leaf node */\n+\tfor (i = 0; i < node->num_children; i++)\n+\t\t/* Fail if node doesn't match with the SW DB\n+\t\t * this recursion is intentional, and wouldn't\n+\t\t * go more than 9 calls\n+\t\t */\n+\t\tif (!ice_sched_is_tree_balanced(hw, node->children[i]))\n+\t\t\treturn false;\n+\n+\treturn ice_sched_check_node(hw, node);\n+}\n+\n+/**\n+ * ice_aq_query_node_to_root - retrieve the tree topology for a given node teid\n+ * @hw: pointer to the hw struct\n+ * @node_teid: node teid\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function retrieves the tree topology from the firmware for a given\n+ * node teid to the root node.\n+ */\n+enum ice_status\n+ice_aq_query_node_to_root(struct ice_hw *hw, u32 node_teid,\n+\t\t\t  struct ice_aqc_get_elem *buf, u16 buf_size,\n+\t\t\t  struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_query_node_to_root *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.query_node_to_root;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_node_to_root);\n+\tcmd->teid = CPU_TO_LE32(node_teid);\n+\treturn ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+}\n+\n+/**\n+ * ice_get_agg_info - get the agg id\n+ * @hw: pointer to the hardware structure\n+ * @agg_id: aggregator id\n+ *\n+ * This function validates agg id. The function returns info if agg id is\n+ * prsent in list otherwise it returns null.\n+ */\n+static struct ice_sched_agg_info*\n+ice_get_agg_info(struct ice_hw *hw, u32 agg_id)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\n+\tLIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,\n+\t\t\t    list_entry)\n+\t\tif (agg_info->agg_id == agg_id)\n+\t\t\treturn agg_info;\n+\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_move_all_vsi_to_dflt_agg - move all VSI(s) to default agg\n+ * @pi: port information structure\n+ * @agg_info: aggregator info\n+ * @tc: traffic class number\n+ * @rm_vsi_info: true or false\n+ *\n+ * This function move all the VSI(s) to the default aggregator and delete\n+ * agg vsi info based on passed in boolean parameter rm_vsi_info. The\n+ * caller holds the scheduler lock.\n+ */\n+static enum ice_status\n+ice_move_all_vsi_to_dflt_agg(struct ice_port_info *pi,\n+\t\t\t     struct ice_sched_agg_info *agg_info, u8 tc,\n+\t\t\t     bool rm_vsi_info)\n+{\n+\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\tstruct ice_sched_agg_vsi_info *tmp;\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, tmp, &agg_info->agg_vsi_list,\n+\t\t\t\t ice_sched_agg_vsi_info, list_entry) {\n+\t\tu16 vsi_handle = agg_vsi_info->vsi_handle;\n+\n+\t\t/* Move VSI to default agg */\n+\t\tif (!ice_is_tc_ena(agg_vsi_info->tc_bitmap[0], tc))\n+\t\t\tcontinue;\n+\n+\t\tstatus = ice_sched_move_vsi_to_agg(pi, vsi_handle,\n+\t\t\t\t\t\t   ICE_DFLT_AGG_ID, tc);\n+\t\tif (status)\n+\t\t\tbreak;\n+\n+\t\tice_clear_bit(tc, agg_vsi_info->tc_bitmap);\n+\t\tif (rm_vsi_info && !agg_vsi_info->tc_bitmap[0]) {\n+\t\t\tLIST_DEL(&agg_vsi_info->list_entry);\n+\t\t\tice_free(pi->hw, agg_vsi_info);\n+\t\t}\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_rm_agg_cfg_tc - remove agg configuration for tc\n+ * @pi: port information structure\n+ * @agg_info: aggregator id\n+ * @tc: tc number\n+ * @rm_vsi_info: bool value true or false\n+ *\n+ * This function removes agg reference to vsi of given tc. It removes the agg\n+ * configuration completely for requested tc. The caller needs to hold the\n+ * scheduler lock.\n+ */\n+static enum ice_status\n+ice_rm_agg_cfg_tc(struct ice_port_info *pi, struct ice_sched_agg_info *agg_info,\n+\t\t  u8 tc, bool rm_vsi_info)\n+{\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\t/* If nothing to remove - return success */\n+\tif (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc))\n+\t\tgoto exit_rm_agg_cfg_tc;\n+\n+\tstatus = ice_move_all_vsi_to_dflt_agg(pi, agg_info, tc, rm_vsi_info);\n+\tif (status)\n+\t\tgoto exit_rm_agg_cfg_tc;\n+\n+\t/* Delete aggregator node(s) */\n+\tstatus = ice_sched_rm_agg_cfg(pi, agg_info->agg_id, tc);\n+\tif (status)\n+\t\tgoto exit_rm_agg_cfg_tc;\n+\n+\tice_clear_bit(tc, agg_info->tc_bitmap);\n+exit_rm_agg_cfg_tc:\n+\treturn status;\n+}\n+\n+/**\n+ * ice_save_agg_tc_bitmap - save agg TC bitmap\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @tc_bitmap: 8 bits TC bitmap\n+ *\n+ * Save agg TC bitmap. This function needs to be called with scheduler\n+ * lock held.\n+ */\n+static enum ice_status\n+ice_save_agg_tc_bitmap(struct ice_port_info *pi, u32 agg_id,\n+\t\t       ice_bitmap_t *tc_bitmap)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\n+\tagg_info = ice_get_agg_info(pi->hw, agg_id);\n+\tif (!agg_info)\n+\t\treturn ICE_ERR_PARAM;\n+\tice_cp_bitmap(agg_info->replay_tc_bitmap, tc_bitmap,\n+\t\t      ICE_MAX_TRAFFIC_CLASS);\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_cfg_agg - configure agg node\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @agg_type: aggregator type queue, VSI, or agg group\n+ * @tc_bitmap: bits TC bitmap\n+ *\n+ * It registers a unique aggregator node into scheduler services. It\n+ * allows a user to register with a unique ID to track it's resources.\n+ * The aggregator type determines if this is a queue group, VSI group\n+ * or aggregator group. It then creates the agg node(s) for requested\n+ * tc(s) or removes an existing agg node including its configuration\n+ * if indicated via tc_bitmap. Call ice_rm_agg_cfg to release agg\n+ * resources and remove agg id.\n+ * This function needs to be called with scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_cfg_agg(struct ice_port_info *pi, u32 agg_id,\n+\t\t  enum ice_agg_type agg_type, ice_bitmap_t *tc_bitmap)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu8 tc;\n+\n+\tagg_info = ice_get_agg_info(hw, agg_id);\n+\tif (!agg_info) {\n+\t\t/* Creat new entry for new agg id */\n+\t\tagg_info = (struct ice_sched_agg_info *)\n+\t\t\tice_malloc(hw, sizeof(*agg_info));\n+\t\tif (!agg_info) {\n+\t\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\t\tgoto exit_reg_agg;\n+\t\t}\n+\t\tagg_info->agg_id = agg_id;\n+\t\tagg_info->agg_type = agg_type;\n+\t\tagg_info->tc_bitmap[0] = 0;\n+\n+\t\t/* Initialize the aggregator vsi list head */\n+\t\tINIT_LIST_HEAD(&agg_info->agg_vsi_list);\n+\n+\t\t/* Add new entry in agg list */\n+\t\tLIST_ADD(&agg_info->list_entry, &hw->agg_list);\n+\t}\n+\t/* Create agg node(s) for requested tc(s) */\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tif (!ice_is_tc_ena(*tc_bitmap, tc)) {\n+\t\t\t/* Delete agg cfg tc if it exists previously */\n+\t\t\tstatus = ice_rm_agg_cfg_tc(pi, agg_info, tc, false);\n+\t\t\tif (status)\n+\t\t\t\tbreak;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* Check if agg node for tc already exists */\n+\t\tif (ice_is_tc_ena(agg_info->tc_bitmap[0], tc))\n+\t\t\tcontinue;\n+\n+\t\t/* Create new agg node for tc */\n+\t\tstatus = ice_sched_add_agg_cfg(pi, agg_id, tc);\n+\t\tif (status)\n+\t\t\tbreak;\n+\n+\t\t/* Save agg node's tc information */\n+\t\tice_set_bit(tc, agg_info->tc_bitmap);\n+\t}\n+exit_reg_agg:\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_agg - config agg node\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @agg_type: aggregator type queue, VSI, or agg group\n+ * @tc_bitmap: bits TC bitmap\n+ *\n+ * This function configures aggregator node(s).\n+ */\n+enum ice_status\n+ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, enum ice_agg_type agg_type,\n+\t    u8 tc_bitmap)\n+{\n+\tice_bitmap_t bitmap = tc_bitmap;\n+\tenum ice_status status;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tstatus = ice_sched_cfg_agg(pi, agg_id, agg_type,\n+\t\t\t\t   (ice_bitmap_t *)&bitmap);\n+\tif (!status)\n+\t\tstatus = ice_save_agg_tc_bitmap(pi, agg_id,\n+\t\t\t\t\t\t(ice_bitmap_t *)&bitmap);\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_get_agg_vsi_info - get the agg id\n+ * @agg_info: aggregator info\n+ * @vsi_handle: software VSI handle\n+ *\n+ * The function returns agg VSI info based on VSI handle. This function needs\n+ * to be called with scheduler lock held.\n+ */\n+static struct ice_sched_agg_vsi_info*\n+ice_get_agg_vsi_info(struct ice_sched_agg_info *agg_info, u16 vsi_handle)\n+{\n+\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\n+\tLIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list,\n+\t\t\t    ice_sched_agg_vsi_info, list_entry)\n+\t\tif (agg_vsi_info->vsi_handle == vsi_handle)\n+\t\t\treturn agg_vsi_info;\n+\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_get_vsi_agg_info - get the agg info of VSI\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: Sw VSI handle\n+ *\n+ * The function returns agg info of VSI represented via vsi_handle. The VSI has\n+ * in this case a different aggregator than the default one. This function\n+ * needs to be called with scheduler lock held.\n+ */\n+static struct ice_sched_agg_info*\n+ice_get_vsi_agg_info(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\n+\tLIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,\n+\t\t\t    list_entry) {\n+\t\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\n+\t\tagg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle);\n+\t\tif (agg_vsi_info)\n+\t\t\treturn agg_info;\n+\t}\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_save_agg_vsi_tc_bitmap - save aggregator VSI TC bitmap\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @vsi_handle: software VSI handle\n+ * @tc_bitmap: TC bitmap of enabled tc(s)\n+ *\n+ * Save VSI to aggregator TC bitmap. This function needs to call with scheduler\n+ * lock held.\n+ */\n+static enum ice_status\n+ice_save_agg_vsi_tc_bitmap(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle,\n+\t\t\t   ice_bitmap_t *tc_bitmap)\n+{\n+\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\tstruct ice_sched_agg_info *agg_info;\n+\n+\tagg_info = ice_get_agg_info(pi->hw, agg_id);\n+\tif (!agg_info)\n+\t\treturn ICE_ERR_PARAM;\n+\t/* check if entry already exist */\n+\tagg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle);\n+\tif (!agg_vsi_info)\n+\t\treturn ICE_ERR_PARAM;\n+\tice_cp_bitmap(agg_vsi_info->replay_tc_bitmap, tc_bitmap,\n+\t\t      ICE_MAX_TRAFFIC_CLASS);\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_assoc_vsi_to_agg - associate or move VSI to new or default agg\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @vsi_handle: software VSI handle\n+ * @tc_bitmap: TC bitmap of enabled tc(s)\n+ *\n+ * This function moves VSI to a new or default aggregator node. If VSI is\n+ * already associated to the agg node then no operation is performed on the\n+ * tree. This function needs to be called with scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32 agg_id,\n+\t\t\t   u16 vsi_handle, ice_bitmap_t *tc_bitmap)\n+{\n+\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\tstruct ice_sched_agg_info *agg_info;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu8 tc;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\tagg_info = ice_get_agg_info(hw, agg_id);\n+\tif (!agg_info)\n+\t\treturn ICE_ERR_PARAM;\n+\t/* check if entry already exist */\n+\tagg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle);\n+\tif (!agg_vsi_info) {\n+\t\t/* Create new entry for vsi under agg list */\n+\t\tagg_vsi_info = (struct ice_sched_agg_vsi_info *)\n+\t\t\tice_malloc(hw, sizeof(*agg_vsi_info));\n+\t\tif (!agg_vsi_info)\n+\t\t\treturn ICE_ERR_PARAM;\n+\n+\t\t/* add vsi id into the agg list */\n+\t\tagg_vsi_info->vsi_handle = vsi_handle;\n+\t\tLIST_ADD(&agg_vsi_info->list_entry, &agg_info->agg_vsi_list);\n+\t}\n+\t/* Move vsi node to new agg node for requested tc(s) */\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tif (!ice_is_tc_ena(*tc_bitmap, tc))\n+\t\t\tcontinue;\n+\n+\t\t/* Move VSI to new agg */\n+\t\tstatus = ice_sched_move_vsi_to_agg(pi, vsi_handle, agg_id, tc);\n+\t\tif (status)\n+\t\t\tbreak;\n+\n+\t\tif (agg_id != ICE_DFLT_AGG_ID)\n+\t\t\tice_set_bit(tc, agg_vsi_info->tc_bitmap);\n+\t\telse\n+\t\t\tice_clear_bit(tc, agg_vsi_info->tc_bitmap);\n+\t}\n+\t/* If vsi moved back to default agg then delete entry agg_vsi_info. */\n+\tif (!ice_is_any_bit_set(agg_vsi_info->tc_bitmap,\n+\t\t\t\tICE_MAX_TRAFFIC_CLASS)) {\n+\t\tLIST_DEL(&agg_vsi_info->list_entry);\n+\t\tice_free(hw, agg_vsi_info);\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_move_vsi_to_agg - moves VSI to new or default agg\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @vsi_handle: software VSI handle\n+ * @tc_bitmap: tc bitmap of enabled tc(s)\n+ *\n+ * Move or associate VSI to a new or default aggregator node.\n+ */\n+enum ice_status\n+ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle,\n+\t\t    u8 tc_bitmap)\n+{\n+\tice_bitmap_t bitmap = tc_bitmap;\n+\tenum ice_status status;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tstatus = ice_sched_assoc_vsi_to_agg(pi, agg_id, vsi_handle,\n+\t\t\t\t\t    (ice_bitmap_t *)&bitmap);\n+\tif (!status)\n+\t\tstatus = ice_save_agg_vsi_tc_bitmap(pi, agg_id, vsi_handle,\n+\t\t\t\t\t\t    (ice_bitmap_t *)&bitmap);\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_rm_agg_cfg - remove agg configuration\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ *\n+ * This function removes agg reference to vsi and delete agg id info.\n+ * It removes the agg configuration completely.\n+ */\n+enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 tc;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tagg_info = ice_get_agg_info(pi->hw, agg_id);\n+\tif (!agg_info) {\n+\t\tstatus = ICE_ERR_DOES_NOT_EXIST;\n+\t\tgoto exit_ice_rm_agg_cfg;\n+\t}\n+\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tstatus = ice_rm_agg_cfg_tc(pi, agg_info, tc, true);\n+\t\tif (status)\n+\t\t\tgoto exit_ice_rm_agg_cfg;\n+\t}\n+\n+\tif (ice_is_any_bit_set(agg_info->tc_bitmap, ICE_MAX_TRAFFIC_CLASS)) {\n+\t\tstatus = ICE_ERR_IN_USE;\n+\t\tgoto exit_ice_rm_agg_cfg;\n+\t}\n+\n+\t/* Safe to delete entry now */\n+\tLIST_DEL(&agg_info->list_entry);\n+\tice_free(pi->hw, agg_info);\n+\n+\t/* Remove unused rl profile ids from HW and SW DB */\n+\tice_sched_rm_unused_rl_prof(pi);\n+\n+exit_ice_rm_agg_cfg:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_set_clear_cir_bw_alloc - set or clear CIR bw alloc information\n+ * @bw_t_info: bandwidth type information structure\n+ * @bw_alloc: Bandwidth allocation information\n+ *\n+ * Save or clear CIR bw alloc information (bw_alloc) in the passed param\n+ * bw_t_info.\n+ */\n+static void\n+ice_set_clear_cir_bw_alloc(struct ice_bw_type_info *bw_t_info, u16 bw_alloc)\n+{\n+\tbw_t_info->cir_bw.bw_alloc = bw_alloc;\n+\tif (bw_t_info->cir_bw.bw_alloc)\n+\t\tice_set_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap);\n+\telse\n+\t\tice_clear_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap);\n+}\n+\n+/**\n+ * ice_set_clear_eir_bw_alloc - set or clear EIR bw alloc information\n+ * @bw_t_info: bandwidth type information structure\n+ * @bw_alloc: Bandwidth allocation information\n+ *\n+ * Save or clear EIR bw alloc information (bw_alloc) in the passed param\n+ * bw_t_info.\n+ */\n+static void\n+ice_set_clear_eir_bw_alloc(struct ice_bw_type_info *bw_t_info, u16 bw_alloc)\n+{\n+\tbw_t_info->eir_bw.bw_alloc = bw_alloc;\n+\tif (bw_t_info->eir_bw.bw_alloc)\n+\t\tice_set_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap);\n+\telse\n+\t\tice_clear_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap);\n+}\n+\n+/**\n+ * ice_sched_save_vsi_bw_alloc - save VSI node's bw alloc information\n+ * @pi: port information structure\n+ * @vsi_handle: sw VSI handle\n+ * @tc: traffic class\n+ * @rl_type: rate limit type min or max\n+ * @bw_alloc: Bandwidth allocation information\n+ *\n+ * Save bw alloc information of VSI type node for post replay use.\n+ */\n+static enum ice_status\n+ice_sched_save_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t\t    enum ice_rl_type rl_type, u16 bw_alloc)\n+{\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn ICE_ERR_PARAM;\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tice_set_clear_cir_bw_alloc(&vsi_ctx->sched.bw_t_info[tc],\n+\t\t\t\t\t   bw_alloc);\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tice_set_clear_eir_bw_alloc(&vsi_ctx->sched.bw_t_info[tc],\n+\t\t\t\t\t   bw_alloc);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_set_clear_cir_bw - set or clear CIR bw\n+ * @bw_t_info: bandwidth type information structure\n+ * @bw: bandwidth in Kbps - Kilo bits per sec\n+ *\n+ * Save or clear CIR bandwidth (bw) in the passed param bw_t_info.\n+ */\n+static void\n+ice_set_clear_cir_bw(struct ice_bw_type_info *bw_t_info, u32 bw)\n+{\n+\tif (bw == ICE_SCHED_DFLT_BW) {\n+\t\tice_clear_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap);\n+\t\tbw_t_info->cir_bw.bw = 0;\n+\t} else {\n+\t\t/* Save type of bw information */\n+\t\tice_set_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap);\n+\t\tbw_t_info->cir_bw.bw = bw;\n+\t}\n+}\n+\n+/**\n+ * ice_set_clear_eir_bw - set or clear EIR bw\n+ * @bw_t_info: bandwidth type information structure\n+ * @bw: bandwidth in Kbps - Kilo bits per sec\n+ *\n+ * Save or clear EIR bandwidth (bw) in the passed param bw_t_info.\n+ */\n+static void\n+ice_set_clear_eir_bw(struct ice_bw_type_info *bw_t_info, u32 bw)\n+{\n+\tif (bw == ICE_SCHED_DFLT_BW) {\n+\t\tice_clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);\n+\t\tbw_t_info->eir_bw.bw = 0;\n+\t} else {\n+\t\t/* EIR bw and Shared bw profiles are mutually exclusive and\n+\t\t * hence only one of them may be set for any given element.\n+\t\t * First clear earlier saved shared bw information.\n+\t\t */\n+\t\tice_clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);\n+\t\tbw_t_info->shared_bw = 0;\n+\t\t/* save EIR bw information */\n+\t\tice_set_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);\n+\t\tbw_t_info->eir_bw.bw = bw;\n+\t}\n+}\n+\n+/**\n+ * ice_set_clear_shared_bw - set or clear shared bw\n+ * @bw_t_info: bandwidth type information structure\n+ * @bw: bandwidth in Kbps - Kilo bits per sec\n+ *\n+ * Save or clear shared bandwidth (bw) in the passed param bw_t_info.\n+ */\n+static void\n+ice_set_clear_shared_bw(struct ice_bw_type_info *bw_t_info, u32 bw)\n+{\n+\tif (bw == ICE_SCHED_DFLT_BW) {\n+\t\tice_clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);\n+\t\tbw_t_info->shared_bw = 0;\n+\t} else {\n+\t\t/* EIR bw and Shared bw profiles are mutually exclusive and\n+\t\t * hence only one of them may be set for any given element.\n+\t\t * First clear earlier saved EIR bw information.\n+\t\t */\n+\t\tice_clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);\n+\t\tbw_t_info->eir_bw.bw = 0;\n+\t\t/* save shared bw information */\n+\t\tice_set_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);\n+\t\tbw_t_info->shared_bw = bw;\n+\t}\n+}\n+\n+/**\n+ * ice_sched_save_vsi_bw - save VSI node's bw information\n+ * @pi: port information structure\n+ * @vsi_handle: sw VSI handle\n+ * @tc: traffic class\n+ * @rl_type: rate limit type min, max, or shared\n+ * @bw: bandwidth in Kbps - Kilo bits per sec\n+ *\n+ * Save bw information of VSI type node for post replay use.\n+ */\n+static enum ice_status\n+ice_sched_save_vsi_bw(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t      enum ice_rl_type rl_type, u32 bw)\n+{\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn ICE_ERR_PARAM;\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tice_set_clear_cir_bw(&vsi_ctx->sched.bw_t_info[tc], bw);\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tice_set_clear_eir_bw(&vsi_ctx->sched.bw_t_info[tc], bw);\n+\t\tbreak;\n+\tcase ICE_SHARED_BW:\n+\t\tice_set_clear_shared_bw(&vsi_ctx->sched.bw_t_info[tc], bw);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_set_clear_prio - set or clear priority information\n+ * @bw_t_info: bandwidth type information structure\n+ * @prio: priority to save\n+ *\n+ * Save or clear priority (prio) in the passed param bw_t_info.\n+ */\n+static void\n+ice_set_clear_prio(struct ice_bw_type_info *bw_t_info, u8 prio)\n+{\n+\tbw_t_info->generic = prio;\n+\tif (bw_t_info->generic)\n+\t\tice_set_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap);\n+\telse\n+\t\tice_clear_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap);\n+}\n+\n+/**\n+ * ice_sched_save_vsi_prio - save VSI node's priority information\n+ * @pi: port information structure\n+ * @vsi_handle: Software VSI handle\n+ * @tc: traffic class\n+ * @prio: priority to save\n+ *\n+ * Save priority information of VSI type node for post replay use.\n+ */\n+static enum ice_status\n+ice_sched_save_vsi_prio(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t\tu8 prio)\n+{\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn ICE_ERR_PARAM;\n+\tif (tc >= ICE_MAX_TRAFFIC_CLASS)\n+\t\treturn ICE_ERR_PARAM;\n+\tice_set_clear_prio(&vsi_ctx->sched.bw_t_info[tc], prio);\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_save_agg_bw_alloc - save agg node's bw alloc information\n+ * @pi: port information structure\n+ * @agg_id: node aggregator id\n+ * @tc: traffic class\n+ * @rl_type: rate limit type min or max\n+ * @bw_alloc: bandwidth alloc information\n+ *\n+ * Save bw alloc information of AGG type node for post replay use.\n+ */\n+static enum ice_status\n+ice_sched_save_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 tc,\n+\t\t\t    enum ice_rl_type rl_type, u16 bw_alloc)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\n+\tagg_info = ice_get_agg_info(pi->hw, agg_id);\n+\tif (!agg_info)\n+\t\treturn ICE_ERR_PARAM;\n+\tif (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc))\n+\t\treturn ICE_ERR_PARAM;\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tice_set_clear_cir_bw_alloc(&agg_info->bw_t_info[tc], bw_alloc);\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tice_set_clear_eir_bw_alloc(&agg_info->bw_t_info[tc], bw_alloc);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_save_agg_bw - save agg node's bw information\n+ * @pi: port information structure\n+ * @agg_id: node aggregator id\n+ * @tc: traffic class\n+ * @rl_type: rate limit type min, max, or shared\n+ * @bw: bandwidth in Kbps - Kilo bits per sec\n+ *\n+ * Save bw information of AGG type node for post replay use.\n+ */\n+static enum ice_status\n+ice_sched_save_agg_bw(struct ice_port_info *pi, u32 agg_id, u8 tc,\n+\t\t      enum ice_rl_type rl_type, u32 bw)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\n+\tagg_info = ice_get_agg_info(pi->hw, agg_id);\n+\tif (!agg_info)\n+\t\treturn ICE_ERR_PARAM;\n+\tif (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc))\n+\t\treturn ICE_ERR_PARAM;\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tice_set_clear_cir_bw(&agg_info->bw_t_info[tc], bw);\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tice_set_clear_eir_bw(&agg_info->bw_t_info[tc], bw);\n+\t\tbreak;\n+\tcase ICE_SHARED_BW:\n+\t\tice_set_clear_shared_bw(&agg_info->bw_t_info[tc], bw);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_cfg_vsi_bw_lmt_per_tc - configure VSI bw limit per tc\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: traffic class\n+ * @rl_type: min or max\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function configures bw limit of VSI scheduling node based on tc\n+ * information.\n+ */\n+enum ice_status\n+ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t\t  enum ice_rl_type rl_type, u32 bw)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_sched_set_node_bw_lmt_per_tc(pi, vsi_handle,\n+\t\t\t\t\t\t  ICE_AGG_TYPE_VSI,\n+\t\t\t\t\t\t  tc, rl_type, bw);\n+\tif (!status) {\n+\t\tice_acquire_lock(&pi->sched_lock);\n+\t\tstatus = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw);\n+\t\tice_release_lock(&pi->sched_lock);\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_dflt_vsi_bw_lmt_per_tc - configure default VSI bw limit per tc\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: traffic class\n+ * @rl_type: min or max\n+ *\n+ * This function configures default bw limit of VSI scheduling node based on tc\n+ * information.\n+ */\n+enum ice_status\n+ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t\t       enum ice_rl_type rl_type)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_sched_set_node_bw_lmt_per_tc(pi, vsi_handle,\n+\t\t\t\t\t\t  ICE_AGG_TYPE_VSI,\n+\t\t\t\t\t\t  tc, rl_type,\n+\t\t\t\t\t\t  ICE_SCHED_DFLT_BW);\n+\tif (!status) {\n+\t\tice_acquire_lock(&pi->sched_lock);\n+\t\tstatus = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type,\n+\t\t\t\t\t       ICE_SCHED_DFLT_BW);\n+\t\tice_release_lock(&pi->sched_lock);\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_agg_bw_lmt_per_tc - configure aggregator bw limit per tc\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @tc: traffic class\n+ * @rl_type: min or max\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function applies bw limit to aggregator scheduling node based on tc\n+ * information.\n+ */\n+enum ice_status\n+ice_cfg_agg_bw_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,\n+\t\t\t  enum ice_rl_type rl_type, u32 bw)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_sched_set_node_bw_lmt_per_tc(pi, agg_id, ICE_AGG_TYPE_AGG,\n+\t\t\t\t\t\t  tc, rl_type, bw);\n+\tif (!status) {\n+\t\tice_acquire_lock(&pi->sched_lock);\n+\t\tstatus = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw);\n+\t\tice_release_lock(&pi->sched_lock);\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_agg_bw_dflt_lmt_per_tc - configure aggregator bw default limit per tc\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @tc: traffic class\n+ * @rl_type: min or max\n+ *\n+ * This function applies default bw limit to aggregator scheduling node based\n+ * on tc information.\n+ */\n+enum ice_status\n+ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,\n+\t\t\t       enum ice_rl_type rl_type)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_sched_set_node_bw_lmt_per_tc(pi, agg_id, ICE_AGG_TYPE_AGG,\n+\t\t\t\t\t\t  tc, rl_type,\n+\t\t\t\t\t\t  ICE_SCHED_DFLT_BW);\n+\tif (!status) {\n+\t\tice_acquire_lock(&pi->sched_lock);\n+\t\tstatus = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type,\n+\t\t\t\t\t       ICE_SCHED_DFLT_BW);\n+\t\tice_release_lock(&pi->sched_lock);\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_vsi_bw_shared_lmt - configure VSI bw shared limit\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function Configures shared rate limiter(SRL) of all VSI type nodes\n+ * across all traffic classes for VSI matching handle.\n+ */\n+enum ice_status\n+ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 bw)\n+{\n+\treturn ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle, bw);\n+}\n+\n+/**\n+ * ice_cfg_vsi_bw_no_shared_lmt - configure VSI bw for no shared limiter\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function removes the shared rate limiter(SRL) of all VSI type nodes\n+ * across all traffic classes for VSI matching handle.\n+ */\n+enum ice_status\n+ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle)\n+{\n+\treturn ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle,\n+\t\t\t\t\t       ICE_SCHED_DFLT_BW);\n+}\n+\n+/**\n+ * ice_cfg_agg_bw_shared_lmt - configure aggregator bw shared limit\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function configures the shared rate limiter(SRL) of all agg type nodes\n+ * across all traffic classes for aggregator matching agg_id.\n+ */\n+enum ice_status\n+ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)\n+{\n+\treturn ice_sched_set_agg_bw_shared_lmt(pi, agg_id, bw);\n+}\n+\n+/**\n+ * ice_cfg_agg_bw_no_shared_lmt - configure aggregator bw for no shared limiter\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ *\n+ * This function removes the shared rate limiter(SRL) of all agg type nodes\n+ * across all traffic classes for aggregator matching agg_id.\n+ */\n+enum ice_status\n+ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id)\n+{\n+\treturn ice_sched_set_agg_bw_shared_lmt(pi, agg_id, ICE_SCHED_DFLT_BW);\n+}\n+\n+/**\n+ * ice_config_vsi_queue_priority - config VSI queue priority of node\n+ * @pi: port information structure\n+ * @num_qs: number of VSI queues\n+ * @q_ids: queue ids array\n+ * @q_ids: queue ids array\n+ * @q_prio: queue priority array\n+ *\n+ * This function configures the queue node priority (Sibling Priority) of the\n+ * passed in VSI's queue(s) for a given traffic class (tc).\n+ */\n+enum ice_status\n+ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,\n+\t\t       u8 *q_prio)\n+{\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu16 i;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\tfor (i = 0; i < num_qs; i++) {\n+\t\tstruct ice_sched_node *node;\n+\n+\t\tnode = ice_sched_find_node_by_teid(pi->root, q_ids[i]);\n+\t\tif (!node || node->info.data.elem_type !=\n+\t\t    ICE_AQC_ELEM_TYPE_LEAF) {\n+\t\t\tstatus = ICE_ERR_PARAM;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* Configure Priority */\n+\t\tstatus = ice_sched_cfg_sibl_node_prio(hw, node, q_prio[i]);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_agg_vsi_priority_per_tc - config agg's VSI priority per tc\n+ * @pi: port information structure\n+ * @agg_id: Aggregator id\n+ * @num_vsis: number of VSI(s)\n+ * @vsi_handle_arr: array of software VSI handles\n+ * @node_prio: pointer to node priority\n+ * @tc: traffic class\n+ *\n+ * This function configures the node priority (Sibling Priority) of the\n+ * passed in VSI's for a given traffic class (tc) of an Aggregator id.\n+ */\n+enum ice_status\n+ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id,\n+\t\t\t\tu16 num_vsis, u16 *vsi_handle_arr,\n+\t\t\t\tu8 *node_prio, u8 tc)\n+{\n+\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\tstruct ice_sched_node *tc_node, *agg_node;\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_sched_agg_info *agg_info;\n+\tbool agg_id_present = false;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu16 i;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tLIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,\n+\t\t\t    list_entry)\n+\t\tif (agg_info->agg_id == agg_id) {\n+\t\t\tagg_id_present = true;\n+\t\t\tbreak;\n+\t\t}\n+\tif (!agg_id_present)\n+\t\tgoto exit_agg_priority_per_tc;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\tgoto exit_agg_priority_per_tc;\n+\n+\tagg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);\n+\tif (!agg_node)\n+\t\tgoto exit_agg_priority_per_tc;\n+\n+\tif (num_vsis > hw->max_children[agg_node->tx_sched_layer])\n+\t\tgoto exit_agg_priority_per_tc;\n+\n+\tfor (i = 0; i < num_vsis; i++) {\n+\t\tstruct ice_sched_node *vsi_node;\n+\t\tbool vsi_handle_valid = false;\n+\t\tu16 vsi_handle;\n+\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tvsi_handle = vsi_handle_arr[i];\n+\t\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\t\tgoto exit_agg_priority_per_tc;\n+\t\t/* Verify child nodes before applying settings */\n+\t\tLIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list,\n+\t\t\t\t    ice_sched_agg_vsi_info, list_entry)\n+\t\t\tif (agg_vsi_info->vsi_handle == vsi_handle) {\n+\t\t\t\tvsi_handle_valid = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\tif (!vsi_handle_valid)\n+\t\t\tgoto exit_agg_priority_per_tc;\n+\n+\t\tvsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);\n+\t\tif (!vsi_node)\n+\t\t\tgoto exit_agg_priority_per_tc;\n+\n+\t\tif (ice_sched_find_node_in_subtree(hw, agg_node, vsi_node)) {\n+\t\t\t/* Configure Priority */\n+\t\t\tstatus = ice_sched_cfg_sibl_node_prio(hw, vsi_node,\n+\t\t\t\t\t\t\t      node_prio[i]);\n+\t\t\tif (status)\n+\t\t\t\tbreak;\n+\t\t\tstatus = ice_sched_save_vsi_prio(pi, vsi_handle, tc,\n+\t\t\t\t\t\t\t node_prio[i]);\n+\t\t\tif (status)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+exit_agg_priority_per_tc:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_vsi_bw_alloc - config VSI bw alloc per tc\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @ena_tcmap: enabled tc map\n+ * @rl_type: Rate limit type CIR/EIR\n+ * @bw_alloc: Array of bw alloc\n+ *\n+ * This function configures the bw allocation of the passed in VSI's\n+ * node(s) for enabled traffic class.\n+ */\n+enum ice_status\n+ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap,\n+\t\t     enum ice_rl_type rl_type, u8 *bw_alloc)\n+{\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 tc;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\t/* Return success if no nodes are present across tc */\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tstruct ice_sched_node *tc_node, *vsi_node;\n+\n+\t\tif (!ice_is_tc_ena(ena_tcmap, tc))\n+\t\t\tcontinue;\n+\n+\t\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\t\tif (!tc_node)\n+\t\t\tcontinue;\n+\n+\t\tvsi_node = ice_sched_get_vsi_node(pi->hw, tc_node, vsi_handle);\n+\t\tif (!vsi_node)\n+\t\t\tcontinue;\n+\n+\t\tstatus = ice_sched_cfg_node_bw_alloc(pi->hw, vsi_node, rl_type,\n+\t\t\t\t\t\t     bw_alloc[tc]);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t\tstatus = ice_sched_save_vsi_bw_alloc(pi, vsi_handle, tc,\n+\t\t\t\t\t\t     rl_type, bw_alloc[tc]);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_agg_bw_alloc - config agg bw alloc\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @ena_tcmap: enabled tc map\n+ * @rl_type: rate limit type CIR/EIR\n+ * @bw_alloc: array of bw alloc\n+ *\n+ * This function configures the bw allocation of passed in aggregator for\n+ * enabled traffic class(s).\n+ */\n+enum ice_status\n+ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap,\n+\t\t     enum ice_rl_type rl_type, u8 *bw_alloc)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\tbool agg_id_present = false;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu8 tc;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tLIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,\n+\t\t\t    list_entry)\n+\t\tif (agg_info->agg_id == agg_id) {\n+\t\t\tagg_id_present = true;\n+\t\t\tbreak;\n+\t\t}\n+\tif (!agg_id_present) {\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto exit_cfg_agg_bw_alloc;\n+\t}\n+\n+\t/* Return success if no nodes are present across tc */\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tstruct ice_sched_node *tc_node, *agg_node;\n+\n+\t\tif (!ice_is_tc_ena(ena_tcmap, tc))\n+\t\t\tcontinue;\n+\n+\t\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\t\tif (!tc_node)\n+\t\t\tcontinue;\n+\n+\t\tagg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);\n+\t\tif (!agg_node)\n+\t\t\tcontinue;\n+\n+\t\tstatus = ice_sched_cfg_node_bw_alloc(hw, agg_node, rl_type,\n+\t\t\t\t\t\t     bw_alloc[tc]);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t\tstatus = ice_sched_save_agg_bw_alloc(pi, agg_id, tc, rl_type,\n+\t\t\t\t\t\t     bw_alloc[tc]);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\n+exit_cfg_agg_bw_alloc:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_calc_wakeup - calculate rl profile wakeup parameter\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function calculates the wakeup parameter of rl profile.\n+ */\n+static u16 ice_sched_calc_wakeup(s32 bw)\n+{\n+\ts64 bytes_per_sec, wakeup_int, wakeup_a, wakeup_b, wakeup_f;\n+\ts32 wakeup_f_int;\n+\tu16 wakeup = 0;\n+\n+\t/* Get the wakeup integer value */\n+\tbytes_per_sec = DIV_64BIT(((s64)bw * 1000), BITS_PER_BYTE);\n+\twakeup_int = DIV_64BIT(ICE_RL_PROF_FREQUENCY, bytes_per_sec);\n+\tif (wakeup_int > 63) {\n+\t\twakeup = (u16)((1 << 15) | wakeup_int);\n+\t} else {\n+\t\t/* Calculate fraction value up to 4 decimals\n+\t\t * Convert Integer value to a constant multiplier\n+\t\t */\n+\t\twakeup_b = (s64)ICE_RL_PROF_MULTIPLIER * wakeup_int;\n+\t\twakeup_a = DIV_64BIT((s64)ICE_RL_PROF_MULTIPLIER *\n+\t\t\t\t     ICE_RL_PROF_FREQUENCY, bytes_per_sec);\n+\n+\t\t/* Get Fraction value */\n+\t\twakeup_f = wakeup_a - wakeup_b;\n+\n+\t\t/* Round up the Fractional value via Ceil(Fractional value) */\n+\t\tif (wakeup_f > DIV_64BIT(ICE_RL_PROF_MULTIPLIER, 2))\n+\t\t\twakeup_f += 1;\n+\n+\t\twakeup_f_int = (s32)DIV_64BIT(wakeup_f * ICE_RL_PROF_FRACTION,\n+\t\t\t\t\t      ICE_RL_PROF_MULTIPLIER);\n+\t\twakeup |= (u16)(wakeup_int << 9);\n+\t\twakeup |= (u16)(0x1ff & wakeup_f_int);\n+\t}\n+\n+\treturn wakeup;\n+}\n+\n+/**\n+ * ice_sched_bw_to_rl_profile - convert bw to profile parameters\n+ * @bw: bandwidth in kbps\n+ * @profile: profile parameters to return\n+ *\n+ * This function converts the bw to profile structure format.\n+ */\n+static enum ice_status\n+ice_sched_bw_to_rl_profile(u32 bw, struct ice_aqc_rl_profile_elem *profile)\n+{\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\ts64 bytes_per_sec, ts_rate, mv_tmp;\n+\tbool found = false;\n+\ts32 encode = 0;\n+\ts64 mv = 0;\n+\ts32 i;\n+\n+\t/* Bw settings range is from 0.5Mb/sec to 100Gb/sec */\n+\tif (bw < ICE_SCHED_MIN_BW || bw > ICE_SCHED_MAX_BW)\n+\t\treturn status;\n+\n+\t/* Bytes per second from kbps */\n+\tbytes_per_sec = DIV_64BIT(((s64)bw * 1000), BITS_PER_BYTE);\n+\n+\t/* encode is 6 bits but really useful are 5 bits */\n+\tfor (i = 0; i < 64; i++) {\n+\t\tu64 pow_result = BIT_ULL(i);\n+\n+\t\tts_rate = DIV_64BIT((s64)ICE_RL_PROF_FREQUENCY,\n+\t\t\t\t    pow_result * ICE_RL_PROF_TS_MULTIPLIER);\n+\t\tif (ts_rate <= 0)\n+\t\t\tcontinue;\n+\n+\t\t/* Multiplier value */\n+\t\tmv_tmp = DIV_64BIT(bytes_per_sec * ICE_RL_PROF_MULTIPLIER,\n+\t\t\t\t   ts_rate);\n+\n+\t\t/* Round to the nearest ICE_RL_PROF_MULTIPLIER */\n+\t\tmv = round_up_64bit(mv_tmp, ICE_RL_PROF_MULTIPLIER);\n+\n+\t\t/* First multiplier value greater than the given\n+\t\t * accuracy bytes\n+\t\t */\n+\t\tif (mv > ICE_RL_PROF_ACCURACY_BYTES) {\n+\t\t\tencode = i;\n+\t\t\tfound = true;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tif (found) {\n+\t\tu16 wm;\n+\n+\t\twm = ice_sched_calc_wakeup(bw);\n+\t\tprofile->rl_multiply = CPU_TO_LE16(mv);\n+\t\tprofile->wake_up_calc = CPU_TO_LE16(wm);\n+\t\tprofile->rl_encode = CPU_TO_LE16(encode);\n+\t\tstatus = ICE_SUCCESS;\n+\t} else {\n+\t\tstatus = ICE_ERR_DOES_NOT_EXIST;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_add_rl_profile - add rl profile\n+ * @pi: port information structure\n+ * @rl_type: type of rate limit bw - min, max, or shared\n+ * @bw: bandwidth in Kbps - Kilo bits per sec\n+ * @layer_num: specifies in which layer to create profile\n+ *\n+ * This function first checks the existing list for corresponding bw\n+ * parameter. If it exists, it returns the associated profile otherwise\n+ * it creates a new rate limit profile for requested bw, and adds it to\n+ * the hw db and local list. It returns the new profile or null on error.\n+ * The caller needs to hold the scheduler lock.\n+ */\n+static struct ice_aqc_rl_profile_info *\n+ice_sched_add_rl_profile(struct ice_port_info *pi,\n+\t\t\t enum ice_rl_type rl_type, u32 bw, u8 layer_num)\n+{\n+\tstruct ice_aqc_rl_profile_generic_elem *buf;\n+\tstruct ice_aqc_rl_profile_info *rl_prof_elem;\n+\tu16 profiles_added = 0, num_profiles = 1;\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_hw *hw;\n+\tu8 profile_type;\n+\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tprofile_type = ICE_AQC_RL_PROFILE_TYPE_CIR;\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tprofile_type = ICE_AQC_RL_PROFILE_TYPE_EIR;\n+\t\tbreak;\n+\tcase ICE_SHARED_BW:\n+\t\tprofile_type = ICE_AQC_RL_PROFILE_TYPE_SRL;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn NULL;\n+\t}\n+\n+\tif (!pi)\n+\t\treturn NULL;\n+\thw = pi->hw;\n+\tLIST_FOR_EACH_ENTRY(rl_prof_elem, &pi->rl_prof_list[layer_num],\n+\t\t\t    ice_aqc_rl_profile_info, list_entry)\n+\t\tif (rl_prof_elem->profile.flags == profile_type &&\n+\t\t    rl_prof_elem->bw == bw)\n+\t\t\t/* Return existing profile id info */\n+\t\t\treturn rl_prof_elem;\n+\n+\t/* Create new profile id */\n+\trl_prof_elem = (struct ice_aqc_rl_profile_info *)\n+\t\tice_malloc(hw, sizeof(*rl_prof_elem));\n+\n+\tif (!rl_prof_elem)\n+\t\treturn NULL;\n+\n+\tstatus = ice_sched_bw_to_rl_profile(bw, &rl_prof_elem->profile);\n+\tif (status != ICE_SUCCESS)\n+\t\tgoto exit_add_rl_prof;\n+\n+\trl_prof_elem->bw = bw;\n+\t/* layer_num is zero relative, and fw expects level from 1 to 9 */\n+\trl_prof_elem->profile.level = layer_num + 1;\n+\trl_prof_elem->profile.flags = profile_type;\n+\trl_prof_elem->profile.max_burst_size = CPU_TO_LE16(hw->max_burst_size);\n+\n+\t/* Create new entry in hw db */\n+\tbuf = (struct ice_aqc_rl_profile_generic_elem *)\n+\t\t&rl_prof_elem->profile;\n+\tstatus = ice_aq_add_rl_profile(hw, num_profiles, buf, sizeof(*buf),\n+\t\t\t\t       &profiles_added, NULL);\n+\tif (status || profiles_added != num_profiles)\n+\t\tgoto exit_add_rl_prof;\n+\n+\t/* Good entry - add in the list */\n+\trl_prof_elem->prof_id_ref = 0;\n+\tLIST_ADD(&rl_prof_elem->list_entry, &pi->rl_prof_list[layer_num]);\n+\treturn rl_prof_elem;\n+\n+exit_add_rl_prof:\n+\tice_free(hw, rl_prof_elem);\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_sched_del_rl_profile - remove rl profile\n+ * @hw: pointer to the hw struct\n+ * @rl_info: rate limit profile information\n+ *\n+ * If the profile id is not referenced anymore, it removes profile id with\n+ * its associated parameters from hw db,and locally. The caller needs to\n+ * hold scheduler lock.\n+ */\n+enum ice_status\n+ice_sched_del_rl_profile(struct ice_hw *hw,\n+\t\t\t struct ice_aqc_rl_profile_info *rl_info)\n+{\n+\tstruct ice_aqc_rl_profile_generic_elem *buf;\n+\tu16 num_profiles_removed;\n+\tenum ice_status status;\n+\tu16 num_profiles = 1;\n+\n+\tif (rl_info->prof_id_ref != 0)\n+\t\treturn ICE_ERR_IN_USE;\n+\n+\t/* Safe to remove profile id */\n+\tbuf = (struct ice_aqc_rl_profile_generic_elem *)\n+\t\t&rl_info->profile;\n+\tstatus = ice_aq_remove_rl_profile(hw, num_profiles, buf, sizeof(*buf),\n+\t\t\t\t\t  &num_profiles_removed, NULL);\n+\tif (status || num_profiles_removed != num_profiles)\n+\t\treturn ICE_ERR_CFG;\n+\n+\t/* Delete stale entry now */\n+\tLIST_DEL(&rl_info->list_entry);\n+\tice_free(hw, rl_info);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_rm_unused_rl_prof - remove unused rl profile\n+ * @pi: port information structure\n+ *\n+ * This function removes unused rate limit profiles from the hw and\n+ * SW DB. The caller needs to hold scheduler lock.\n+ */\n+void ice_sched_rm_unused_rl_prof(struct ice_port_info *pi)\n+{\n+\tu8 ln;\n+\n+\tfor (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {\n+\t\tstruct ice_aqc_rl_profile_info *rl_prof_elem;\n+\t\tstruct ice_aqc_rl_profile_info *rl_prof_tmp;\n+\n+\t\tLIST_FOR_EACH_ENTRY_SAFE(rl_prof_elem, rl_prof_tmp,\n+\t\t\t\t\t &pi->rl_prof_list[ln],\n+\t\t\t\t\t ice_aqc_rl_profile_info, list_entry) {\n+\t\t\tif (!ice_sched_del_rl_profile(pi->hw, rl_prof_elem))\n+\t\t\t\tice_debug(pi->hw, ICE_DBG_SCHED,\n+\t\t\t\t\t  \"Removed rl profile\\n\");\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * ice_sched_update_elem - update element\n+ * @hw: pointer to the hw struct\n+ * @node: pointer to node\n+ * @info: node info to update\n+ *\n+ * It updates the HW DB, and local SW DB of node. It updates the scheduling\n+ * parameters of node from argument info data buffer (Info->data buf) and\n+ * returns success or error on config sched element failure. The caller\n+ * needs to hold scheduler lock.\n+ */\n+static enum ice_status\n+ice_sched_update_elem(struct ice_hw *hw, struct ice_sched_node *node,\n+\t\t      struct ice_aqc_txsched_elem_data *info)\n+{\n+\tstruct ice_aqc_conf_elem buf;\n+\tenum ice_status status;\n+\tu16 elem_cfgd = 0;\n+\tu16 num_elems = 1;\n+\n+\tbuf.generic[0] = *info;\n+\t/* Parent teid is reserved field in this aq call */\n+\tbuf.generic[0].parent_teid = 0;\n+\t/* Element type is reserved field in this aq call */\n+\tbuf.generic[0].data.elem_type = 0;\n+\t/* Flags is reserved field in this aq call */\n+\tbuf.generic[0].data.flags = 0;\n+\n+\t/* Update HW DB */\n+\t/* Configure element node */\n+\tstatus = ice_aq_cfg_sched_elems(hw, num_elems, &buf, sizeof(buf),\n+\t\t\t\t\t&elem_cfgd, NULL);\n+\tif (status || elem_cfgd != num_elems) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"Config sched elem error\\n\");\n+\t\treturn ICE_ERR_CFG;\n+\t}\n+\n+\t/* Config success case */\n+\t/* Now update local SW DB */\n+\t/* Only copy the data portion of info buffer */\n+\tnode->info.data = info->data;\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_cfg_node_bw_lmt - configure node sched params\n+ * @hw: pointer to the hw struct\n+ * @node: sched node to configure\n+ * @rl_type: rate limit type cir, eir, or shared\n+ * @rl_prof_id: rate limit profile id\n+ *\n+ * This function configures node element's bw limit.\n+ */\n+static enum ice_status\n+ice_sched_cfg_node_bw_lmt(struct ice_hw *hw, struct ice_sched_node *node,\n+\t\t\t  enum ice_rl_type rl_type, u16 rl_prof_id)\n+{\n+\tstruct ice_aqc_txsched_elem_data buf;\n+\tstruct ice_aqc_txsched_elem *data;\n+\n+\tbuf = node->info;\n+\tdata = &buf.data;\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tdata->valid_sections |= ICE_AQC_ELEM_VALID_CIR;\n+\t\tdata->cir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id);\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\t/* EIR bw and Shared bw profiles are mutually exclusive and\n+\t\t * hence only one of them may be set for any given element\n+\t\t */\n+\t\tif (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED)\n+\t\t\treturn ICE_ERR_CFG;\n+\t\tdata->valid_sections |= ICE_AQC_ELEM_VALID_EIR;\n+\t\tdata->eir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id);\n+\t\tbreak;\n+\tcase ICE_SHARED_BW:\n+\t\t/* Check for removing shared bw */\n+\t\tif (rl_prof_id == ICE_SCHED_NO_SHARED_RL_PROF_ID) {\n+\t\t\t/* remove shared profile */\n+\t\t\tdata->valid_sections &= ~ICE_AQC_ELEM_VALID_SHARED;\n+\t\t\tdata->srl_id = 0; /* clear srl field */\n+\n+\t\t\t/* enable back EIR to default profile */\n+\t\t\tdata->valid_sections |= ICE_AQC_ELEM_VALID_EIR;\n+\t\t\tdata->eir_bw.bw_profile_idx =\n+\t\t\t\tCPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* EIR bw and Shared bw profiles are mutually exclusive and\n+\t\t * hence only one of them may be set for any given element\n+\t\t */\n+\t\tif ((data->valid_sections & ICE_AQC_ELEM_VALID_EIR) &&\n+\t\t    (LE16_TO_CPU(data->eir_bw.bw_profile_idx) !=\n+\t\t\t    ICE_SCHED_DFLT_RL_PROF_ID))\n+\t\t\treturn ICE_ERR_CFG;\n+\t\t/* EIR bw is set to default, disable it */\n+\t\tdata->valid_sections &= ~ICE_AQC_ELEM_VALID_EIR;\n+\t\t/* Okay to enable shared bw now */\n+\t\tdata->valid_sections |= ICE_AQC_ELEM_VALID_SHARED;\n+\t\tdata->srl_id = CPU_TO_LE16(rl_prof_id);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Unknown rate limit type */\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\t/* Configure element */\n+\treturn ice_sched_update_elem(hw, node, &buf);\n+}\n+\n+/**\n+ * ice_sched_get_node_rl_prof_id - get node's rate limit profile id\n+ * @node: sched node\n+ * @rl_type: rate limit type\n+ *\n+ * If existing profile matches, it returns the corresponding rate\n+ * limit profile id, otherwise it returns an invalid id as error.\n+ */\n+static u16\n+ice_sched_get_node_rl_prof_id(struct ice_sched_node *node,\n+\t\t\t      enum ice_rl_type rl_type)\n+{\n+\tu16 rl_prof_id = ICE_SCHED_INVAL_PROF_ID;\n+\tstruct ice_aqc_txsched_elem *data;\n+\n+\tdata = &node->info.data;\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tif (data->valid_sections & ICE_AQC_ELEM_VALID_CIR)\n+\t\t\trl_prof_id = LE16_TO_CPU(data->cir_bw.bw_profile_idx);\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tif (data->valid_sections & ICE_AQC_ELEM_VALID_EIR)\n+\t\t\trl_prof_id = LE16_TO_CPU(data->eir_bw.bw_profile_idx);\n+\t\tbreak;\n+\tcase ICE_SHARED_BW:\n+\t\tif (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED)\n+\t\t\trl_prof_id = LE16_TO_CPU(data->srl_id);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn rl_prof_id;\n+}\n+\n+/**\n+ * ice_sched_get_rl_prof_layer - selects rate limit profile creation layer\n+ * @pi: port information structure\n+ * @rl_type: type of rate limit bw - min, max, or shared\n+ * @layer_index: layer index\n+ *\n+ * This function returns requested profile creation layer.\n+ */\n+static u8\n+ice_sched_get_rl_prof_layer(struct ice_port_info *pi, enum ice_rl_type rl_type,\n+\t\t\t    u8 layer_index)\n+{\n+\tstruct ice_hw *hw = pi->hw;\n+\n+\tif (layer_index >= hw->num_tx_sched_layers)\n+\t\treturn ICE_SCHED_INVAL_LAYER_NUM;\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tif (hw->layer_info[layer_index].max_cir_rl_profiles)\n+\t\t\treturn layer_index;\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tif (hw->layer_info[layer_index].max_eir_rl_profiles)\n+\t\t\treturn layer_index;\n+\t\tbreak;\n+\tcase ICE_SHARED_BW:\n+\t\t/* if current layer doesn't support SRL profile creation\n+\t\t * then try a layer up or down.\n+\t\t */\n+\t\tif (hw->layer_info[layer_index].max_srl_profiles)\n+\t\t\treturn layer_index;\n+\t\telse if (layer_index < hw->num_tx_sched_layers - 1 &&\n+\t\t\t hw->layer_info[layer_index + 1].max_srl_profiles)\n+\t\t\treturn layer_index + 1;\n+\t\telse if (layer_index > 0 &&\n+\t\t\t hw->layer_info[layer_index - 1].max_srl_profiles)\n+\t\t\treturn layer_index - 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn ICE_SCHED_INVAL_LAYER_NUM;\n+}\n+\n+/**\n+ * ice_sched_get_srl_node - get shared rate limit node\n+ * @node: tree node\n+ * @srl_layer: shared rate limit layer\n+ *\n+ * This function returns SRL node to be used for shared rate limit purpose.\n+ * The caller needs to hold scheduler lock.\n+ */\n+static struct ice_sched_node *\n+ice_sched_get_srl_node(struct ice_sched_node *node, u8 srl_layer)\n+{\n+\tif (srl_layer > node->tx_sched_layer)\n+\t\treturn node->children[0];\n+\telse if (srl_layer < node->tx_sched_layer)\n+\t\t/* Node can't be created without a parent. It will always\n+\t\t * have a valid parent except root node.\n+\t\t */\n+\t\treturn node->parent;\n+\telse\n+\t\treturn node;\n+}\n+\n+/**\n+ * ice_sched_rm_rl_profile - remove rl profile id\n+ * @pi: port information structure\n+ * @layer_num: layer number where profiles are saved\n+ * @profile_type: profile type like EIR, CIR, or SRL\n+ * @profile_id: profile id to remove\n+ *\n+ * This function removes rate limit profile from layer 'layer_num' of type\n+ * 'profile_type' and profile id as 'profile_id'. The caller needs to hold\n+ * scheduler lock.\n+ */\n+static enum ice_status\n+ice_sched_rm_rl_profile(struct ice_port_info *pi, u8 layer_num, u8 profile_type,\n+\t\t\tu16 profile_id)\n+{\n+\tstruct ice_aqc_rl_profile_info *rl_prof_elem;\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\t/* Check the existing list for rl profile */\n+\tLIST_FOR_EACH_ENTRY(rl_prof_elem, &pi->rl_prof_list[layer_num],\n+\t\t\t    ice_aqc_rl_profile_info, list_entry)\n+\t\tif (rl_prof_elem->profile.flags == profile_type &&\n+\t\t    LE16_TO_CPU(rl_prof_elem->profile.profile_id) ==\n+\t\t    profile_id) {\n+\t\t\tif (rl_prof_elem->prof_id_ref)\n+\t\t\t\trl_prof_elem->prof_id_ref--;\n+\n+\t\t\t/* Remove old profile id from database */\n+\t\t\tstatus = ice_sched_del_rl_profile(pi->hw, rl_prof_elem);\n+\t\t\tif (status && status != ICE_ERR_IN_USE)\n+\t\t\t\tice_debug(pi->hw, ICE_DBG_SCHED,\n+\t\t\t\t\t  \"Remove rl profile failed\\n\");\n+\t\t\tbreak;\n+\t\t}\n+\tif (status == ICE_ERR_IN_USE)\n+\t\tstatus = ICE_SUCCESS;\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_set_node_bw_dflt - set node's bandwidth limit to default\n+ * @pi: port information structure\n+ * @node: pointer to node structure\n+ * @rl_type: rate limit type min, max, or shared\n+ * @layer_num: layer number where rl profiles are saved\n+ *\n+ * This function configures node element's bw rate limit profile id of\n+ * type cir, eir, or srl to default. This function needs to be called\n+ * with the scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_set_node_bw_dflt(struct ice_port_info *pi,\n+\t\t\t   struct ice_sched_node *node,\n+\t\t\t   enum ice_rl_type rl_type, u8 layer_num)\n+{\n+\tenum ice_status status;\n+\tstruct ice_hw *hw;\n+\tu8 profile_type;\n+\tu16 rl_prof_id;\n+\tu16 old_id;\n+\n+\thw = pi->hw;\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tprofile_type = ICE_AQC_RL_PROFILE_TYPE_CIR;\n+\t\trl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID;\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tprofile_type = ICE_AQC_RL_PROFILE_TYPE_EIR;\n+\t\trl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID;\n+\t\tbreak;\n+\tcase ICE_SHARED_BW:\n+\t\tprofile_type = ICE_AQC_RL_PROFILE_TYPE_SRL;\n+\t\t/* No SRL is configured for default case */\n+\t\trl_prof_id = ICE_SCHED_NO_SHARED_RL_PROF_ID;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\t/* Save existing rl prof id for later clean up */\n+\told_id = ice_sched_get_node_rl_prof_id(node, rl_type);\n+\t/* Configure bw scheduling parameters */\n+\tstatus = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Remove stale rl profile id */\n+\tif (old_id == ICE_SCHED_DFLT_RL_PROF_ID ||\n+\t    old_id == ICE_SCHED_INVAL_PROF_ID)\n+\t\treturn status;\n+\treturn ice_sched_rm_rl_profile(pi, layer_num, profile_type, old_id);\n+}\n+\n+/**\n+ * ice_sched_set_eir_srl_excl - set EIR/SRL exclusiveness\n+ * @pi: port information structure\n+ * @node: pointer to node structure\n+ * @layer_num: layer number where rate limit profiles are saved\n+ * @rl_type: rate limit type min, max, or shared\n+ * @bw: bandwidth value\n+ *\n+ * This function prepares node element's bandwidth to SRL or EIR exclusively.\n+ * EIR bw and Shared bw profiles are mutually exclusive and hence only one of\n+ * them may be set for any given element. This function needs to be called\n+ * with the scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_set_eir_srl_excl(struct ice_port_info *pi,\n+\t\t\t   struct ice_sched_node *node,\n+\t\t\t   u8 layer_num, enum ice_rl_type rl_type, u32 bw)\n+{\n+\tif (rl_type == ICE_SHARED_BW) {\n+\t\t/* SRL node passed in this case, it may be different node */\n+\t\tif (bw == ICE_SCHED_DFLT_BW)\n+\t\t\t/* SRL being removed, ice_sched_cfg_node_bw_lmt()\n+\t\t\t * enables EIR to default. EIR is not set in this\n+\t\t\t * case, so no additional action is required.\n+\t\t\t */\n+\t\t\treturn ICE_SUCCESS;\n+\n+\t\t/* SRL being configured, set EIR to default here.\n+\t\t * ice_sched_cfg_node_bw_lmt() disables EIR when it\n+\t\t * configures SRL\n+\t\t */\n+\t\treturn ice_sched_set_node_bw_dflt(pi, node, ICE_MAX_BW,\n+\t\t\t\t\t\t  layer_num);\n+\t} else if (rl_type == ICE_MAX_BW &&\n+\t\t   node->info.data.valid_sections & ICE_AQC_ELEM_VALID_SHARED) {\n+\t\t/* Remove Shared profile. Set default shared bw call\n+\t\t * removes shared profile for a node.\n+\t\t */\n+\t\treturn ice_sched_set_node_bw_dflt(pi, node,\n+\t\t\t\t\t\t  ICE_SHARED_BW,\n+\t\t\t\t\t\t  layer_num);\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_set_node_bw - set node's bandwidth\n+ * @pi: port information structure\n+ * @node: tree node\n+ * @rl_type: rate limit type min, max, or shared\n+ * @bw: bandwidth in Kbps - Kilo bits per sec\n+ * @layer_num: layer number\n+ *\n+ * This function adds new profile corresponding to requested bw, configures\n+ * node's rl profile id of type cir, eir, or srl, and removes old profile\n+ * id from local database. The caller needs to hold scheduler lock.\n+ */\n+static enum ice_status\n+ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,\n+\t\t      enum ice_rl_type rl_type, u32 bw, u8 layer_num)\n+{\n+\tstruct ice_aqc_rl_profile_info *rl_prof_info;\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu16 old_id, rl_prof_id;\n+\n+\trl_prof_info = ice_sched_add_rl_profile(pi, rl_type, bw, layer_num);\n+\tif (!rl_prof_info)\n+\t\treturn status;\n+\n+\trl_prof_id = LE16_TO_CPU(rl_prof_info->profile.profile_id);\n+\n+\t/* Save existing rl prof id for later clean up */\n+\told_id = ice_sched_get_node_rl_prof_id(node, rl_type);\n+\t/* Configure bw scheduling parameters */\n+\tstatus = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* New changes has been applied */\n+\t/* Increment the profile id reference count */\n+\trl_prof_info->prof_id_ref++;\n+\n+\t/* Check for old id removal */\n+\tif ((old_id == ICE_SCHED_DFLT_RL_PROF_ID && rl_type != ICE_SHARED_BW) ||\n+\t    old_id == ICE_SCHED_INVAL_PROF_ID || old_id == rl_prof_id)\n+\t\treturn status;\n+\n+\treturn ice_sched_rm_rl_profile(pi, layer_num,\n+\t\t\t\t       rl_prof_info->profile.flags,\n+\t\t\t\t       old_id);\n+}\n+\n+/**\n+ * ice_sched_set_node_bw_lmt - set node's bw limit\n+ * @pi: port information structure\n+ * @node: tree node\n+ * @rl_type: rate limit type min, max, or shared\n+ * @bw: bandwidth in Kbps - Kilo bits per sec\n+ *\n+ * It updates node's bw limit parameters like bw rl profile id of type cir,\n+ * eir, or srl. The caller needs to hold scheduler lock.\n+ */\n+enum ice_status\n+ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,\n+\t\t\t  enum ice_rl_type rl_type, u32 bw)\n+{\n+\tstruct ice_sched_node *cfg_node = node;\n+\tenum ice_status status;\n+\n+\tstruct ice_hw *hw;\n+\tu8 layer_num;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\thw = pi->hw;\n+\t/* Remove unused rl profile ids from HW and SW DB */\n+\tice_sched_rm_unused_rl_prof(pi);\n+\tlayer_num = ice_sched_get_rl_prof_layer(pi, rl_type,\n+\t\t\t\t\t\tnode->tx_sched_layer);\n+\tif (layer_num >= hw->num_tx_sched_layers)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (rl_type == ICE_SHARED_BW) {\n+\t\t/* SRL node may be different */\n+\t\tcfg_node = ice_sched_get_srl_node(node, layer_num);\n+\t\tif (!cfg_node)\n+\t\t\treturn ICE_ERR_CFG;\n+\t}\n+\t/* EIR bw and Shared bw profiles are mutually exclusive and\n+\t * hence only one of them may be set for any given element\n+\t */\n+\tstatus = ice_sched_set_eir_srl_excl(pi, cfg_node, layer_num, rl_type,\n+\t\t\t\t\t    bw);\n+\tif (status)\n+\t\treturn status;\n+\tif (bw == ICE_SCHED_DFLT_BW)\n+\t\treturn ice_sched_set_node_bw_dflt(pi, cfg_node, rl_type,\n+\t\t\t\t\t\t  layer_num);\n+\treturn ice_sched_set_node_bw(pi, cfg_node, rl_type, bw, layer_num);\n+}\n+\n+/**\n+ * ice_sched_set_node_bw_dflt_lmt - set node's bw limit to default\n+ * @pi: port information structure\n+ * @node: pointer to node structure\n+ * @rl_type: rate limit type min, max, or shared\n+ *\n+ * This function configures node element's bw rate limit profile id of\n+ * type cir, eir, or srl to default. This function needs to be called\n+ * with the scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_set_node_bw_dflt_lmt(struct ice_port_info *pi,\n+\t\t\t       struct ice_sched_node *node,\n+\t\t\t       enum ice_rl_type rl_type)\n+{\n+\treturn ice_sched_set_node_bw_lmt(pi, node, rl_type,\n+\t\t\t\t\t ICE_SCHED_DFLT_BW);\n+}\n+\n+/**\n+ * ice_sched_validate_srl_node - Check node for SRL applicability\n+ * @node: sched node to configure\n+ * @sel_layer: selected SRL layer\n+ *\n+ * This function checks if the SRL can be applied to a selceted layer node on\n+ * behalf of the requested node (first argument). This function needs to be\n+ * called with scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_validate_srl_node(struct ice_sched_node *node, u8 sel_layer)\n+{\n+\t/* SRL profiles are not available on all layers. Check if the\n+\t * SRL profile can be applied to a node above or below the\n+\t * requested node. SRL configuration is possible only if the\n+\t * selected layer's node has single child.\n+\t */\n+\tif (sel_layer == node->tx_sched_layer ||\n+\t    ((sel_layer == node->tx_sched_layer + 1) &&\n+\t    node->num_children == 1) ||\n+\t    ((sel_layer == node->tx_sched_layer - 1) &&\n+\t    (node->parent && node->parent->num_children == 1)))\n+\t\treturn ICE_SUCCESS;\n+\n+\treturn ICE_ERR_CFG;\n+}\n+\n+/**\n+ * ice_sched_set_q_bw_lmt - sets queue bw limit\n+ * @pi: port information structure\n+ * @q_id: queue id (leaf node teid)\n+ * @rl_type: min, max, or shared\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function sets bw limit of queue scheduling node.\n+ */\n+static enum ice_status\n+ice_sched_set_q_bw_lmt(struct ice_port_info *pi, u32 q_id,\n+\t\t       enum ice_rl_type rl_type, u32 bw)\n+{\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_sched_node *node;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\tnode = ice_sched_find_node_by_teid(pi->root, q_id);\n+\tif (!node) {\n+\t\tice_debug(pi->hw, ICE_DBG_SCHED, \"Wrong q_id\\n\");\n+\t\tgoto exit_q_bw_lmt;\n+\t}\n+\n+\t/* Return error if it is not a leaf node */\n+\tif (node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF)\n+\t\tgoto exit_q_bw_lmt;\n+\n+\t/* SRL bandwidth layer selection */\n+\tif (rl_type == ICE_SHARED_BW) {\n+\t\tu8 sel_layer; /* selected layer */\n+\n+\t\tsel_layer = ice_sched_get_rl_prof_layer(pi, rl_type,\n+\t\t\t\t\t\t\tnode->tx_sched_layer);\n+\t\tif (sel_layer >= pi->hw->num_tx_sched_layers) {\n+\t\t\tstatus = ICE_ERR_PARAM;\n+\t\t\tgoto exit_q_bw_lmt;\n+\t\t}\n+\t\tstatus = ice_sched_validate_srl_node(node, sel_layer);\n+\t\tif (status)\n+\t\t\tgoto exit_q_bw_lmt;\n+\t}\n+\n+\tif (bw == ICE_SCHED_DFLT_BW)\n+\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type);\n+\telse\n+\t\tstatus = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw);\n+\n+exit_q_bw_lmt:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_q_bw_lmt - configure queue bw limit\n+ * @pi: port information structure\n+ * @q_id: queue id (leaf node teid)\n+ * @rl_type: min, max, or shared\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function configures bw limit of queue scheduling node.\n+ */\n+enum ice_status\n+ice_cfg_q_bw_lmt(struct ice_port_info *pi, u32 q_id, enum ice_rl_type rl_type,\n+\t\t u32 bw)\n+{\n+\treturn ice_sched_set_q_bw_lmt(pi, q_id, rl_type, bw);\n+}\n+\n+/**\n+ * ice_cfg_q_bw_dflt_lmt - configure queue bw default limit\n+ * @pi: port information structure\n+ * @q_id: queue id (leaf node teid)\n+ * @rl_type: min, max, or shared\n+ *\n+ * This function configures bw default limit of queue scheduling node.\n+ */\n+enum ice_status\n+ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u32 q_id,\n+\t\t      enum ice_rl_type rl_type)\n+{\n+\treturn ice_sched_set_q_bw_lmt(pi, q_id, rl_type, ICE_SCHED_DFLT_BW);\n+}\n+\n+/**\n+ * ice_sched_save_tc_node_bw - save tc node bw limit\n+ * @pi: port information structure\n+ * @tc: tc number\n+ * @rl_type: min or max\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function saves the modified values of bandwidth settings for later\n+ * replay purpose (restore) after reset.\n+ */\n+static enum ice_status\n+ice_sched_save_tc_node_bw(struct ice_port_info *pi, u8 tc,\n+\t\t\t  enum ice_rl_type rl_type, u32 bw)\n+{\n+\tstruct ice_hw *hw = pi->hw;\n+\n+\tif (tc >= ICE_MAX_TRAFFIC_CLASS)\n+\t\treturn ICE_ERR_PARAM;\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tice_set_clear_cir_bw(&hw->tc_node_bw_t_info[tc], bw);\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tice_set_clear_eir_bw(&hw->tc_node_bw_t_info[tc], bw);\n+\t\tbreak;\n+\tcase ICE_SHARED_BW:\n+\t\tice_set_clear_shared_bw(&hw->tc_node_bw_t_info[tc], bw);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_set_tc_node_bw_lmt - sets tc node bw limit\n+ * @pi: port information structure\n+ * @tc: tc number\n+ * @rl_type: min or max\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function configures bandwidth limit of tc node.\n+ */\n+static enum ice_status\n+ice_sched_set_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc,\n+\t\t\t     enum ice_rl_type rl_type, u32 bw)\n+{\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_sched_node *tc_node;\n+\n+\tif (tc >= ICE_MAX_TRAFFIC_CLASS)\n+\t\treturn status;\n+\tice_acquire_lock(&pi->sched_lock);\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\tgoto exit_set_tc_node_bw;\n+\tif (bw == ICE_SCHED_DFLT_BW)\n+\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, tc_node, rl_type);\n+\telse\n+\t\tstatus = ice_sched_set_node_bw_lmt(pi, tc_node, rl_type, bw);\n+\tif (!status)\n+\t\tstatus = ice_sched_save_tc_node_bw(pi, tc, rl_type, bw);\n+\n+exit_set_tc_node_bw:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_tc_node_bw_lmt - configure tc node bw limit\n+ * @pi: port information structure\n+ * @tc: tc number\n+ * @rl_type: min or max\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function configures bw limit of tc node.\n+ * Note: The minimum guaranteed reservation is done via DCBX.\n+ */\n+enum ice_status\n+ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc,\n+\t\t       enum ice_rl_type rl_type, u32 bw)\n+{\n+\treturn ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, bw);\n+}\n+\n+/**\n+ * ice_cfg_tc_node_bw_dflt_lmt - configure tc node bw default limit\n+ * @pi: port information structure\n+ * @tc: tc number\n+ * @rl_type: min or max\n+ *\n+ * This function configures bw default limit of tc node.\n+ */\n+enum ice_status\n+ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc,\n+\t\t\t    enum ice_rl_type rl_type)\n+{\n+\treturn ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, ICE_SCHED_DFLT_BW);\n+}\n+\n+/**\n+ * ice_sched_save_tc_node_bw_alloc - save tc node's bw alloc information\n+ * @pi: port information structure\n+ * @tc: traffic class\n+ * @rl_type: rate limit type min or max\n+ * @bw_alloc: Bandwidth allocation information\n+ *\n+ * Save bw alloc information of VSI type node for post replay use.\n+ */\n+static enum ice_status\n+ice_sched_save_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,\n+\t\t\t\tenum ice_rl_type rl_type, u16 bw_alloc)\n+{\n+\tstruct ice_hw *hw = pi->hw;\n+\n+\tif (tc >= ICE_MAX_TRAFFIC_CLASS)\n+\t\treturn ICE_ERR_PARAM;\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tice_set_clear_cir_bw_alloc(&hw->tc_node_bw_t_info[tc],\n+\t\t\t\t\t   bw_alloc);\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tice_set_clear_eir_bw_alloc(&hw->tc_node_bw_t_info[tc],\n+\t\t\t\t\t   bw_alloc);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_set_tc_node_bw_alloc - set tc node bw alloc\n+ * @pi: port information structure\n+ * @tc: tc number\n+ * @rl_type: min or max\n+ * @bw_alloc: bandwidth alloc\n+ *\n+ * This function configures bandwidth alloc of tc node, also saves the\n+ * changed settings for replay purpose, and return success if it succeeds\n+ * in modifying bandwidth alloc setting.\n+ */\n+static enum ice_status\n+ice_sched_set_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,\n+\t\t\t       enum ice_rl_type rl_type, u8 bw_alloc)\n+{\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_sched_node *tc_node;\n+\n+\tif (tc >= ICE_MAX_TRAFFIC_CLASS)\n+\t\treturn status;\n+\tice_acquire_lock(&pi->sched_lock);\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\tgoto exit_set_tc_node_bw_alloc;\n+\tstatus = ice_sched_cfg_node_bw_alloc(pi->hw, tc_node, rl_type,\n+\t\t\t\t\t     bw_alloc);\n+\tif (status)\n+\t\tgoto exit_set_tc_node_bw_alloc;\n+\tstatus = ice_sched_save_tc_node_bw_alloc(pi, tc, rl_type, bw_alloc);\n+\n+exit_set_tc_node_bw_alloc:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_tc_node_bw_alloc - configure tc node bw alloc\n+ * @pi: port information structure\n+ * @tc: tc number\n+ * @rl_type: min or max\n+ * @bw_alloc: bandwidth alloc\n+ *\n+ * This function configures bw limit of tc node.\n+ * Note: The minimum guaranteed reservation is done via DCBX.\n+ */\n+enum ice_status\n+ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,\n+\t\t\t enum ice_rl_type rl_type, u8 bw_alloc)\n+{\n+\treturn ice_sched_set_tc_node_bw_alloc(pi, tc, rl_type, bw_alloc);\n+}\n+\n+/**\n+ * ice_sched_set_agg_bw_dflt_lmt - set agg node's bw limit to default\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function retrieves the aggregator id based on VSI id and tc,\n+ * and sets node's bw limit to default. This function needs to be\n+ * called with the scheduler lock held.\n+ */\n+enum ice_status\n+ice_sched_set_agg_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle)\n+{\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 tc;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tstruct ice_sched_node *node;\n+\n+\t\tnode = vsi_ctx->sched.ag_node[tc];\n+\t\tif (!node)\n+\t\t\tcontinue;\n+\n+\t\t/* Set min profile to default */\n+\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, node, ICE_MIN_BW);\n+\t\tif (status)\n+\t\t\tbreak;\n+\n+\t\t/* Set max profile to default */\n+\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, node, ICE_MAX_BW);\n+\t\tif (status)\n+\t\t\tbreak;\n+\n+\t\t/* Remove shared profile, if there is one */\n+\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, node,\n+\t\t\t\t\t\t\tICE_SHARED_BW);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_get_node_by_id_type - get node from id type\n+ * @pi: port information structure\n+ * @id: identifier\n+ * @agg_type: type of aggregator\n+ * @tc: traffic class\n+ *\n+ * This function returns node identified by id of type aggregator, and\n+ * based on traffic class (tc). This function needs to be called with\n+ * the scheduler lock held.\n+ */\n+static struct ice_sched_node *\n+ice_sched_get_node_by_id_type(struct ice_port_info *pi, u32 id,\n+\t\t\t      enum ice_agg_type agg_type, u8 tc)\n+{\n+\tstruct ice_sched_node *node = NULL;\n+\tstruct ice_sched_node *child_node;\n+\n+\tswitch (agg_type) {\n+\tcase ICE_AGG_TYPE_VSI: {\n+\t\tstruct ice_vsi_ctx *vsi_ctx;\n+\t\tu16 vsi_handle = (u16)id;\n+\n+\t\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\t\tbreak;\n+\t\t/* Get sched_vsi_info */\n+\t\tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n+\t\tif (!vsi_ctx)\n+\t\t\tbreak;\n+\t\tnode = vsi_ctx->sched.vsi_node[tc];\n+\t\tbreak;\n+\t}\n+\n+\tcase ICE_AGG_TYPE_AGG: {\n+\t\tstruct ice_sched_node *tc_node;\n+\n+\t\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\t\tif (tc_node)\n+\t\t\tnode = ice_sched_get_agg_node(pi->hw, tc_node, id);\n+\t\tbreak;\n+\t}\n+\n+\tcase ICE_AGG_TYPE_Q:\n+\t\t/* The current implementation allows single queue to modify */\n+\t\tnode = ice_sched_get_node(pi, id);\n+\t\tbreak;\n+\n+\tcase ICE_AGG_TYPE_QG:\n+\t\t/* The current implementation allows single qg to modify */\n+\t\tchild_node = ice_sched_get_node(pi, id);\n+\t\tif (!child_node)\n+\t\t\tbreak;\n+\t\tnode = child_node->parent;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn node;\n+}\n+\n+/**\n+ * ice_sched_set_node_bw_lmt_per_tc - set node bw limit per tc\n+ * @pi: port information structure\n+ * @id: id (software VSI handle or AGG id)\n+ * @agg_type: aggregator type (VSI or AGG type node)\n+ * @tc: traffic class\n+ * @rl_type: min or max\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function sets bw limit of VSI or Aggregator scheduling node\n+ * based on tc information from passed in argument bw.\n+ */\n+enum ice_status\n+ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id,\n+\t\t\t\t enum ice_agg_type agg_type, u8 tc,\n+\t\t\t\t enum ice_rl_type rl_type, u32 bw)\n+{\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_sched_node *node;\n+\n+\tif (!pi)\n+\t\treturn status;\n+\n+\tif (rl_type == ICE_UNKNOWN_BW)\n+\t\treturn status;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tnode = ice_sched_get_node_by_id_type(pi, id, agg_type, tc);\n+\tif (!node) {\n+\t\tice_debug(pi->hw, ICE_DBG_SCHED, \"Wrong id, agg type, or tc\\n\");\n+\t\tgoto exit_set_node_bw_lmt_per_tc;\n+\t}\n+\tif (bw == ICE_SCHED_DFLT_BW)\n+\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type);\n+\telse\n+\t\tstatus = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw);\n+\n+exit_set_node_bw_lmt_per_tc:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_validate_vsi_srl_node - validate VSI SRL node\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function validates SRL node of the VSI node if available SRL layer is\n+ * different than the VSI node layer on all tc(s).This function needs to be\n+ * called with scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_validate_vsi_srl_node(struct ice_port_info *pi, u16 vsi_handle)\n+{\n+\tu8 sel_layer = ICE_SCHED_INVAL_LAYER_NUM;\n+\tu8 tc;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Return success if no nodes are present across tc */\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tstruct ice_sched_node *tc_node, *vsi_node;\n+\t\tenum ice_rl_type rl_type = ICE_SHARED_BW;\n+\t\tenum ice_status status;\n+\n+\t\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\t\tif (!tc_node)\n+\t\t\tcontinue;\n+\n+\t\tvsi_node = ice_sched_get_vsi_node(pi->hw, tc_node, vsi_handle);\n+\t\tif (!vsi_node)\n+\t\t\tcontinue;\n+\n+\t\t/* SRL bandwidth layer selection */\n+\t\tif (sel_layer == ICE_SCHED_INVAL_LAYER_NUM) {\n+\t\t\tu8 node_layer = vsi_node->tx_sched_layer;\n+\t\t\tu8 layer_num;\n+\n+\t\t\tlayer_num = ice_sched_get_rl_prof_layer(pi, rl_type,\n+\t\t\t\t\t\t\t\tnode_layer);\n+\t\t\tif (layer_num >= pi->hw->num_tx_sched_layers)\n+\t\t\t\treturn ICE_ERR_PARAM;\n+\t\t\tsel_layer = layer_num;\n+\t\t}\n+\n+\t\tstatus = ice_sched_validate_srl_node(vsi_node, sel_layer);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_set_vsi_bw_shared_lmt - set VSI bw shared limit\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function Configures shared rate limiter(SRL) of all VSI type nodes\n+ * across all traffic classes for VSI matching handle. When bw value of\n+ * ICE_SCHED_DFLT_BW is passed, it removes the SRL from the node.\n+ */\n+enum ice_status\n+ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle,\n+\t\t\t\tu32 bw)\n+{\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 tc;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tstatus = ice_sched_validate_vsi_srl_node(pi, vsi_handle);\n+\tif (status)\n+\t\tgoto exit_set_vsi_bw_shared_lmt;\n+\t/* Return success if no nodes are present across tc */\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tstruct ice_sched_node *tc_node, *vsi_node;\n+\t\tenum ice_rl_type rl_type = ICE_SHARED_BW;\n+\n+\t\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\t\tif (!tc_node)\n+\t\t\tcontinue;\n+\n+\t\tvsi_node = ice_sched_get_vsi_node(pi->hw, tc_node, vsi_handle);\n+\t\tif (!vsi_node)\n+\t\t\tcontinue;\n+\n+\t\tif (bw == ICE_SCHED_DFLT_BW)\n+\t\t\t/* It removes existing SRL from the node */\n+\t\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, vsi_node,\n+\t\t\t\t\t\t\t\trl_type);\n+\t\telse\n+\t\t\tstatus = ice_sched_set_node_bw_lmt(pi, vsi_node,\n+\t\t\t\t\t\t\t   rl_type, bw);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t\tstatus = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\n+exit_set_vsi_bw_shared_lmt:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_validate_agg_srl_node - validate AGG SRL node\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ *\n+ * This function validates SRL node of the AGG node if available SRL layer is\n+ * different than the AGG node layer on all tc(s).This function needs to be\n+ * called with scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_validate_agg_srl_node(struct ice_port_info *pi, u32 agg_id)\n+{\n+\tu8 sel_layer = ICE_SCHED_INVAL_LAYER_NUM;\n+\tstruct ice_sched_agg_info *agg_info;\n+\tbool agg_id_present = false;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 tc;\n+\n+\tLIST_FOR_EACH_ENTRY(agg_info, &pi->hw->agg_list, ice_sched_agg_info,\n+\t\t\t    list_entry)\n+\t\tif (agg_info->agg_id == agg_id) {\n+\t\t\tagg_id_present = true;\n+\t\t\tbreak;\n+\t\t}\n+\tif (!agg_id_present)\n+\t\treturn ICE_ERR_PARAM;\n+\t/* Return success if no nodes are present across tc */\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tstruct ice_sched_node *tc_node, *agg_node;\n+\t\tenum ice_rl_type rl_type = ICE_SHARED_BW;\n+\n+\t\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\t\tif (!tc_node)\n+\t\t\tcontinue;\n+\n+\t\tagg_node = ice_sched_get_agg_node(pi->hw, tc_node, agg_id);\n+\t\tif (!agg_node)\n+\t\t\tcontinue;\n+\t\t/* SRL bandwidth layer selection */\n+\t\tif (sel_layer == ICE_SCHED_INVAL_LAYER_NUM) {\n+\t\t\tu8 node_layer = agg_node->tx_sched_layer;\n+\t\t\tu8 layer_num;\n+\n+\t\t\tlayer_num = ice_sched_get_rl_prof_layer(pi, rl_type,\n+\t\t\t\t\t\t\t\tnode_layer);\n+\t\t\tif (layer_num >= pi->hw->num_tx_sched_layers)\n+\t\t\t\treturn ICE_ERR_PARAM;\n+\t\t\tsel_layer = layer_num;\n+\t\t}\n+\n+\t\tstatus = ice_sched_validate_srl_node(agg_node, sel_layer);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_set_agg_bw_shared_lmt - set aggregator bw shared limit\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @bw: bandwidth in kbps\n+ *\n+ * This function configures the shared rate limiter(SRL) of all agg type\n+ * nodes across all traffic classes for aggregator matching agg_id. When\n+ * bw value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the\n+ * node(s).\n+ */\n+enum ice_status\n+ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\tstruct ice_sched_agg_info *tmp;\n+\tbool agg_id_present = false;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 tc;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tstatus = ice_sched_validate_agg_srl_node(pi, agg_id);\n+\tif (status)\n+\t\tgoto exit_agg_bw_shared_lmt;\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(agg_info, tmp, &pi->hw->agg_list,\n+\t\t\t\t ice_sched_agg_info, list_entry)\n+\t\tif (agg_info->agg_id == agg_id) {\n+\t\t\tagg_id_present = true;\n+\t\t\tbreak;\n+\t\t}\n+\n+\tif (!agg_id_present) {\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto exit_agg_bw_shared_lmt;\n+\t}\n+\n+\t/* Return success if no nodes are present across tc */\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tenum ice_rl_type rl_type = ICE_SHARED_BW;\n+\t\tstruct ice_sched_node *tc_node, *agg_node;\n+\n+\t\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\t\tif (!tc_node)\n+\t\t\tcontinue;\n+\n+\t\tagg_node = ice_sched_get_agg_node(pi->hw, tc_node, agg_id);\n+\t\tif (!agg_node)\n+\t\t\tcontinue;\n+\n+\t\tif (bw == ICE_SCHED_DFLT_BW)\n+\t\t\t/* It removes existing SRL from the node */\n+\t\t\tstatus = ice_sched_set_node_bw_dflt_lmt(pi, agg_node,\n+\t\t\t\t\t\t\t\trl_type);\n+\t\telse\n+\t\t\tstatus = ice_sched_set_node_bw_lmt(pi, agg_node,\n+\t\t\t\t\t\t\t   rl_type, bw);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t\tstatus = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\n+exit_agg_bw_shared_lmt:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_cfg_sibl_node_prio - configure node sibling priority\n+ * @hw: pointer to the hw struct\n+ * @node: sched node to configure\n+ * @priority: sibling priority\n+ *\n+ * This function configures node element's sibling priority only. This\n+ * function needs to be called with scheduler lock held.\n+ */\n+enum ice_status\n+ice_sched_cfg_sibl_node_prio(struct ice_hw *hw, struct ice_sched_node *node,\n+\t\t\t     u8 priority)\n+{\n+\tstruct ice_aqc_txsched_elem_data buf;\n+\tstruct ice_aqc_txsched_elem *data;\n+\tenum ice_status status;\n+\n+\tbuf = node->info;\n+\tdata = &buf.data;\n+\tdata->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC;\n+\tpriority = (priority << ICE_AQC_ELEM_GENERIC_PRIO_S) &\n+\t\t   ICE_AQC_ELEM_GENERIC_PRIO_M;\n+\tdata->generic &= ~ICE_AQC_ELEM_GENERIC_PRIO_M;\n+\tdata->generic |= priority;\n+\n+\t/* Configure element */\n+\tstatus = ice_sched_update_elem(hw, node, &buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_cfg_node_bw_alloc - configure node bw weight/alloc params\n+ * @hw: pointer to the hw struct\n+ * @node: sched node to configure\n+ * @rl_type: rate limit type cir, eir, or shared\n+ * @bw_alloc: bw weight/allocation\n+ *\n+ * This function configures node element's bw allocation.\n+ */\n+enum ice_status\n+ice_sched_cfg_node_bw_alloc(struct ice_hw *hw, struct ice_sched_node *node,\n+\t\t\t    enum ice_rl_type rl_type, u8 bw_alloc)\n+{\n+\tstruct ice_aqc_txsched_elem_data buf;\n+\tstruct ice_aqc_txsched_elem *data;\n+\tenum ice_status status;\n+\n+\tbuf = node->info;\n+\tdata = &buf.data;\n+\tif (rl_type == ICE_MIN_BW) {\n+\t\tdata->valid_sections |= ICE_AQC_ELEM_VALID_CIR;\n+\t\tdata->cir_bw.bw_alloc = CPU_TO_LE16(bw_alloc);\n+\t} else if (rl_type == ICE_MAX_BW) {\n+\t\tdata->valid_sections |= ICE_AQC_ELEM_VALID_EIR;\n+\t\tdata->eir_bw.bw_alloc = CPU_TO_LE16(bw_alloc);\n+\t} else {\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\t/* Configure element */\n+\tstatus = ice_sched_update_elem(hw, node, &buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_add_agg_cfg - create an aggregator node\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @tc: TC number\n+ *\n+ * This function creates an aggregator node and intermediate nodes if required\n+ * for the given TC\n+ */\n+enum ice_status\n+ice_sched_add_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc)\n+{\n+\tstruct ice_sched_node *parent, *agg_node, *tc_node;\n+\tu16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu32 first_node_teid;\n+\tu16 num_nodes_added;\n+\tu8 i, aggl;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tagg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);\n+\t/* Does Agg node already exist ? */\n+\tif (agg_node)\n+\t\treturn status;\n+\n+\taggl = ice_sched_get_agg_layer(hw);\n+\n+\t/* need one node in Agg layer */\n+\tnum_nodes[aggl] = 1;\n+\n+\t/* Check whether the intermediate nodes have space to add the\n+\t * new agg. If they are full, then SW needs to allocate a new\n+\t * intermediate node on those layers\n+\t */\n+\tfor (i = hw->sw_entry_point_layer; i < aggl; i++) {\n+\t\tparent = ice_sched_get_first_node(hw, tc_node, i);\n+\n+\t\t/* scan all the siblings */\n+\t\twhile (parent) {\n+\t\t\tif (parent->num_children < hw->max_children[i])\n+\t\t\t\tbreak;\n+\t\t\tparent = parent->sibling;\n+\t\t}\n+\n+\t\t/* all the nodes are full, reserve one for this layer */\n+\t\tif (!parent)\n+\t\t\tnum_nodes[i]++;\n+\t}\n+\n+\t/* add the agg node */\n+\tparent = tc_node;\n+\tfor (i = hw->sw_entry_point_layer; i <= aggl; i++) {\n+\t\tif (!parent)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\tstatus = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i,\n+\t\t\t\t\t\t      num_nodes[i],\n+\t\t\t\t\t\t      &first_node_teid,\n+\t\t\t\t\t\t      &num_nodes_added);\n+\t\tif (status != ICE_SUCCESS || num_nodes[i] != num_nodes_added)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\t/* The newly added node can be a new parent for the next\n+\t\t * layer nodes\n+\t\t */\n+\t\tif (num_nodes_added) {\n+\t\t\tparent = ice_sched_find_node_by_teid(tc_node,\n+\t\t\t\t\t\t\t     first_node_teid);\n+\t\t\t/* register the aggregator id with the agg node */\n+\t\t\tif (parent && i == aggl)\n+\t\t\t\tparent->agg_id = agg_id;\n+\t\t} else {\n+\t\t\tparent = parent->children[0];\n+\t\t}\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_is_agg_inuse - check whether the agg is in use or not\n+ * @pi: port information structure\n+ * @node: node pointer\n+ *\n+ * This function checks whether the agg is attached with any vsi or not.\n+ */\n+static bool\n+ice_sched_is_agg_inuse(struct ice_port_info *pi, struct ice_sched_node *node)\n+{\n+\tu8 vsil, i;\n+\n+\tvsil = ice_sched_get_vsi_layer(pi->hw);\n+\tif (node->tx_sched_layer < vsil - 1) {\n+\t\tfor (i = 0; i < node->num_children; i++)\n+\t\t\tif (ice_sched_is_agg_inuse(pi, node->children[i]))\n+\t\t\t\treturn true;\n+\t\treturn false;\n+\t} else {\n+\t\treturn node->num_children ? true : false;\n+\t}\n+}\n+\n+/**\n+ * ice_sched_rm_agg_cfg - remove the aggregator node\n+ * @pi: port information structure\n+ * @agg_id: aggregator id\n+ * @tc: TC number\n+ *\n+ * This function removes the aggregator node and intermediate nodes if any\n+ * from the given TC\n+ */\n+enum ice_status\n+ice_sched_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc)\n+{\n+\tstruct ice_sched_node *tc_node, *agg_node;\n+\tstruct ice_hw *hw = pi->hw;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tagg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);\n+\tif (!agg_node)\n+\t\treturn ICE_ERR_DOES_NOT_EXIST;\n+\n+\t/* Can't remove the agg node if it has children */\n+\tif (ice_sched_is_agg_inuse(pi, agg_node))\n+\t\treturn ICE_ERR_IN_USE;\n+\n+\t/* need to remove the whole subtree if agg node is the\n+\t * only child.\n+\t */\n+\twhile (agg_node->tx_sched_layer > hw->sw_entry_point_layer) {\n+\t\tstruct ice_sched_node *parent = agg_node->parent;\n+\n+\t\tif (!parent)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\tif (parent->num_children > 1)\n+\t\t\tbreak;\n+\n+\t\tagg_node = parent;\n+\t}\n+\n+\tice_free_sched_node(pi, agg_node);\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_get_free_vsi_parent - Find a free parent node in agg subtree\n+ * @hw: pointer to the hw struct\n+ * @node: pointer to a child node\n+ * @num_nodes: num nodes count array\n+ *\n+ * This function walks through the aggregator subtree to find a free parent\n+ * node\n+ */\n+static struct ice_sched_node *\n+ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node,\n+\t\t\t      u16 *num_nodes)\n+{\n+\tu8 l = node->tx_sched_layer;\n+\tu8 vsil, i;\n+\n+\tvsil = ice_sched_get_vsi_layer(hw);\n+\n+\t/* Is it VSI parent layer ? */\n+\tif (l == vsil - 1)\n+\t\treturn (node->num_children < hw->max_children[l]) ? node : NULL;\n+\n+\t/* We have intermediate nodes. Let's walk through the subtree. If the\n+\t * intermediate node has space to add a new node then clear the count\n+\t */\n+\tif (node->num_children < hw->max_children[l])\n+\t\tnum_nodes[l] = 0;\n+\t/* The below recursive call is intentional and wouldn't go more than\n+\t * 2 or 3 iterations.\n+\t */\n+\n+\tfor (i = 0; i < node->num_children; i++) {\n+\t\tstruct ice_sched_node *parent;\n+\n+\t\tparent = ice_sched_get_free_vsi_parent(hw, node->children[i],\n+\t\t\t\t\t\t       num_nodes);\n+\t\tif (parent)\n+\t\t\treturn parent;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_sched_update_new_parent - update the new parent in SW DB\n+ * @new_parent: pointer to a new parent node\n+ * @node: pointer to a child node\n+ *\n+ * This function removes the child from the old parent and adds it to a new\n+ * parent\n+ */\n+static void\n+ice_sched_update_parent(struct ice_sched_node *new_parent,\n+\t\t\tstruct ice_sched_node *node)\n+{\n+\tstruct ice_sched_node *old_parent;\n+\tu8 i, j;\n+\n+\told_parent = node->parent;\n+\n+\t/* update the old parent children */\n+\tfor (i = 0; i < old_parent->num_children; i++)\n+\t\tif (old_parent->children[i] == node) {\n+\t\t\tfor (j = i + 1; j < old_parent->num_children; j++)\n+\t\t\t\told_parent->children[j - 1] =\n+\t\t\t\t\told_parent->children[j];\n+\t\t\told_parent->num_children--;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t/* now move the node to a new parent */\n+\tnew_parent->children[new_parent->num_children++] = node;\n+\tnode->parent = new_parent;\n+\tnode->info.parent_teid = new_parent->info.node_teid;\n+}\n+\n+/**\n+ * ice_sched_move_nodes - move child nodes to a given parent\n+ * @pi: port information structure\n+ * @parent: pointer to parent node\n+ * @num_items: number of child nodes to be moved\n+ * @list: pointer to child node teids\n+ *\n+ * This function move the child nodes to a given parent.\n+ */\n+static enum ice_status\n+ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent,\n+\t\t     u16 num_items, u32 *list)\n+{\n+\tstruct ice_aqc_move_elem *buf;\n+\tstruct ice_sched_node *node;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw;\n+\tu16 grps_movd = 0;\n+\tu8 i;\n+\n+\thw = pi->hw;\n+\n+\tif (!parent || !num_items)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Does parent have enough space */\n+\tif (parent->num_children + num_items >=\n+\t    hw->max_children[parent->tx_sched_layer])\n+\t\treturn ICE_ERR_AQ_FULL;\n+\n+\tbuf = (struct ice_aqc_move_elem *) ice_malloc(hw, sizeof(*buf));\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tfor (i = 0; i < num_items; i++) {\n+\t\tnode = ice_sched_find_node_by_teid(pi->root, list[i]);\n+\t\tif (!node) {\n+\t\t\tstatus = ICE_ERR_PARAM;\n+\t\t\tgoto move_err_exit;\n+\t\t}\n+\n+\t\tbuf->hdr.src_parent_teid = node->info.parent_teid;\n+\t\tbuf->hdr.dest_parent_teid = parent->info.node_teid;\n+\t\tbuf->teid[0] = node->info.node_teid;\n+\t\tbuf->hdr.num_elems = CPU_TO_LE16(1);\n+\t\tstatus = ice_aq_move_sched_elems(hw, 1, buf, sizeof(*buf),\n+\t\t\t\t\t\t &grps_movd, NULL);\n+\t\tif (status && grps_movd != 1) {\n+\t\t\tstatus = ICE_ERR_CFG;\n+\t\t\tgoto move_err_exit;\n+\t\t}\n+\n+\t\t/* update the SW DB */\n+\t\tice_sched_update_parent(parent, node);\n+\t}\n+\n+move_err_exit:\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_move_vsi_to_agg - move VSI to aggregator node\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @agg_id: aggregator id\n+ * @tc: TC number\n+ *\n+ * This function moves a VSI to an aggregator node or its subtree.\n+ * Intermediate nodes may be created if required.\n+ */\n+enum ice_status\n+ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 vsi_handle, u32 agg_id,\n+\t\t\t  u8 tc)\n+{\n+\tstruct ice_sched_node *vsi_node, *agg_node, *tc_node, *parent;\n+\tu16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };\n+\tu32 first_node_teid, vsi_teid;\n+\tenum ice_status status;\n+\tu16 num_nodes_added;\n+\tu8 aggl, vsil, i;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tagg_node = ice_sched_get_agg_node(pi->hw, tc_node, agg_id);\n+\tif (!agg_node)\n+\t\treturn ICE_ERR_DOES_NOT_EXIST;\n+\n+\tvsi_node = ice_sched_get_vsi_node(pi->hw, tc_node, vsi_handle);\n+\tif (!vsi_node)\n+\t\treturn ICE_ERR_DOES_NOT_EXIST;\n+\n+\taggl = ice_sched_get_agg_layer(pi->hw);\n+\tvsil = ice_sched_get_vsi_layer(pi->hw);\n+\n+\t/* initialize intermediate node count to 1 between agg and VSI layers */\n+\tfor (i = aggl + 1; i < vsil; i++)\n+\t\tnum_nodes[i] = 1;\n+\n+\t/* Check whether the agg subtree has any free node to add the VSI */\n+\tfor (i = 0; i < agg_node->num_children; i++) {\n+\t\tparent = ice_sched_get_free_vsi_parent(pi->hw,\n+\t\t\t\t\t\t       agg_node->children[i],\n+\t\t\t\t\t\t       num_nodes);\n+\t\tif (parent)\n+\t\t\tgoto move_nodes;\n+\t}\n+\n+\t/* add new nodes */\n+\tparent = agg_node;\n+\tfor (i = aggl + 1; i < vsil; i++) {\n+\t\tstatus = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i,\n+\t\t\t\t\t\t      num_nodes[i],\n+\t\t\t\t\t\t      &first_node_teid,\n+\t\t\t\t\t\t      &num_nodes_added);\n+\t\tif (status != ICE_SUCCESS || num_nodes[i] != num_nodes_added)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\t/* The newly added node can be a new parent for the next\n+\t\t * layer nodes\n+\t\t */\n+\t\tif (num_nodes_added)\n+\t\t\tparent = ice_sched_find_node_by_teid(tc_node,\n+\t\t\t\t\t\t\t     first_node_teid);\n+\t\telse\n+\t\t\tparent = parent->children[0];\n+\n+\t\tif (!parent)\n+\t\t\treturn ICE_ERR_CFG;\n+\t}\n+\n+move_nodes:\n+\tvsi_teid = LE32_TO_CPU(vsi_node->info.node_teid);\n+\treturn ice_sched_move_nodes(pi, parent, 1, &vsi_teid);\n+}\n+\n+/**\n+ * ice_cfg_rl_burst_size - Set burst size value\n+ * @hw: pointer to the hw struct\n+ * @bytes: burst size in bytes\n+ *\n+ * This function configures/set the burst size to requested new value. The new\n+ * burst size value is used for future rate limit calls. It doesn't change the\n+ * existing or previously created RL profiles.\n+ */\n+enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes)\n+{\n+\tu16 burst_size_to_prog;\n+\n+\tif (bytes < ICE_MIN_BURST_SIZE_ALLOWED ||\n+\t    bytes > ICE_MAX_BURST_SIZE_ALLOWED)\n+\t\treturn ICE_ERR_PARAM;\n+\tif (bytes <= ICE_MAX_BURST_SIZE_BYTE_GRANULARITY) {\n+\t\t/* byte granularity case */\n+\t\t/* Disable MSB granularity bit */\n+\t\tburst_size_to_prog = ICE_BYTE_GRANULARITY;\n+\t\t/* round number to nearest 256 granularity */\n+\t\tbytes = ice_round_to_num(bytes, 256);\n+\t\t/* check rounding doesn't go beyound allowed */\n+\t\tif (bytes > ICE_MAX_BURST_SIZE_BYTE_GRANULARITY)\n+\t\t\tbytes = ICE_MAX_BURST_SIZE_BYTE_GRANULARITY;\n+\t\tburst_size_to_prog |= (u16)bytes;\n+\t} else {\n+\t\t/* k bytes granularity case */\n+\t\t/* Enable MSB granularity bit */\n+\t\tburst_size_to_prog = ICE_KBYTE_GRANULARITY;\n+\t\t/* round number to nearest 1024 granularity */\n+\t\tbytes = ice_round_to_num(bytes, 1024);\n+\t\t/* check rounding doesn't go beyound allowed */\n+\t\tif (bytes > ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY)\n+\t\t\tbytes = ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY;\n+\t\t/* The value is in k bytes */\n+\t\tburst_size_to_prog |= (u16)(bytes / 1024);\n+\t}\n+\thw->max_burst_size = burst_size_to_prog;\n+\treturn ICE_SUCCESS;\n+}\n+\n+/*\n+ * ice_sched_replay_node_prio - re-configure node priority\n+ * @hw: pointer to the hw struct\n+ * @node: sched node to configure\n+ * @priority: priority value\n+ *\n+ * This function configures node element's priority value. It\n+ * needs to be called with scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_replay_node_prio(struct ice_hw *hw, struct ice_sched_node *node,\n+\t\t\t   u8 priority)\n+{\n+\tstruct ice_aqc_txsched_elem_data buf;\n+\tstruct ice_aqc_txsched_elem *data;\n+\tenum ice_status status;\n+\n+\tbuf = node->info;\n+\tdata = &buf.data;\n+\tdata->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC;\n+\tdata->generic = priority;\n+\n+\t/* Configure element */\n+\tstatus = ice_sched_update_elem(hw, node, &buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_replay_node_bw - replay node(s) bw\n+ * @hw: pointer to the hw struct\n+ * @node: sched node to configure\n+ * @bw_t_info: bw type information\n+ *\n+ * This function restores node's bw from bw_t_info. The caller needs\n+ * to hold the scheduler lock.\n+ */\n+static enum ice_status\n+ice_sched_replay_node_bw(struct ice_hw *hw, struct ice_sched_node *node,\n+\t\t\t struct ice_bw_type_info *bw_t_info)\n+{\n+\tstruct ice_port_info *pi = hw->port_info;\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tu16 bw_alloc;\n+\n+\tif (!node)\n+\t\treturn status;\n+\tif (!ice_is_any_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CNT))\n+\t\treturn ICE_SUCCESS;\n+\tif (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_PRIO)) {\n+\t\tstatus = ice_sched_replay_node_prio(hw, node,\n+\t\t\t\t\t\t    bw_t_info->generic);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\tif (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CIR)) {\n+\t\tstatus = ice_sched_set_node_bw_lmt(pi, node, ICE_MIN_BW,\n+\t\t\t\t\t\t   bw_t_info->cir_bw.bw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\tif (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CIR_WT)) {\n+\t\tbw_alloc = bw_t_info->cir_bw.bw_alloc;\n+\t\tstatus = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MIN_BW,\n+\t\t\t\t\t\t     bw_alloc);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\tif (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_EIR)) {\n+\t\tstatus = ice_sched_set_node_bw_lmt(pi, node, ICE_MAX_BW,\n+\t\t\t\t\t\t   bw_t_info->eir_bw.bw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\tif (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_EIR_WT)) {\n+\t\tbw_alloc = bw_t_info->eir_bw.bw_alloc;\n+\t\tstatus = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MAX_BW,\n+\t\t\t\t\t\t     bw_alloc);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\tif (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_SHARED))\n+\t\tstatus = ice_sched_set_node_bw_lmt(pi, node, ICE_SHARED_BW,\n+\t\t\t\t\t\t   bw_t_info->shared_bw);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_replay_agg_bw - replay aggregator node(s) bw\n+ * @hw: pointer to the hw struct\n+ * @agg_info: aggregator data structure\n+ *\n+ * This function re-creates aggregator type nodes. The caller needs to hold\n+ * the scheduler lock.\n+ */\n+static enum ice_status\n+ice_sched_replay_agg_bw(struct ice_hw *hw, struct ice_sched_agg_info *agg_info)\n+{\n+\tstruct ice_sched_node *tc_node, *agg_node;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 tc;\n+\n+\tif (!agg_info)\n+\t\treturn ICE_ERR_PARAM;\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tif (!ice_is_any_bit_set(agg_info->bw_t_info[tc].bw_t_bitmap,\n+\t\t\t\t\tICE_BW_TYPE_CNT))\n+\t\t\tcontinue;\n+\t\ttc_node = ice_sched_get_tc_node(hw->port_info, tc);\n+\t\tif (!tc_node) {\n+\t\t\tstatus = ICE_ERR_PARAM;\n+\t\t\tbreak;\n+\t\t}\n+\t\tagg_node = ice_sched_get_agg_node(hw, tc_node,\n+\t\t\t\t\t\t  agg_info->agg_id);\n+\t\tif (!agg_node) {\n+\t\t\tstatus = ICE_ERR_PARAM;\n+\t\t\tbreak;\n+\t\t}\n+\t\tstatus = ice_sched_replay_node_bw(hw, agg_node,\n+\t\t\t\t\t\t  &agg_info->bw_t_info[tc]);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_get_ena_tc_bitmap - get enabled TC bitmap\n+ * @pi: port info struct\n+ * @tc_bitmap: 8 bits TC bitmap to check\n+ * @ena_tc_bitmap: 8 bits enabled TC bitmap to return\n+ *\n+ * This function returns enabled TC bitmap in variable ena_tc_bitmap. Some TCs\n+ * may be missing, it returns enabled TCs. This function needs to be called with\n+ * scheduler lock held.\n+ */\n+static void\n+ice_sched_get_ena_tc_bitmap(struct ice_port_info *pi, ice_bitmap_t *tc_bitmap,\n+\t\t\t    ice_bitmap_t *ena_tc_bitmap)\n+{\n+\tu8 tc;\n+\n+\t/* Some tc(s) may be missing after reset, adjust for replay */\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++)\n+\t\tif (ice_is_tc_ena(*tc_bitmap, tc) &&\n+\t\t    (ice_sched_get_tc_node(pi, tc)))\n+\t\t\tice_set_bit(tc, ena_tc_bitmap);\n+}\n+\n+/**\n+ * ice_sched_replay_agg - recreate aggregator node(s)\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function recreate aggregator type nodes which are not replayed earlier.\n+ * It also replay aggregator bw information. These aggregator nodes are not\n+ * associated with VSI type node yet.\n+ */\n+void ice_sched_replay_agg(struct ice_hw *hw)\n+{\n+\tstruct ice_port_info *pi = hw->port_info;\n+\tstruct ice_sched_agg_info *agg_info;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tLIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,\n+\t\t\t    list_entry) {\n+\t\t/* replay agg (re-create aggregator node) */\n+\t\tif (!ice_cmp_bitmap(agg_info->tc_bitmap,\n+\t\t\t\t    agg_info->replay_tc_bitmap,\n+\t\t\t\t    ICE_MAX_TRAFFIC_CLASS)) {\n+\t\t\tice_declare_bitmap(replay_bitmap,\n+\t\t\t\t\t   ICE_MAX_TRAFFIC_CLASS);\n+\t\t\tenum ice_status status;\n+\n+\t\t\tice_zero_bitmap(replay_bitmap,\n+\t\t\t\t\tsizeof(replay_bitmap) * BITS_PER_BYTE);\n+\t\t\tice_sched_get_ena_tc_bitmap(pi,\n+\t\t\t\t\t\t    agg_info->replay_tc_bitmap,\n+\t\t\t\t\t\t    replay_bitmap);\n+\t\t\tstatus = ice_sched_cfg_agg(hw->port_info,\n+\t\t\t\t\t\t   agg_info->agg_id,\n+\t\t\t\t\t\t   ICE_AGG_TYPE_AGG,\n+\t\t\t\t\t\t   replay_bitmap);\n+\t\t\tif (status) {\n+\t\t\t\tice_info(hw, \"Replay agg id[%d] failed\\n\",\n+\t\t\t\t\t agg_info->agg_id);\n+\t\t\t\t/* Move on to next one */\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\t/* Replay agg node bw (restore agg bw) */\n+\t\t\tstatus = ice_sched_replay_agg_bw(hw, agg_info);\n+\t\t\tif (status)\n+\t\t\t\tice_info(hw, \"Replay agg bw [id=%d] failed\\n\",\n+\t\t\t\t\t agg_info->agg_id);\n+\t\t}\n+\t}\n+\tice_release_lock(&pi->sched_lock);\n+}\n+\n+/**\n+ * ice_sched_replay_agg_vsi_preinit - Agg/VSI replay pre initialization\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function initialize aggregator(s) TC bitmap to zero. A required\n+ * preinit step for replaying aggregators.\n+ */\n+void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw)\n+{\n+\tstruct ice_port_info *pi = hw->port_info;\n+\tstruct ice_sched_agg_info *agg_info;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tLIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,\n+\t\t\t    list_entry) {\n+\t\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\n+\t\tagg_info->tc_bitmap[0] = 0;\n+\t\tLIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list,\n+\t\t\t\t    ice_sched_agg_vsi_info, list_entry)\n+\t\t\tagg_vsi_info->tc_bitmap[0] = 0;\n+\t}\n+\tice_release_lock(&pi->sched_lock);\n+}\n+\n+/**\n+ * ice_sched_replay_tc_node_bw - replay tc node(s) bw\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function replay tc nodes. The caller needs to hold the scheduler lock.\n+ */\n+enum ice_status\n+ice_sched_replay_tc_node_bw(struct ice_hw *hw)\n+{\n+\tstruct ice_port_info *pi = hw->port_info;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 tc;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tstruct ice_sched_node *tc_node;\n+\n+\t\ttc_node = ice_sched_get_tc_node(hw->port_info, tc);\n+\t\tif (!tc_node)\n+\t\t\tcontinue; /* tc not present */\n+\t\tstatus = ice_sched_replay_node_bw(hw, tc_node,\n+\t\t\t\t\t\t  &hw->tc_node_bw_t_info[tc]);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_replay_vsi_bw - replay VSI type node(s) bw\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: software VSI handle\n+ * @tc_bitmap: 8 bits TC bitmap\n+ *\n+ * This function replays VSI type nodes bandwidth. This function needs to be\n+ * called with scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_replay_vsi_bw(struct ice_hw *hw, u16 vsi_handle,\n+\t\t\tice_bitmap_t *tc_bitmap)\n+{\n+\tstruct ice_sched_node *vsi_node, *tc_node;\n+\tstruct ice_port_info *pi = hw->port_info;\n+\tstruct ice_bw_type_info *bw_t_info;\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 tc;\n+\n+\tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn ICE_ERR_PARAM;\n+\tfor (tc = 0; tc < ICE_MAX_TRAFFIC_CLASS; tc++) {\n+\t\tif (!ice_is_tc_ena(*tc_bitmap, tc))\n+\t\t\tcontinue;\n+\t\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\t\tif (!tc_node)\n+\t\t\tcontinue;\n+\t\tvsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);\n+\t\tif (!vsi_node)\n+\t\t\tcontinue;\n+\t\tbw_t_info = &vsi_ctx->sched.bw_t_info[tc];\n+\t\tstatus = ice_sched_replay_node_bw(hw, vsi_node, bw_t_info);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_replay_vsi_agg - replay agg & VSI to aggregator node(s)\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function replays aggregator node, VSI to aggregator type nodes, and\n+ * their node bandwidth information. This function needs to be called with\n+ * scheduler lock held.\n+ */\n+static enum ice_status\n+ice_sched_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\tice_declare_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS);\n+\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\tstruct ice_port_info *pi = hw->port_info;\n+\tstruct ice_sched_agg_info *agg_info;\n+\tenum ice_status status;\n+\n+\tice_zero_bitmap(replay_bitmap, sizeof(replay_bitmap) * BITS_PER_BYTE);\n+\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\tagg_info = ice_get_vsi_agg_info(hw, vsi_handle);\n+\tif (!agg_info)\n+\t\treturn ICE_SUCCESS; /* Not present in list - default Agg case */\n+\tagg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle);\n+\tif (!agg_vsi_info)\n+\t\treturn ICE_SUCCESS; /* Not present in list - default Agg case */\n+\tice_sched_get_ena_tc_bitmap(pi, agg_info->replay_tc_bitmap,\n+\t\t\t\t    replay_bitmap);\n+\t/* Replay agg node associated to vsi_handle */\n+\tstatus = ice_sched_cfg_agg(hw->port_info, agg_info->agg_id,\n+\t\t\t\t   ICE_AGG_TYPE_AGG, replay_bitmap);\n+\tif (status)\n+\t\treturn status;\n+\t/* Replay agg node bw (restore agg bw) */\n+\tstatus = ice_sched_replay_agg_bw(hw, agg_info);\n+\tif (status)\n+\t\treturn status;\n+\n+\tice_zero_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS);\n+\tice_sched_get_ena_tc_bitmap(pi, agg_vsi_info->replay_tc_bitmap,\n+\t\t\t\t    replay_bitmap);\n+\t/* Move this VSI (vsi_handle) to above aggregator */\n+\tstatus = ice_sched_assoc_vsi_to_agg(pi, agg_info->agg_id, vsi_handle,\n+\t\t\t\t\t    replay_bitmap);\n+\tif (status)\n+\t\treturn status;\n+\t/* Replay VSI bw (restore VSI bw) */\n+\treturn ice_sched_replay_vsi_bw(hw, vsi_handle,\n+\t\t\t\t       agg_vsi_info->tc_bitmap);\n+}\n+\n+/**\n+ * ice_replay_vsi_agg - replay VSI to aggregator node\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function replays association of VSI to aggregator type nodes, and\n+ * node bandwidth information.\n+ */\n+enum ice_status\n+ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\tstruct ice_port_info *pi = hw->port_info;\n+\tenum ice_status status;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tstatus = ice_sched_replay_vsi_agg(hw, vsi_handle);\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\ndiff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h\nnew file mode 100644\nindex 0000000..a556594\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_sched.h\n@@ -0,0 +1,210 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_SCHED_H_\n+#define _ICE_SCHED_H_\n+\n+#include \"ice_common.h\"\n+\n+#define ICE_QGRP_LAYER_OFFSET\t2\n+#define ICE_VSI_LAYER_OFFSET\t4\n+#define ICE_AGG_LAYER_OFFSET\t6\n+#define ICE_SCHED_INVAL_LAYER_NUM\t0xFF\n+/* Burst size is a 12 bits register that is configured while creating the RL\n+ * profile(s). MSB is a granularity bit and tells the granularity type\n+ * 0 - LSB bits are in bytes granularity\n+ * 1 - LSB bits are in 1K bytes granularity\n+ */\n+#define ICE_BYTE_GRANULARITY\t\t\t0\n+#define ICE_KBYTE_GRANULARITY\t\t\t0x800\n+#define ICE_MIN_BURST_SIZE_ALLOWED\t\t1 /* In Bytes */\n+#define ICE_MAX_BURST_SIZE_ALLOWED\t\t(2047 * 1024) /* In Bytes */\n+#define ICE_MAX_BURST_SIZE_BYTE_GRANULARITY\t2047 /* In Bytes */\n+#define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY\tICE_MAX_BURST_SIZE_ALLOWED\n+\n+#define ICE_RL_PROF_FREQUENCY 446000000\n+#define ICE_RL_PROF_ACCURACY_BYTES 128\n+#define ICE_RL_PROF_MULTIPLIER 10000\n+#define ICE_RL_PROF_TS_MULTIPLIER 32\n+#define ICE_RL_PROF_FRACTION 512\n+\n+struct rl_profile_params {\n+\tu32 bw;\t\t\t/* in Kbps */\n+\tu16 rl_multiplier;\n+\tu16 wake_up_calc;\n+\tu16 rl_encode;\n+};\n+\n+/* BW rate limit profile parameters list entry along\n+ * with bandwidth maintained per layer in port info\n+ */\n+struct ice_aqc_rl_profile_info {\n+\tstruct ice_aqc_rl_profile_elem profile;\n+\tstruct LIST_ENTRY_TYPE list_entry;\n+\tu32 bw;\t\t\t/* requested */\n+\tu16 prof_id_ref;\t/* profile id to node association ref count */\n+};\n+\n+struct ice_sched_agg_vsi_info {\n+\tstruct LIST_ENTRY_TYPE list_entry;\n+\tice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);\n+\tu16 vsi_handle;\n+\t/* save agg vsi TC bitmap */\n+\tice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);\n+};\n+\n+struct ice_sched_agg_info {\n+\tstruct LIST_HEAD_TYPE agg_vsi_list;\n+\tstruct LIST_ENTRY_TYPE list_entry;\n+\tice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);\n+\tu32 agg_id;\n+\tenum ice_agg_type agg_type;\n+\t/* bw_t_info saves agg bw information */\n+\tstruct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];\n+\t/* save agg TC bitmap */\n+\tice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);\n+};\n+\n+/* FW AQ command calls */\n+enum ice_status\n+ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles,\n+\t\t\tstruct ice_aqc_rl_profile_generic_elem *buf,\n+\t\t\tu16 buf_size, struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_nodes,\n+\t\t       struct ice_aqc_cfg_l2_node_cgd_data *buf, u16 buf_size,\n+\t\t       struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req,\n+\t\t\tstruct ice_aqc_move_elem *buf, u16 buf_size,\n+\t\t\tu16 *grps_movd, struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,\n+\t\t\t struct ice_aqc_get_elem *buf, u16 buf_size,\n+\t\t\t u16 *elems_ret, struct ice_sq_cd *cd);\n+enum ice_status ice_sched_init_port(struct ice_port_info *pi);\n+enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw);\n+\n+/* Functions to cleanup scheduler SW DB */\n+void ice_sched_clear_port(struct ice_port_info *pi);\n+void ice_sched_cleanup_all(struct ice_hw *hw);\n+void ice_sched_clear_agg(struct ice_hw *hw);\n+\n+/* Get a scheduling node from SW DB for given TEID */\n+struct ice_sched_node *ice_sched_get_node(struct ice_port_info *pi, u32 teid);\n+struct ice_sched_node *\n+ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid);\n+/* Add a scheduling node into SW DB for given info */\n+enum ice_status\n+ice_sched_add_node(struct ice_port_info *pi, u8 layer,\n+\t\t   struct ice_aqc_txsched_elem_data *info);\n+void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node);\n+struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc);\n+struct ice_sched_node *\n+ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t\t   u8 owner);\n+enum ice_status\n+ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,\n+\t\t  u8 owner, bool enable);\n+enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle);\n+struct ice_sched_node *\n+ice_sched_get_agg_node(struct ice_hw *hw, struct ice_sched_node *tc_node,\n+\t\t       u32 agg_id);\n+struct ice_sched_node *\n+ice_sched_get_vsi_node(struct ice_hw *hw, struct ice_sched_node *tc_node,\n+\t\t       u16 vsi_handle);\n+bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node);\n+enum ice_status\n+ice_aq_query_node_to_root(struct ice_hw *hw, u32 node_teid,\n+\t\t\t  struct ice_aqc_get_elem *buf, u16 buf_size,\n+\t\t\t  struct ice_sq_cd *cd);\n+\n+/* Tx scheduler rate limiter functions */\n+enum ice_status\n+ice_cfg_agg(struct ice_port_info *pi, u32 agg_id,\n+\t    enum ice_agg_type agg_type, u8 tc_bitmap);\n+enum ice_status\n+ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle,\n+\t\t    u8 tc_bitmap);\n+enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id);\n+enum ice_status\n+ice_cfg_q_bw_lmt(struct ice_port_info *pi, u32 q_id, enum ice_rl_type rl_type,\n+\t\t u32 bw);\n+enum ice_status\n+ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u32 q_id,\n+\t\t      enum ice_rl_type rl_type);\n+enum ice_status\n+ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc,\n+\t\t       enum ice_rl_type rl_type, u32 bw);\n+enum ice_status\n+ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc,\n+\t\t\t    enum ice_rl_type rl_type);\n+enum ice_status\n+ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t\t  enum ice_rl_type rl_type, u32 bw);\n+enum ice_status\n+ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t\t       enum ice_rl_type rl_type);\n+enum ice_status\n+ice_cfg_agg_bw_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,\n+\t\t\t  enum ice_rl_type rl_type, u32 bw);\n+enum ice_status\n+ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc,\n+\t\t\t       enum ice_rl_type rl_type);\n+enum ice_status\n+ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 bw);\n+enum ice_status\n+ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle);\n+enum ice_status\n+ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw);\n+enum ice_status\n+ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id);\n+enum ice_status\n+ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,\n+\t\t       u8 *q_prio);\n+enum ice_status\n+ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap,\n+\t\t     enum ice_rl_type rl_type, u8 *bw_alloc);\n+enum ice_status\n+ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id,\n+\t\t\t\tu16 num_vsis, u16 *vsi_handle_arr,\n+\t\t\t\tu8 *node_prio, u8 tc);\n+enum ice_status\n+ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap,\n+\t\t     enum ice_rl_type rl_type, u8 *bw_alloc);\n+bool\n+ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base,\n+\t\t\t       struct ice_sched_node *node);\n+enum ice_status\n+ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,\n+\t\t\t  enum ice_rl_type rl_type, u32 bw);\n+enum ice_status\n+ice_sched_set_agg_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle);\n+enum ice_status\n+ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id,\n+\t\t\t\t enum ice_agg_type agg_type, u8 tc,\n+\t\t\t\t enum ice_rl_type rl_type, u32 bw);\n+enum ice_status\n+ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle,\n+\t\t\t\tu32 bw);\n+enum ice_status\n+ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw);\n+enum ice_status\n+ice_sched_cfg_sibl_node_prio(struct ice_hw *hw, struct ice_sched_node *node,\n+\t\t\t     u8 priority);\n+enum ice_status\n+ice_sched_cfg_node_bw_alloc(struct ice_hw *hw, struct ice_sched_node *node,\n+\t\t\t    enum ice_rl_type rl_type, u8 bw_alloc);\n+enum ice_status\n+ice_sched_add_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc);\n+enum ice_status\n+ice_sched_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc);\n+enum ice_status\n+ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 vsi_handle, u32 agg_id,\n+\t\t\t  u8 tc);\n+enum ice_status\n+ice_sched_del_rl_profile(struct ice_hw *hw,\n+\t\t\t struct ice_aqc_rl_profile_info *rl_info);\n+void ice_sched_rm_unused_rl_prof(struct ice_port_info *pi);\n+#endif /* _ICE_SCHED_H_ */\n",
    "prefixes": [
        "v5",
        "07/31"
    ]
}