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GET /api/patches/48971/?format=api
{ "id": 48971, "url": "https://patches.dpdk.org/api/patches/48971/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-4-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1545032259-77179-4-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1545032259-77179-4-git-send-email-wenzhuo.lu@intel.com", "date": "2018-12-17T07:37:11", "name": "[v5,03/31] net/ice/base: add admin queue structures and commands", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "25156e6ec680384b8686e2eec169d8d59f94bf5b", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-4-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 2824, "url": "https://patches.dpdk.org/api/series/2824/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2824", "date": "2018-12-17T07:37:08", "name": "A new net PMD - ICE", "version": 5, "mbox": "https://patches.dpdk.org/series/2824/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/48971/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/48971/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F38631B5A1;\n\tMon, 17 Dec 2018 08:33:00 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id D6FF81B57F\n\tfor <dev@dpdk.org>; Mon, 17 Dec 2018 08:32:58 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Dec 2018 23:32:57 -0800", "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby orsmga002.jf.intel.com with ESMTP; 16 Dec 2018 23:32:57 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,364,1539673200\"; d=\"scan'208\";a=\"118899076\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 17 Dec 2018 15:37:11 +0800", "Message-Id": "<1545032259-77179-4-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 03/31] net/ice/base: add admin queue\n\tstructures and commands", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n\nAdd the commands, error codes, and structures for\nthe admin queue.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 1891 +++++++++++++++++++++++++++++++++\n 1 file changed, 1891 insertions(+)\n create mode 100644 drivers/net/ice/base/ice_adminq_cmd.h", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nnew file mode 100644\nindex 0000000..9332f84\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -0,0 +1,1891 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_ADMINQ_CMD_H_\n+#define _ICE_ADMINQ_CMD_H_\n+\n+/* This header file defines the Admin Queue commands, error codes and\n+ * descriptor format. It is shared between Firmware and Software.\n+ */\n+\n+\n+#define ICE_MAX_VSI\t\t\t768\n+#define ICE_AQC_TOPO_MAX_LEVEL_NUM\t0x9\n+#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX\t9728\n+\n+\n+struct ice_aqc_generic {\n+\t__le32 param0;\n+\t__le32 param1;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Get version (direct 0x0001) */\n+struct ice_aqc_get_ver {\n+\t__le32 rom_ver;\n+\t__le32 fw_build;\n+\tu8 fw_branch;\n+\tu8 fw_major;\n+\tu8 fw_minor;\n+\tu8 fw_patch;\n+\tu8 api_branch;\n+\tu8 api_major;\n+\tu8 api_minor;\n+\tu8 api_patch;\n+};\n+\n+\n+\n+/* Queue Shutdown (direct 0x0003) */\n+struct ice_aqc_q_shutdown {\n+\t__le32 driver_unloading;\n+#define ICE_AQC_DRIVER_UNLOADING\tBIT(0)\n+\tu8 reserved[12];\n+};\n+\n+\n+\n+\n+/* Request resource ownership (direct 0x0008)\n+ * Release resource ownership (direct 0x0009)\n+ */\n+struct ice_aqc_req_res {\n+\t__le16 res_id;\n+#define ICE_AQC_RES_ID_NVM\t\t1\n+#define ICE_AQC_RES_ID_SDP\t\t2\n+#define ICE_AQC_RES_ID_CHNG_LOCK\t3\n+#define ICE_AQC_RES_ID_GLBL_LOCK\t4\n+\t__le16 access_type;\n+#define ICE_AQC_RES_ACCESS_READ\t\t1\n+#define ICE_AQC_RES_ACCESS_WRITE\t2\n+\n+\t/* Upon successful completion, FW writes this value and driver is\n+\t * expected to release resource before timeout. This value is provided\n+\t * in milliseconds.\n+\t */\n+\t__le32 timeout;\n+#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS\t3000\n+#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS\t180000\n+#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS\t1000\n+#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS\t3000\n+\t/* For SDP: pin id of the SDP */\n+\t__le32 res_number;\n+\t/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */\n+\t__le16 status;\n+#define ICE_AQ_RES_GLBL_SUCCESS\t\t0\n+#define ICE_AQ_RES_GLBL_IN_PROG\t\t1\n+#define ICE_AQ_RES_GLBL_DONE\t\t2\n+\tu8 reserved[2];\n+};\n+\n+\n+/* Get function capabilities (indirect 0x000A)\n+ * Get device capabilities (indirect 0x000B)\n+ */\n+struct ice_aqc_list_caps {\n+\tu8 cmd_flags;\n+\tu8 pf_index;\n+\tu8 reserved[2];\n+\t__le32 count;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Device/Function buffer entry, repeated per reported capability */\n+struct ice_aqc_list_caps_elem {\n+\t__le16 cap;\n+#define ICE_AQC_CAPS_VALID_FUNCTIONS\t\t\t0x0005\n+#define ICE_AQC_CAPS_VSI\t\t\t\t0x0017\n+#define ICE_AQC_CAPS_RSS\t\t\t\t0x0040\n+#define ICE_AQC_CAPS_RXQS\t\t\t\t0x0041\n+#define ICE_AQC_CAPS_TXQS\t\t\t\t0x0042\n+#define ICE_AQC_CAPS_MSIX\t\t\t\t0x0043\n+#define ICE_AQC_CAPS_MAX_MTU\t\t\t\t0x0047\n+\n+\tu8 major_ver;\n+\tu8 minor_ver;\n+\t/* Number of resources described by this capability */\n+\t__le32 number;\n+\t/* Only meaningful for some types of resources */\n+\t__le32 logical_id;\n+\t/* Only meaningful for some types of resources */\n+\t__le32 phys_id;\n+\t__le64 rsvd1;\n+\t__le64 rsvd2;\n+};\n+\n+\n+/* Manage MAC address, read command - indirect (0x0107)\n+ * This struct is also used for the response\n+ */\n+struct ice_aqc_manage_mac_read {\n+\t__le16 flags; /* Zeroed by device driver */\n+#define ICE_AQC_MAN_MAC_LAN_ADDR_VALID\t\tBIT(4)\n+#define ICE_AQC_MAN_MAC_SAN_ADDR_VALID\t\tBIT(5)\n+#define ICE_AQC_MAN_MAC_PORT_ADDR_VALID\t\tBIT(6)\n+#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID\t\tBIT(7)\n+#define ICE_AQC_MAN_MAC_READ_S\t\t\t4\n+#define ICE_AQC_MAN_MAC_READ_M\t\t\t(0xF << ICE_AQC_MAN_MAC_READ_S)\n+\tu8 lport_num;\n+\tu8 lport_num_valid;\n+#define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID\tBIT(0)\n+\tu8 num_addr; /* Used in response */\n+\tu8 reserved[3];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Response buffer format for manage MAC read command */\n+struct ice_aqc_manage_mac_read_resp {\n+\tu8 lport_num;\n+\tu8 addr_type;\n+#define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN\t\t0\n+#define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL\t\t1\n+\tu8 mac_addr[ETH_ALEN];\n+};\n+\n+\n+/* Manage MAC address, write command - direct (0x0108) */\n+struct ice_aqc_manage_mac_write {\n+\tu8 port_num;\n+\tu8 flags;\n+#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN\t\tBIT(0)\n+#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP\tBIT(1)\n+#define ICE_AQC_MAN_MAC_WR_S\t\t6\n+#define ICE_AQC_MAN_MAC_WR_M\t\t(3 << ICE_AQC_MAN_MAC_WR_S)\n+#define ICE_AQC_MAN_MAC_UPDATE_LAA\t0\n+#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL\t(BIT(0) << ICE_AQC_MAN_MAC_WR_S)\n+\t/* High 16 bits of MAC address in big endian order */\n+\t__be16 sah;\n+\t/* Low 32 bits of MAC address in big endian order */\n+\t__be32 sal;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Clear PXE Command and response (direct 0x0110) */\n+struct ice_aqc_clear_pxe {\n+\tu8 rx_cnt;\n+#define ICE_AQC_CLEAR_PXE_RX_CNT\t\t0x2\n+\tu8 reserved[15];\n+};\n+\n+\n+/* Get switch configuration (0x0200) */\n+struct ice_aqc_get_sw_cfg {\n+\t/* Reserved for command and copy of request flags for response */\n+\t__le16 flags;\n+\t/* First desc in case of command and next_elem in case of response\n+\t * In case of response, if it is not zero, means all the configuration\n+\t * was not returned and new command shall be sent with this value in\n+\t * the 'first desc' field\n+\t */\n+\t__le16 element;\n+\t/* Reserved for command, only used for response */\n+\t__le16 num_elems;\n+\t__le16 rsvd;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Each entry in the response buffer is of the following type: */\n+struct ice_aqc_get_sw_cfg_resp_elem {\n+\t/* VSI/Port Number */\n+\t__le16 vsi_port_num;\n+#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S\t0\n+#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M\t\\\n+\t\t\t(0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)\n+#define ICE_AQC_GET_SW_CONF_RESP_TYPE_S\t14\n+#define ICE_AQC_GET_SW_CONF_RESP_TYPE_M\t(0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)\n+#define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT\t0\n+#define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT\t1\n+#define ICE_AQC_GET_SW_CONF_RESP_VSI\t\t2\n+\n+\t/* SWID VSI/Port belongs to */\n+\t__le16 swid;\n+\n+\t/* Bit 14..0 : PF/VF number VSI belongs to\n+\t * Bit 15 : VF indication bit\n+\t */\n+\t__le16 pf_vf_num;\n+#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S\t0\n+#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M\t\\\n+\t\t\t\t(0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)\n+#define ICE_AQC_GET_SW_CONF_RESP_IS_VF\t\tBIT(15)\n+};\n+\n+\n+/* The response buffer is as follows. Note that the length of the\n+ * elements array varies with the length of the command response.\n+ */\n+struct ice_aqc_get_sw_cfg_resp {\n+\tstruct ice_aqc_get_sw_cfg_resp_elem elements[1];\n+};\n+\n+\n+\n+/* These resource type defines are used for all switch resource\n+ * commands where a resource type is required, such as:\n+ * Get Resource Allocation command (indirect 0x0204)\n+ * Allocate Resources command (indirect 0x0208)\n+ * Free Resources command (indirect 0x0209)\n+ * Get Allocated Resource Descriptors Command (indirect 0x020A)\n+ */\n+#define ICE_AQC_RES_TYPE_VSI_LIST_REP\t\t\t0x03\n+#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE\t\t\t0x04\n+\n+#define ICE_AQC_RES_TYPE_FLAG_SHARED\t\t\tBIT(7)\n+#define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM\t\tBIT(12)\n+#define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX\t\tBIT(13)\n+\n+#define ICE_AQC_RES_TYPE_FLAG_DEDICATED\t\t\t0x00\n+\n+\n+\n+/* Allocate Resources command (indirect 0x0208)\n+ * Free Resources command (indirect 0x0209)\n+ */\n+struct ice_aqc_alloc_free_res_cmd {\n+\t__le16 num_entries; /* Number of Resource entries */\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Resource descriptor */\n+struct ice_aqc_res_elem {\n+\tunion {\n+\t\t__le16 sw_resp;\n+\t\t__le16 flu_resp;\n+\t} e;\n+};\n+\n+\n+/* Buffer for Allocate/Free Resources commands */\n+struct ice_aqc_alloc_free_res_elem {\n+\t__le16 res_type; /* Types defined above cmd 0x0204 */\n+#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S\t8\n+#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M\t\\\n+\t\t\t\t(0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)\n+\t__le16 num_elems;\n+\tstruct ice_aqc_res_elem elem[1];\n+};\n+\n+\n+\n+\n+/* Add VSI (indirect 0x0210)\n+ * Update VSI (indirect 0x0211)\n+ * Get VSI (indirect 0x0212)\n+ * Free VSI (indirect 0x0213)\n+ */\n+struct ice_aqc_add_get_update_free_vsi {\n+\t__le16 vsi_num;\n+#define ICE_AQ_VSI_NUM_S\t0\n+#define ICE_AQ_VSI_NUM_M\t(0x03FF << ICE_AQ_VSI_NUM_S)\n+#define ICE_AQ_VSI_IS_VALID\tBIT(15)\n+\t__le16 cmd_flags;\n+#define ICE_AQ_VSI_KEEP_ALLOC\t0x1\n+\tu8 vf_id;\n+\tu8 reserved;\n+\t__le16 vsi_flags;\n+#define ICE_AQ_VSI_TYPE_S\t0\n+#define ICE_AQ_VSI_TYPE_M\t(0x3 << ICE_AQ_VSI_TYPE_S)\n+#define ICE_AQ_VSI_TYPE_VF\t0x0\n+#define ICE_AQ_VSI_TYPE_VMDQ2\t0x1\n+#define ICE_AQ_VSI_TYPE_PF\t0x2\n+#define ICE_AQ_VSI_TYPE_EMP_MNG\t0x3\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Response descriptor for:\n+ * Add VSI (indirect 0x0210)\n+ * Update VSI (indirect 0x0211)\n+ * Free VSI (indirect 0x0213)\n+ */\n+struct ice_aqc_add_update_free_vsi_resp {\n+\t__le16 vsi_num;\n+\t__le16 ext_status;\n+\t__le16 vsi_used;\n+\t__le16 vsi_free;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+\n+struct ice_aqc_vsi_props {\n+\t__le16 valid_sections;\n+#define ICE_AQ_VSI_PROP_SW_VALID\t\tBIT(0)\n+#define ICE_AQ_VSI_PROP_SECURITY_VALID\t\tBIT(1)\n+#define ICE_AQ_VSI_PROP_VLAN_VALID\t\tBIT(2)\n+#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID\t\tBIT(3)\n+#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID\tBIT(4)\n+#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID\t\tBIT(5)\n+#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID\t\tBIT(6)\n+#define ICE_AQ_VSI_PROP_Q_OPT_VALID\t\tBIT(7)\n+#define ICE_AQ_VSI_PROP_OUTER_UP_VALID\t\tBIT(8)\n+#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID\t\tBIT(11)\n+#define ICE_AQ_VSI_PROP_PASID_VALID\t\tBIT(12)\n+\t/* switch section */\n+\tu8 sw_id;\n+\tu8 sw_flags;\n+#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB\t\tBIT(5)\n+#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB\t\tBIT(6)\n+#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE\t\tBIT(7)\n+\tu8 sw_flags2;\n+#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S\t0\n+#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M\t\\\n+\t\t\t\t(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)\n+#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA\tBIT(0)\n+#define ICE_AQ_VSI_SW_FLAG_LAN_ENA\t\tBIT(4)\n+\tu8 veb_stat_id;\n+#define ICE_AQ_VSI_SW_VEB_STAT_ID_S\t\t0\n+#define ICE_AQ_VSI_SW_VEB_STAT_ID_M\t(0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)\n+#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID\t\tBIT(5)\n+\t/* security section */\n+\tu8 sec_flags;\n+#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD\tBIT(0)\n+#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF\tBIT(2)\n+#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S\t4\n+#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M\t(0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)\n+#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA\tBIT(0)\n+\tu8 sec_reserved;\n+\t/* VLAN section */\n+\t__le16 pvid; /* VLANS include priority bits */\n+\tu8 pvlan_reserved[2];\n+\tu8 vlan_flags;\n+#define ICE_AQ_VSI_VLAN_MODE_S\t0\n+#define ICE_AQ_VSI_VLAN_MODE_M\t(0x3 << ICE_AQ_VSI_VLAN_MODE_S)\n+#define ICE_AQ_VSI_VLAN_MODE_UNTAGGED\t0x1\n+#define ICE_AQ_VSI_VLAN_MODE_TAGGED\t0x2\n+#define ICE_AQ_VSI_VLAN_MODE_ALL\t0x3\n+#define ICE_AQ_VSI_PVLAN_INSERT_PVID\tBIT(2)\n+#define ICE_AQ_VSI_VLAN_EMOD_S\t3\n+#define ICE_AQ_VSI_VLAN_EMOD_M\t(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)\n+#define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH\t(0x0 << ICE_AQ_VSI_VLAN_EMOD_S)\n+#define ICE_AQ_VSI_VLAN_EMOD_STR_UP\t(0x1 << ICE_AQ_VSI_VLAN_EMOD_S)\n+#define ICE_AQ_VSI_VLAN_EMOD_STR\t(0x2 << ICE_AQ_VSI_VLAN_EMOD_S)\n+#define ICE_AQ_VSI_VLAN_EMOD_NOTHING\t(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)\n+\tu8 pvlan_reserved2[3];\n+\t/* ingress egress up sections */\n+\t__le32 ingress_table; /* bitmap, 3 bits per up */\n+#define ICE_AQ_VSI_UP_TABLE_UP0_S\t0\n+#define ICE_AQ_VSI_UP_TABLE_UP0_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP1_S\t3\n+#define ICE_AQ_VSI_UP_TABLE_UP1_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP2_S\t6\n+#define ICE_AQ_VSI_UP_TABLE_UP2_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP3_S\t9\n+#define ICE_AQ_VSI_UP_TABLE_UP3_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP4_S\t12\n+#define ICE_AQ_VSI_UP_TABLE_UP4_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP5_S\t15\n+#define ICE_AQ_VSI_UP_TABLE_UP5_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP6_S\t18\n+#define ICE_AQ_VSI_UP_TABLE_UP6_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP7_S\t21\n+#define ICE_AQ_VSI_UP_TABLE_UP7_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)\n+\t__le32 egress_table; /* same defines as for ingress table */\n+\t/* outer tags section */\n+\t__le16 outer_tag;\n+\tu8 outer_tag_flags;\n+#define ICE_AQ_VSI_OUTER_TAG_MODE_S\t0\n+#define ICE_AQ_VSI_OUTER_TAG_MODE_M\t(0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)\n+#define ICE_AQ_VSI_OUTER_TAG_NOTHING\t0x0\n+#define ICE_AQ_VSI_OUTER_TAG_REMOVE\t0x1\n+#define ICE_AQ_VSI_OUTER_TAG_COPY\t0x2\n+#define ICE_AQ_VSI_OUTER_TAG_TYPE_S\t2\n+#define ICE_AQ_VSI_OUTER_TAG_TYPE_M\t(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)\n+#define ICE_AQ_VSI_OUTER_TAG_NONE\t0x0\n+#define ICE_AQ_VSI_OUTER_TAG_STAG\t0x1\n+#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100\t0x2\n+#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100\t0x3\n+#define ICE_AQ_VSI_OUTER_TAG_INSERT\tBIT(4)\n+#define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)\n+\tu8 outer_tag_reserved;\n+\t/* queue mapping section */\n+\t__le16 mapping_flags;\n+#define ICE_AQ_VSI_Q_MAP_CONTIG\t0x0\n+#define ICE_AQ_VSI_Q_MAP_NONCONTIG\tBIT(0)\n+\t__le16 q_mapping[16];\n+#define ICE_AQ_VSI_Q_S\t\t0\n+#define ICE_AQ_VSI_Q_M\t\t(0x7FF << ICE_AQ_VSI_Q_S)\n+\t__le16 tc_mapping[8];\n+#define ICE_AQ_VSI_TC_Q_OFFSET_S\t0\n+#define ICE_AQ_VSI_TC_Q_OFFSET_M\t(0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)\n+#define ICE_AQ_VSI_TC_Q_NUM_S\t\t11\n+#define ICE_AQ_VSI_TC_Q_NUM_M\t\t(0xF << ICE_AQ_VSI_TC_Q_NUM_S)\n+\t/* queueing option section */\n+\tu8 q_opt_rss;\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S\t0\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI\t0x0\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF\t0x2\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL\t0x3\n+#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S\t2\n+#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M\t(0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S\t6\n+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ\t(0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ\t(0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_XOR\t(0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_JHASH\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+\tu8 q_opt_tc;\n+#define ICE_AQ_VSI_Q_OPT_TC_OVR_S\t0\n+#define ICE_AQ_VSI_Q_OPT_TC_OVR_M\t(0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)\n+#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR\tBIT(7)\n+\tu8 q_opt_flags;\n+#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN\tBIT(0)\n+\tu8 q_opt_reserved[3];\n+\t/* outer up section */\n+\t__le32 outer_up_table; /* same structure and defines as ingress tbl */\n+\t/* section 10 */\n+\t__le16 sect_10_reserved;\n+\t/* flow director section */\n+\t__le16 fd_options;\n+#define ICE_AQ_VSI_FD_ENABLE\t\tBIT(0)\n+#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE\tBIT(1)\n+#define ICE_AQ_VSI_FD_PROG_ENABLE\tBIT(3)\n+\t__le16 max_fd_fltr_dedicated;\n+\t__le16 max_fd_fltr_shared;\n+\t__le16 fd_def_q;\n+#define ICE_AQ_VSI_FD_DEF_Q_S\t\t0\n+#define ICE_AQ_VSI_FD_DEF_Q_M\t\t(0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)\n+#define ICE_AQ_VSI_FD_DEF_GRP_S\t12\n+#define ICE_AQ_VSI_FD_DEF_GRP_M\t(0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)\n+\t__le16 fd_report_opt;\n+#define ICE_AQ_VSI_FD_REPORT_Q_S\t0\n+#define ICE_AQ_VSI_FD_REPORT_Q_M\t(0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)\n+#define ICE_AQ_VSI_FD_DEF_PRIORITY_S\t12\n+#define ICE_AQ_VSI_FD_DEF_PRIORITY_M\t(0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)\n+#define ICE_AQ_VSI_FD_DEF_DROP\t\tBIT(15)\n+\t/* PASID section */\n+\t__le32 pasid_id;\n+#define ICE_AQ_VSI_PASID_ID_S\t\t0\n+#define ICE_AQ_VSI_PASID_ID_M\t\t(0xFFFFF << ICE_AQ_VSI_PASID_ID_S)\n+#define ICE_AQ_VSI_PASID_ID_VALID\tBIT(31)\n+\tu8 reserved[24];\n+};\n+\n+\n+\n+#define ICE_MAX_NUM_RECIPES 64\n+\n+\n+/* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)\n+ */\n+struct ice_aqc_sw_rules {\n+\t/* ops: add switch rules, referring the number of rules.\n+\t * ops: update switch rules, referring the number of filters\n+\t * ops: remove switch rules, referring the entry index.\n+\t * ops: get switch rules, referring to the number of filters.\n+\t */\n+\t__le16 num_rules_fltr_entry_index;\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+#pragma pack(1)\n+/* Add/Update/Get/Remove lookup Rx/Tx command/response entry\n+ * This structures describes the lookup rules and associated actions. \"index\"\n+ * is returned as part of a response to a successful Add command, and can be\n+ * used to identify the rule for Update/Get/Remove commands.\n+ */\n+struct ice_sw_rule_lkup_rx_tx {\n+\t__le16 recipe_id;\n+#define ICE_SW_RECIPE_LOGICAL_PORT_FWD\t\t10\n+\t/* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */\n+\t__le16 src;\n+\t__le32 act;\n+\n+\t/* Bit 0:1 - Action type */\n+#define ICE_SINGLE_ACT_TYPE_S\t0x00\n+#define ICE_SINGLE_ACT_TYPE_M\t(0x3 << ICE_SINGLE_ACT_TYPE_S)\n+\n+\t/* Bit 2 - Loop back enable\n+\t * Bit 3 - LAN enable\n+\t */\n+#define ICE_SINGLE_ACT_LB_ENABLE\tBIT(2)\n+#define ICE_SINGLE_ACT_LAN_ENABLE\tBIT(3)\n+\n+\t/* Action type = 0 - Forward to VSI or VSI list */\n+#define ICE_SINGLE_ACT_VSI_FORWARDING\t0x0\n+\n+#define ICE_SINGLE_ACT_VSI_ID_S\t\t4\n+#define ICE_SINGLE_ACT_VSI_ID_M\t\t(0x3FF << ICE_SINGLE_ACT_VSI_ID_S)\n+#define ICE_SINGLE_ACT_VSI_LIST_ID_S\t4\n+#define ICE_SINGLE_ACT_VSI_LIST_ID_M\t(0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)\n+\t/* This bit needs to be set if action is forward to VSI list */\n+#define ICE_SINGLE_ACT_VSI_LIST\t\tBIT(14)\n+#define ICE_SINGLE_ACT_VALID_BIT\tBIT(17)\n+#define ICE_SINGLE_ACT_DROP\t\tBIT(18)\n+\n+\t/* Action type = 1 - Forward to Queue of Queue group */\n+#define ICE_SINGLE_ACT_TO_Q\t\t0x1\n+#define ICE_SINGLE_ACT_Q_INDEX_S\t4\n+#define ICE_SINGLE_ACT_Q_INDEX_M\t(0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)\n+#define ICE_SINGLE_ACT_Q_REGION_S\t15\n+#define ICE_SINGLE_ACT_Q_REGION_M\t(0x7 << ICE_SINGLE_ACT_Q_REGION_S)\n+#define ICE_SINGLE_ACT_Q_PRIORITY\tBIT(18)\n+\n+\t/* Action type = 2 - Prune */\n+#define ICE_SINGLE_ACT_PRUNE\t\t0x2\n+#define ICE_SINGLE_ACT_EGRESS\t\tBIT(15)\n+#define ICE_SINGLE_ACT_INGRESS\t\tBIT(16)\n+#define ICE_SINGLE_ACT_PRUNET\t\tBIT(17)\n+\t/* Bit 18 should be set to 0 for this action */\n+\n+\t/* Action type = 2 - Pointer */\n+#define ICE_SINGLE_ACT_PTR\t\t0x2\n+#define ICE_SINGLE_ACT_PTR_VAL_S\t4\n+#define ICE_SINGLE_ACT_PTR_VAL_M\t(0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)\n+\t/* Bit 18 should be set to 1 */\n+#define ICE_SINGLE_ACT_PTR_BIT\t\tBIT(18)\n+\n+\t/* Action type = 3 - Other actions. Last two bits\n+\t * are other action identifier\n+\t */\n+#define ICE_SINGLE_ACT_OTHER_ACTS\t\t0x3\n+#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S\t17\n+#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M\t\\\n+\t\t\t\t(0x3 << \\ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)\n+\n+\t/* Bit 17:18 - Defines other actions */\n+\t/* Other action = 0 - Mirror VSI */\n+#define ICE_SINGLE_OTHER_ACT_MIRROR\t\t0\n+#define ICE_SINGLE_ACT_MIRROR_VSI_ID_S\t4\n+#define ICE_SINGLE_ACT_MIRROR_VSI_ID_M\t\\\n+\t\t\t\t(0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)\n+\n+\t/* Other action = 3 - Set Stat count */\n+#define ICE_SINGLE_OTHER_ACT_STAT_COUNT\t\t3\n+#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S\t4\n+#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M\t\\\n+\t\t\t\t(0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)\n+\n+\t__le16 index; /* The index of the rule in the lookup table */\n+\t/* Length and values of the header to be matched per recipe or\n+\t * lookup-type\n+\t */\n+\t__le16 hdr_len;\n+\tu8 hdr[1];\n+};\n+#pragma pack()\n+\n+\n+/* Add/Update/Remove large action command/response entry\n+ * \"index\" is returned as part of a response to a successful Add command, and\n+ * can be used to identify the action for Update/Get/Remove commands.\n+ */\n+struct ice_sw_rule_lg_act {\n+\t__le16 index; /* Index in large action table */\n+\t__le16 size;\n+\t__le32 act[1]; /* array of size for actions */\n+\t/* Max number of large actions */\n+#define ICE_MAX_LG_ACT\t4\n+\t/* Bit 0:1 - Action type */\n+#define ICE_LG_ACT_TYPE_S\t0\n+#define ICE_LG_ACT_TYPE_M\t(0x7 << ICE_LG_ACT_TYPE_S)\n+\n+\t/* Action type = 0 - Forward to VSI or VSI list */\n+#define ICE_LG_ACT_VSI_FORWARDING\t0\n+#define ICE_LG_ACT_VSI_ID_S\t\t3\n+#define ICE_LG_ACT_VSI_ID_M\t\t(0x3FF << ICE_LG_ACT_VSI_ID_S)\n+#define ICE_LG_ACT_VSI_LIST_ID_S\t3\n+#define ICE_LG_ACT_VSI_LIST_ID_M\t(0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)\n+\t/* This bit needs to be set if action is forward to VSI list */\n+#define ICE_LG_ACT_VSI_LIST\t\tBIT(13)\n+\n+#define ICE_LG_ACT_VALID_BIT\t\tBIT(16)\n+\n+\t/* Action type = 1 - Forward to Queue of Queue group */\n+#define ICE_LG_ACT_TO_Q\t\t\t0x1\n+#define ICE_LG_ACT_Q_INDEX_S\t\t3\n+#define ICE_LG_ACT_Q_INDEX_M\t\t(0x7FF << ICE_LG_ACT_Q_INDEX_S)\n+#define ICE_LG_ACT_Q_REGION_S\t\t14\n+#define ICE_LG_ACT_Q_REGION_M\t\t(0x7 << ICE_LG_ACT_Q_REGION_S)\n+#define ICE_LG_ACT_Q_PRIORITY_SET\tBIT(17)\n+\n+\t/* Action type = 2 - Prune */\n+#define ICE_LG_ACT_PRUNE\t\t0x2\n+#define ICE_LG_ACT_EGRESS\t\tBIT(14)\n+#define ICE_LG_ACT_INGRESS\t\tBIT(15)\n+#define ICE_LG_ACT_PRUNET\t\tBIT(16)\n+\n+\t/* Action type = 3 - Mirror VSI */\n+#define ICE_LG_OTHER_ACT_MIRROR\t\t0x3\n+#define ICE_LG_ACT_MIRROR_VSI_ID_S\t3\n+#define ICE_LG_ACT_MIRROR_VSI_ID_M\t(0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)\n+\n+\t/* Action type = 5 - Generic Value */\n+#define ICE_LG_ACT_GENERIC\t\t0x5\n+#define ICE_LG_ACT_GENERIC_VALUE_S\t3\n+#define ICE_LG_ACT_GENERIC_VALUE_M\t(0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)\n+#define ICE_LG_ACT_GENERIC_OFFSET_S\t19\n+#define ICE_LG_ACT_GENERIC_OFFSET_M\t(0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)\n+#define ICE_LG_ACT_GENERIC_PRIORITY_S\t22\n+#define ICE_LG_ACT_GENERIC_PRIORITY_M\t(0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)\n+#define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX\t7\n+\n+\t/* Action = 7 - Set Stat count */\n+#define ICE_LG_ACT_STAT_COUNT\t\t0x7\n+#define ICE_LG_ACT_STAT_COUNT_S\t\t3\n+#define ICE_LG_ACT_STAT_COUNT_M\t\t(0x7F << ICE_LG_ACT_STAT_COUNT_S)\n+};\n+\n+\n+/* Add/Update/Remove VSI list command/response entry\n+ * \"index\" is returned as part of a response to a successful Add command, and\n+ * can be used to identify the VSI list for Update/Get/Remove commands.\n+ */\n+struct ice_sw_rule_vsi_list {\n+\t__le16 index; /* Index of VSI/Prune list */\n+\t__le16 number_vsi;\n+\t__le16 vsi[1]; /* Array of number_vsi VSI numbers */\n+};\n+\n+\n+#pragma pack(1)\n+/* Query VSI list command/response entry */\n+struct ice_sw_rule_vsi_list_query {\n+\t__le16 index;\n+\tice_declare_bitmap(vsi_list, ICE_MAX_VSI);\n+};\n+#pragma pack()\n+\n+\n+#pragma pack(1)\n+/* Add switch rule response:\n+ * Content of return buffer is same as the input buffer. The status field and\n+ * LUT index are updated as part of the response\n+ */\n+struct ice_aqc_sw_rules_elem {\n+\t__le16 type; /* Switch rule type, one of T_... */\n+#define ICE_AQC_SW_RULES_T_LKUP_RX\t\t0x0\n+#define ICE_AQC_SW_RULES_T_LKUP_TX\t\t0x1\n+#define ICE_AQC_SW_RULES_T_LG_ACT\t\t0x2\n+#define ICE_AQC_SW_RULES_T_VSI_LIST_SET\t\t0x3\n+#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR\t0x4\n+#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET\t0x5\n+#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR\t0x6\n+\t__le16 status;\n+\tunion {\n+\t\tstruct ice_sw_rule_lkup_rx_tx lkup_tx_rx;\n+\t\tstruct ice_sw_rule_lg_act lg_act;\n+\t\tstruct ice_sw_rule_vsi_list vsi_list;\n+\t\tstruct ice_sw_rule_vsi_list_query vsi_list_query;\n+\t} pdata;\n+};\n+\n+#pragma pack()\n+\n+\n+\n+/* Get Default Topology (indirect 0x0400) */\n+struct ice_aqc_get_topo {\n+\tu8 port_num;\n+\tu8 num_branches;\n+\t__le16 reserved1;\n+\t__le32 reserved2;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Update TSE (indirect 0x0403)\n+ * Get TSE (indirect 0x0404)\n+ * Add TSE (indirect 0x0401)\n+ * Delete TSE (indirect 0x040F)\n+ * Move TSE (indirect 0x0408)\n+ * Suspend Nodes (indirect 0x0409)\n+ * Resume Nodes (indirect 0x040A)\n+ */\n+struct ice_aqc_sched_elem_cmd {\n+\t__le16 num_elem_req;\t/* Used by commands */\n+\t__le16 num_elem_resp;\t/* Used by responses */\n+\t__le32 reserved;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* This is the buffer for:\n+ * Suspend Nodes (indirect 0x0409)\n+ * Resume Nodes (indirect 0x040A)\n+ */\n+struct ice_aqc_suspend_resume_elem {\n+\t__le32 teid[1];\n+};\n+\n+\n+struct ice_aqc_txsched_move_grp_info_hdr {\n+\t__le32 src_parent_teid;\n+\t__le32 dest_parent_teid;\n+\t__le16 num_elems;\n+\t__le16 reserved;\n+};\n+\n+\n+struct ice_aqc_move_elem {\n+\tstruct ice_aqc_txsched_move_grp_info_hdr hdr;\n+\t__le32 teid[1];\n+};\n+\n+\n+struct ice_aqc_elem_info_bw {\n+\t__le16 bw_profile_idx;\n+\t__le16 bw_alloc;\n+};\n+\n+\n+struct ice_aqc_txsched_elem {\n+\tu8 elem_type; /* Special field, reserved for some aq calls */\n+#define ICE_AQC_ELEM_TYPE_UNDEFINED\t\t0x0\n+#define ICE_AQC_ELEM_TYPE_ROOT_PORT\t\t0x1\n+#define ICE_AQC_ELEM_TYPE_TC\t\t\t0x2\n+#define ICE_AQC_ELEM_TYPE_SE_GENERIC\t\t0x3\n+#define ICE_AQC_ELEM_TYPE_ENTRY_POINT\t\t0x4\n+#define ICE_AQC_ELEM_TYPE_LEAF\t\t\t0x5\n+#define ICE_AQC_ELEM_TYPE_SE_PADDED\t\t0x6\n+\tu8 valid_sections;\n+#define ICE_AQC_ELEM_VALID_GENERIC\t\tBIT(0)\n+#define ICE_AQC_ELEM_VALID_CIR\t\t\tBIT(1)\n+#define ICE_AQC_ELEM_VALID_EIR\t\t\tBIT(2)\n+#define ICE_AQC_ELEM_VALID_SHARED\t\tBIT(3)\n+\tu8 generic;\n+#define ICE_AQC_ELEM_GENERIC_MODE_M\t\t0x1\n+#define ICE_AQC_ELEM_GENERIC_PRIO_S\t\t0x1\n+#define ICE_AQC_ELEM_GENERIC_PRIO_M\t(0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)\n+#define ICE_AQC_ELEM_GENERIC_SP_S\t\t0x4\n+#define ICE_AQC_ELEM_GENERIC_SP_M\t(0x1 << ICE_AQC_ELEM_GENERIC_SP_S)\n+#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S\t0x5\n+#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M\t\\\n+\t(0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)\n+\tu8 flags; /* Special field, reserved for some aq calls */\n+#define ICE_AQC_ELEM_FLAG_SUSPEND_M\t\t0x1\n+\tstruct ice_aqc_elem_info_bw cir_bw;\n+\tstruct ice_aqc_elem_info_bw eir_bw;\n+\t__le16 srl_id;\n+\t__le16 reserved2;\n+};\n+\n+\n+struct ice_aqc_txsched_elem_data {\n+\t__le32 parent_teid;\n+\t__le32 node_teid;\n+\tstruct ice_aqc_txsched_elem data;\n+};\n+\n+\n+struct ice_aqc_txsched_topo_grp_info_hdr {\n+\t__le32 parent_teid;\n+\t__le16 num_elems;\n+\t__le16 reserved2;\n+};\n+\n+\n+struct ice_aqc_add_elem {\n+\tstruct ice_aqc_txsched_topo_grp_info_hdr hdr;\n+\tstruct ice_aqc_txsched_elem_data generic[1];\n+};\n+\n+\n+struct ice_aqc_conf_elem {\n+\tstruct ice_aqc_txsched_elem_data generic[1];\n+};\n+\n+\n+struct ice_aqc_get_elem {\n+\tstruct ice_aqc_txsched_elem_data generic[1];\n+};\n+\n+\n+struct ice_aqc_get_topo_elem {\n+\tstruct ice_aqc_txsched_topo_grp_info_hdr hdr;\n+\tstruct ice_aqc_txsched_elem_data\n+\t\tgeneric[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n+};\n+\n+\n+struct ice_aqc_delete_elem {\n+\tstruct ice_aqc_txsched_topo_grp_info_hdr hdr;\n+\t__le32 teid[1];\n+};\n+\n+\n+\n+\n+/* Rate limiting profile for\n+ * Add RL profile (indirect 0x0410)\n+ * Query RL profile (indirect 0x0411)\n+ * Remove RL profile (indirect 0x0415)\n+ * These indirect commands acts on single or multiple\n+ * RL profiles with specified data.\n+ */\n+struct ice_aqc_rl_profile {\n+\t__le16 num_profiles;\n+\t__le16 num_processed; /* Only for response. Reserved in Command. */\n+\tu8 reserved[4];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+struct ice_aqc_rl_profile_elem {\n+\tu8 level;\n+\tu8 flags;\n+#define ICE_AQC_RL_PROFILE_TYPE_S\t0x0\n+#define ICE_AQC_RL_PROFILE_TYPE_M\t(0x3 << ICE_AQC_RL_PROFILE_TYPE_S)\n+#define ICE_AQC_RL_PROFILE_TYPE_CIR\t0\n+#define ICE_AQC_RL_PROFILE_TYPE_EIR\t1\n+#define ICE_AQC_RL_PROFILE_TYPE_SRL\t2\n+/* The following flag is used for Query RL Profile Data */\n+#define ICE_AQC_RL_PROFILE_INVAL_S\t0x7\n+#define ICE_AQC_RL_PROFILE_INVAL_M\t(0x1 << ICE_AQC_RL_PROFILE_INVAL_S)\n+\n+\t__le16 profile_id;\n+\t__le16 max_burst_size;\n+\t__le16 rl_multiply;\n+\t__le16 wake_up_calc;\n+\t__le16 rl_encode;\n+};\n+\n+\n+struct ice_aqc_rl_profile_generic_elem {\n+\tstruct ice_aqc_rl_profile_elem generic[1];\n+};\n+\n+\n+\n+/* Configure L2 Node CGD (indirect 0x0414)\n+ * This indirect command allows configuring a congestion domain for given L2\n+ * node TEIDs in the scheduler topology.\n+ */\n+struct ice_aqc_cfg_l2_node_cgd {\n+\t__le16 num_l2_nodes;\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+struct ice_aqc_cfg_l2_node_cgd_elem {\n+\t__le32 node_teid;\n+\tu8 cgd;\n+\tu8 reserved[3];\n+};\n+\n+\n+struct ice_aqc_cfg_l2_node_cgd_data {\n+\tstruct ice_aqc_cfg_l2_node_cgd_elem elem[1];\n+};\n+\n+\n+/* Query Scheduler Resource Allocation (indirect 0x0412)\n+ * This indirect command retrieves the scheduler resources allocated by\n+ * EMP Firmware to the given PF.\n+ */\n+struct ice_aqc_query_txsched_res {\n+\tu8 reserved[8];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+struct ice_aqc_generic_sched_props {\n+\t__le16 phys_levels;\n+\t__le16 logical_levels;\n+\tu8 flattening_bitmap;\n+\tu8 max_device_cgds;\n+\tu8 max_pf_cgds;\n+\tu8 rsvd0;\n+\t__le16 rdma_qsets;\n+\tu8 rsvd1[22];\n+};\n+\n+\n+struct ice_aqc_layer_props {\n+\tu8 logical_layer;\n+\tu8 chunk_size;\n+\t__le16 max_device_nodes;\n+\t__le16 max_pf_nodes;\n+\tu8 rsvd0[4];\n+\t__le16 max_sibl_grp_sz;\n+\t__le16 max_cir_rl_profiles;\n+\t__le16 max_eir_rl_profiles;\n+\t__le16 max_srl_profiles;\n+\tu8 rsvd1[14];\n+};\n+\n+\n+struct ice_aqc_query_txsched_res_resp {\n+\tstruct ice_aqc_generic_sched_props sched_props;\n+\tstruct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n+};\n+\n+\n+/* Query Node to Root Topology (indirect 0x0413)\n+ * This command uses ice_aqc_get_elem as its data buffer.\n+ */\n+struct ice_aqc_query_node_to_root {\n+\t__le32 teid;\n+\t__le32 num_nodes; /* Response only */\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Get PHY capabilities (indirect 0x0600) */\n+struct ice_aqc_get_phy_caps {\n+\tu8 lport_num;\n+\tu8 reserved;\n+\t__le16 param0;\n+\t/* 18.0 - Report qualified modules */\n+#define ICE_AQC_GET_PHY_RQM\t\tBIT(0)\n+\t/* 18.1 - 18.2 : Report mode\n+\t * 00b - Report NVM capabilities\n+\t * 01b - Report topology capabilities\n+\t * 10b - Report SW configured\n+\t */\n+#define ICE_AQC_REPORT_MODE_S\t\t1\n+#define ICE_AQC_REPORT_MODE_M\t\t(3 << ICE_AQC_REPORT_MODE_S)\n+#define ICE_AQC_REPORT_NVM_CAP\t\t0\n+#define ICE_AQC_REPORT_TOPO_CAP\t\tBIT(1)\n+#define ICE_AQC_REPORT_SW_CFG\t\tBIT(2)\n+\t__le32 reserved1;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* This is #define of PHY type (Extended):\n+ * The first set of defines is for phy_type_low.\n+ */\n+#define ICE_PHY_TYPE_LOW_100BASE_TX\t\tBIT_ULL(0)\n+#define ICE_PHY_TYPE_LOW_100M_SGMII\t\tBIT_ULL(1)\n+#define ICE_PHY_TYPE_LOW_1000BASE_T\t\tBIT_ULL(2)\n+#define ICE_PHY_TYPE_LOW_1000BASE_SX\t\tBIT_ULL(3)\n+#define ICE_PHY_TYPE_LOW_1000BASE_LX\t\tBIT_ULL(4)\n+#define ICE_PHY_TYPE_LOW_1000BASE_KX\t\tBIT_ULL(5)\n+#define ICE_PHY_TYPE_LOW_1G_SGMII\t\tBIT_ULL(6)\n+#define ICE_PHY_TYPE_LOW_2500BASE_T\t\tBIT_ULL(7)\n+#define ICE_PHY_TYPE_LOW_2500BASE_X\t\tBIT_ULL(8)\n+#define ICE_PHY_TYPE_LOW_2500BASE_KX\t\tBIT_ULL(9)\n+#define ICE_PHY_TYPE_LOW_5GBASE_T\t\tBIT_ULL(10)\n+#define ICE_PHY_TYPE_LOW_5GBASE_KR\t\tBIT_ULL(11)\n+#define ICE_PHY_TYPE_LOW_10GBASE_T\t\tBIT_ULL(12)\n+#define ICE_PHY_TYPE_LOW_10G_SFI_DA\t\tBIT_ULL(13)\n+#define ICE_PHY_TYPE_LOW_10GBASE_SR\t\tBIT_ULL(14)\n+#define ICE_PHY_TYPE_LOW_10GBASE_LR\t\tBIT_ULL(15)\n+#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1\t\tBIT_ULL(16)\n+#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC\tBIT_ULL(17)\n+#define ICE_PHY_TYPE_LOW_10G_SFI_C2C\t\tBIT_ULL(18)\n+#define ICE_PHY_TYPE_LOW_25GBASE_T\t\tBIT_ULL(19)\n+#define ICE_PHY_TYPE_LOW_25GBASE_CR\t\tBIT_ULL(20)\n+#define ICE_PHY_TYPE_LOW_25GBASE_CR_S\t\tBIT_ULL(21)\n+#define ICE_PHY_TYPE_LOW_25GBASE_CR1\t\tBIT_ULL(22)\n+#define ICE_PHY_TYPE_LOW_25GBASE_SR\t\tBIT_ULL(23)\n+#define ICE_PHY_TYPE_LOW_25GBASE_LR\t\tBIT_ULL(24)\n+#define ICE_PHY_TYPE_LOW_25GBASE_KR\t\tBIT_ULL(25)\n+#define ICE_PHY_TYPE_LOW_25GBASE_KR_S\t\tBIT_ULL(26)\n+#define ICE_PHY_TYPE_LOW_25GBASE_KR1\t\tBIT_ULL(27)\n+#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC\tBIT_ULL(28)\n+#define ICE_PHY_TYPE_LOW_25G_AUI_C2C\t\tBIT_ULL(29)\n+#define ICE_PHY_TYPE_LOW_40GBASE_CR4\t\tBIT_ULL(30)\n+#define ICE_PHY_TYPE_LOW_40GBASE_SR4\t\tBIT_ULL(31)\n+#define ICE_PHY_TYPE_LOW_40GBASE_LR4\t\tBIT_ULL(32)\n+#define ICE_PHY_TYPE_LOW_40GBASE_KR4\t\tBIT_ULL(33)\n+#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC\tBIT_ULL(34)\n+#define ICE_PHY_TYPE_LOW_40G_XLAUI\t\tBIT_ULL(35)\n+#define ICE_PHY_TYPE_LOW_50GBASE_CR2\t\tBIT_ULL(36)\n+#define ICE_PHY_TYPE_LOW_50GBASE_SR2\t\tBIT_ULL(37)\n+#define ICE_PHY_TYPE_LOW_50GBASE_LR2\t\tBIT_ULL(38)\n+#define ICE_PHY_TYPE_LOW_50GBASE_KR2\t\tBIT_ULL(39)\n+#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC\tBIT_ULL(40)\n+#define ICE_PHY_TYPE_LOW_50G_LAUI2\t\tBIT_ULL(41)\n+#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC\tBIT_ULL(42)\n+#define ICE_PHY_TYPE_LOW_50G_AUI2\t\tBIT_ULL(43)\n+#define ICE_PHY_TYPE_LOW_50GBASE_CP\t\tBIT_ULL(44)\n+#define ICE_PHY_TYPE_LOW_50GBASE_SR\t\tBIT_ULL(45)\n+#define ICE_PHY_TYPE_LOW_50GBASE_FR\t\tBIT_ULL(46)\n+#define ICE_PHY_TYPE_LOW_50GBASE_LR\t\tBIT_ULL(47)\n+#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4\tBIT_ULL(48)\n+#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC\tBIT_ULL(49)\n+#define ICE_PHY_TYPE_LOW_50G_AUI1\t\tBIT_ULL(50)\n+#define ICE_PHY_TYPE_LOW_100GBASE_CR4\t\tBIT_ULL(51)\n+#define ICE_PHY_TYPE_LOW_100GBASE_SR4\t\tBIT_ULL(52)\n+#define ICE_PHY_TYPE_LOW_100GBASE_LR4\t\tBIT_ULL(53)\n+#define ICE_PHY_TYPE_LOW_100GBASE_KR4\t\tBIT_ULL(54)\n+#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC\tBIT_ULL(55)\n+#define ICE_PHY_TYPE_LOW_100G_CAUI4\t\tBIT_ULL(56)\n+#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC\tBIT_ULL(57)\n+#define ICE_PHY_TYPE_LOW_100G_AUI4\t\tBIT_ULL(58)\n+#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4\tBIT_ULL(59)\n+#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4\tBIT_ULL(60)\n+#define ICE_PHY_TYPE_LOW_100GBASE_CP2\t\tBIT_ULL(61)\n+#define ICE_PHY_TYPE_LOW_100GBASE_SR2\t\tBIT_ULL(62)\n+#define ICE_PHY_TYPE_LOW_100GBASE_DR\t\tBIT_ULL(63)\n+#define ICE_PHY_TYPE_LOW_MAX_INDEX\t\t63\n+/* The second set of defines is for phy_type_high. */\n+#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4\tBIT_ULL(0)\n+#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC\tBIT_ULL(1)\n+#define ICE_PHY_TYPE_HIGH_100G_CAUI2\t\tBIT_ULL(2)\n+#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC\tBIT_ULL(3)\n+#define ICE_PHY_TYPE_HIGH_100G_AUI2\t\tBIT_ULL(4)\n+#define ICE_PHY_TYPE_HIGH_MAX_INDEX\t\t19\n+\n+struct ice_aqc_get_phy_caps_data {\n+\t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n+\t__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */\n+\tu8 caps;\n+#define ICE_AQC_PHY_EN_TX_LINK_PAUSE\t\t\tBIT(0)\n+#define ICE_AQC_PHY_EN_RX_LINK_PAUSE\t\t\tBIT(1)\n+#define ICE_AQC_PHY_LOW_POWER_MODE\t\t\tBIT(2)\n+#define ICE_AQC_PHY_EN_LINK\t\t\t\tBIT(3)\n+#define ICE_AQC_PHY_AN_MODE\t\t\t\tBIT(4)\n+#define ICE_AQC_PHY_EN_MOD_QUAL\t\t\t\tBIT(5)\n+#define ICE_AQC_PHY_EN_LESM\t\t\t\tBIT(6)\n+#define ICE_AQC_PHY_EN_AUTO_FEC\t\t\t\tBIT(7)\n+#define ICE_AQC_PHY_CAPS_MASK\t\t\t\tMAKEMASK(0xff, 0)\n+\tu8 low_power_ctrl;\n+#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG\t\tBIT(0)\n+\t__le16 eee_cap;\n+#define ICE_AQC_PHY_EEE_EN_100BASE_TX\t\t\tBIT(0)\n+#define ICE_AQC_PHY_EEE_EN_1000BASE_T\t\t\tBIT(1)\n+#define ICE_AQC_PHY_EEE_EN_10GBASE_T\t\t\tBIT(2)\n+#define ICE_AQC_PHY_EEE_EN_1000BASE_KX\t\t\tBIT(3)\n+#define ICE_AQC_PHY_EEE_EN_10GBASE_KR\t\t\tBIT(4)\n+#define ICE_AQC_PHY_EEE_EN_25GBASE_KR\t\t\tBIT(5)\n+#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4\t\t\tBIT(6)\n+#define ICE_AQC_PHY_EEE_EN_50GBASE_KR2\t\t\tBIT(7)\n+#define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4\t\tBIT(8)\n+#define ICE_AQC_PHY_EEE_EN_100GBASE_KR4\t\t\tBIT(9)\n+#define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4\t\tBIT(10)\n+\t__le16 eeer_value;\n+\tu8 phy_id_oui[4]; /* PHY/Module ID connected on the port */\n+\tu8 phy_fw_ver[8];\n+\tu8 link_fec_options;\n+#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN\t\tBIT(0)\n+#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ\t\tBIT(1)\n+#define ICE_AQC_PHY_FEC_25G_RS_528_REQ\t\t\tBIT(2)\n+#define ICE_AQC_PHY_FEC_25G_KR_REQ\t\t\tBIT(3)\n+#define ICE_AQC_PHY_FEC_25G_RS_544_REQ\t\t\tBIT(4)\n+#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN\t\tBIT(6)\n+#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN\t\tBIT(7)\n+#define ICE_AQC_PHY_FEC_MASK\t\t\t\tMAKEMASK(0xdf, 0)\n+\tu8 extended_compliance_code;\n+#define ICE_MODULE_TYPE_TOTAL_BYTE\t\t\t3\n+\tu8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];\n+#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS\t\t\t0xA0\n+#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS\t\t0x80\n+#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE\tBIT(0)\n+#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE\tBIT(1)\n+#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR\t\tBIT(4)\n+#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR\t\tBIT(5)\n+#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM\t\tBIT(6)\n+#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER\t\tBIT(7)\n+#define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS\t\t\t0xA0\n+#define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS\t\t0x86\n+\tu8 qualified_module_count;\n+#define ICE_AQC_QUAL_MOD_COUNT_MAX\t\t\t16\n+\tstruct {\n+\t\tu8 v_oui[3];\n+\t\tu8 rsvd3;\n+\t\tu8 v_part[16];\n+\t\t__le32 v_rev;\n+\t\t__le64 rsvd8;\n+\t} qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];\n+};\n+\n+\n+/* Set PHY capabilities (direct 0x0601)\n+ * NOTE: This command must be followed by setup link and restart auto-neg\n+ */\n+struct ice_aqc_set_phy_cfg {\n+\tu8 lport_num;\n+\tu8 reserved[7];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Set PHY config command data structure */\n+struct ice_aqc_set_phy_cfg_data {\n+\t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n+\t__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */\n+\tu8 caps;\n+#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY\t\tBIT(0)\n+#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY\t\tBIT(1)\n+#define ICE_AQ_PHY_ENA_LOW_POWER\tBIT(2)\n+#define ICE_AQ_PHY_ENA_LINK\t\tBIT(3)\n+#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT\tBIT(5)\n+#define ICE_AQ_PHY_ENA_LESM\t\tBIT(6)\n+#define ICE_AQ_PHY_ENA_AUTO_FEC\t\tBIT(7)\n+\tu8 low_power_ctrl;\n+\t__le16 eee_cap; /* Value from ice_aqc_get_phy_caps */\n+\t__le16 eeer_value;\n+\tu8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */\n+\tu8 rsvd1;\n+};\n+\n+\n+\n+/* Restart AN command data structure (direct 0x0605)\n+ * Also used for response, with only the lport_num field present.\n+ */\n+struct ice_aqc_restart_an {\n+\tu8 lport_num;\n+\tu8 reserved;\n+\tu8 cmd_flags;\n+#define ICE_AQC_RESTART_AN_LINK_RESTART\tBIT(1)\n+#define ICE_AQC_RESTART_AN_LINK_ENABLE\tBIT(2)\n+\tu8 reserved2[13];\n+};\n+\n+\n+/* Get link status (indirect 0x0607), also used for Link Status Event */\n+struct ice_aqc_get_link_status {\n+\tu8 lport_num;\n+\tu8 reserved;\n+\t__le16 cmd_flags;\n+#define ICE_AQ_LSE_M\t\t\t0x3\n+#define ICE_AQ_LSE_NOP\t\t\t0x0\n+#define ICE_AQ_LSE_DIS\t\t\t0x2\n+#define ICE_AQ_LSE_ENA\t\t\t0x3\n+\t/* only response uses this flag */\n+#define ICE_AQ_LSE_IS_ENABLED\t\t0x1\n+\t__le32 reserved2;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Get link status response data structure, also used for Link Status Event */\n+struct ice_aqc_get_link_status_data {\n+\tu8 topo_media_conflict;\n+#define ICE_AQ_LINK_TOPO_CONFLICT\tBIT(0)\n+#define ICE_AQ_LINK_MEDIA_CONFLICT\tBIT(1)\n+#define ICE_AQ_LINK_TOPO_CORRUPT\tBIT(2)\n+\tu8 reserved1;\n+\tu8 link_info;\n+#define ICE_AQ_LINK_UP\t\t\tBIT(0)\t/* Link Status */\n+#define ICE_AQ_LINK_FAULT\t\tBIT(1)\n+#define ICE_AQ_LINK_FAULT_TX\t\tBIT(2)\n+#define ICE_AQ_LINK_FAULT_RX\t\tBIT(3)\n+#define ICE_AQ_LINK_FAULT_REMOTE\tBIT(4)\n+#define ICE_AQ_LINK_UP_PORT\t\tBIT(5)\t/* External Port Link Status */\n+#define ICE_AQ_MEDIA_AVAILABLE\t\tBIT(6)\n+#define ICE_AQ_SIGNAL_DETECT\t\tBIT(7)\n+\tu8 an_info;\n+#define ICE_AQ_AN_COMPLETED\t\tBIT(0)\n+#define ICE_AQ_LP_AN_ABILITY\t\tBIT(1)\n+#define ICE_AQ_PD_FAULT\t\t\tBIT(2)\t/* Parallel Detection Fault */\n+#define ICE_AQ_FEC_EN\t\t\tBIT(3)\n+#define ICE_AQ_PHY_LOW_POWER\t\tBIT(4)\t/* Low Power State */\n+#define ICE_AQ_LINK_PAUSE_TX\t\tBIT(5)\n+#define ICE_AQ_LINK_PAUSE_RX\t\tBIT(6)\n+#define ICE_AQ_QUALIFIED_MODULE\t\tBIT(7)\n+\tu8 ext_info;\n+#define ICE_AQ_LINK_PHY_TEMP_ALARM\tBIT(0)\n+#define ICE_AQ_LINK_EXCESSIVE_ERRORS\tBIT(1)\t/* Excessive Link Errors */\n+\t/* Port TX Suspended */\n+#define ICE_AQ_LINK_TX_S\t\t2\n+#define ICE_AQ_LINK_TX_M\t\t(0x03 << ICE_AQ_LINK_TX_S)\n+#define ICE_AQ_LINK_TX_ACTIVE\t\t0\n+#define ICE_AQ_LINK_TX_DRAINED\t\t1\n+#define ICE_AQ_LINK_TX_FLUSHED\t\t3\n+\tu8 reserved2;\n+\t__le16 max_frame_size;\n+\tu8 cfg;\n+#define ICE_AQ_LINK_25G_KR_FEC_EN\tBIT(0)\n+#define ICE_AQ_LINK_25G_RS_528_FEC_EN\tBIT(1)\n+#define ICE_AQ_LINK_25G_RS_544_FEC_EN\tBIT(2)\n+#define ICE_AQ_FEC_MASK\t\t\tMAKEMASK(0x7, 0)\n+\t/* Pacing Config */\n+#define ICE_AQ_CFG_PACING_S\t\t3\n+#define ICE_AQ_CFG_PACING_M\t\t(0xF << ICE_AQ_CFG_PACING_S)\n+#define ICE_AQ_CFG_PACING_TYPE_M\tBIT(7)\n+#define ICE_AQ_CFG_PACING_TYPE_AVG\t0\n+#define ICE_AQ_CFG_PACING_TYPE_FIXED\tICE_AQ_CFG_PACING_TYPE_M\n+\t/* External Device Power Ability */\n+\tu8 power_desc;\n+#define ICE_AQ_PWR_CLASS_M\t\t0x3\n+#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH\t0\n+#define ICE_AQ_LINK_PWR_BASET_HIGH\t1\n+#define ICE_AQ_LINK_PWR_QSFP_CLASS_1\t0\n+#define ICE_AQ_LINK_PWR_QSFP_CLASS_2\t1\n+#define ICE_AQ_LINK_PWR_QSFP_CLASS_3\t2\n+#define ICE_AQ_LINK_PWR_QSFP_CLASS_4\t3\n+\t__le16 link_speed;\n+#define ICE_AQ_LINK_SPEED_10MB\t\tBIT(0)\n+#define ICE_AQ_LINK_SPEED_100MB\t\tBIT(1)\n+#define ICE_AQ_LINK_SPEED_1000MB\tBIT(2)\n+#define ICE_AQ_LINK_SPEED_2500MB\tBIT(3)\n+#define ICE_AQ_LINK_SPEED_5GB\t\tBIT(4)\n+#define ICE_AQ_LINK_SPEED_10GB\t\tBIT(5)\n+#define ICE_AQ_LINK_SPEED_20GB\t\tBIT(6)\n+#define ICE_AQ_LINK_SPEED_25GB\t\tBIT(7)\n+#define ICE_AQ_LINK_SPEED_40GB\t\tBIT(8)\n+#define ICE_AQ_LINK_SPEED_50GB\t\tBIT(9)\n+#define ICE_AQ_LINK_SPEED_100GB\t\tBIT(10)\n+#define ICE_AQ_LINK_SPEED_UNKNOWN\tBIT(15)\n+\t__le32 reserved3; /* Aligns next field to 8-byte boundary */\n+\t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n+\t__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */\n+};\n+\n+\n+/* Set event mask command (direct 0x0613) */\n+struct ice_aqc_set_event_mask {\n+\tu8\tlport_num;\n+\tu8\treserved[7];\n+\t__le16\tevent_mask;\n+#define ICE_AQ_LINK_EVENT_UPDOWN\t\tBIT(1)\n+#define ICE_AQ_LINK_EVENT_MEDIA_NA\t\tBIT(2)\n+#define ICE_AQ_LINK_EVENT_LINK_FAULT\t\tBIT(3)\n+#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM\tBIT(4)\n+#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS\tBIT(5)\n+#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT\t\tBIT(6)\n+#define ICE_AQ_LINK_EVENT_AN_COMPLETED\t\tBIT(7)\n+#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL\tBIT(8)\n+#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED\tBIT(9)\n+\tu8\treserved1[6];\n+};\n+\n+\n+\n+/* Set MAC Loopback command (direct 0x0620) */\n+struct ice_aqc_set_mac_lb {\n+\tu8 lb_mode;\n+#define ICE_AQ_MAC_LB_EN\t\tBIT(0)\n+#define ICE_AQ_MAC_LB_OSC_CLK\t\tBIT(1)\n+\tu8 reserved[15];\n+};\n+\n+\n+\n+\n+\n+/* Set Port Identification LED (direct, 0x06E9) */\n+struct ice_aqc_set_port_id_led {\n+\tu8 lport_num;\n+\tu8 lport_num_valid;\n+#define ICE_AQC_PORT_ID_PORT_NUM_VALID\tBIT(0)\n+\tu8 ident_mode;\n+#define ICE_AQC_PORT_IDENT_LED_BLINK\tBIT(0)\n+#define ICE_AQC_PORT_IDENT_LED_ORIG\t0\n+\tu8 rsvd[13];\n+};\n+\n+\n+\n+/* NVM Read command (indirect 0x0701)\n+ * NVM Erase commands (direct 0x0702)\n+ * NVM Update commands (indirect 0x0703)\n+ */\n+struct ice_aqc_nvm {\n+\t__le16 offset_low;\n+\tu8 offset_high;\n+\tu8 cmd_flags;\n+#define ICE_AQC_NVM_LAST_CMD\t\tBIT(0)\n+#define ICE_AQC_NVM_PCIR_REQ\t\tBIT(0)\t/* Used by NVM Update reply */\n+#define ICE_AQC_NVM_PRESERVATION_S\t1\n+#define ICE_AQC_NVM_PRESERVATION_M\t(3 << ICE_AQC_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_NO_PRESERVATION\t(0 << ICE_AQC_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_PRESERVE_ALL\tBIT(1)\n+#define ICE_AQC_NVM_FACTORY_DEFAULT\t(2 << ICE_AQC_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_PRESERVE_SELECTED\t(3 << ICE_AQC_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_FLASH_ONLY\t\tBIT(7)\n+\t__le16 module_typeid;\n+\t__le16 length;\n+#define ICE_AQC_NVM_ERASE_LEN\t0xFFFF\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Used for 0x0704 as well as for 0x0705 commands */\n+struct ice_aqc_nvm_cfg {\n+\tu8\tcmd_flags;\n+#define ICE_AQC_ANVM_MULTIPLE_ELEMS\tBIT(0)\n+#define ICE_AQC_ANVM_IMMEDIATE_FIELD\tBIT(1)\n+#define ICE_AQC_ANVM_NEW_CFG\t\tBIT(2)\n+\tu8\treserved;\n+\t__le16 count;\n+\t__le16 id;\n+\tu8 reserved1[2];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+struct ice_aqc_nvm_cfg_data {\n+\t__le16 field_id;\n+\t__le16 field_options;\n+\t__le16 field_value;\n+};\n+\n+\n+/* NVM Checksum Command (direct, 0x0706) */\n+struct ice_aqc_nvm_checksum {\n+\tu8 flags;\n+#define ICE_AQC_NVM_CHECKSUM_VERIFY\tBIT(0)\n+#define ICE_AQC_NVM_CHECKSUM_RECALC\tBIT(1)\n+\tu8 rsvd;\n+\t__le16 checksum; /* Used only by response */\n+#define ICE_AQC_NVM_CHECKSUM_CORRECT\t0xBABA\n+\tu8 rsvd2[12];\n+};\n+\n+\n+\n+\n+\n+/* Get/Set RSS key (indirect 0x0B04/0x0B02) */\n+struct ice_aqc_get_set_rss_key {\n+#define ICE_AQC_GSET_RSS_KEY_VSI_VALID\tBIT(15)\n+#define ICE_AQC_GSET_RSS_KEY_VSI_ID_S\t0\n+#define ICE_AQC_GSET_RSS_KEY_VSI_ID_M\t(0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)\n+\t__le16 vsi_id;\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE\t0x28\n+#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE\t0xC\n+\n+struct ice_aqc_get_set_rss_keys {\n+\tu8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];\n+\tu8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];\n+};\n+\n+\n+/* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */\n+struct ice_aqc_get_set_rss_lut {\n+#define ICE_AQC_GSET_RSS_LUT_VSI_VALID\tBIT(15)\n+#define ICE_AQC_GSET_RSS_LUT_VSI_ID_S\t0\n+#define ICE_AQC_GSET_RSS_LUT_VSI_ID_M\t(0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)\n+\t__le16 vsi_id;\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S\t0\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M\t\\\n+\t\t\t\t(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)\n+\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI\t 0\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF\t 1\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL\t 2\n+\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S\t 2\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M\t \\\n+\t\t\t\t(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)\n+\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128\t 128\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512\t 512\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K\t 2048\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG\t 2\n+\n+#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S\t 4\n+#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M\t \\\n+\t\t\t\t(0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)\n+\n+\t__le16 flags;\n+\t__le32 reserved;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+\n+\n+\n+/* Add TX LAN Queues (indirect 0x0C30) */\n+struct ice_aqc_add_txqs {\n+\tu8 num_qgrps;\n+\tu8 reserved[3];\n+\t__le32 reserved1;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* This is the descriptor of each queue entry for the Add TX LAN Queues\n+ * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.\n+ */\n+struct ice_aqc_add_txqs_perq {\n+\t__le16 txq_id;\n+\tu8 rsvd[2];\n+\t__le32 q_teid;\n+\tu8 txq_ctx[22];\n+\tu8 rsvd2[2];\n+\tstruct ice_aqc_txsched_elem info;\n+};\n+\n+\n+/* The format of the command buffer for Add TX LAN Queues (0x0C30)\n+ * is an array of the following structs. Please note that the length of\n+ * each struct ice_aqc_add_tx_qgrp is variable due\n+ * to the variable number of queues in each group!\n+ */\n+struct ice_aqc_add_tx_qgrp {\n+\t__le32 parent_teid;\n+\tu8 num_txqs;\n+\tu8 rsvd[3];\n+\tstruct ice_aqc_add_txqs_perq txqs[1];\n+};\n+\n+\n+/* Disable TX LAN Queues (indirect 0x0C31) */\n+struct ice_aqc_dis_txqs {\n+\tu8 cmd_type;\n+#define ICE_AQC_Q_DIS_CMD_S\t\t0\n+#define ICE_AQC_Q_DIS_CMD_M\t\t(0x3 << ICE_AQC_Q_DIS_CMD_S)\n+#define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET\t(0 << ICE_AQC_Q_DIS_CMD_S)\n+#define ICE_AQC_Q_DIS_CMD_VM_RESET\tBIT(ICE_AQC_Q_DIS_CMD_S)\n+#define ICE_AQC_Q_DIS_CMD_VF_RESET\t(2 << ICE_AQC_Q_DIS_CMD_S)\n+#define ICE_AQC_Q_DIS_CMD_PF_RESET\t(3 << ICE_AQC_Q_DIS_CMD_S)\n+#define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL\tBIT(2)\n+#define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE\tBIT(3)\n+\tu8 num_entries;\n+\t__le16 vmvf_and_timeout;\n+#define ICE_AQC_Q_DIS_VMVF_NUM_S\t0\n+#define ICE_AQC_Q_DIS_VMVF_NUM_M\t(0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)\n+#define ICE_AQC_Q_DIS_TIMEOUT_S\t\t10\n+#define ICE_AQC_Q_DIS_TIMEOUT_M\t\t(0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)\n+\t__le32 blocked_cgds;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* The buffer for Disable TX LAN Queues (indirect 0x0C31)\n+ * contains the following structures, arrayed one after the\n+ * other.\n+ * Note: Since the q_id is 16 bits wide, if the\n+ * number of queues is even, then 2 bytes of alignment MUST be\n+ * added before the start of the next group, to allow correct\n+ * alignment of the parent_teid field.\n+ */\n+struct ice_aqc_dis_txq_item {\n+\t__le32 parent_teid;\n+\tu8 num_qs;\n+\tu8 rsvd;\n+\t/* The length of the q_id array varies according to num_qs */\n+\t__le16 q_id[1];\n+\t/* This only applies from F8 onward */\n+#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S\t\t15\n+#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q\t\\\n+\t\t\t(0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)\n+#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET\t\\\n+\t\t\t(1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)\n+};\n+\n+\n+struct ice_aqc_dis_txq {\n+\tstruct ice_aqc_dis_txq_item qgrps[1];\n+};\n+\n+\n+/* TX LAN Queues Cleanup Event (0x0C31) */\n+struct ice_aqc_txqs_cleanup {\n+\t__le16 caller_opc;\n+\t__le16 cmd_tag;\n+\tu8 reserved[12];\n+};\n+\n+\n+/* Move / Reconfigure TX Queues (indirect 0x0C32) */\n+struct ice_aqc_move_txqs {\n+\tu8 cmd_type;\n+#define ICE_AQC_Q_CMD_TYPE_S\t\t0\n+#define ICE_AQC_Q_CMD_TYPE_M\t\t(0x3 << ICE_AQC_Q_CMD_TYPE_S)\n+#define ICE_AQC_Q_CMD_TYPE_MOVE\t\t1\n+#define ICE_AQC_Q_CMD_TYPE_TC_CHANGE\t2\n+#define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC\t3\n+#define ICE_AQC_Q_CMD_SUBSEQ_CALL\tBIT(2)\n+#define ICE_AQC_Q_CMD_FLUSH_PIPE\tBIT(3)\n+\tu8 num_qs;\n+\tu8 rsvd;\n+\tu8 timeout;\n+#define ICE_AQC_Q_CMD_TIMEOUT_S\t\t2\n+#define ICE_AQC_Q_CMD_TIMEOUT_M\t\t(0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)\n+\t__le32 blocked_cgds;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* This is the descriptor of each queue entry for the move TX LAN Queues\n+ * command (0x0C32).\n+ */\n+struct ice_aqc_move_txqs_elem {\n+\t__le16 txq_id;\n+\tu8 q_cgd;\n+\tu8 rsvd;\n+\t__le32 q_teid;\n+};\n+\n+\n+struct ice_aqc_move_txqs_data {\n+\t__le32 src_teid;\n+\t__le32 dest_teid;\n+\tstruct ice_aqc_move_txqs_elem txqs[1];\n+};\n+\n+\n+\n+\n+\n+\n+/* Lan Queue Overflow Event (direct, 0x1001) */\n+struct ice_aqc_event_lan_overflow {\n+\t__le32 prtdcb_ruptq;\n+\t__le32 qtx_ctl;\n+\tu8 reserved[8];\n+};\n+\n+\n+\n+/* Configure Firmware Logging Command (indirect 0xFF09)\n+ * Logging Information Read Response (indirect 0xFF10)\n+ * Note: The 0xFF10 command has no input parameters.\n+ */\n+struct ice_aqc_fw_logging {\n+\tu8 log_ctrl;\n+#define ICE_AQC_FW_LOG_AQ_EN\t\tBIT(0)\n+#define ICE_AQC_FW_LOG_UART_EN\t\tBIT(1)\n+\tu8 rsvd0;\n+\tu8 log_ctrl_valid; /* Not used by 0xFF10 Response */\n+#define ICE_AQC_FW_LOG_AQ_VALID\t\tBIT(0)\n+#define ICE_AQC_FW_LOG_UART_VALID\tBIT(1)\n+\tu8 rsvd1[5];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+enum ice_aqc_fw_logging_mod {\n+\tICE_AQC_FW_LOG_ID_GENERAL = 0,\n+\tICE_AQC_FW_LOG_ID_CTRL,\n+\tICE_AQC_FW_LOG_ID_LINK,\n+\tICE_AQC_FW_LOG_ID_LINK_TOPO,\n+\tICE_AQC_FW_LOG_ID_DNL,\n+\tICE_AQC_FW_LOG_ID_I2C,\n+\tICE_AQC_FW_LOG_ID_SDP,\n+\tICE_AQC_FW_LOG_ID_MDIO,\n+\tICE_AQC_FW_LOG_ID_ADMINQ,\n+\tICE_AQC_FW_LOG_ID_HDMA,\n+\tICE_AQC_FW_LOG_ID_LLDP,\n+\tICE_AQC_FW_LOG_ID_DCBX,\n+\tICE_AQC_FW_LOG_ID_DCB,\n+\tICE_AQC_FW_LOG_ID_NETPROXY,\n+\tICE_AQC_FW_LOG_ID_NVM,\n+\tICE_AQC_FW_LOG_ID_AUTH,\n+\tICE_AQC_FW_LOG_ID_VPD,\n+\tICE_AQC_FW_LOG_ID_IOSF,\n+\tICE_AQC_FW_LOG_ID_PARSER,\n+\tICE_AQC_FW_LOG_ID_SW,\n+\tICE_AQC_FW_LOG_ID_SCHEDULER,\n+\tICE_AQC_FW_LOG_ID_TXQ,\n+\tICE_AQC_FW_LOG_ID_RSVD,\n+\tICE_AQC_FW_LOG_ID_POST,\n+\tICE_AQC_FW_LOG_ID_WATCHDOG,\n+\tICE_AQC_FW_LOG_ID_TASK_DISPATCH,\n+\tICE_AQC_FW_LOG_ID_MNG,\n+\tICE_AQC_FW_LOG_ID_MAX,\n+};\n+\n+/* This is the buffer for both of the logging commands.\n+ * The entry array size depends on the datalen parameter in the descriptor.\n+ * There will be a total of datalen / 2 entries.\n+ */\n+struct ice_aqc_fw_logging_data {\n+\t__le16 entry[1];\n+#define ICE_AQC_FW_LOG_ID_S\t\t0\n+#define ICE_AQC_FW_LOG_ID_M\t\t(0xFFF << ICE_AQC_FW_LOG_ID_S)\n+\n+#define ICE_AQC_FW_LOG_CONF_SUCCESS\t0\t/* Used by response */\n+#define ICE_AQC_FW_LOG_CONF_BAD_INDX\tBIT(12)\t/* Used by response */\n+\n+#define ICE_AQC_FW_LOG_EN_S\t\t12\n+#define ICE_AQC_FW_LOG_EN_M\t\t(0xF << ICE_AQC_FW_LOG_EN_S)\n+#define ICE_AQC_FW_LOG_INFO_EN\t\tBIT(12)\t/* Used by command */\n+#define ICE_AQC_FW_LOG_INIT_EN\t\tBIT(13)\t/* Used by command */\n+#define ICE_AQC_FW_LOG_FLOW_EN\t\tBIT(14)\t/* Used by command */\n+#define ICE_AQC_FW_LOG_ERR_EN\t\tBIT(15)\t/* Used by command */\n+};\n+\n+\n+/* Get/Clear FW Log (indirect 0xFF11) */\n+struct ice_aqc_get_clear_fw_log {\n+\tu8 flags;\n+#define ICE_AQC_FW_LOG_CLEAR\t\tBIT(0)\n+#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL\tBIT(1)\n+\tu8 rsvd1[7];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/**\n+ * struct ice_aq_desc - Admin Queue (AQ) descriptor\n+ * @flags: ICE_AQ_FLAG_* flags\n+ * @opcode: AQ command opcode\n+ * @datalen: length in bytes of indirect/external data buffer\n+ * @retval: return value from firmware\n+ * @cookie_h: opaque data high-half\n+ * @cookie_l: opaque data low-half\n+ * @params: command-specific parameters\n+ *\n+ * Descriptor format for commands the driver posts on the Admin Transmit Queue\n+ * (ATQ). The firmware writes back onto the command descriptor and returns\n+ * the result of the command. Asynchronous events that are not an immediate\n+ * result of the command are written to the Admin Receive Queue (ARQ) using\n+ * the same descriptor format. Descriptors are in little-endian notation with\n+ * 32-bit words.\n+ */\n+struct ice_aq_desc {\n+\t__le16 flags;\n+\t__le16 opcode;\n+\t__le16 datalen;\n+\t__le16 retval;\n+\t__le32 cookie_high;\n+\t__le32 cookie_low;\n+\tunion {\n+\t\tu8 raw[16];\n+\t\tstruct ice_aqc_generic generic;\n+\t\tstruct ice_aqc_get_ver get_ver;\n+\t\tstruct ice_aqc_q_shutdown q_shutdown;\n+\t\tstruct ice_aqc_req_res res_owner;\n+\t\tstruct ice_aqc_manage_mac_read mac_read;\n+\t\tstruct ice_aqc_manage_mac_write mac_write;\n+\t\tstruct ice_aqc_clear_pxe clear_pxe;\n+\t\tstruct ice_aqc_list_caps get_cap;\n+\t\tstruct ice_aqc_get_phy_caps get_phy;\n+\t\tstruct ice_aqc_set_phy_cfg set_phy;\n+\t\tstruct ice_aqc_restart_an restart_an;\n+\t\tstruct ice_aqc_set_port_id_led set_port_id_led;\n+\t\tstruct ice_aqc_get_sw_cfg get_sw_conf;\n+\t\tstruct ice_aqc_sw_rules sw_rules;\n+\t\tstruct ice_aqc_get_topo get_topo;\n+\t\tstruct ice_aqc_sched_elem_cmd sched_elem_cmd;\n+\t\tstruct ice_aqc_query_txsched_res query_sched_res;\n+\t\tstruct ice_aqc_query_node_to_root query_node_to_root;\n+\t\tstruct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;\n+\t\tstruct ice_aqc_rl_profile rl_profile;\n+\n+\t\tstruct ice_aqc_nvm nvm;\n+\t\tstruct ice_aqc_nvm_cfg nvm_cfg;\n+\t\tstruct ice_aqc_nvm_checksum nvm_checksum;\n+\t\tstruct ice_aqc_get_set_rss_lut get_set_rss_lut;\n+\t\tstruct ice_aqc_get_set_rss_key get_set_rss_key;\n+\t\tstruct ice_aqc_add_txqs add_txqs;\n+\t\tstruct ice_aqc_dis_txqs dis_txqs;\n+\t\tstruct ice_aqc_txqs_cleanup txqs_cleanup;\n+\t\tstruct ice_aqc_add_get_update_free_vsi vsi_cmd;\n+\t\tstruct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;\n+\t\tstruct ice_aqc_fw_logging fw_logging;\n+\t\tstruct ice_aqc_get_clear_fw_log get_clear_fw_log;\n+\t\tstruct ice_aqc_set_mac_lb set_mac_lb;\n+\t\tstruct ice_aqc_alloc_free_res_cmd sw_res_ctrl;\n+\t\tstruct ice_aqc_set_event_mask set_event_mask;\n+\t\tstruct ice_aqc_get_link_status get_link_status;\n+\t} params;\n+};\n+\n+\n+/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */\n+#define ICE_AQ_LG_BUF\t512\n+\n+/* Flags sub-structure\n+ * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |\n+ * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |\n+ */\n+\n+/* command flags and offsets */\n+#define ICE_AQ_FLAG_DD_S\t0\n+#define ICE_AQ_FLAG_CMP_S\t1\n+#define ICE_AQ_FLAG_ERR_S\t2\n+#define ICE_AQ_FLAG_VFE_S\t3\n+#define ICE_AQ_FLAG_LB_S\t9\n+#define ICE_AQ_FLAG_RD_S\t10\n+#define ICE_AQ_FLAG_VFC_S\t11\n+#define ICE_AQ_FLAG_BUF_S\t12\n+#define ICE_AQ_FLAG_SI_S\t13\n+#define ICE_AQ_FLAG_EI_S\t14\n+#define ICE_AQ_FLAG_FE_S\t15\n+\n+#define ICE_AQ_FLAG_DD\t\tBIT(ICE_AQ_FLAG_DD_S) /* 0x1 */\n+#define ICE_AQ_FLAG_CMP\t\tBIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */\n+#define ICE_AQ_FLAG_ERR\t\tBIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */\n+#define ICE_AQ_FLAG_VFE\t\tBIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */\n+#define ICE_AQ_FLAG_LB\t\tBIT(ICE_AQ_FLAG_LB_S) /* 0x200 */\n+#define ICE_AQ_FLAG_RD\t\tBIT(ICE_AQ_FLAG_RD_S) /* 0x400 */\n+#define ICE_AQ_FLAG_VFC\t\tBIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */\n+#define ICE_AQ_FLAG_BUF\t\tBIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */\n+#define ICE_AQ_FLAG_SI\t\tBIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */\n+#define ICE_AQ_FLAG_EI\t\tBIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */\n+#define ICE_AQ_FLAG_FE\t\tBIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */\n+\n+/* error codes */\n+enum ice_aq_err {\n+\tICE_AQ_RC_OK\t\t= 0, /* Success */\n+\tICE_AQ_RC_EPERM\t\t= 1, /* Operation not permitted */\n+\tICE_AQ_RC_ENOENT\t= 2, /* No such element */\n+\tICE_AQ_RC_ESRCH\t\t= 3, /* Bad opcode */\n+\tICE_AQ_RC_EINTR\t\t= 4, /* Operation interrupted */\n+\tICE_AQ_RC_EIO\t\t= 5, /* I/O error */\n+\tICE_AQ_RC_ENXIO\t\t= 6, /* No such resource */\n+\tICE_AQ_RC_E2BIG\t\t= 7, /* Arg too long */\n+\tICE_AQ_RC_EAGAIN\t= 8, /* Try again */\n+\tICE_AQ_RC_ENOMEM\t= 9, /* Out of memory */\n+\tICE_AQ_RC_EACCES\t= 10, /* Permission denied */\n+\tICE_AQ_RC_EFAULT\t= 11, /* Bad address */\n+\tICE_AQ_RC_EBUSY\t\t= 12, /* Device or resource busy */\n+\tICE_AQ_RC_EEXIST\t= 13, /* Object already exists */\n+\tICE_AQ_RC_EINVAL\t= 14, /* Invalid argument */\n+\tICE_AQ_RC_ENOTTY\t= 15, /* Not a typewriter */\n+\tICE_AQ_RC_ENOSPC\t= 16, /* No space left or allocation failure */\n+\tICE_AQ_RC_ENOSYS\t= 17, /* Function not implemented */\n+\tICE_AQ_RC_ERANGE\t= 18, /* Parameter out of range */\n+\tICE_AQ_RC_EFLUSHED\t= 19, /* Cmd flushed due to prev cmd error */\n+\tICE_AQ_RC_BAD_ADDR\t= 20, /* Descriptor contains a bad pointer */\n+\tICE_AQ_RC_EMODE\t\t= 21, /* Op not allowed in current dev mode */\n+\tICE_AQ_RC_EFBIG\t\t= 22, /* File too big */\n+\tICE_AQ_RC_ESBCOMP\t= 23, /* SB-IOSF completion unsuccessful */\n+\tICE_AQ_RC_ENOSEC\t= 24, /* Missing security manifest */\n+\tICE_AQ_RC_EBADSIG\t= 25, /* Bad RSA signature */\n+\tICE_AQ_RC_ESVN\t\t= 26, /* SVN number prohibits this package */\n+\tICE_AQ_RC_EBADMAN\t= 27, /* Manifest hash mismatch */\n+\tICE_AQ_RC_EBADBUF\t= 28, /* Buffer hash mismatches manifest */\n+};\n+\n+/* Admin Queue command opcodes */\n+enum ice_adminq_opc {\n+\t/* AQ commands */\n+\tice_aqc_opc_get_ver\t\t\t\t= 0x0001,\n+\tice_aqc_opc_driver_ver\t\t\t\t= 0x0002,\n+\tice_aqc_opc_q_shutdown\t\t\t\t= 0x0003,\n+\tice_aqc_opc_get_exp_err\t\t\t\t= 0x0005,\n+\n+\t/* resource ownership */\n+\tice_aqc_opc_req_res\t\t\t\t= 0x0008,\n+\tice_aqc_opc_release_res\t\t\t\t= 0x0009,\n+\n+\t/* device/function capabilities */\n+\tice_aqc_opc_list_func_caps\t\t\t= 0x000A,\n+\tice_aqc_opc_list_dev_caps\t\t\t= 0x000B,\n+\n+\t/* manage MAC address */\n+\tice_aqc_opc_manage_mac_read\t\t\t= 0x0107,\n+\tice_aqc_opc_manage_mac_write\t\t\t= 0x0108,\n+\n+\t/* PXE */\n+\tice_aqc_opc_clear_pxe_mode\t\t\t= 0x0110,\n+\n+\t/* internal switch commands */\n+\tice_aqc_opc_get_sw_cfg\t\t\t\t= 0x0200,\n+\n+\t/* Alloc/Free/Get Resources */\n+\tice_aqc_opc_get_res_alloc\t\t\t= 0x0204,\n+\tice_aqc_opc_alloc_res\t\t\t\t= 0x0208,\n+\tice_aqc_opc_free_res\t\t\t\t= 0x0209,\n+\tice_aqc_opc_get_allocd_res_desc\t\t\t= 0x020A,\n+\n+\t/* VSI commands */\n+\tice_aqc_opc_add_vsi\t\t\t\t= 0x0210,\n+\tice_aqc_opc_update_vsi\t\t\t\t= 0x0211,\n+\tice_aqc_opc_get_vsi_params\t\t\t= 0x0212,\n+\tice_aqc_opc_free_vsi\t\t\t\t= 0x0213,\n+\n+\n+\n+\t/* switch rules population commands */\n+\tice_aqc_opc_add_sw_rules\t\t\t= 0x02A0,\n+\tice_aqc_opc_update_sw_rules\t\t\t= 0x02A1,\n+\tice_aqc_opc_remove_sw_rules\t\t\t= 0x02A2,\n+\tice_aqc_opc_get_sw_rules\t\t\t= 0x02A3,\n+\tice_aqc_opc_clear_pf_cfg\t\t\t= 0x02A4,\n+\n+\n+\t/* transmit scheduler commands */\n+\tice_aqc_opc_get_dflt_topo\t\t\t= 0x0400,\n+\tice_aqc_opc_add_sched_elems\t\t\t= 0x0401,\n+\tice_aqc_opc_cfg_sched_elems\t\t\t= 0x0403,\n+\tice_aqc_opc_get_sched_elems\t\t\t= 0x0404,\n+\tice_aqc_opc_move_sched_elems\t\t\t= 0x0408,\n+\tice_aqc_opc_suspend_sched_elems\t\t\t= 0x0409,\n+\tice_aqc_opc_resume_sched_elems\t\t\t= 0x040A,\n+\tice_aqc_opc_suspend_sched_traffic\t\t= 0x040B,\n+\tice_aqc_opc_resume_sched_traffic\t\t= 0x040C,\n+\tice_aqc_opc_delete_sched_elems\t\t\t= 0x040F,\n+\tice_aqc_opc_add_rl_profiles\t\t\t= 0x0410,\n+\tice_aqc_opc_query_rl_profiles\t\t\t= 0x0411,\n+\tice_aqc_opc_query_sched_res\t\t\t= 0x0412,\n+\tice_aqc_opc_query_node_to_root\t\t\t= 0x0413,\n+\tice_aqc_opc_cfg_l2_node_cgd\t\t\t= 0x0414,\n+\tice_aqc_opc_remove_rl_profiles\t\t\t= 0x0415,\n+\n+\t/* PHY commands */\n+\tice_aqc_opc_get_phy_caps\t\t\t= 0x0600,\n+\tice_aqc_opc_set_phy_cfg\t\t\t\t= 0x0601,\n+\tice_aqc_opc_set_mac_cfg\t\t\t\t= 0x0603,\n+\tice_aqc_opc_restart_an\t\t\t\t= 0x0605,\n+\tice_aqc_opc_get_link_status\t\t\t= 0x0607,\n+\tice_aqc_opc_set_event_mask\t\t\t= 0x0613,\n+\tice_aqc_opc_set_mac_lb\t\t\t\t= 0x0620,\n+\tice_aqc_opc_set_port_id_led\t\t\t= 0x06E9,\n+\tice_aqc_opc_get_port_options\t\t\t= 0x06EA,\n+\tice_aqc_opc_set_port_option\t\t\t= 0x06EB,\n+\tice_aqc_opc_set_gpio\t\t\t\t= 0x06EC,\n+\tice_aqc_opc_get_gpio\t\t\t\t= 0x06ED,\n+\n+\t/* NVM commands */\n+\tice_aqc_opc_nvm_read\t\t\t\t= 0x0701,\n+\tice_aqc_opc_nvm_erase\t\t\t\t= 0x0702,\n+\tice_aqc_opc_nvm_update\t\t\t\t= 0x0703,\n+\tice_aqc_opc_nvm_cfg_read\t\t\t= 0x0704,\n+\tice_aqc_opc_nvm_cfg_write\t\t\t= 0x0705,\n+\tice_aqc_opc_nvm_checksum\t\t\t= 0x0706,\n+\n+\n+\t/* RSS commands */\n+\tice_aqc_opc_set_rss_key\t\t\t\t= 0x0B02,\n+\tice_aqc_opc_set_rss_lut\t\t\t\t= 0x0B03,\n+\tice_aqc_opc_get_rss_key\t\t\t\t= 0x0B04,\n+\tice_aqc_opc_get_rss_lut\t\t\t\t= 0x0B05,\n+\n+\t/* TX queue handling commands/events */\n+\tice_aqc_opc_add_txqs\t\t\t\t= 0x0C30,\n+\tice_aqc_opc_dis_txqs\t\t\t\t= 0x0C31,\n+\tice_aqc_opc_txqs_cleanup\t\t\t= 0x0C31,\n+\tice_aqc_opc_move_recfg_txqs\t\t\t= 0x0C32,\n+\n+\n+\n+\n+\t/* Standalone Commands/Events */\n+\tice_aqc_opc_event_lan_overflow\t\t\t= 0x1001,\n+\n+\t/* debug commands */\n+\tice_aqc_opc_fw_logging\t\t\t\t= 0xFF09,\n+\tice_aqc_opc_fw_logging_info\t\t\t= 0xFF10,\n+\tice_aqc_opc_get_clear_fw_log\t\t\t= 0xFF11\n+};\n+\n+#endif /* _ICE_ADMINQ_CMD_H_ */\n", "prefixes": [ "v5", "03/31" ] }