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GET /api/patches/48970/?format=api
{ "id": 48970, "url": "https://patches.dpdk.org/api/patches/48970/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-3-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1545032259-77179-3-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1545032259-77179-3-git-send-email-wenzhuo.lu@intel.com", "date": "2018-12-17T07:37:10", "name": "[v5,02/31] net/ice/base: add basic structures", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c6b46748ecfd53f97a7d437e358adb671e5c9f2a", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-3-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 2824, "url": "https://patches.dpdk.org/api/series/2824/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2824", "date": "2018-12-17T07:37:08", "name": "A new net PMD - ICE", "version": 5, "mbox": "https://patches.dpdk.org/series/2824/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/48970/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/48970/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 06A271B583;\n\tMon, 17 Dec 2018 08:33:00 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 0DC591B583\n\tfor <dev@dpdk.org>; Mon, 17 Dec 2018 08:32:57 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Dec 2018 23:32:56 -0800", "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby orsmga002.jf.intel.com with ESMTP; 16 Dec 2018 23:32:56 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,364,1539673200\"; d=\"scan'208\";a=\"118899066\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 17 Dec 2018 15:37:10 +0800", "Message-Id": "<1545032259-77179-3-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 02/31] net/ice/base: add basic structures", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n\nAdd the structures required by the NIC.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n---\n drivers/net/ice/base/ice_type.h | 869 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 869 insertions(+)\n create mode 100644 drivers/net/ice/base/ice_type.h", "diff": "diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nnew file mode 100644\nindex 0000000..256bf3f\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -0,0 +1,869 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_TYPE_H_\n+#define _ICE_TYPE_H_\n+\n+#define ETH_ALEN\t6\n+\n+#define ETH_HEADER_LEN\t14\n+\n+#define BIT(a) (1UL << (a))\n+#define BIT_ULL(a) (1ULL << (a))\n+\n+#define BITS_PER_BYTE\t8\n+\n+#define ICE_BYTES_PER_WORD\t2\n+#define ICE_BYTES_PER_DWORD\t4\n+#define ICE_MAX_TRAFFIC_CLASS\t8\n+\n+\n+#include \"ice_status.h\"\n+#include \"ice_hw_autogen.h\"\n+#include \"ice_devids.h\"\n+#include \"ice_osdep.h\"\n+#include \"ice_controlq.h\"\n+#include \"ice_lan_tx_rx.h\"\n+#include \"ice_flex_type.h\"\n+#include \"ice_protocol_type.h\"\n+\n+static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)\n+{\n+\treturn ice_is_bit_set(&bitmap, tc);\n+}\n+\n+#ifndef DIV_64BIT\n+#define DIV_64BIT(n, d) ((n) / (d))\n+#endif /* DIV_64BIT */\n+\n+static inline u64 round_up_64bit(u64 a, u32 b)\n+{\n+\treturn DIV_64BIT(((a) + (b) / 2), (b));\n+}\n+\n+static inline u32 ice_round_to_num(u32 N, u32 R)\n+{\n+\treturn ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :\n+\t\t((((N) + (R) - 1) / (R)) * (R)));\n+}\n+\n+/* Driver always calls main vsi_handle first */\n+#define ICE_MAIN_VSI_HANDLE\t\t0\n+\n+/* Switch from ms to the 1usec global time (this is the GTIME resolution) */\n+#define ICE_MS_TO_GTIME(time)\t\t((time) * 1000)\n+\n+/* Data type manipulation macros. */\n+#define ICE_HI_DWORD(x)\t\t((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))\n+#define ICE_LO_DWORD(x)\t\t((u32)((x) & 0xFFFFFFFF))\n+#define ICE_HI_WORD(x)\t\t((u16)(((x) >> 16) & 0xFFFF))\n+\n+/* debug masks - set these bits in hw->debug_mask to control output */\n+#define ICE_DBG_INIT\t\tBIT_ULL(1)\n+#define ICE_DBG_RELEASE\t\tBIT_ULL(2)\n+\n+#define ICE_DBG_LINK\t\tBIT_ULL(4)\n+#define ICE_DBG_PHY\t\tBIT_ULL(5)\n+#define ICE_DBG_QCTX\t\tBIT_ULL(6)\n+#define ICE_DBG_NVM\t\tBIT_ULL(7)\n+#define ICE_DBG_LAN\t\tBIT_ULL(8)\n+#define ICE_DBG_FLOW\t\tBIT_ULL(9)\n+#define ICE_DBG_DCB\t\tBIT_ULL(10)\n+#define ICE_DBG_DIAG\t\tBIT_ULL(11)\n+#define ICE_DBG_FD\t\tBIT_ULL(12)\n+#define ICE_DBG_SW\t\tBIT_ULL(13)\n+#define ICE_DBG_SCHED\t\tBIT_ULL(14)\n+\n+#define ICE_DBG_PKG\t\tBIT_ULL(16)\n+#define ICE_DBG_RES\t\tBIT_ULL(17)\n+#define ICE_DBG_AQ_MSG\t\tBIT_ULL(24)\n+#define ICE_DBG_AQ_DESC\t\tBIT_ULL(25)\n+#define ICE_DBG_AQ_DESC_BUF\tBIT_ULL(26)\n+#define ICE_DBG_AQ_CMD\t\tBIT_ULL(27)\n+#define ICE_DBG_AQ\t\t(ICE_DBG_AQ_MSG\t\t| \\\n+\t\t\t\t ICE_DBG_AQ_DESC\t| \\\n+\t\t\t\t ICE_DBG_AQ_DESC_BUF\t| \\\n+\t\t\t\t ICE_DBG_AQ_CMD)\n+\n+#define ICE_DBG_USER\t\tBIT_ULL(31)\n+#define ICE_DBG_ALL\t\t0xFFFFFFFFFFFFFFFFULL\n+\n+\n+\n+\n+\n+\n+enum ice_aq_res_ids {\n+\tICE_NVM_RES_ID = 1,\n+\tICE_SPD_RES_ID,\n+\tICE_CHANGE_LOCK_RES_ID,\n+\tICE_GLOBAL_CFG_LOCK_RES_ID\n+};\n+\n+/* FW update timeout definitions are in milliseconds */\n+#define ICE_NVM_TIMEOUT\t\t\t180000\n+#define ICE_CHANGE_LOCK_TIMEOUT\t\t1000\n+#define ICE_GLOBAL_CFG_LOCK_TIMEOUT\t3000\n+\n+enum ice_aq_res_access_type {\n+\tICE_RES_READ = 1,\n+\tICE_RES_WRITE\n+};\n+\n+struct ice_driver_ver {\n+\tu8 major_ver;\n+\tu8 minor_ver;\n+\tu8 build_ver;\n+\tu8 subbuild_ver;\n+\tu8 driver_string[32];\n+};\n+\n+enum ice_fc_mode {\n+\tICE_FC_NONE = 0,\n+\tICE_FC_RX_PAUSE,\n+\tICE_FC_TX_PAUSE,\n+\tICE_FC_FULL,\n+\tICE_FC_PFC,\n+\tICE_FC_DFLT\n+};\n+\n+enum ice_fec_mode {\n+\tICE_FEC_NONE = 0,\n+\tICE_FEC_RS,\n+\tICE_FEC_BASER,\n+\tICE_FEC_AUTO\n+};\n+\n+enum ice_set_fc_aq_failures {\n+\tICE_SET_FC_AQ_FAIL_NONE = 0,\n+\tICE_SET_FC_AQ_FAIL_GET,\n+\tICE_SET_FC_AQ_FAIL_SET,\n+\tICE_SET_FC_AQ_FAIL_UPDATE\n+};\n+\n+/* These are structs for managing the hardware information and the operations */\n+/* MAC types */\n+enum ice_mac_type {\n+\tICE_MAC_UNKNOWN = 0,\n+\tICE_MAC_GENERIC,\n+};\n+\n+/* Media Types */\n+enum ice_media_type {\n+\tICE_MEDIA_UNKNOWN = 0,\n+\tICE_MEDIA_FIBER,\n+\tICE_MEDIA_BASET,\n+\tICE_MEDIA_BACKPLANE,\n+\tICE_MEDIA_DA,\n+};\n+\n+/* Software VSI types. */\n+enum ice_vsi_type {\n+\tICE_VSI_PF = 0,\n+#ifdef ADQ_SUPPORT\n+\tICE_VSI_CHNL = 4,\n+#endif /* ADQ_SUPPORT */\n+};\n+\n+struct ice_link_status {\n+\t/* Refer to ice_aq_phy_type for bits definition */\n+\tu64 phy_type_low;\n+\tu64 phy_type_high;\n+\tu8 topo_media_conflict;\n+\tu16 max_frame_size;\n+\tu16 link_speed;\n+\tu16 req_speeds;\n+\tu8 lse_ena;\t/* Link Status Event notification */\n+\tu8 link_info;\n+\tu8 an_info;\n+\tu8 ext_info;\n+\tu8 fec_info;\n+\tu8 pacing;\n+\t/* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of\n+\t * ice_aqc_get_phy_caps structure\n+\t */\n+\tu8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];\n+};\n+\n+/* Different data queue types: These are mainly for SW consumption. */\n+enum ice_q {\n+\tICE_DATA_Q_DOORBELL,\n+\tICE_DATA_Q_CMPL,\n+\tICE_DATA_Q_QUANTA,\n+\tICE_DATA_Q_RX,\n+\tICE_DATA_Q_TX,\n+};\n+\n+/* Different reset sources for which a disable queue AQ call has to be made in\n+ * order to clean the TX scheduler as a part of the reset\n+ */\n+enum ice_disq_rst_src {\n+\tICE_NO_RESET = 0,\n+\tICE_VM_RESET,\n+};\n+\n+/* PHY info such as phy_type, etc... */\n+struct ice_phy_info {\n+\tstruct ice_link_status link_info;\n+\tstruct ice_link_status link_info_old;\n+\tu64 phy_type_low;\n+\tu64 phy_type_high;\n+\tenum ice_media_type media_type;\n+\tu8 get_link_info;\n+};\n+\n+#define ICE_MAX_NUM_MIRROR_RULES\t64\n+\n+/* Common HW capabilities for SW use */\n+struct ice_hw_common_caps {\n+\t/* Write CSR protection */\n+\tu64 wr_csr_prot;\n+\tu32 switching_mode;\n+\t/* switching mode supported - EVB switching (including cloud) */\n+#define ICE_NVM_IMAGE_TYPE_EVB\t\t0x0\n+\n+\t/* Manageablity mode & supported protocols over MCTP */\n+\tu32 mgmt_mode;\n+#define ICE_MGMT_MODE_PASS_THRU_MODE_M\t\t0xF\n+#define ICE_MGMT_MODE_CTL_INTERFACE_M\t\t0xF0\n+#define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M\t0xF00\n+\n+\tu32 mgmt_protocols_mctp;\n+#define ICE_MGMT_MODE_PROTO_RSVD\tBIT(0)\n+#define ICE_MGMT_MODE_PROTO_PLDM\tBIT(1)\n+#define ICE_MGMT_MODE_PROTO_OEM\t\tBIT(2)\n+#define ICE_MGMT_MODE_PROTO_NC_SI\tBIT(3)\n+\n+\tu32 os2bmc;\n+\tu32 valid_functions;\n+\n+\t/* RSS related capabilities */\n+\tu32 rss_table_size;\t\t/* 512 for PFs and 64 for VFs */\n+\tu32 rss_table_entry_width;\t/* RSS Entry width in bits */\n+\n+\t/* TX/RX queues */\n+\tu32 num_rxq;\t\t\t/* Number/Total RX queues */\n+\tu32 rxq_first_id;\t\t/* First queue ID for RX queues */\n+\tu32 num_txq;\t\t\t/* Number/Total TX queues */\n+\tu32 txq_first_id;\t\t/* First queue ID for TX queues */\n+\n+\t/* MSI-X vectors */\n+\tu32 num_msix_vectors;\n+\tu32 msix_vector_first_id;\n+\n+\t/* Max MTU for function or device */\n+\tu32 max_mtu;\n+\n+\t/* WOL related */\n+\tu32 num_wol_proxy_fltr;\n+\tu32 wol_proxy_vsi_seid;\n+\n+\t/* LED/SDP pin count */\n+\tu32 led_pin_num;\n+\tu32 sdp_pin_num;\n+\n+\t/* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */\n+#define ICE_MAX_SUPPORTED_GPIO_LED\t12\n+#define ICE_MAX_SUPPORTED_GPIO_SDP\t8\n+\tu8 led[ICE_MAX_SUPPORTED_GPIO_LED];\n+\tu8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];\n+\n+\t/* EVB capabilities */\n+\tu8 evb_802_1_qbg;\t\t/* Edge Virtual Bridging */\n+\tu8 evb_802_1_qbh;\t\t/* Bridge Port Extension */\n+\n+\tu8 iscsi;\n+\tu8 mgmt_cem;\n+\n+\t/* WoL and APM support */\n+#define ICE_WOL_SUPPORT_M\t\tBIT(0)\n+#define ICE_ACPI_PROG_MTHD_M\t\tBIT(1)\n+#define ICE_PROXY_SUPPORT_M\t\tBIT(2)\n+\tu8 apm_wol_support;\n+\tu8 acpi_prog_mthd;\n+\tu8 proxy_support;\n+};\n+\n+\n+/* Function specific capabilities */\n+struct ice_hw_func_caps {\n+\tstruct ice_hw_common_caps common_cap;\n+\tu32 guar_num_vsi;\n+};\n+\n+/* Device wide capabilities */\n+struct ice_hw_dev_caps {\n+\tstruct ice_hw_common_caps common_cap;\n+\tu32 num_vsi_allocd_to_host;\t/* Excluding EMP VSI */\n+};\n+\n+\n+/* Information about MAC such as address, etc... */\n+struct ice_mac_info {\n+\tu8 lan_addr[ETH_ALEN];\n+\tu8 perm_addr[ETH_ALEN];\n+\tu8 port_addr[ETH_ALEN];\n+\tu8 wol_addr[ETH_ALEN];\n+};\n+\n+/* PCI bus types */\n+enum ice_bus_type {\n+\tice_bus_unknown = 0,\n+\tice_bus_pci_express,\n+\tice_bus_embedded, /* Is device Embedded versus card */\n+\tice_bus_reserved\n+};\n+\n+/* PCI bus speeds */\n+enum ice_pcie_bus_speed {\n+\tice_pcie_speed_unknown\t= 0xff,\n+\tice_pcie_speed_2_5GT\t= 0x14,\n+\tice_pcie_speed_5_0GT\t= 0x15,\n+\tice_pcie_speed_8_0GT\t= 0x16,\n+\tice_pcie_speed_16_0GT\t= 0x17\n+};\n+\n+/* PCI bus widths */\n+enum ice_pcie_link_width {\n+\tice_pcie_lnk_width_resrv\t= 0x00,\n+\tice_pcie_lnk_x1\t\t\t= 0x01,\n+\tice_pcie_lnk_x2\t\t\t= 0x02,\n+\tice_pcie_lnk_x4\t\t\t= 0x04,\n+\tice_pcie_lnk_x8\t\t\t= 0x08,\n+\tice_pcie_lnk_x12\t\t= 0x0C,\n+\tice_pcie_lnk_x16\t\t= 0x10,\n+\tice_pcie_lnk_x32\t\t= 0x20,\n+\tice_pcie_lnk_width_unknown\t= 0xff,\n+};\n+\n+/* Reset types used to determine which kind of reset was requested. These\n+ * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.\n+ * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register\n+ * because its reset source is different than the other types listed.\n+ */\n+enum ice_reset_req {\n+\tICE_RESET_POR\t= 0,\n+\tICE_RESET_INVAL\t= 0,\n+\tICE_RESET_CORER\t= 1,\n+\tICE_RESET_GLOBR\t= 2,\n+\tICE_RESET_EMPR\t= 3,\n+\tICE_RESET_PFR\t= 4,\n+};\n+\n+/* Bus parameters */\n+struct ice_bus_info {\n+\tenum ice_pcie_bus_speed speed;\n+\tenum ice_pcie_link_width width;\n+\tenum ice_bus_type type;\n+\tu16 domain_num;\n+\tu16 device;\n+\tu8 func;\n+\tu8 bus_num;\n+};\n+\n+/* Flow control (FC) parameters */\n+struct ice_fc_info {\n+\tenum ice_fc_mode current_mode;\t/* FC mode in effect */\n+\tenum ice_fc_mode req_mode;\t/* FC mode requested by caller */\n+};\n+\n+/* NVM Information */\n+struct ice_nvm_info {\n+\tu32 eetrack;\t\t\t/* NVM data version */\n+\tu32 oem_ver;\t\t\t/* OEM version info */\n+\tu16 sr_words;\t\t\t/* Shadow RAM size in words */\n+\tu16 ver;\t\t\t/* NVM package version */\n+\tu8 blank_nvm_mode;\t\t/* is NVM empty (no FW present)*/\n+};\n+\n+/* Max number of port to queue branches w.r.t topology */\n+#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS\n+/* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects\n+ * to driver defined policy for default aggregator\n+ */\n+#define ICE_INVAL_TEID 0xFFFFFFFF\n+#define ICE_DFLT_AGG_ID 0\n+\n+struct ice_sched_node {\n+\tstruct ice_sched_node *parent;\n+\tstruct ice_sched_node *sibling; /* next sibling in the same layer */\n+\tstruct ice_sched_node **children;\n+\tstruct ice_aqc_txsched_elem_data info;\n+\tu32 agg_id;\t\t\t/* aggregator group id */\n+\tu16 vsi_handle;\n+\tu8 in_use;\t\t\t/* suspended or in use */\n+\tu8 tx_sched_layer;\t\t/* Logical Layer (1-9) */\n+\tu8 num_children;\n+\tu8 tc_num;\n+\tu8 owner;\n+#define ICE_SCHED_NODE_OWNER_LAN\t0\n+#define ICE_SCHED_NODE_OWNER_AE\t\t1\n+#define ICE_SCHED_NODE_OWNER_RDMA\t2\n+};\n+\n+/* Access Macros for Tx Sched Elements data */\n+#define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)\n+#define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)\n+#define ICE_TXSCHED_GET_CIR_RL_ID(x)\t\\\n+\tLE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)\n+#define ICE_TXSCHED_GET_EIR_RL_ID(x)\t\\\n+\tLE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)\n+#define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)\n+#define ICE_TXSCHED_GET_CIR_BWALLOC(x)\t\\\n+\tLE16_TO_CPU((x)->info.cir_bw.bw_alloc)\n+#define ICE_TXSCHED_GET_EIR_BWALLOC(x)\t\\\n+\tLE16_TO_CPU((x)->info.eir_bw.bw_alloc)\n+\n+struct ice_sched_rl_profle {\n+\tu32 rate; /* In Kbps */\n+\tstruct ice_aqc_rl_profile_elem info;\n+};\n+\n+/* The aggregator type determines if identifier is for a VSI group,\n+ * aggregator group, aggregator of queues, or queue group.\n+ */\n+enum ice_agg_type {\n+\tICE_AGG_TYPE_UNKNOWN = 0,\n+\tICE_AGG_TYPE_TC,\n+\tICE_AGG_TYPE_AGG, /* aggregator */\n+\tICE_AGG_TYPE_VSI,\n+\tICE_AGG_TYPE_QG,\n+\tICE_AGG_TYPE_Q\n+};\n+\n+/* Rate limit types */\n+enum ice_rl_type {\n+\tICE_UNKNOWN_BW = 0,\n+\tICE_MIN_BW,\t\t/* for cir profile */\n+\tICE_MAX_BW,\t\t/* for eir profile */\n+\tICE_SHARED_BW\t\t/* for shared profile */\n+};\n+\n+#define ICE_SCHED_MIN_BW\t\t500\t\t/* in Kbps */\n+#define ICE_SCHED_MAX_BW\t\t100000000\t/* in Kbps */\n+#define ICE_SCHED_DFLT_BW\t\t0xFFFFFFFF\t/* unlimited */\n+#define ICE_SCHED_NO_PRIORITY\t\t0\n+#define ICE_SCHED_NO_BW_WT\t\t0\n+#define ICE_SCHED_DFLT_RL_PROF_ID\t0\n+#define ICE_SCHED_NO_SHARED_RL_PROF_ID\t0xFFFF\n+#define ICE_SCHED_DFLT_BW_WT\t\t1\n+#define ICE_SCHED_INVAL_PROF_ID\t\t0xFFFF\n+#define ICE_SCHED_DFLT_BURST_SIZE\t(15 * 1024)\t/* in bytes (15k) */\n+\n+/* Access Macros for Tx Sched RL Profile data */\n+#define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)\n+#define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)\n+#define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)\n+#define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)\n+#define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)\n+\n+\n+/* The following tree example shows the naming conventions followed under\n+ * ice_port_info struct for default scheduler tree topology.\n+ *\n+ * A tree on a port\n+ * * ---> root node\n+ * (TC0)/ / / / \\ \\ \\ \\(TC7) ---> num_branches (range:1- 8)\n+ * * * * * * * * * |\n+ * / |\n+ * * |\n+ * / |-> num_elements (range:1 - 9)\n+ * * | implies num_of_layers\n+ * / |\n+ * (a)* |\n+ *\n+ * (a) is the last_node_teid(not of type Leaf). A leaf node is created under\n+ * (a) as child node where queues get added, add Tx/Rx queue admin commands;\n+ * need teid of (a) to add queues.\n+ *\n+ * This tree\n+ * -> has 8 branches (one for each TC)\n+ * -> First branch (TC0) has 4 elements\n+ * -> has 4 layers\n+ * -> (a) is the topmost layer node created by firmware on branch 0\n+ *\n+ * Note: Above asterisk tree covers only basic terminology and scenario.\n+ * Refer to the documentation for more info.\n+ */\n+\n+ /* Data structure for saving bw information */\n+enum ice_bw_type {\n+\tICE_BW_TYPE_PRIO,\n+\tICE_BW_TYPE_CIR,\n+\tICE_BW_TYPE_CIR_WT,\n+\tICE_BW_TYPE_EIR,\n+\tICE_BW_TYPE_EIR_WT,\n+\tICE_BW_TYPE_SHARED,\n+\tICE_BW_TYPE_CNT\t\t/* This must be last */\n+};\n+\n+struct ice_bw {\n+\tu32 bw;\n+\tu16 bw_alloc;\n+};\n+\n+struct ice_bw_type_info {\n+\tice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);\n+\tu8 generic;\n+\tstruct ice_bw cir_bw;\n+\tstruct ice_bw eir_bw;\n+\tu32 shared_bw;\n+};\n+\n+/* vsi type list entry to locate corresponding vsi/ag nodes */\n+struct ice_sched_vsi_info {\n+\tstruct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];\n+\tstruct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];\n+\tu16 max_lanq[ICE_MAX_TRAFFIC_CLASS];\n+\t/* bw_t_info saves VSI bw information */\n+\tstruct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];\n+};\n+\n+#if !defined(NO_DCB_SUPPORT) || defined(ADQ_SUPPORT)\n+/* CEE or IEEE 802.1Qaz ETS Configuration data */\n+struct ice_dcb_ets_cfg {\n+\tu8 willing;\n+\tu8 cbs;\n+\tu8 maxtcs;\n+\tu8 prio_table[ICE_MAX_TRAFFIC_CLASS];\n+\tu8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];\n+\tu8 tsatable[ICE_MAX_TRAFFIC_CLASS];\n+};\n+\n+/* CEE or IEEE 802.1Qaz PFC Configuration data */\n+struct ice_dcb_pfc_cfg {\n+\tu8 willing;\n+\tu8 mbc;\n+\tu8 pfccap;\n+\tu8 pfcena;\n+};\n+\n+/* CEE or IEEE 802.1Qaz Application Priority data */\n+struct ice_dcb_app_priority_table {\n+\tu16 prot_id;\n+\tu8 priority;\n+\tu8 selector;\n+};\n+\n+#define ICE_MAX_USER_PRIORITY\t8\n+#define ICE_DCBX_MAX_APPS\t32\n+#define ICE_LLDPDU_SIZE\t\t1500\n+#define ICE_TLV_STATUS_OPER\t0x1\n+#define ICE_TLV_STATUS_SYNC\t0x2\n+#define ICE_TLV_STATUS_ERR\t0x4\n+#define ICE_APP_PROT_ID_FCOE\t0x8906\n+#define ICE_APP_PROT_ID_ISCSI\t0x0cbc\n+#define ICE_APP_PROT_ID_FIP\t0x8914\n+#define ICE_APP_SEL_ETHTYPE\t0x1\n+#define ICE_APP_SEL_TCPIP\t0x2\n+#define ICE_CEE_APP_SEL_ETHTYPE\t0x0\n+#define ICE_CEE_APP_SEL_TCPIP\t0x1\n+\n+struct ice_dcbx_cfg {\n+\tu32 numapps;\n+\tu32 tlv_status; /* CEE mode TLV status */\n+\tstruct ice_dcb_ets_cfg etscfg;\n+\tstruct ice_dcb_ets_cfg etsrec;\n+\tstruct ice_dcb_pfc_cfg pfc;\n+\tstruct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];\n+\tu8 dcbx_mode;\n+#define ICE_DCBX_MODE_CEE\t0x1\n+#define ICE_DCBX_MODE_IEEE\t0x2\n+\tu8 app_mode;\n+#define ICE_DCBX_APPS_NON_WILLING\t0x1\n+};\n+#endif /* !NO_DCB_SUPPORT || ADQ_SUPPORT */\n+\n+struct ice_port_info {\n+\tstruct ice_sched_node *root;\t/* Root Node per Port */\n+\tstruct ice_hw *hw;\t\t/* back pointer to hw instance */\n+\tu32 last_node_teid;\t\t/* scheduler last node info */\n+\tu16 sw_id;\t\t\t/* Initial switch ID belongs to port */\n+\tu16 pf_vf_num;\n+\tu8 port_state;\n+#define ICE_SCHED_PORT_STATE_INIT\t0x0\n+#define ICE_SCHED_PORT_STATE_READY\t0x1\n+\tu16 dflt_tx_vsi_rule_id;\n+\tu16 dflt_tx_vsi_num;\n+\tu16 dflt_rx_vsi_rule_id;\n+\tu16 dflt_rx_vsi_num;\n+\tstruct ice_fc_info fc;\n+\tstruct ice_mac_info mac;\n+\tstruct ice_phy_info phy;\n+\tstruct ice_lock sched_lock;\t/* protect access to TXSched tree */\n+\t/* List contain profile id(s) and other params per layer */\n+\tstruct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n+#if !defined(NO_DCB_SUPPORT) || defined(ADQ_SUPPORT)\n+\tstruct ice_dcbx_cfg local_dcbx_cfg;\t/* Oper/Local Cfg */\n+#endif /* !NO_DCB_SUPPORT || ADQ_SUPPORT */\n+\tu8 lport;\n+#define ICE_LPORT_MASK\t\t0xff\n+\tu8 is_vf;\n+};\n+\n+struct ice_switch_info {\n+\tstruct LIST_HEAD_TYPE vsi_list_map_head;\n+\tstruct ice_sw_recipe *recp_list;\n+};\n+\n+/* FW logging configuration */\n+struct ice_fw_log_evnt {\n+\tu8 cfg : 4;\t/* New event enables to configure */\n+\tu8 cur : 4;\t/* Current/active event enables */\n+};\n+\n+struct ice_fw_log_cfg {\n+\tu8 cq_en : 1; /* FW logging is enabled via the control queue */\n+\tu8 uart_en : 1; /* FW logging is enabled via UART for all PFs */\n+\tu8 actv_evnts; /* Cumulation of currently enabled log events */\n+\n+#define ICE_FW_LOG_EVNT_INFO\t(ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)\n+#define ICE_FW_LOG_EVNT_INIT\t(ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)\n+#define ICE_FW_LOG_EVNT_FLOW\t(ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)\n+#define ICE_FW_LOG_EVNT_ERR\t(ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)\n+\tstruct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];\n+};\n+\n+/* Port hardware description */\n+struct ice_hw {\n+\tu8 *hw_addr;\n+\tvoid *back;\n+\tstruct ice_aqc_layer_props *layer_info;\n+\tstruct ice_port_info *port_info;\n+\t/* 2D Array for each Tx Sched RL Profile type */\n+\tstruct ice_sched_rl_profile **cir_profiles;\n+\tstruct ice_sched_rl_profile **eir_profiles;\n+\tstruct ice_sched_rl_profile **srl_profiles;\n+\tu64 debug_mask;\t\t/* BITMAP for debug mask */\n+\tenum ice_mac_type mac_type;\n+\n+\t/* pci info */\n+\tu16 device_id;\n+\tu16 vendor_id;\n+\tu16 subsystem_device_id;\n+\tu16 subsystem_vendor_id;\n+\tu8 revision_id;\n+\n+\tu8 pf_id;\t\t/* device profile info */\n+\n+\tu16 max_burst_size;\t/* driver sets this value */\n+\t/* TX Scheduler values */\n+\tu16 num_tx_sched_layers;\n+\tu16 num_tx_sched_phys_layers;\n+\tu8 flattened_layers;\n+\tu8 max_cgds;\n+\tu8 sw_entry_point_layer;\n+\tu16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n+\tstruct LIST_HEAD_TYPE agg_list;\t/* lists all aggregator */\n+\tstruct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];\n+\tstruct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];\n+\tu8 evb_veb;\t\t/* true for VEB, false for VEPA */\n+\tu8 reset_ongoing;\t/* true if hw is in reset, false otherwise */\n+\tstruct ice_bus_info bus;\n+\tstruct ice_nvm_info nvm;\n+\tstruct ice_hw_dev_caps dev_caps;\t/* device capabilities */\n+\tstruct ice_hw_func_caps func_caps;\t/* function capabilities */\n+\n+\tstruct ice_switch_info *switch_info;\t/* switch filter lists */\n+\n+\t/* Control Queue info */\n+\tstruct ice_ctl_q_info adminq;\n+\tstruct ice_ctl_q_info mailboxq;\n+\n+\tu8 api_branch;\t\t/* API branch version */\n+\tu8 api_maj_ver;\t\t/* API major version */\n+\tu8 api_min_ver;\t\t/* API minor version */\n+\tu8 api_patch;\t\t/* API patch version */\n+\tu8 fw_branch;\t\t/* firmware branch version */\n+\tu8 fw_maj_ver;\t\t/* firmware major version */\n+\tu8 fw_min_ver;\t\t/* firmware minor version */\n+\tu8 fw_patch;\t\t/* firmware patch version */\n+\tu32 fw_build;\t\t/* firmware build number */\n+\n+\tstruct ice_fw_log_cfg fw_log;\n+\n+/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL\n+ * register. Used for determining the itr/intrl granularity during\n+ * initialization.\n+ */\n+#define ICE_MAX_AGG_BW_200G\t0x0\n+#define ICE_MAX_AGG_BW_100G\t0X1\n+#define ICE_MAX_AGG_BW_50G\t0x2\n+#define ICE_MAX_AGG_BW_25G\t0x3\n+\t/* ITR granularity for different speeds */\n+#define ICE_ITR_GRAN_ABOVE_25\t2\n+#define ICE_ITR_GRAN_MAX_25\t4\n+\t/* ITR granularity in 1 us */\n+\tu8 itr_gran;\n+\t/* INTRL granularity for different speeds */\n+#define ICE_INTRL_GRAN_ABOVE_25\t4\n+#define ICE_INTRL_GRAN_MAX_25\t8\n+\t/* INTRL granularity in 1 us */\n+\tu8 intrl_gran;\n+\n+\tu8 ucast_shared;\t/* true if VSIs can share unicast addr */\n+\n+\n+};\n+\n+/* Statistics collected by each port, VSI, VEB, and S-channel */\n+struct ice_eth_stats {\n+\tu64 rx_bytes;\t\t\t/* gorc */\n+\tu64 rx_unicast;\t\t\t/* uprc */\n+\tu64 rx_multicast;\t\t/* mprc */\n+\tu64 rx_broadcast;\t\t/* bprc */\n+\tu64 rx_discards;\t\t/* rdpc */\n+\tu64 rx_unknown_protocol;\t/* rupp */\n+\tu64 tx_bytes;\t\t\t/* gotc */\n+\tu64 tx_unicast;\t\t\t/* uptc */\n+\tu64 tx_multicast;\t\t/* mptc */\n+\tu64 tx_broadcast;\t\t/* bptc */\n+\tu64 tx_discards;\t\t/* tdpc */\n+\tu64 tx_errors;\t\t\t/* tepc */\n+};\n+\n+#define ICE_MAX_UP\t8\n+\n+/* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */\n+struct ice_veb_up_stats {\n+\tu64 up_rx_pkts[ICE_MAX_UP];\n+\tu64 up_rx_bytes[ICE_MAX_UP];\n+\tu64 up_tx_pkts[ICE_MAX_UP];\n+\tu64 up_tx_bytes[ICE_MAX_UP];\n+};\n+\n+/* Statistics collected by the MAC */\n+struct ice_hw_port_stats {\n+\t/* eth stats collected by the port */\n+\tstruct ice_eth_stats eth;\n+\t/* additional port specific stats */\n+\tu64 tx_dropped_link_down;\t/* tdold */\n+\tu64 crc_errors;\t\t\t/* crcerrs */\n+\tu64 illegal_bytes;\t\t/* illerrc */\n+\tu64 error_bytes;\t\t/* errbc */\n+\tu64 mac_local_faults;\t\t/* mlfc */\n+\tu64 mac_remote_faults;\t\t/* mrfc */\n+\tu64 rx_len_errors;\t\t/* rlec */\n+\tu64 link_xon_rx;\t\t/* lxonrxc */\n+\tu64 link_xoff_rx;\t\t/* lxoffrxc */\n+\tu64 link_xon_tx;\t\t/* lxontxc */\n+\tu64 link_xoff_tx;\t\t/* lxofftxc */\n+\tu64 rx_size_64;\t\t\t/* prc64 */\n+\tu64 rx_size_127;\t\t/* prc127 */\n+\tu64 rx_size_255;\t\t/* prc255 */\n+\tu64 rx_size_511;\t\t/* prc511 */\n+\tu64 rx_size_1023;\t\t/* prc1023 */\n+\tu64 rx_size_1522;\t\t/* prc1522 */\n+\tu64 rx_size_big;\t\t/* prc9522 */\n+\tu64 rx_undersize;\t\t/* ruc */\n+\tu64 rx_fragments;\t\t/* rfc */\n+\tu64 rx_oversize;\t\t/* roc */\n+\tu64 rx_jabber;\t\t\t/* rjc */\n+\tu64 tx_size_64;\t\t\t/* ptc64 */\n+\tu64 tx_size_127;\t\t/* ptc127 */\n+\tu64 tx_size_255;\t\t/* ptc255 */\n+\tu64 tx_size_511;\t\t/* ptc511 */\n+\tu64 tx_size_1023;\t\t/* ptc1023 */\n+\tu64 tx_size_1522;\t\t/* ptc1522 */\n+\tu64 tx_size_big;\t\t/* ptc9522 */\n+\tu64 mac_short_pkt_dropped;\t/* mspdc */\n+};\n+\n+enum ice_sw_fwd_act_type {\n+\tICE_FWD_TO_VSI = 0,\n+\tICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */\n+\tICE_FWD_TO_Q,\n+\tICE_FWD_TO_QGRP,\n+\tICE_DROP_PACKET,\n+\tICE_INVAL_ACT\n+};\n+\n+/* Checksum and Shadow RAM pointers */\n+#define ICE_SR_NVM_CTRL_WORD\t\t\t0x00\n+#define ICE_SR_PHY_ANALOG_PTR\t\t\t0x04\n+#define ICE_SR_OPTION_ROM_PTR\t\t\t0x05\n+#define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR\t0x06\n+#define ICE_SR_AUTO_GENERATED_POINTERS_PTR\t0x07\n+#define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR\t\t0x08\n+#define ICE_SR_EMP_GLOBAL_MODULE_PTR\t\t0x09\n+#define ICE_SR_EMP_IMAGE_PTR\t\t\t0x0B\n+#define ICE_SR_PE_IMAGE_PTR\t\t\t0x0C\n+#define ICE_SR_CSR_PROTECTED_LIST_PTR\t\t0x0D\n+#define ICE_SR_MNG_CFG_PTR\t\t\t0x0E\n+#define ICE_SR_EMP_MODULE_PTR\t\t\t0x0F\n+#define ICE_SR_PBA_FLAGS\t\t\t0x15\n+#define ICE_SR_PBA_BLOCK_PTR\t\t\t0x16\n+#define ICE_SR_BOOT_CFG_PTR\t\t\t0x17\n+#define ICE_SR_NVM_WOL_CFG\t\t\t0x19\n+#define ICE_NVM_OEM_VER_OFF\t\t\t0x83\n+#define ICE_SR_NVM_DEV_STARTER_VER\t\t0x18\n+#define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR\t0x27\n+#define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR\t0x28\n+#define ICE_SR_NVM_MAP_VER\t\t\t0x29\n+#define ICE_SR_NVM_IMAGE_VER\t\t\t0x2A\n+#define ICE_SR_NVM_STRUCTURE_VER\t\t0x2B\n+#define ICE_SR_NVM_EETRACK_LO\t\t\t0x2D\n+#define ICE_SR_NVM_EETRACK_HI\t\t\t0x2E\n+#define ICE_NVM_VER_LO_SHIFT\t\t\t0\n+#define ICE_NVM_VER_LO_MASK\t\t\t(0xff << ICE_NVM_VER_LO_SHIFT)\n+#define ICE_NVM_VER_HI_SHIFT\t\t\t12\n+#define ICE_NVM_VER_HI_MASK\t\t\t(0xf << ICE_NVM_VER_HI_SHIFT)\n+#define ICE_OEM_EETRACK_ID\t\t\t0xffffffff\n+#define ICE_OEM_VER_PATCH_SHIFT\t\t\t0\n+#define ICE_OEM_VER_PATCH_MASK\t\t(0xff << ICE_OEM_VER_PATCH_SHIFT)\n+#define ICE_OEM_VER_BUILD_SHIFT\t\t\t8\n+#define ICE_OEM_VER_BUILD_MASK\t\t(0xffff << ICE_OEM_VER_BUILD_SHIFT)\n+#define ICE_OEM_VER_SHIFT\t\t\t24\n+#define ICE_OEM_VER_MASK\t\t\t(0xff << ICE_OEM_VER_SHIFT)\n+#define ICE_SR_VPD_PTR\t\t\t\t0x2F\n+#define ICE_SR_PXE_SETUP_PTR\t\t\t0x30\n+#define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR\t\t0x31\n+#define ICE_SR_NVM_ORIGINAL_EETRACK_LO\t\t0x34\n+#define ICE_SR_NVM_ORIGINAL_EETRACK_HI\t\t0x35\n+#define ICE_SR_VLAN_CFG_PTR\t\t\t0x37\n+#define ICE_SR_POR_REGS_AUTO_LOAD_PTR\t\t0x38\n+#define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR\t\t0x3A\n+#define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR\t\t0x3B\n+#define ICE_SR_CORER_REGS_AUTO_LOAD_PTR\t\t0x3C\n+#define ICE_SR_PHY_CFG_SCRIPT_PTR\t\t0x3D\n+#define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR\t\t0x3E\n+#define ICE_SR_SW_CHECKSUM_WORD\t\t\t0x3F\n+#define ICE_SR_PFA_PTR\t\t\t\t0x40\n+#define ICE_SR_1ST_SCRATCH_PAD_PTR\t\t0x41\n+#define ICE_SR_1ST_NVM_BANK_PTR\t\t\t0x42\n+#define ICE_SR_NVM_BANK_SIZE\t\t\t0x43\n+#define ICE_SR_1ND_OROM_BANK_PTR\t\t0x44\n+#define ICE_SR_OROM_BANK_SIZE\t\t\t0x45\n+#define ICE_SR_EMP_SR_SETTINGS_PTR\t\t0x48\n+#define ICE_SR_CONFIGURATION_METADATA_PTR\t0x4D\n+#define ICE_SR_IMMEDIATE_VALUES_PTR\t\t0x4E\n+\n+/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n+#define ICE_SR_VPD_SIZE_WORDS\t\t512\n+#define ICE_SR_PCIE_ALT_SIZE_WORDS\t512\n+#define ICE_SR_CTRL_WORD_1_S\t\t0x06\n+#define ICE_SR_CTRL_WORD_1_M\t\t(0x03 << ICE_SR_CTRL_WORD_1_S)\n+\n+/* Shadow RAM related */\n+#define ICE_SR_SECTOR_SIZE_IN_WORDS\t0x800\n+#define ICE_SR_BUF_ALIGNMENT\t\t4096\n+#define ICE_SR_WORDS_IN_1KB\t\t512\n+/* Checksum should be calculated such that after adding all the words,\n+ * including the checksum word itself, the sum should be 0xBABA.\n+ */\n+#define ICE_SR_SW_CHECKSUM_BASE\t\t0xBABA\n+\n+#define ICE_PBA_FLAG_DFLT\t\t0xFAFA\n+/* Hash redirection LUT for VSI - maximum array size */\n+#define ICE_VSIQF_HLUT_ARRAY_SIZE\t((VSIQF_HLUT_MAX_INDEX + 1) * 4)\n+\n+/*\n+ * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.\n+ * This is needed to determine the BAR0 space for the VFs\n+ */\n+#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0\n+#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1\n+#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2\n+\n+#endif /* _ICE_TYPE_H_ */\n", "prefixes": [ "v5", "02/31" ] }