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[ { "id": 951, "web_url": "https://patches.dpdk.org/comment/951/", "msgid": "<C37D651A908B024F974696C65296B57B0F2A780C@SHSMSX101.ccr.corp.intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/C37D651A908B024F974696C65296B57B0F2A780C@SHSMSX101.ccr.corp.intel.com", "date": "2014-09-24T10:58:25", "subject": "Re: [dpdk-dev] [PATCH] examples/vmdq: support i40e in vmdq example", "submitter": { "id": 16, "url": "https://patches.dpdk.org/api/people/16/?format=api", "name": "Huawei Xie", "email": "huawei.xie@intel.com" }, "content": "This patch depends on \"[dpdk-dev] [PATCH 0/6] i40e VMDQ support\"\n\n> -----Original Message-----\n> From: Xie, Huawei\n> Sent: Wednesday, September 24, 2014 6:54 PM\n> To: dev@dpdk.org\n> Cc: Xie, Huawei\n> Subject: [PATCH] examples/vmdq: support i40e in vmdq example\n> \n> This patch supports i40e in vmdq example.\n> 1. queue index is added by vmdq queue base in rte_eth_rx_burst.\n> 2. pool index is added by vmdq pool base when mac address is added to pools.\n> 3. add some error message print\n> Besides, due to some limitation in PMD,\n> 1. mac addresses are needed to be pre-allocated to VMDQ pools.\n> 2. ports are started before mac allocation.\n> \n> Signed-off-by: Huawei Xie <huawei.xie@intel.com>\n> Acked-by: Chen Jing D(Mark) <jing.d.chen@intel.com>\n> Acked-by: Jijiang Liu <jijiang.liu@intel.com>\n> Acked-by: Changchun Ouyang <changchun.ouyang.intel.com>\n> ---\n> examples/vmdq/main.c | 162 ++++++++++++++++++++++++++++++---------------\n> ------\n> 1 file changed, 97 insertions(+), 65 deletions(-)\n> \n> diff --git a/examples/vmdq/main.c b/examples/vmdq/main.c\n> index 35df234..a7ffdef 100644\n> --- a/examples/vmdq/main.c\n> +++ b/examples/vmdq/main.c\n> @@ -194,6 +194,13 @@ const uint16_t vlan_tags[] = {\n> \t48, 49, 50, 51, 52, 53, 54, 55,\n> \t56, 57, 58, 59, 60, 61, 62, 63,\n> };\n> +const uint16_t num_vlans = RTE_DIM(vlan_tags);\n> +static uint16_t num_pf_queues, num_vmdq_queues;\n> +static uint16_t vmdq_pool_base, vmdq_queue_base;\n> +/* pool mac addr template, pool mac addr is like: 52 54 00 12 port# pool# */\n> +static struct ether_addr pool_addr_template = {\n> +\t.addr_bytes = {0x52, 0x54, 0x00, 0x12, 0x00, 0x00}\n> +};\n> \n> /* ethernet addresses of ports */\n> static struct ether_addr vmdq_ports_eth_addr[RTE_MAX_ETHPORTS];\n> @@ -213,22 +220,9 @@ get_eth_conf(struct rte_eth_conf *eth_conf, uint32_t\n> num_pools)\n> \tunsigned i;\n> \n> \tconf.nb_queue_pools = (enum rte_eth_nb_pools)num_pools;\n> +\tconf.nb_pool_maps = num_pools;\n> \tconf.enable_default_pool = 0;\n> \tconf.default_pool = 0; /* set explicit value, even if not used */\n> -\tswitch (num_pools) {\n> -\t/* For 10G NIC like 82599, 128 is valid for queue number */\n> -\tcase MAX_POOL_NUM_10G:\n> -\t\tnum_queues = MAX_QUEUE_NUM_10G;\n> -\t\tconf.nb_pool_maps = MAX_POOL_MAP_NUM_10G;\n> -\t\tbreak;\n> -\t/* For 1G NIC like i350, 82580 and 82576, 8 is valid for queue number */\n> -\tcase MAX_POOL_NUM_1G:\n> -\t\tnum_queues = MAX_QUEUE_NUM_1G;\n> -\t\tconf.nb_pool_maps = MAX_POOL_MAP_NUM_1G;\n> -\t\tbreak;\n> -\tdefault:\n> -\t\treturn -1;\n> -\t}\n> \n> \tfor (i = 0; i < conf.nb_pool_maps; i++){\n> \t\tconf.pool_map[i].vlan_id = vlan_tags[ i ];\n> @@ -242,40 +236,6 @@ get_eth_conf(struct rte_eth_conf *eth_conf, uint32_t\n> num_pools)\n> }\n> \n> /*\n> - * Validate the pool number accrording to the max pool number gotten form\n> dev_info\n> - * If the pool number is invalid, give the error message and return -1\n> - */\n> -static inline int\n> -validate_num_pools(uint32_t max_nb_pools)\n> -{\n> -\tif (num_pools > max_nb_pools) {\n> -\t\tprintf(\"invalid number of pools\\n\");\n> -\t\treturn -1;\n> -\t}\n> -\n> -\tswitch (max_nb_pools) {\n> -\t/* For 10G NIC like 82599, 64 is valid for pool number */\n> -\tcase MAX_POOL_NUM_10G:\n> -\t\tif (num_pools != MAX_POOL_NUM_10G) {\n> -\t\t\tprintf(\"invalid number of pools\\n\");\n> -\t\t\treturn -1;\n> -\t\t}\n> -\t\tbreak;\n> -\t/* For 1G NIC like i350, 82580 and 82576, 8 is valid for pool number */\n> -\tcase MAX_POOL_NUM_1G:\n> -\t\tif (num_pools != MAX_POOL_NUM_1G) {\n> -\t\t\tprintf(\"invalid number of pools\\n\");\n> -\t\t\treturn -1;\n> -\t\t}\n> -\t\tbreak;\n> -\tdefault:\n> -\t\treturn -1;\n> -\t}\n> -\n> -\treturn 0;\n> -}\n> -\n> -/*\n> * Initialises a given port using global settings and with the rx buffers\n> * coming from the mbuf_pool passed as parameter\n> */\n> @@ -284,26 +244,55 @@ port_init(uint8_t port, struct rte_mempool\n> *mbuf_pool)\n> {\n> \tstruct rte_eth_dev_info dev_info;\n> \tstruct rte_eth_conf port_conf;\n> -\tuint16_t rxRings, txRings = (uint16_t)rte_lcore_count();\n> +\tuint16_t rxRings, txRings;\n> \tconst uint16_t rxRingSize = RTE_TEST_RX_DESC_DEFAULT, txRingSize =\n> RTE_TEST_TX_DESC_DEFAULT;\n> \tint retval;\n> \tuint16_t q;\n> +\tuint16_t queues_per_pool;\n> \tuint32_t max_nb_pools;\n> \n> \t/* The max pool number from dev_info will be used to validate the pool\n> number specified in cmd line */\n> \trte_eth_dev_info_get (port, &dev_info);\n> \tmax_nb_pools = (uint32_t)dev_info.max_vmdq_pools;\n> -\tretval = validate_num_pools(max_nb_pools);\n> -\tif (retval < 0)\n> -\t\treturn retval;\n> +\tif (num_pools != max_nb_pools) {\n> +\t\tprintf(\"num_pools %d != max_nb_pools %d! Currently we only\"\n> +\t\t\t\"support configuring all vmdq pools\\n\",\n> +\t\t\tnum_pools, max_nb_pools);\n> +\t\treturn -1;\n> +\t}\n> \n> \tretval = get_eth_conf(&port_conf, num_pools);\n> \tif (retval < 0)\n> \t\treturn retval;\n> \n> +\t/*\n> +\t * NIC queues are divided into pf queues and vmdq queues.\n> +\t */\n> +\t/* There is assumption here all ports have the same configuration */\n> +\tnum_pf_queues = dev_info.max_rx_queues -\n> dev_info.vmdq_queue_num;\n> +\tqueues_per_pool = dev_info.vmdq_queue_num /\n> dev_info.max_vmdq_pools;\n> +\tnum_vmdq_queues = num_pools * queues_per_pool;\n> +\tnum_queues = num_pf_queues + num_vmdq_queues;\n> +\tvmdq_queue_base = dev_info.vmdq_queue_base;\n> +\tvmdq_pool_base = dev_info.vmdq_pool_base;\n> +\n> +\tprintf(\"pf queue num: %u, configured vmdq pool num: %u,\"\n> +\t\t\" each vmdq pool has %u queues\\n\",\n> +\t\tnum_pf_queues, num_pools, queues_per_pool);\n> +\tprintf(\"vmdq queue base: %d pool base %d\\n\",\n> +\t\tvmdq_queue_base, vmdq_pool_base);\n> \tif (port >= rte_eth_dev_count()) return -1;\n> \n> -\trxRings = (uint16_t)num_queues,\n> +\t/*\n> +\t * Though in this example, we only receive packets from the first queue\n> +\t * of each pool and send packets through first rte_lcore_count() tx\n> +\t * queues of vmdq queues, all queues including pf queues are setup.\n> +\t * This is because VMDQ queues doesn't always start from zero, and the\n> +\t * PMD layer doesn't support selectively initialising part of rx/tx\n> +\t * queues well.\n> +\t */\n> +\trxRings = (uint16_t)dev_info.max_rx_queues;\n> +\ttxRings = (uint16_t)dev_info.max_tx_queues;\n> \tretval = rte_eth_dev_configure(port, rxRings, txRings, &port_conf);\n> \tif (retval != 0)\n> \t\treturn retval;\n> @@ -312,20 +301,26 @@ port_init(uint8_t port, struct rte_mempool\n> *mbuf_pool)\n> \t\tretval = rte_eth_rx_queue_setup(port, q, rxRingSize,\n> \t\t\t\t\t\trte_eth_dev_socket_id(port),\n> &rx_conf_default,\n> \t\t\t\t\t\tmbuf_pool);\n> -\t\tif (retval < 0)\n> +\t\tif (retval < 0) {\n> +\t\t\tprintf(\"initialise rx queue %d failed\\n\", q);\n> \t\t\treturn retval;\n> +\t\t}\n> \t}\n> \n> \tfor (q = 0; q < txRings; q ++) {\n> \t\tretval = rte_eth_tx_queue_setup(port, q, txRingSize,\n> \t\t\t\t\t\trte_eth_dev_socket_id(port),\n> &tx_conf_default);\n> -\t\tif (retval < 0)\n> +\t\tif (retval < 0) {\n> +\t\t\tprintf(\"initialise tx queue %d failed\\n\", q);\n> \t\t\treturn retval;\n> +\t\t}\n> \t}\n> \n> \tretval = rte_eth_dev_start(port);\n> -\tif (retval < 0)\n> +\tif (retval < 0) {\n> +\t\tprintf(\"port %d start failed\\n\", port);\n> \t\treturn retval;\n> +\t}\n> \n> \trte_eth_macaddr_get(port, &vmdq_ports_eth_addr[port]);\n> \tprintf(\"Port %u MAC: %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\n> @@ -338,6 +333,25 @@ port_init(uint8_t port, struct rte_mempool\n> *mbuf_pool)\n> \t\t\tvmdq_ports_eth_addr[port].addr_bytes[4],\n> \t\t\tvmdq_ports_eth_addr[port].addr_bytes[5]);\n> \n> +\t/* Set mac for each pool */\n> +\tfor (q = 0; q < num_pools; q++) {\n> +\t\tstruct ether_addr mac;\n> +\t\tmac = pool_addr_template;\n> +\t\tmac.addr_bytes[4] = port;\n> +\t\tmac.addr_bytes[5] = q;\n> +\t\tprintf(\"Port %u vmdq pool %u set\n> mac %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n> +\t\t\tport, q,\n> +\t\t\tmac.addr_bytes[0], mac.addr_bytes[1],\n> +\t\t\tmac.addr_bytes[2], mac.addr_bytes[3],\n> +\t\t\tmac.addr_bytes[4], mac.addr_bytes[5]);\n> +\t\tretval = rte_eth_dev_mac_addr_add(port, &mac,\n> +\t\t\t\tq + vmdq_pool_base);\n> +\t\tif (retval) {\n> +\t\t\tprintf(\"mac addr add failed at pool %d\\n\", q);\n> +\t\t\treturn retval;\n> +\t\t}\n> +\t}\n> +\n> \treturn 0;\n> }\n> \n> @@ -353,6 +367,11 @@ vmdq_parse_num_pools(const char *q_arg)\n> \tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n> \t\treturn -1;\n> \n> +\tif (num_pools > num_vlans) {\n> +\t\tprintf(\"num_pools %d > num_vlans %d\\n\", num_pools,\n> num_vlans);\n> +\t\treturn -1;\n> +\t}\n> +\n> \tnum_pools = n;\n> \n> \treturn 0;\n> @@ -481,7 +500,7 @@ lcore_main(__attribute__((__unused__)) void* dummy)\n> \tuint16_t core_id = 0;\n> \tuint16_t startQueue, endQueue;\n> \tuint16_t q, i, p;\n> -\tconst uint16_t remainder = (uint16_t)(num_queues % num_cores);\n> +\tconst uint16_t remainder = (uint16_t)(num_vmdq_queues % num_cores);\n> \n> \tfor (i = 0; i < num_cores; i ++)\n> \t\tif (lcore_ids[i] == lcore_id) {\n> @@ -491,17 +510,27 @@ lcore_main(__attribute__((__unused__)) void*\n> dummy)\n> \n> \tif (remainder != 0) {\n> \t\tif (core_id < remainder) {\n> -\t\t\tstartQueue = (uint16_t)(core_id *\n> (num_queues/num_cores + 1));\n> -\t\t\tendQueue = (uint16_t)(startQueue +\n> (num_queues/num_cores) + 1);\n> +\t\t\tstartQueue = (uint16_t)(core_id *\n> +\t\t\t\t\t(num_vmdq_queues / num_cores + 1));\n> +\t\t\tendQueue = (uint16_t)(startQueue +\n> +\t\t\t\t\t(num_vmdq_queues / num_cores) + 1);\n> \t\t} else {\n> -\t\t\tstartQueue = (uint16_t)(core_id *\n> (num_queues/num_cores) + remainder);\n> -\t\t\tendQueue = (uint16_t)(startQueue +\n> (num_queues/num_cores));\n> +\t\t\tstartQueue = (uint16_t)(core_id *\n> +\t\t\t\t\t(num_vmdq_queues / num_cores) +\n> +\t\t\t\t\tremainder);\n> +\t\t\tendQueue = (uint16_t)(startQueue +\n> +\t\t\t\t\t(num_vmdq_queues / num_cores));\n> \t\t}\n> \t} else {\n> -\t\tstartQueue = (uint16_t)(core_id * (num_queues/num_cores));\n> -\t\tendQueue = (uint16_t)(startQueue + (num_queues/num_cores));\n> +\t\tstartQueue = (uint16_t)(core_id *\n> +\t\t\t\t(num_vmdq_queues / num_cores));\n> +\t\tendQueue = (uint16_t)(startQueue +\n> +\t\t\t\t(num_vmdq_queues / num_cores));\n> \t}\n> \n> +\t/* vmdq queue idx doesn't always start from zero.*/\n> +\tstartQueue += vmdq_queue_base;\n> +\tendQueue += vmdq_queue_base;\n> \tprintf(\"core %u(lcore %u) reading queues %i-%i\\n\", (unsigned)core_id,\n> \t\t(unsigned)lcore_id, startQueue, endQueue - 1);\n> \n> @@ -533,8 +562,11 @@ lcore_main(__attribute__((__unused__)) void* dummy)\n> \t\t\t\tfor (i = 0; i < rxCount; i++)\n> \t\t\t\t\tupdate_mac_address(buf[i], dport);\n> \n> -\t\t\t\tconst uint16_t txCount =\n> rte_eth_tx_burst(dport,\n> -\t\t\t\t\tcore_id, buf, rxCount);\n> +\t\t\t\tconst uint16_t txCount = rte_eth_tx_burst(\n> +\t\t\t\t\tdport,\n> +\t\t\t\t\tvmdq_queue_base + core_id,\n> +\t\t\t\t\tbuf,\n> +\t\t\t\t\trxCount);\n> \n> \t\t\t\tif (txCount != rxCount) {\n> \t\t\t\t\tfor (i = txCount; i < rxCount; i++)\n> --\n> 1.8.1.4", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 92A9AB373;\n\tWed, 24 Sep 2014 12:52:24 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 7DAD6B346\n\tfor <dev@dpdk.org>; Wed, 24 Sep 2014 12:52:22 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga101.fm.intel.com with ESMTP; 24 Sep 2014 03:58:34 -0700", "from fmsmsx108.amr.corp.intel.com ([10.18.124.206])\n\tby fmsmga001.fm.intel.com with ESMTP; 24 Sep 2014 03:58:33 -0700", "from fmsmsx151.amr.corp.intel.com (10.18.125.4) by\n\tFMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP\n\tServer (TLS) id 14.3.195.1; Wed, 24 Sep 2014 03:58:33 -0700", "from shsmsx152.ccr.corp.intel.com (10.239.6.52) by\n\tFMSMSX151.amr.corp.intel.com (10.18.125.4) with Microsoft SMTP Server\n\t(TLS) id 14.3.195.1; Wed, 24 Sep 2014 03:58:27 -0700", "from shsmsx101.ccr.corp.intel.com ([169.254.1.203]) by\n\tSHSMSX152.ccr.corp.intel.com ([169.254.6.190]) with mapi id\n\t14.03.0195.001; Wed, 24 Sep 2014 18:58:25 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,588,1406617200\"; d=\"scan'208\";a=\"596117801\"", "From": "\"Xie, Huawei\" <huawei.xie@intel.com>", "To": "\"dev@dpdk.org\" <dev@dpdk.org>", "Thread-Topic": "[PATCH] examples/vmdq: support i40e in vmdq example", "Thread-Index": "AQHP1+XYW0yODSm1jE6fig+4eGw535wQHQew", "Date": "Wed, 24 Sep 2014 10:58:25 +0000", "Message-ID": "<C37D651A908B024F974696C65296B57B0F2A780C@SHSMSX101.ccr.corp.intel.com>", "References": "<1411556015-27518-1-git-send-email-huawei.xie@intel.com>\n\t<1411556015-27518-2-git-send-email-huawei.xie@intel.com>", "In-Reply-To": "<1411556015-27518-2-git-send-email-huawei.xie@intel.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-originating-ip": "[10.239.127.40]", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "Subject": "Re: [dpdk-dev] [PATCH] examples/vmdq: support i40e in vmdq example", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "addressed": null }, { "id": 952, "web_url": "https://patches.dpdk.org/comment/952/", "msgid": "<C37D651A908B024F974696C65296B57B0F2A7828@SHSMSX101.ccr.corp.intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/C37D651A908B024F974696C65296B57B0F2A7828@SHSMSX101.ccr.corp.intel.com", "date": "2014-09-24T11:01:41", "subject": "Re: [dpdk-dev] [PATCH] examples/vmdq: support i40e in vmdq example", "submitter": { "id": 16, "url": "https://patches.dpdk.org/api/people/16/?format=api", "name": "Huawei Xie", "email": "huawei.xie@intel.com" }, "content": "> -----Original Message-----\n> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Xie, Huawei\n> Sent: Wednesday, September 24, 2014 6:58 PM\n> To: dev@dpdk.org\n> Subject: Re: [dpdk-dev] [PATCH] examples/vmdq: support i40e in vmdq example\n> \n> This patch depends on \"[dpdk-dev] [PATCH 0/6] i40e VMDQ support\"\n> \n> > -----Original Message-----\n> > From: Xie, Huawei\n> > Sent: Wednesday, September 24, 2014 6:54 PM\n> > To: dev@dpdk.org\n> > Cc: Xie, Huawei\n> > Subject: [PATCH] examples/vmdq: support i40e in vmdq example\n> >\n> > This patch supports i40e in vmdq example.\n> > 1. queue index is added by vmdq queue base in rte_eth_rx_burst.\n> > 2. pool index is added by vmdq pool base when mac address is added to pools.\n> > 3. add some error message print\n> > Besides, due to some limitation in PMD,\n> > 1. mac addresses are needed to be pre-allocated to VMDQ pools.\n> > 2. ports are started before mac allocation.\n> >\n> > Signed-off-by: Huawei Xie <huawei.xie@intel.com>\n> > Acked-by: Chen Jing D(Mark) <jing.d.chen@intel.com>\n> > Acked-by: Jijiang Liu <jijiang.liu@intel.com>\n> > Acked-by: Changchun Ouyang <changchun.ouyang.intel.com>\nSorry, there is typo error, changchun.ouyang@intel.com\n> > ---\n> > examples/vmdq/main.c | 162 ++++++++++++++++++++++++++++++-------------\n> --\n> > ------\n> > 1 file changed, 97 insertions(+), 65 deletions(-)\n> >\n> > diff --git a/examples/vmdq/main.c b/examples/vmdq/main.c\n> > index 35df234..a7ffdef 100644\n> > --- a/examples/vmdq/main.c\n> > +++ b/examples/vmdq/main.c\n> > @@ -194,6 +194,13 @@ const uint16_t vlan_tags[] = {\n> > \t48, 49, 50, 51, 52, 53, 54, 55,\n> > \t56, 57, 58, 59, 60, 61, 62, 63,\n> > };\n> > +const uint16_t num_vlans = RTE_DIM(vlan_tags);\n> > +static uint16_t num_pf_queues, num_vmdq_queues;\n> > +static uint16_t vmdq_pool_base, vmdq_queue_base;\n> > +/* pool mac addr template, pool mac addr is like: 52 54 00 12 port# pool# */\n> > +static struct ether_addr pool_addr_template = {\n> > +\t.addr_bytes = {0x52, 0x54, 0x00, 0x12, 0x00, 0x00}\n> > +};\n> >\n> > /* ethernet addresses of ports */\n> > static struct ether_addr vmdq_ports_eth_addr[RTE_MAX_ETHPORTS];\n> > @@ -213,22 +220,9 @@ get_eth_conf(struct rte_eth_conf *eth_conf,\n> uint32_t\n> > num_pools)\n> > \tunsigned i;\n> >\n> > \tconf.nb_queue_pools = (enum rte_eth_nb_pools)num_pools;\n> > +\tconf.nb_pool_maps = num_pools;\n> > \tconf.enable_default_pool = 0;\n> > \tconf.default_pool = 0; /* set explicit value, even if not used */\n> > -\tswitch (num_pools) {\n> > -\t/* For 10G NIC like 82599, 128 is valid for queue number */\n> > -\tcase MAX_POOL_NUM_10G:\n> > -\t\tnum_queues = MAX_QUEUE_NUM_10G;\n> > -\t\tconf.nb_pool_maps = MAX_POOL_MAP_NUM_10G;\n> > -\t\tbreak;\n> > -\t/* For 1G NIC like i350, 82580 and 82576, 8 is valid for queue number */\n> > -\tcase MAX_POOL_NUM_1G:\n> > -\t\tnum_queues = MAX_QUEUE_NUM_1G;\n> > -\t\tconf.nb_pool_maps = MAX_POOL_MAP_NUM_1G;\n> > -\t\tbreak;\n> > -\tdefault:\n> > -\t\treturn -1;\n> > -\t}\n> >\n> > \tfor (i = 0; i < conf.nb_pool_maps; i++){\n> > \t\tconf.pool_map[i].vlan_id = vlan_tags[ i ];\n> > @@ -242,40 +236,6 @@ get_eth_conf(struct rte_eth_conf *eth_conf,\n> uint32_t\n> > num_pools)\n> > }\n> >\n> > /*\n> > - * Validate the pool number accrording to the max pool number gotten form\n> > dev_info\n> > - * If the pool number is invalid, give the error message and return -1\n> > - */\n> > -static inline int\n> > -validate_num_pools(uint32_t max_nb_pools)\n> > -{\n> > -\tif (num_pools > max_nb_pools) {\n> > -\t\tprintf(\"invalid number of pools\\n\");\n> > -\t\treturn -1;\n> > -\t}\n> > -\n> > -\tswitch (max_nb_pools) {\n> > -\t/* For 10G NIC like 82599, 64 is valid for pool number */\n> > -\tcase MAX_POOL_NUM_10G:\n> > -\t\tif (num_pools != MAX_POOL_NUM_10G) {\n> > -\t\t\tprintf(\"invalid number of pools\\n\");\n> > -\t\t\treturn -1;\n> > -\t\t}\n> > -\t\tbreak;\n> > -\t/* For 1G NIC like i350, 82580 and 82576, 8 is valid for pool number */\n> > -\tcase MAX_POOL_NUM_1G:\n> > -\t\tif (num_pools != MAX_POOL_NUM_1G) {\n> > -\t\t\tprintf(\"invalid number of pools\\n\");\n> > -\t\t\treturn -1;\n> > -\t\t}\n> > -\t\tbreak;\n> > -\tdefault:\n> > -\t\treturn -1;\n> > -\t}\n> > -\n> > -\treturn 0;\n> > -}\n> > -\n> > -/*\n> > * Initialises a given port using global settings and with the rx buffers\n> > * coming from the mbuf_pool passed as parameter\n> > */\n> > @@ -284,26 +244,55 @@ port_init(uint8_t port, struct rte_mempool\n> > *mbuf_pool)\n> > {\n> > \tstruct rte_eth_dev_info dev_info;\n> > \tstruct rte_eth_conf port_conf;\n> > -\tuint16_t rxRings, txRings = (uint16_t)rte_lcore_count();\n> > +\tuint16_t rxRings, txRings;\n> > \tconst uint16_t rxRingSize = RTE_TEST_RX_DESC_DEFAULT, txRingSize =\n> > RTE_TEST_TX_DESC_DEFAULT;\n> > \tint retval;\n> > \tuint16_t q;\n> > +\tuint16_t queues_per_pool;\n> > \tuint32_t max_nb_pools;\n> >\n> > \t/* The max pool number from dev_info will be used to validate the pool\n> > number specified in cmd line */\n> > \trte_eth_dev_info_get (port, &dev_info);\n> > \tmax_nb_pools = (uint32_t)dev_info.max_vmdq_pools;\n> > -\tretval = validate_num_pools(max_nb_pools);\n> > -\tif (retval < 0)\n> > -\t\treturn retval;\n> > +\tif (num_pools != max_nb_pools) {\n> > +\t\tprintf(\"num_pools %d != max_nb_pools %d! Currently we only\"\n> > +\t\t\t\"support configuring all vmdq pools\\n\",\n> > +\t\t\tnum_pools, max_nb_pools);\n> > +\t\treturn -1;\n> > +\t}\n> >\n> > \tretval = get_eth_conf(&port_conf, num_pools);\n> > \tif (retval < 0)\n> > \t\treturn retval;\n> >\n> > +\t/*\n> > +\t * NIC queues are divided into pf queues and vmdq queues.\n> > +\t */\n> > +\t/* There is assumption here all ports have the same configuration */\n> > +\tnum_pf_queues = dev_info.max_rx_queues -\n> > dev_info.vmdq_queue_num;\n> > +\tqueues_per_pool = dev_info.vmdq_queue_num /\n> > dev_info.max_vmdq_pools;\n> > +\tnum_vmdq_queues = num_pools * queues_per_pool;\n> > +\tnum_queues = num_pf_queues + num_vmdq_queues;\n> > +\tvmdq_queue_base = dev_info.vmdq_queue_base;\n> > +\tvmdq_pool_base = dev_info.vmdq_pool_base;\n> > +\n> > +\tprintf(\"pf queue num: %u, configured vmdq pool num: %u,\"\n> > +\t\t\" each vmdq pool has %u queues\\n\",\n> > +\t\tnum_pf_queues, num_pools, queues_per_pool);\n> > +\tprintf(\"vmdq queue base: %d pool base %d\\n\",\n> > +\t\tvmdq_queue_base, vmdq_pool_base);\n> > \tif (port >= rte_eth_dev_count()) return -1;\n> >\n> > -\trxRings = (uint16_t)num_queues,\n> > +\t/*\n> > +\t * Though in this example, we only receive packets from the first queue\n> > +\t * of each pool and send packets through first rte_lcore_count() tx\n> > +\t * queues of vmdq queues, all queues including pf queues are setup.\n> > +\t * This is because VMDQ queues doesn't always start from zero, and the\n> > +\t * PMD layer doesn't support selectively initialising part of rx/tx\n> > +\t * queues well.\n> > +\t */\n> > +\trxRings = (uint16_t)dev_info.max_rx_queues;\n> > +\ttxRings = (uint16_t)dev_info.max_tx_queues;\n> > \tretval = rte_eth_dev_configure(port, rxRings, txRings, &port_conf);\n> > \tif (retval != 0)\n> > \t\treturn retval;\n> > @@ -312,20 +301,26 @@ port_init(uint8_t port, struct rte_mempool\n> > *mbuf_pool)\n> > \t\tretval = rte_eth_rx_queue_setup(port, q, rxRingSize,\n> > \t\t\t\t\t\trte_eth_dev_socket_id(port),\n> > &rx_conf_default,\n> > \t\t\t\t\t\tmbuf_pool);\n> > -\t\tif (retval < 0)\n> > +\t\tif (retval < 0) {\n> > +\t\t\tprintf(\"initialise rx queue %d failed\\n\", q);\n> > \t\t\treturn retval;\n> > +\t\t}\n> > \t}\n> >\n> > \tfor (q = 0; q < txRings; q ++) {\n> > \t\tretval = rte_eth_tx_queue_setup(port, q, txRingSize,\n> > \t\t\t\t\t\trte_eth_dev_socket_id(port),\n> > &tx_conf_default);\n> > -\t\tif (retval < 0)\n> > +\t\tif (retval < 0) {\n> > +\t\t\tprintf(\"initialise tx queue %d failed\\n\", q);\n> > \t\t\treturn retval;\n> > +\t\t}\n> > \t}\n> >\n> > \tretval = rte_eth_dev_start(port);\n> > -\tif (retval < 0)\n> > +\tif (retval < 0) {\n> > +\t\tprintf(\"port %d start failed\\n\", port);\n> > \t\treturn retval;\n> > +\t}\n> >\n> > \trte_eth_macaddr_get(port, &vmdq_ports_eth_addr[port]);\n> > \tprintf(\"Port %u MAC: %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\n> > @@ -338,6 +333,25 @@ port_init(uint8_t port, struct rte_mempool\n> > *mbuf_pool)\n> > \t\t\tvmdq_ports_eth_addr[port].addr_bytes[4],\n> > \t\t\tvmdq_ports_eth_addr[port].addr_bytes[5]);\n> >\n> > +\t/* Set mac for each pool */\n> > +\tfor (q = 0; q < num_pools; q++) {\n> > +\t\tstruct ether_addr mac;\n> > +\t\tmac = pool_addr_template;\n> > +\t\tmac.addr_bytes[4] = port;\n> > +\t\tmac.addr_bytes[5] = q;\n> > +\t\tprintf(\"Port %u vmdq pool %u set\n> > mac %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n> > +\t\t\tport, q,\n> > +\t\t\tmac.addr_bytes[0], mac.addr_bytes[1],\n> > +\t\t\tmac.addr_bytes[2], mac.addr_bytes[3],\n> > +\t\t\tmac.addr_bytes[4], mac.addr_bytes[5]);\n> > +\t\tretval = rte_eth_dev_mac_addr_add(port, &mac,\n> > +\t\t\t\tq + vmdq_pool_base);\n> > +\t\tif (retval) {\n> > +\t\t\tprintf(\"mac addr add failed at pool %d\\n\", q);\n> > +\t\t\treturn retval;\n> > +\t\t}\n> > +\t}\n> > +\n> > \treturn 0;\n> > }\n> >\n> > @@ -353,6 +367,11 @@ vmdq_parse_num_pools(const char *q_arg)\n> > \tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n> > \t\treturn -1;\n> >\n> > +\tif (num_pools > num_vlans) {\n> > +\t\tprintf(\"num_pools %d > num_vlans %d\\n\", num_pools,\n> > num_vlans);\n> > +\t\treturn -1;\n> > +\t}\n> > +\n> > \tnum_pools = n;\n> >\n> > \treturn 0;\n> > @@ -481,7 +500,7 @@ lcore_main(__attribute__((__unused__)) void* dummy)\n> > \tuint16_t core_id = 0;\n> > \tuint16_t startQueue, endQueue;\n> > \tuint16_t q, i, p;\n> > -\tconst uint16_t remainder = (uint16_t)(num_queues % num_cores);\n> > +\tconst uint16_t remainder = (uint16_t)(num_vmdq_queues % num_cores);\n> >\n> > \tfor (i = 0; i < num_cores; i ++)\n> > \t\tif (lcore_ids[i] == lcore_id) {\n> > @@ -491,17 +510,27 @@ lcore_main(__attribute__((__unused__)) void*\n> > dummy)\n> >\n> > \tif (remainder != 0) {\n> > \t\tif (core_id < remainder) {\n> > -\t\t\tstartQueue = (uint16_t)(core_id *\n> > (num_queues/num_cores + 1));\n> > -\t\t\tendQueue = (uint16_t)(startQueue +\n> > (num_queues/num_cores) + 1);\n> > +\t\t\tstartQueue = (uint16_t)(core_id *\n> > +\t\t\t\t\t(num_vmdq_queues / num_cores + 1));\n> > +\t\t\tendQueue = (uint16_t)(startQueue +\n> > +\t\t\t\t\t(num_vmdq_queues / num_cores) + 1);\n> > \t\t} else {\n> > -\t\t\tstartQueue = (uint16_t)(core_id *\n> > (num_queues/num_cores) + remainder);\n> > -\t\t\tendQueue = (uint16_t)(startQueue +\n> > (num_queues/num_cores));\n> > +\t\t\tstartQueue = (uint16_t)(core_id *\n> > +\t\t\t\t\t(num_vmdq_queues / num_cores) +\n> > +\t\t\t\t\tremainder);\n> > +\t\t\tendQueue = (uint16_t)(startQueue +\n> > +\t\t\t\t\t(num_vmdq_queues / num_cores));\n> > \t\t}\n> > \t} else {\n> > -\t\tstartQueue = (uint16_t)(core_id * (num_queues/num_cores));\n> > -\t\tendQueue = (uint16_t)(startQueue + (num_queues/num_cores));\n> > +\t\tstartQueue = (uint16_t)(core_id *\n> > +\t\t\t\t(num_vmdq_queues / num_cores));\n> > +\t\tendQueue = (uint16_t)(startQueue +\n> > +\t\t\t\t(num_vmdq_queues / num_cores));\n> > \t}\n> >\n> > +\t/* vmdq queue idx doesn't always start from zero.*/\n> > +\tstartQueue += vmdq_queue_base;\n> > +\tendQueue += vmdq_queue_base;\n> > \tprintf(\"core %u(lcore %u) reading queues %i-%i\\n\", (unsigned)core_id,\n> > \t\t(unsigned)lcore_id, startQueue, endQueue - 1);\n> >\n> > @@ -533,8 +562,11 @@ lcore_main(__attribute__((__unused__)) void*\n> dummy)\n> > \t\t\t\tfor (i = 0; i < rxCount; i++)\n> > \t\t\t\t\tupdate_mac_address(buf[i], dport);\n> >\n> > -\t\t\t\tconst uint16_t txCount =\n> > rte_eth_tx_burst(dport,\n> > -\t\t\t\t\tcore_id, buf, rxCount);\n> > +\t\t\t\tconst uint16_t txCount = rte_eth_tx_burst(\n> > +\t\t\t\t\tdport,\n> > +\t\t\t\t\tvmdq_queue_base + core_id,\n> > +\t\t\t\t\tbuf,\n> > +\t\t\t\t\trxCount);\n> >\n> > \t\t\t\tif (txCount != rxCount) {\n> > \t\t\t\t\tfor (i = txCount; i < rxCount; i++)\n> > --\n> > 1.8.1.4", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 96D35B373;\n\tWed, 24 Sep 2014 12:55:42 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 424BBB346\n\tfor <dev@dpdk.org>; Wed, 24 Sep 2014 12:55:40 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga101.jf.intel.com with ESMTP; 24 Sep 2014 04:01:51 -0700", "from fmsmsx104.amr.corp.intel.com ([10.18.124.202])\n\tby orsmga002.jf.intel.com with ESMTP; 24 Sep 2014 04:01:50 -0700", "from fmsmsx101.amr.corp.intel.com (10.18.124.199) by\n\tfmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP\n\tServer (TLS) id 14.3.195.1; Wed, 24 Sep 2014 04:01:50 -0700", "from shsmsx104.ccr.corp.intel.com (10.239.4.70) by\n\tfmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP\n\tServer (TLS) id 14.3.195.1; Wed, 24 Sep 2014 04:01:50 -0700", "from shsmsx101.ccr.corp.intel.com ([169.254.1.203]) by\n\tSHSMSX104.ccr.corp.intel.com ([169.254.5.230]) with mapi id\n\t14.03.0195.001; Wed, 24 Sep 2014 19:01:42 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,588,1406617200\"; d=\"scan'208\";a=\"607757956\"", "From": "\"Xie, Huawei\" <huawei.xie@intel.com>", "To": "\"Xie, Huawei\" <huawei.xie@intel.com>, \"dev@dpdk.org\" <dev@dpdk.org>", "Thread-Topic": "[PATCH] examples/vmdq: support i40e in vmdq example", "Thread-Index": "AQHP1+XYW0yODSm1jE6fig+4eGw535wQHQewgAAAzdA=", "Date": "Wed, 24 Sep 2014 11:01:41 +0000", "Message-ID": "<C37D651A908B024F974696C65296B57B0F2A7828@SHSMSX101.ccr.corp.intel.com>", "References": "<1411556015-27518-1-git-send-email-huawei.xie@intel.com>\n\t<1411556015-27518-2-git-send-email-huawei.xie@intel.com>\n\t<C37D651A908B024F974696C65296B57B0F2A780C@SHSMSX101.ccr.corp.intel.com>", "In-Reply-To": "<C37D651A908B024F974696C65296B57B0F2A780C@SHSMSX101.ccr.corp.intel.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-originating-ip": "[10.239.127.40]", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "Subject": "Re: [dpdk-dev] [PATCH] examples/vmdq: support i40e in vmdq example", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "addressed": null } ]