Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/46652/?format=api
{ "id": 46652, "url": "https://patches.dpdk.org/api/patches/46652/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1539277380-17359-1-git-send-email-fiona.trahe@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1539277380-17359-1-git-send-email-fiona.trahe@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1539277380-17359-1-git-send-email-fiona.trahe@intel.com", "date": "2018-10-11T17:03:00", "name": "[v3] compress/qat: enable dynamic huffman encoding", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5845a575e69845eb957cee971e27b8297a795047", "submitter": { "id": 423, "url": "https://patches.dpdk.org/api/people/423/?format=api", "name": "Fiona Trahe", "email": "fiona.trahe@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1539277380-17359-1-git-send-email-fiona.trahe@intel.com/mbox/", "series": [ { "id": 1847, "url": "https://patches.dpdk.org/api/series/1847/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=1847", "date": "2018-10-11T17:03:00", "name": "[v3] compress/qat: enable dynamic huffman encoding", "version": 3, "mbox": "https://patches.dpdk.org/series/1847/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/46652/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/46652/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 950021B5DC;\n\tThu, 11 Oct 2018 19:03:19 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id A59E41B5D5\n\tfor <dev@dpdk.org>; Thu, 11 Oct 2018 19:03:17 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t11 Oct 2018 10:03:16 -0700", "from sivswdev01.ir.intel.com (HELO localhost.localdomain)\n\t([10.237.217.45])\n\tby fmsmga002.fm.intel.com with ESMTP; 11 Oct 2018 10:03:05 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.54,369,1534834800\"; d=\"scan'208\";a=\"94384643\"", "From": "Fiona Trahe <fiona.trahe@intel.com>", "To": "dev@dpdk.org", "Cc": "akhil.goyal@nxp.com, tomaszx.jozwiak@intel.com,\n\tarkadiuszx.kusztal@intel.com, Fiona Trahe <fiona.trahe@intel.com>", "Date": "Thu, 11 Oct 2018 18:03:00 +0100", "Message-Id": "<1539277380-17359-1-git-send-email-fiona.trahe@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "In-Reply-To": "<1538756310-13472-1-git-send-email-fiona.trahe@intel.com>", "References": "<1538756310-13472-1-git-send-email-fiona.trahe@intel.com>", "Subject": "[dpdk-dev] [PATCH v3] compress/qat: enable dynamic huffman encoding", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Enable dynamic huffman encoding in the QAT comp PMD.\n\nSigned-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>\nSigned-off-by: Fiona Trahe <fiona.trahe@intel.com>\n---\nv3 changes:\n - reverted to 1 buffer per intermediate buffer sgl\n\nv2 changes: \n - allocate 2 buffers per intermediate buffer sgl\n - Compile out trace for debugging intermediate buffers\n\n config/common_base | 1 +\n config/rte_config.h | 1 +\n doc/guides/compressdevs/features/qat.ini | 1 +\n doc/guides/compressdevs/qat_comp.rst | 7 +-\n drivers/common/qat/qat_device.c | 4 +\n drivers/common/qat/qat_device.h | 7 ++\n drivers/compress/qat/qat_comp.c | 39 +++++++---\n drivers/compress/qat/qat_comp.h | 13 ++++\n drivers/compress/qat/qat_comp_pmd.c | 123 ++++++++++++++++++++++++++++++-\n 9 files changed, 179 insertions(+), 17 deletions(-)", "diff": "diff --git a/config/common_base b/config/common_base\nindex 85fad0c..9bbce31 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -500,6 +500,7 @@ CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n\n #\n CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48\n CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16\n+CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536\n \n #\n # Compile PMD for virtio crypto devices\ndiff --git a/config/rte_config.h b/config/rte_config.h\nindex 20c58df..4e501b3 100644\n--- a/config/rte_config.h\n+++ b/config/rte_config.h\n@@ -94,6 +94,7 @@\n /* Max. number of QuickAssist devices which can be attached */\n #define RTE_PMD_QAT_MAX_PCI_DEVICES 48\n #define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16\n+#define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536\n \n /* virtio crypto defines */\n #define RTE_MAX_VIRTIO_CRYPTO 32\ndiff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini\nindex 5cd4524..6b1e7f9 100644\n--- a/doc/guides/compressdevs/features/qat.ini\n+++ b/doc/guides/compressdevs/features/qat.ini\n@@ -13,3 +13,4 @@ Adler32 = Y\n Crc32 = Y\n Adler32&Crc32 = Y\n Fixed = Y\n+Dynamic = Y\ndiff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst\nindex 7bffbe6..aee3b99 100644\n--- a/doc/guides/compressdevs/qat_comp.rst\n+++ b/doc/guides/compressdevs/qat_comp.rst\n@@ -18,11 +18,7 @@ QAT compression PMD has support for:\n \n Compression/Decompression algorithm:\n \n- * DEFLATE\n-\n-Huffman code type:\n-\n- * FIXED\n+ * DEFLATE - using Fixed and Dynamic Huffman encoding\n \n Window size support:\n \n@@ -36,7 +32,6 @@ Limitations\n -----------\n \n * Compressdev level 0, no compression, is not supported.\n-* Dynamic Huffman encoding is not yet supported.\n * Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).\n * No BSD support as BSD QAT kernel driver not available.\n \ndiff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c\nindex 6e64e22..e662e43 100644\n--- a/drivers/common/qat/qat_device.c\n+++ b/drivers/common/qat/qat_device.c\n@@ -7,6 +7,7 @@\n #include \"qat_device.h\"\n #include \"adf_transport_access_macros.h\"\n #include \"qat_sym_pmd.h\"\n+#include \"qat_comp_pmd.h\"\n \n /* Hardware device information per generation */\n __extension__\n@@ -14,15 +15,18 @@ struct qat_gen_hw_data qat_gen_config[] = {\n \t[QAT_GEN1] = {\n \t\t.dev_gen = QAT_GEN1,\n \t\t.qp_hw_data = qat_gen1_qps,\n+\t\t.comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN1\n \t},\n \t[QAT_GEN2] = {\n \t\t.dev_gen = QAT_GEN2,\n \t\t.qp_hw_data = qat_gen1_qps,\n \t\t/* gen2 has same ring layout as gen1 */\n+\t\t.comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN2\n \t},\n \t[QAT_GEN3] = {\n \t\t.dev_gen = QAT_GEN3,\n \t\t.qp_hw_data = qat_gen3_qps,\n+\t\t.comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN3\n \t},\n };\n \ndiff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h\nindex 3a71cd4..eb81c78 100644\n--- a/drivers/common/qat/qat_device.h\n+++ b/drivers/common/qat/qat_device.h\n@@ -16,6 +16,12 @@\n \n #define QAT_DEV_NAME_MAX_LEN\t64\n \n+enum qat_comp_num_im_buffers {\n+\tQAT_NUM_INTERM_BUFS_GEN1 = 12,\n+\tQAT_NUM_INTERM_BUFS_GEN2 = 20,\n+\tQAT_NUM_INTERM_BUFS_GEN3 = 20\n+};\n+\n /*\n * This struct holds all the data about a QAT pci device\n * including data about all services it supports.\n@@ -72,6 +78,7 @@ struct qat_pci_device {\n struct qat_gen_hw_data {\n \tenum qat_device_gen dev_gen;\n \tconst struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];\n+\tenum qat_comp_num_im_buffers comp_num_im_bufs_required;\n };\n \n extern struct qat_gen_hw_data qat_gen_config[];\ndiff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c\nindex b9336f3..d70c594 100644\n--- a/drivers/compress/qat/qat_comp.c\n+++ b/drivers/compress/qat/qat_comp.c\n@@ -192,7 +192,7 @@ static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,\n }\n \n static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,\n-\t\t\tconst struct rte_memzone *interm_buff_mz __rte_unused,\n+\t\t\tconst struct rte_memzone *interm_buff_mz,\n \t\t\tconst struct rte_comp_xform *xform)\n {\n \tstruct icp_qat_fw_comp_req *comp_req;\n@@ -280,10 +280,20 @@ static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,\n \t\tICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,\n \t\t\t\t\t ICP_QAT_FW_SLICE_COMP);\n \t} else if (qat_xform->qat_comp_request_type ==\n-\t\t QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {\n+\t\t\tQAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {\n \n-\t\tQAT_LOG(ERR, \"Dynamic huffman encoding not supported\");\n-\t\treturn -EINVAL;\n+\t\tICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,\n+\t\t\t\tICP_QAT_FW_SLICE_XLAT);\n+\t\tICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,\n+\t\t\t\tICP_QAT_FW_SLICE_COMP);\n+\n+\t\tICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->u2.xlt_cd_ctrl,\n+\t\t\t\tICP_QAT_FW_SLICE_DRAM_WR);\n+\t\tICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->u2.xlt_cd_ctrl,\n+\t\t\t\tICP_QAT_FW_SLICE_XLAT);\n+\n+\t\tcomp_req->u1.xlt_pars.inter_buff_ptr =\n+\t\t\t\tinterm_buff_mz->phys_addr;\n \t}\n \n #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n@@ -334,12 +344,6 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,\n \t\t\t(struct qat_comp_xform *)*private_xform;\n \n \tif (xform->type == RTE_COMP_COMPRESS) {\n-\t\tif (xform->compress.deflate.huffman ==\n-\t\t\t\tRTE_COMP_HUFFMAN_DYNAMIC) {\n-\t\t\tQAT_LOG(ERR,\n-\t\t\t\"QAT device doesn't support dynamic compression\");\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n \n \t\tif (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||\n \t\t ((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)\n@@ -347,6 +351,21 @@ qat_comp_private_xform_create(struct rte_compressdev *dev,\n \t\t\tqat_xform->qat_comp_request_type =\n \t\t\t\t\tQAT_COMP_REQUEST_FIXED_COMP_STATELESS;\n \n+\t\telse if ((xform->compress.deflate.huffman ==\n+\t\t\t\tRTE_COMP_HUFFMAN_DYNAMIC ||\n+\t\t\t\txform->compress.deflate.huffman ==\n+\t\t\t\t\t\tRTE_COMP_HUFFMAN_DEFAULT) &&\n+\t\t\t\tqat->interm_buff_mz != NULL)\n+\n+\t\t\tqat_xform->qat_comp_request_type =\n+\t\t\t\t\tQAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS;\n+\n+\t\telse {\n+\t\t\tQAT_LOG(ERR,\n+\t\t\t\t\t\"IM buffers needed for dynamic deflate. Set size in config file\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n \t\tqat_xform->checksum_type = xform->compress.chksum;\n \n \t} else {\ndiff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h\nindex 8d315ef..99a4462 100644\n--- a/drivers/compress/qat/qat_comp.h\n+++ b/drivers/compress/qat/qat_comp.h\n@@ -15,6 +15,10 @@\n #include \"icp_qat_fw_comp.h\"\n #include \"icp_qat_fw_la.h\"\n \n+#define QAT_64_BYTE_ALIGN_MASK (~0x3f)\n+#define QAT_64_BYTE_ALIGN (64)\n+#define QAT_NUM_BUFS_IN_IM_SGL 1\n+\n #define ERR_CODE_QAT_COMP_WRONG_FW -99\n \n enum qat_comp_request_type {\n@@ -24,6 +28,15 @@ enum qat_comp_request_type {\n \tREQ_COMP_END\n };\n \n+struct array_of_ptrs {\n+\tphys_addr_t pointer[0];\n+};\n+\n+struct qat_inter_sgl {\n+\tqat_sgl_hdr;\n+\tstruct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];\n+} __rte_packed __rte_cache_aligned;\n+\n struct qat_comp_sgl {\n \tqat_sgl_hdr;\n \tstruct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];\ndiff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c\nindex 63af23a..8f34682 100644\n--- a/drivers/compress/qat/qat_comp_pmd.c\n+++ b/drivers/compress/qat/qat_comp_pmd.c\n@@ -14,6 +14,7 @@ static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {\n \t\t\t\tRTE_COMP_FF_CRC32_ADLER32_CHECKSUM |\n \t\t\t\tRTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n \t\t\t\tRTE_COMP_FF_HUFFMAN_FIXED |\n+\t\t\t\tRTE_COMP_FF_HUFFMAN_DYNAMIC |\n \t\t\t\tRTE_COMP_FF_OOP_SGL_IN_SGL_OUT |\n \t\t\t\tRTE_COMP_FF_OOP_SGL_IN_LB_OUT |\n \t\t\t\tRTE_COMP_FF_OOP_LB_IN_SGL_OUT,\n@@ -112,7 +113,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \n \t/* store a link to the qp in the qat_pci_device */\n \tqat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]\n-\t\t\t\t\t\t\t= *qp_addr;\n+\t\t\t\t\t\t\t\t= *qp_addr;\n \n \tqp = (struct qat_qp *)*qp_addr;\n \n@@ -135,6 +136,101 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \treturn ret;\n }\n \n+\n+static const struct rte_memzone *\n+qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,\n+\t\t\t uint32_t buff_size)\n+{\n+\tchar inter_buff_mz_name[RTE_MEMZONE_NAMESIZE];\n+\tconst struct rte_memzone *memzone;\n+\tuint8_t *mz_start = NULL;\n+\tphys_addr_t mz_start_phys = 0;\n+\tstruct array_of_ptrs *array_of_pointers;\n+\tint size_of_ptr_array;\n+\tuint32_t full_size;\n+\tuint32_t offset_of_sgls, offset_of_flat_buffs = 0;\n+\tint i;\n+\tint num_im_sgls = qat_gen_config[\n+\t\tcomp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required;\n+\n+\tQAT_LOG(DEBUG, \"QAT COMP device %s needs %d sgls\",\n+\t\t\t\tcomp_dev->qat_dev->name, num_im_sgls);\n+\tsnprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,\n+\t\t\t\t\"%s_inter_buff\", comp_dev->qat_dev->name);\n+\tmemzone = rte_memzone_lookup(inter_buff_mz_name);\n+\tif (memzone != NULL) {\n+\t\tQAT_LOG(DEBUG, \"QAT COMP im buffer memzone created already\");\n+\t\treturn memzone;\n+\t}\n+\n+\t/* Create a memzone to hold intermediate buffers and associated\n+\t * meta-data needed by the firmware. The memzone contains:\n+\t * - a list of num_im_sgls physical pointers to sgls\n+\t * - the num_im_sgl sgl structures, each pointing to 2 flat buffers\n+\t * - the flat buffers: num_im_sgl * 2\n+\t * where num_im_sgls depends on the hardware generation of the device\n+\t */\n+\n+\tsize_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);\n+\toffset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))\n+\t\t\t& QAT_64_BYTE_ALIGN_MASK;\n+\toffset_of_flat_buffs =\n+\t offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);\n+\tfull_size = offset_of_flat_buffs +\n+\t\t\tnum_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;\n+\n+\tmemzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,\n+\t\t\tcomp_dev->compressdev->data->socket_id,\n+\t\t\tRTE_MEMZONE_2MB, QAT_64_BYTE_ALIGN);\n+\tif (memzone == NULL) {\n+\t\tQAT_LOG(ERR, \"Can't allocate intermediate buffers\"\n+\t\t\t\t\" for device %s\", comp_dev->qat_dev->name);\n+\t\treturn NULL;\n+\t}\n+\n+\tmz_start = (uint8_t *)memzone->addr;\n+\tmz_start_phys = memzone->phys_addr;\n+\tQAT_LOG(DEBUG, \"Memzone %s: addr = %p, phys = %lx, size required %d,\"\n+\t\t\t\"size created %ld\",\n+\t\t\tinter_buff_mz_name, mz_start, mz_start_phys,\n+\t\t\tfull_size, memzone->len);\n+\n+\tarray_of_pointers = (struct array_of_ptrs *)mz_start;\n+\tfor (i = 0; i < num_im_sgls; i++) {\n+\t\tuint32_t curr_sgl_offset =\n+\t\t offset_of_sgls + i * sizeof(struct qat_inter_sgl);\n+\t\tstruct qat_inter_sgl *sgl =\n+\t\t (struct qat_inter_sgl *)(mz_start +\tcurr_sgl_offset);\n+\t\tarray_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;\n+\n+\t\tsgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;\n+\t\tsgl->num_mapped_bufs = 0;\n+\t\tsgl->resrvd = 0;\n+\t\tsgl->buffers[0].addr = mz_start_phys + offset_of_flat_buffs +\n+\t\t\t((i * QAT_NUM_BUFS_IN_IM_SGL) * buff_size);\n+\t\tsgl->buffers[0].len = buff_size;\n+\t\tsgl->buffers[0].resrvd = 0;\n+\t\tsgl->buffers[1].addr = mz_start_phys + offset_of_flat_buffs +\n+\t\t\t(((i * QAT_NUM_BUFS_IN_IM_SGL) + 1) * buff_size);\n+\t\tsgl->buffers[1].len = buff_size;\n+\t\tsgl->buffers[1].resrvd = 0;\n+\n+#if 1\n+\t\tQAT_LOG(DEBUG, \" : phys addr of sgl[%i] in array_of_pointers\"\n+\t\t\t \"= %lx\", i, array_of_pointers->pointer[i]);\n+\t\tQAT_LOG(DEBUG, \" : virt address of sgl[%i] = %p\", i, sgl);\n+\t\tQAT_LOG(DEBUG, \" : sgl->buffers[0].addr = %lx, len=%d\",\n+\t\t\tsgl->buffers[0].addr, sgl->buffers[0].len);\n+\t\tQAT_LOG(DEBUG, \" : sgl->buffers[1].addr = %lx, len=%d\",\n+\t\t\tsgl->buffers[1].addr, sgl->buffers[1].len);\n+#endif\n+\t\t}\n+#if 0\n+\tQAT_DP_HEXDUMP_LOG(DEBUG, \"IM buffer memzone:\", mz_start, 1504);\n+#endif\n+\treturn memzone;\n+}\n+\n static struct rte_mempool *\n qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,\n \t\t\t uint32_t num_elements)\n@@ -176,6 +272,12 @@ qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,\n static void\n _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)\n {\n+\t/* Free intermediate buffers */\n+\tif (comp_dev->interm_buff_mz) {\n+\t\trte_memzone_free(comp_dev->interm_buff_mz);\n+\t\tcomp_dev->interm_buff_mz = NULL;\n+\t}\n+\n \t/* Free private_xform pool */\n \tif (comp_dev->xformpool) {\n \t\t/* Free internal mempool for private xforms */\n@@ -197,6 +299,21 @@ qat_comp_dev_config(struct rte_compressdev *dev,\n \t\treturn -EINVAL;\n \t}\n \n+\tif (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {\n+\t\tQAT_LOG(WARNING,\n+\t\t\t\"RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so\"\n+\t\t\t\" QAT device can't be used for Dynamic Deflate. \"\n+\t\t\t\"Did you really intend to do this?\");\n+\t} else {\n+\t\tcomp_dev->interm_buff_mz =\n+\t\t\t\tqat_comp_setup_inter_buffers(comp_dev,\n+\t\t\t\t\tRTE_PMD_QAT_COMP_IM_BUFFER_SIZE);\n+\t\tif (comp_dev->interm_buff_mz == NULL) {\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto error_out;\n+\t\t}\n+\t}\n+\n \tcomp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,\n \t\t\t\t\tconfig->max_nb_priv_xforms);\n \tif (comp_dev->xformpool == NULL) {\n@@ -365,6 +482,10 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)\n \t\tQAT_LOG(ERR, \"Compression PMD not supported on QAT dh895xcc\");\n \t\treturn 0;\n \t}\n+\tif (qat_pci_dev->qat_dev_gen == QAT_GEN3) {\n+\t\tQAT_LOG(ERR, \"Compression PMD not supported on QAT c4xxx\");\n+\t\treturn 0;\n+\t}\n \n \tstruct rte_compressdev_pmd_init_params init_params = {\n \t\t.name = \"\",\n", "prefixes": [ "v3" ] }