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GET /api/patches/4575/?format=api
{ "id": 4575, "url": "https://patches.dpdk.org/api/patches/4575/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1430406219-23901-22-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1430406219-23901-22-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1430406219-23901-22-git-send-email-helin.zhang@intel.com", "date": "2015-04-30T15:03:27", "name": "[dpdk-dev,v2,21/33] i40e/base: add new interfaces for future use", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "4e2a35ed8eec57e36fcf485037ccdf3d61310cd4", "submitter": { "id": 14, "url": "https://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1430406219-23901-22-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/4575/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/4575/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 20A8BCC22;\n\tThu, 30 Apr 2015 17:05:18 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id ADFF7CCAC\n\tfor <dev@dpdk.org>; Thu, 30 Apr 2015 17:05:15 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga102.jf.intel.com with ESMTP; 30 Apr 2015 08:04:34 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 30 Apr 2015 08:04:34 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t3UF4VuB028803;\n\tThu, 30 Apr 2015 23:04:31 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t3UF4RwC024083; Thu, 30 Apr 2015 23:04:29 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t3UF4RuP024079; \n\tThu, 30 Apr 2015 23:04:27 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.11,677,1422950400\"; d=\"scan'208\";a=\"487715999\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 30 Apr 2015 23:03:27 +0800", "Message-Id": "<1430406219-23901-22-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1430406219-23901-1-git-send-email-helin.zhang@intel.com>", "References": "<1429518150-28098-1-git-send-email-helin.zhang@intel.com>\n\t<1430406219-23901-1-git-send-email-helin.zhang@intel.com>", "Cc": "monica.kenguva@intel.com, steven.j.murray@intel.com,\n\tshannon.nelson@intel.com", "Subject": "[dpdk-dev] [PATCH v2 21/33] i40e/base: add new interfaces for\n\tfuture use", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Four new interfaces are added for future use, as follows, together\nwith their relevant strucure and macro definitions.\n- i40e_aq_read_nvm_config()\n- i40e_aq_write_nvm_config()\n- i40e_aq_set_lldp_mib()\n- i40e_read_pba_string()\nIn addition, removed i40e_read_nvm_srrd() as needed.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\n---\n lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h | 17 ++-\n lib/librte_pmd_i40e/i40e/i40e_common.c | 193 +++++++++++++++++++++++++++--\n lib/librte_pmd_i40e/i40e/i40e_prototype.h | 17 ++-\n lib/librte_pmd_i40e/i40e/i40e_type.h | 1 +\n 4 files changed, 208 insertions(+), 20 deletions(-)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h b/lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h\nindex a2c4394..ac410a5 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h\n+++ b/lib/librte_pmd_i40e/i40e/i40e_adminq_cmd.h\n@@ -1797,12 +1797,12 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);\n /* NVM Config Read (indirect 0x0704) */\n struct i40e_aqc_nvm_config_read {\n \t__le16\tcmd_flags;\n-#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK\t1\n-#define ANVM_READ_SINGLE_FEATURE\t\t0\n-#define ANVM_READ_MULTIPLE_FEATURES\t\t1\n+#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK\t1\n+#define I40E_AQ_ANVM_READ_SINGLE_FEATURE\t\t0\n+#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES\t\t1\n \t__le16\telement_count;\n \t__le16\telement_id; /* Feature/field ID */\n-\tu8\treserved[2];\n+\t__le16\telement_id_msw;\t/* MSWord of field ID */\n \t__le32\taddress_high;\n \t__le32\taddress_low;\n };\n@@ -1820,9 +1820,16 @@ struct i40e_aqc_nvm_config_write {\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);\n \n+/* Used for 0x0704 as well as for 0x0705 commands */\n+#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT\t\t1\n+#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK\t\t(1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)\n+#define I40E_AQ_ANVM_FEATURE\t\t\t\t0\n+#define I40E_AQ_ANVM_IMMEDIATE_FIELD\t\t\t(1 << FEATURE_OR_IMMEDIATE_SHIFT)\n struct i40e_aqc_nvm_config_data_feature {\n \t__le16 feature_id;\n-\t__le16 instance_id;\n+#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY\t\t0x01\n+#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP\t\t0x08\n+#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR\t\t0x10\n \t__le16 feature_options;\n \t__le16 feature_selection;\n };\ndiff --git a/lib/librte_pmd_i40e/i40e/i40e_common.c b/lib/librte_pmd_i40e/i40e/i40e_common.c\nindex 3524aba..c2c14eb 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_common.c\n+++ b/lib/librte_pmd_i40e/i40e/i40e_common.c\n@@ -547,6 +547,30 @@ struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {\n \tI40E_PTT_UNUSED_ENTRY(255)\n };\n \n+\n+/**\n+ * i40e_validate_mac_addr - Validate unicast MAC address\n+ * @mac_addr: pointer to MAC address\n+ *\n+ * Tests a MAC address to ensure it is a valid Individual Address\n+ **/\n+enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)\n+{\n+\tenum i40e_status_code status = I40E_SUCCESS;\n+\n+\tDEBUGFUNC(\"i40e_validate_mac_addr\");\n+\n+\t/* Broadcast addresses ARE multicast addresses\n+\t * Make sure it is not a multicast address\n+\t * Reject the zero address\n+\t */\n+\tif (I40E_IS_MULTICAST(mac_addr) ||\n+\t (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&\n+\t mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))\n+\t\tstatus = I40E_ERR_INVALID_MAC_ADDR;\n+\n+\treturn status;\n+}\n #ifdef PF_DRIVER\n \n /**\n@@ -732,25 +756,60 @@ void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)\n }\n \n /**\n- * i40e_validate_mac_addr - Validate unicast MAC address\n- * @mac_addr: pointer to MAC address\n+ * i40e_read_pba_string - Reads part number string from EEPROM\n+ * @hw: pointer to hardware structure\n+ * @pba_num: stores the part number string from the EEPROM\n+ * @pba_num_size: part number string buffer length\n *\n- * Tests a MAC address to ensure it is a valid Individual Address\n+ * Reads the part number string from the EEPROM.\n **/\n-enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)\n+enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,\n+\t\t\t\t\t u32 pba_num_size)\n {\n \tenum i40e_status_code status = I40E_SUCCESS;\n+\tu16 pba_word = 0;\n+\tu16 pba_size = 0;\n+\tu16 pba_ptr = 0;\n+\tu16 i = 0;\n+\n+\tstatus = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);\n+\tif ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {\n+\t\tDEBUGOUT(\"Failed to read PBA flags or flag is invalid.\\n\");\n+\t\treturn status;\n+\t}\n \n-\tDEBUGFUNC(\"i40e_validate_mac_addr\");\n+\tstatus = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);\n+\tif (status != I40E_SUCCESS) {\n+\t\tDEBUGOUT(\"Failed to read PBA Block pointer.\\n\");\n+\t\treturn status;\n+\t}\n \n-\t/* Broadcast addresses ARE multicast addresses\n-\t * Make sure it is not a multicast address\n-\t * Reject the zero address\n+\tstatus = i40e_read_nvm_word(hw, pba_ptr, &pba_size);\n+\tif (status != I40E_SUCCESS) {\n+\t\tDEBUGOUT(\"Failed to read PBA Block size.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\t/* Subtract one to get PBA word count (PBA Size word is included in\n+\t * total size)\n \t */\n-\tif (I40E_IS_MULTICAST(mac_addr) ||\n-\t (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&\n-\t mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))\n-\t\tstatus = I40E_ERR_INVALID_MAC_ADDR;\n+\tpba_size--;\n+\tif (pba_num_size < (((u32)pba_size * 2) + 1)) {\n+\t\tDEBUGOUT(\"Buffer to small for PBA data.\\n\");\n+\t\treturn I40E_ERR_PARAM;\n+\t}\n+\n+\tfor (i = 0; i < pba_size; i++) {\n+\t\tstatus = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);\n+\t\tif (status != I40E_SUCCESS) {\n+\t\t\tDEBUGOUT1(\"Failed to read PBA Block word %d.\\n\", i);\n+\t\t\treturn status;\n+\t\t}\n+\n+\t\tpba_num[(i * 2)] = (pba_word >> 8) & 0xFF;\n+\t\tpba_num[(i * 2) + 1] = pba_word & 0xFF;\n+\t}\n+\tpba_num[(pba_size * 2)] = '\\0';\n \n \treturn status;\n }\n@@ -2580,6 +2639,77 @@ i40e_aq_read_nvm_exit:\n }\n \n /**\n+ * i40e_aq_read_nvm_config - read an nvm config block\n+ * @hw: pointer to the hw struct\n+ * @cmd_flags: NVM access admin command bits\n+ * @field_id: field or feature id\n+ * @data: buffer for result\n+ * @buf_size: buffer size\n+ * @element_count: pointer to count of elements read by FW\n+ * @cmd_details: pointer to command details structure or NULL\n+ **/\n+enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,\n+\t\t\t\tu8 cmd_flags, u32 field_id, void *data,\n+\t\t\t\tu16 buf_size, u16 *element_count,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_nvm_config_read *cmd =\n+\t\t(struct i40e_aqc_nvm_config_read *)&desc.params.raw;\n+\tenum i40e_status_code status;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);\n+\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));\n+\tif (buf_size > I40E_AQ_LARGE_BUF)\n+\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n+\n+\tcmd->cmd_flags = CPU_TO_LE16(cmd_flags);\n+\tcmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));\n+\tif (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)\n+\t\tcmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));\n+\telse\n+\t\tcmd->element_id_msw = 0;\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);\n+\n+\tif (!status && element_count)\n+\t\t*element_count = LE16_TO_CPU(cmd->element_count);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_aq_write_nvm_config - write an nvm config block\n+ * @hw: pointer to the hw struct\n+ * @cmd_flags: NVM access admin command bits\n+ * @data: buffer for result\n+ * @buf_size: buffer size\n+ * @element_count: count of elements to be written\n+ * @cmd_details: pointer to command details structure or NULL\n+ **/\n+enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,\n+\t\t\t\tu8 cmd_flags, void *data, u16 buf_size,\n+\t\t\t\tu16 element_count,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_nvm_config_write *cmd =\n+\t\t(struct i40e_aqc_nvm_config_write *)&desc.params.raw;\n+\tenum i40e_status_code status;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);\n+\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n+\tif (buf_size > I40E_AQ_LARGE_BUF)\n+\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n+\n+\tcmd->element_count = CPU_TO_LE16(element_count);\n+\tcmd->cmd_flags = CPU_TO_LE16(cmd_flags);\n+\tstatus = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);\n+\n+\treturn status;\n+}\n+\n+/**\n * i40e_aq_erase_nvm\n * @hw: pointer to the hw struct\n * @module_pointer: module pointer location in words from the NVM beginning\n@@ -2954,6 +3084,45 @@ enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,\n }\n \n /**\n+ * i40e_aq_set_lldp_mib - Set the LLDP MIB\n+ * @hw: pointer to the hw struct\n+ * @mib_type: Local, Remote or both Local and Remote MIBs\n+ * @buff: pointer to a user supplied buffer to store the MIB block\n+ * @buff_size: size of the buffer (in bytes)\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Set the LLDP MIB.\n+ **/\n+enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,\n+\t\t\t\tu8 mib_type, void *buff, u16 buff_size,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_lldp_set_local_mib *cmd =\n+\t\t(struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;\n+\tenum i40e_status_code status;\n+\n+\tif (buff_size == 0 || !buff)\n+\t\treturn I40E_ERR_PARAM;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\ti40e_aqc_opc_lldp_set_local_mib);\n+\t/* Indirect Command */\n+\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n+\tif (buff_size > I40E_AQ_LARGE_BUF)\n+\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n+\tdesc.datalen = CPU_TO_LE16(buff_size);\n+\n+\tcmd->type = mib_type;\n+\tcmd->length = CPU_TO_LE16(buff_size);\n+\tcmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));\n+\tcmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n+\treturn status;\n+}\n+\n+/**\n * i40e_aq_cfg_lldp_mib_change_event\n * @hw: pointer to the hw struct\n * @enable_update: Enable or Disable event posting\ndiff --git a/lib/librte_pmd_i40e/i40e/i40e_prototype.h b/lib/librte_pmd_i40e/i40e/i40e_prototype.h\nindex 7bb02fc..ef541f7 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_prototype.h\n+++ b/lib/librte_pmd_i40e/i40e/i40e_prototype.h\n@@ -57,6 +57,7 @@ enum i40e_status_code i40e_shutdown_arq(struct i40e_hw *hw);\n u16 i40e_clean_asq(struct i40e_hw *hw);\n void i40e_free_adminq_asq(struct i40e_hw *hw);\n void i40e_free_adminq_arq(struct i40e_hw *hw);\n+enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr);\n void i40e_adminq_init_ring_data(struct i40e_hw *hw);\n enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,\n \t\t\t\t\t struct i40e_arq_event_info *e,\n@@ -195,6 +196,14 @@ enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,\n enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,\n \t\t\t\tu32 offset, u16 length, bool last_command,\n \t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n+enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,\n+\t\t\t\tu8 cmd_flags, u32 field_id, void *data,\n+\t\t\t\tu16 buf_size, u16 *element_count,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n+enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,\n+\t\t\t\tu8 cmd_flags, void *data, u16 buf_size,\n+\t\t\t\tu16 element_count,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,\n \t\t\t\tvoid *buff, u16 buff_size, u16 *data_size,\n \t\t\t\tenum i40e_admin_queue_opc list_type_opc,\n@@ -207,6 +216,9 @@ enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,\n \t\t\t\tu8 mib_type, void *buff, u16 buff_size,\n \t\t\t\tu16 *local_len, u16 *remote_len,\n \t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n+enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,\n+\t\t\t\tu8 mib_type, void *buff, u16 buff_size,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,\n \t\t\t\tbool enable_update,\n \t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n@@ -373,16 +385,15 @@ enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,\n \t\t\tstruct i40e_aqc_configure_partition_bw_data *bw_data,\n \t\t\tstruct i40e_asq_cmd_details *cmd_details);\n enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr);\n+enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,\n+\t\t\t\t\t u32 pba_num_size);\n void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable);\n-enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr);\n enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw);\n /* prototype for functions used for NVM access */\n enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw);\n enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,\n \t\t\t\t enum i40e_aq_resource_access_type access);\n void i40e_release_nvm(struct i40e_hw *hw);\n-enum i40e_status_code i40e_read_nvm_srrd(struct i40e_hw *hw, u16 offset,\n-\t\t\t\t\t u16 *data);\n enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,\n \t\t\t\t\t u16 *data);\n enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,\ndiff --git a/lib/librte_pmd_i40e/i40e/i40e_type.h b/lib/librte_pmd_i40e/i40e/i40e_type.h\nindex 6050e42..e434e7d 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_type.h\n+++ b/lib/librte_pmd_i40e/i40e/i40e_type.h\n@@ -1274,6 +1274,7 @@ struct i40e_hw_port_stats {\n #define I40E_SR_CSR_PROTECTED_LIST_PTR\t\t0x0D\n #define I40E_SR_MNG_CONFIG_PTR\t\t\t0x0E\n #define I40E_SR_EMP_MODULE_PTR\t\t\t0x0F\n+#define I40E_SR_PBA_FLAGS\t\t\t0x15\n #define I40E_SR_PBA_BLOCK_PTR\t\t\t0x16\n #define I40E_SR_BOOT_CONFIG_PTR\t\t\t0x17\n #define I40E_SR_NVM_DEV_STARTER_VERSION\t\t0x18\n", "prefixes": [ "dpdk-dev", "v2", "21/33" ] }