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GET /api/patches/4559/?format=api
{ "id": 4559, "url": "https://patches.dpdk.org/api/patches/4559/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1430406219-23901-4-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1430406219-23901-4-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1430406219-23901-4-git-send-email-helin.zhang@intel.com", "date": "2015-04-30T15:03:09", "name": "[dpdk-dev,v2,03/33] i40e: adjustment of register definitions and relevant", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8c3e72f4b18626871fa77b3f8a6b94bf07b7f38c", "submitter": { "id": 14, "url": "https://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1430406219-23901-4-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/4559/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/4559/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 9D581CBE0;\n\tThu, 30 Apr 2015 17:03:57 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 07B0BCBDA\n\tfor <dev@dpdk.org>; Thu, 30 Apr 2015 17:03:55 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga102.fm.intel.com with ESMTP; 30 Apr 2015 08:03:54 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 30 Apr 2015 08:03:54 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t3UF3pVw028367;\n\tThu, 30 Apr 2015 23:03:51 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t3UF3lkr023956; Thu, 30 Apr 2015 23:03:49 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t3UF3lXE023952; \n\tThu, 30 Apr 2015 23:03:47 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.11,677,1422950400\"; d=\"scan'208\";a=\"688065637\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 30 Apr 2015 23:03:09 +0800", "Message-Id": "<1430406219-23901-4-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1430406219-23901-1-git-send-email-helin.zhang@intel.com>", "References": "<1429518150-28098-1-git-send-email-helin.zhang@intel.com>\n\t<1430406219-23901-1-git-send-email-helin.zhang@intel.com>", "Cc": "monica.kenguva@intel.com, steven.j.murray@intel.com,\n\tshannon.nelson@intel.com", "Subject": "[dpdk-dev] [PATCH v2 03/33] i40e: adjustment of register\n\tdefinitions and relevant", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Some macros of register definitions or relevant are added, modified\nor deleted. In detail, they are as follows.\n- I40E_PRTDCB_RUPTQ\n- I40E_GLGEN_GPIO_CTL\n- I40E_GLGEN_MDIO_CTRL\n- I40E_GLGEN_RSTENA_EMP\n- I40E_GLPCI_LATCT\n- I40E_GLTPH_CTRL\n- I40E_GLPRT_BPRCH\n- I40E_GLPRT_TDPC\n- I40E_GLSCD_QUANTA\nAlso reading the register of I40E_GLPRT_TDPC is deleted as its\ndefinition is deleted.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\n---\n lib/librte_pmd_i40e/i40e/i40e_register.h | 52 ++++++++++++++++----------------\n lib/librte_pmd_i40e/i40e_ethdev.c | 3 --\n 2 files changed, 26 insertions(+), 29 deletions(-)\n\nv2 changes:\nRemoved anything about Fortpark or FPGA as they shouldn't be there.", "diff": "diff --git a/lib/librte_pmd_i40e/i40e/i40e_register.h b/lib/librte_pmd_i40e/i40e/i40e_register.h\nindex 888c3c3..c8a8d77 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_register.h\n+++ b/lib/librte_pmd_i40e/i40e/i40e_register.h\n@@ -318,6 +318,10 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)\n #define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21\n #define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)\n+#define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */\n+#define I40E_PRTDCB_RUPTQ_MAX_INDEX 7\n+#define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0\n+#define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT)\n #define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */\n #define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0\n #define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)\n@@ -429,6 +433,8 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)\n #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20\n #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)\n+#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT 26\n+#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT)\n #define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */\n #define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0\n #define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)\n@@ -492,7 +498,9 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17\n #define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)\n #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18\n-#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x3FFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)\n+#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x7FF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)\n+#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29\n+#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT)\n #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */\n #define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3\n #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0\n@@ -556,9 +564,6 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)\n #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8\n #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)\n-#define I40E_GLGEN_RSTENA_EMP 0x000B818C /* Reset: POR */\n-#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0\n-#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT)\n #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */\n #define I40E_GLGEN_RTRIG_CORER_SHIFT 0\n #define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT)\n@@ -1074,7 +1079,7 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT)\n #define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6\n #define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT)\n-#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: PFR */\n+#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */\n #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2\n #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)\n #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */\n@@ -1179,7 +1184,7 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_VFINT_ITRN_MAX_INDEX 2\n #define I40E_VFINT_ITRN_INTERVAL_SHIFT 0\n #define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT)\n-#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */\n+#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */\n #define I40E_VFINT_STAT_CTL0_MAX_INDEX 127\n #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2\n #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)\n@@ -1811,9 +1816,6 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3\n #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0\n #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)\n-#define I40E_GLPCI_LATCT 0x0009C4B4 /* Reset: PCIR */\n-#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0\n-#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT)\n #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */\n #define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0\n #define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)\n@@ -1910,6 +1912,11 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)\n #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1\n #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)\n+#define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCIR */\n+#define I40E_GLTPH_CTRL_DESC_PH_SHIFT 9\n+#define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DESC_PH_SHIFT)\n+#define I40E_GLTPH_CTRL_DATA_PH_SHIFT 11\n+#define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DATA_PH_SHIFT)\n #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */\n #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0\n #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)\n@@ -2382,20 +2389,20 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT)\n #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n #define I40E_GLPRT_BPRCH_MAX_INDEX 3\n-#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0\n-#define I40E_GLPRT_BPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_UPRCH_SHIFT)\n+#define I40E_GLPRT_BPRCH_BPRCH_SHIFT 0\n+#define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_BPRCH_SHIFT)\n #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n #define I40E_GLPRT_BPRCL_MAX_INDEX 3\n-#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0\n-#define I40E_GLPRT_BPRCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_UPRCH_SHIFT)\n+#define I40E_GLPRT_BPRCL_BPRCL_SHIFT 0\n+#define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_BPRCL_SHIFT)\n #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n #define I40E_GLPRT_BPTCH_MAX_INDEX 3\n-#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0\n-#define I40E_GLPRT_BPTCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_UPRCH_SHIFT)\n+#define I40E_GLPRT_BPTCH_BPTCH_SHIFT 0\n+#define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_BPTCH_SHIFT)\n #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n #define I40E_GLPRT_BPTCL_MAX_INDEX 3\n-#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0\n-#define I40E_GLPRT_BPTCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_UPRCH_SHIFT)\n+#define I40E_GLPRT_BPTCL_BPTCL_SHIFT 0\n+#define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_BPTCL_SHIFT)\n #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n #define I40E_GLPRT_CRCERRS_MAX_INDEX 3\n #define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0\n@@ -2628,10 +2635,6 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_GLPRT_TDOLD_MAX_INDEX 3\n #define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0\n #define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)\n-#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n-#define I40E_GLPRT_TDPC_MAX_INDEX 3\n-#define I40E_GLPRT_TDPC_TDPC_SHIFT 0\n-#define I40E_GLPRT_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDPC_TDPC_SHIFT)\n #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n #define I40E_GLPRT_UPRCH_MAX_INDEX 3\n #define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0\n@@ -2998,9 +3001,6 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */\n #define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0\n #define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)\n-#define I40E_GLSCD_QUANTA 0x000B2080 /* Reset: CORER */\n-#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0\n-#define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK I40E_MASK(0x7, I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT)\n #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */\n #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0\n #define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)\n@@ -3266,7 +3266,7 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_VFINT_ITRN1_MAX_INDEX 2\n #define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0\n #define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)\n-#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: VFR */\n+#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */\n #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2\n #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)\n #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */\n@@ -3374,4 +3374,4 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)\n #define I40E_VFQF_HREGION_REGION_7_SHIFT 29\n #define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)\n-#endif\n+#endif /* _I40E_REGISTER_H_ */\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex 49d1067..3d45429 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -1269,9 +1269,6 @@ i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n \t\t\t I40E_GLPRT_BPTCL(hw->port),\n \t\t\t pf->offset_loaded, &os->eth.tx_broadcast,\n \t\t\t &ns->eth.tx_broadcast);\n-\ti40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),\n-\t\t\t pf->offset_loaded, &os->eth.tx_discards,\n-\t\t\t &ns->eth.tx_discards);\n \t/* GLPRT_TEPC not supported */\n \n \t/* additional port specific stats */\n", "prefixes": [ "dpdk-dev", "v2", "03/33" ] }