Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 45186,
    "url": "https://patches.dpdk.org/api/patches/45186/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20180924080220.5569-3-pbhagavatula@caviumnetworks.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20180924080220.5569-3-pbhagavatula@caviumnetworks.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20180924080220.5569-3-pbhagavatula@caviumnetworks.com",
    "date": "2018-09-24T08:02:19",
    "name": "[v4,3/4] app/test-eventdev: add Tx adapter support",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "421b0b72278c04b7fc535f9fc76f98194d3a48e7",
    "submitter": {
        "id": 768,
        "url": "https://patches.dpdk.org/api/people/768/?format=api",
        "name": "Pavan Nikhilesh",
        "email": "pbhagavatula@caviumnetworks.com"
    },
    "delegate": {
        "id": 310,
        "url": "https://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20180924080220.5569-3-pbhagavatula@caviumnetworks.com/mbox/",
    "series": [
        {
            "id": 1458,
            "url": "https://patches.dpdk.org/api/series/1458/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=1458",
            "date": "2018-09-24T08:02:17",
            "name": "[v4,1/4] app/test-eventdev: fix minor typos",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/1458/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/45186/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/45186/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 416064CA2;\n\tMon, 24 Sep 2018 10:03:06 +0200 (CEST)",
            "from NAM03-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam03on0041.outbound.protection.outlook.com [104.47.42.41])\n\tby dpdk.org (Postfix) with ESMTP id 8EC4C4C99\n\tfor <dev@dpdk.org>; Mon, 24 Sep 2018 10:03:01 +0200 (CEST)",
            "from localhost.localdomain (115.113.156.3) by\n\tSN6PR07MB4973.namprd07.prod.outlook.com (2603:10b6:805:ac::23) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1143.18; Mon, 24 Sep 2018 08:02:57 +0000"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=cWvMsmfZxyVAgqgYAJZ7x1RyNHWcCqAZWcdG8jvlMUM=;\n\tb=Qcb6wfMh74vF0S7Sn1k0g+clLTdcoCD8JlPm5PJh7Eiq8Dc5Vk5WdsbO4Ar4o93rZwKrbZXUQOzRiDhHRKZfQvAbR0REknXmnnXd/myvzA+MhnhEALaPNZo5xnTuecPVUGXICHL4cjJL/C3cBq190x4k95i+QHL6K+daTAT6+U0=",
        "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Pavan.Bhagavatula@cavium.com; ",
        "From": "Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>",
        "To": "jerin.jacob@caviumnetworks.com, nikhil.rao@intel.com,\n\tanoob.joseph@caviumnetworks.com",
        "Cc": "dev@dpdk.org,\n\tPavan Nikhilesh <pbhagavatula@caviumnetworks.com>",
        "Date": "Mon, 24 Sep 2018 13:32:19 +0530",
        "Message-Id": "<20180924080220.5569-3-pbhagavatula@caviumnetworks.com>",
        "X-Mailer": "git-send-email 2.18.0",
        "In-Reply-To": "<20180924080220.5569-1-pbhagavatula@caviumnetworks.com>",
        "References": "<20180904141223.24216-1-pbhagavatula@caviumnetworks.com>\n\t<20180924080220.5569-1-pbhagavatula@caviumnetworks.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[115.113.156.3]",
        "X-ClientProxiedBy": "PN1PR01CA0077.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:c00:1::17) To SN6PR07MB4973.namprd07.prod.outlook.com\n\t(2603:10b6:805:ac::23)",
        "X-MS-PublicTrafficType": "Email",
        "X-MS-Office365-Filtering-Correlation-Id": "814973c5-7ab6-4c33-816c-08d621f424dc",
        "X-Microsoft-Antispam": "BCL:0; PCL:0;\n\tRULEID:(7020095)(4652040)(8989299)(5600074)(711020)(2017052603328)(7153060)(7193020);\n\tSRVR:SN6PR07MB4973; ",
        "X-Microsoft-Exchange-Diagnostics": [
            "1; SN6PR07MB4973;\n\t3:FwzH41Kq1jDFTl17e2hvGK4uuBySt3JAzVrab4RqbgCUxHn2rNI/C/F1Mq8eDptskfRC4xyVMB7TJtjDwdUm6JvLhFHPUSA/aSjZW0wGTYwdvPs2riYOITiyUvo/wNVh+mQRS0QaJahfLd/0dkOjaX9S1w1y8iaH0s4theVp6wIPd4v8PxuH20FvkGM7TSS5pfypX77NobLeNUeWeBoC3PgGzzYsPbi2JymWleiYK+5jsBjOLnYdILAvcYiu+5tD;\n\t25:gpgDbftlm83ANR09EJ9sMeZTFkkLiFpnalUBLFF9hf0VQPUq84A+JrfC0/R3tTOHvkItHwum/98x7OpjDHgSPXMJ4Nwx2Qr/czrYIifbooxUkXO7Ept1XmKHTyERQBDF/tCJcNnt3+hfQgwX5JulXC5b5PHKnazAMlICoNazpAmcmLTjG4IDWScaNwvoJBdmo5OJUyZkX8afyupKU1mBq0WturpAbDGx3NvGmAaEQQ0KHSCVcjr+d45v+dglmIcVwm0xrM+xtq1/ScyVJ8IrWhzHHz+2junXoN6/XY29rwpYtjcxzFv7GGqPHMV80z0VaQl2NJqrwAwFXCixfBnBug==;\n\t31:upSFw1eg0GGZp+8FUbcRxEu4gDFacsPm20oSs0Uidha6QYx/ad+/P2r7LiSSY9fTkp0F9s/f3XmpRyQyaiTIB0ewj1wkTQ56aMxvLZm3hoXdwfXOuBSF/3F4TPR+9Dbk5pgyxso3yRlgf9yxA9O/ZKAyfI3to1RaaiwtaIrEboISieysgmTIY1oU8hzMbiS1+IK/WCsLxPM6e/9Ue7wjxOZPHWQ37jabQ1xHO6UfejA=",
            "1; SN6PR07MB4973;\n\t20:ZhigBw/75Rgn3r1qDtJOi5ASZsSC8ae6FV7X3eymkhN6uhntBa+csjq1UKtwQOjWqcl77I8IjQjEMcmmRsIQgZLSMWoxKuAF0DcgIJ5ESQ/dbflGTL63NFQ64vg4GrGHsXgOJhY6+P2f7Tgw5OueCei3JlePIAI8iHFETl29gCDJn3VofsXN25na3IM17gDWcwXjuK1clYtWH+uWUh4YsPkZpmv5mWkkaIFaLwLdrrw6dX3FAQ5tYZJo9yMb/jynVnI6khAuRY7I0KvcULU7PZ5ML+OBe6V7d0OXxEJ2eMWZyz1Wb4HjG12SyjVaqGjv6FQ8BgL0GWsNYJPYQnAdWbqYU36+tGEawwoIX5e8R/N+vgiVlXDVnnEceCHggmEOYmhmhipPtCW1Q8kmIwtMO5n51Uzwz2ZoS+TPxY7x7vunlZ9erdUZKEI3iQiIjnJO0X3MqT7JLzvpHIcW3kpSigqvnlH+Ktqr6b95fJ/az5awwFtGOcrdjyrCRviqZ4MglfjGHptmZZTglYahsbzgPFoiTygvoSXastva2p/kVdoYgF1DNRx+C1dh54jpE04wkqBbVe1/CzB2Tk5yDJjMdBF/OReOihB08XMQ0JVwJs0=;\n\t4:TakuNBSbdvAbtyTs4Opz4PiBG6mO57F2Q1MbEUOtfIONK+uZvfC20Ml+K6JxkGnnjW8miYozR6+OjSfXYFkAv+Nej+baD3qYx7xYnQuSy/l7P758rnEzojZR0ua/RnRSq1wF8Ws6JerF64i0UwguJYyBLjHHSytQQqAvFXRuOkWWl4sdRHDzm3tmtNZLkxV3ZnM0lWdxS7LMkZhuxqAXfzXGMXW36IKwt9MjLk66v5PXZR6BOh9G0LIlvzE9ugH5ZuP4TfsX0UllNlWyRmioP7viWpvZUda0CJQv3r5hXuoqHIt4x1bPM/YKMoDxOkO3",
            "=?us-ascii?Q?1; SN6PR07MB4973;\n\t23:ENQDuQUNbsGPYnlBUG4axjhGG+qYAL+vYaaONas1N?=\n\tsJMG6p8sQr4FvJxKr7cJc58VQ8uhY5J2WOPMVHF+vqlhVXpeEv6yZ8YDQSnClnL0mPZJRFKlNoeqc1q34tuY8WNKmG5M7vkQJt/JUTRxvX3jM6adaR7uygwU8Y0YJ+Xnu74CwXE6sqyiO7AYjZ9jUZFe5Hr9UoIM0hQiEdIfaHWggSqm35PsHhasMXinegUh+yk9TFbBLD3yMC5HlgRAuLg6yxJVs7FqyRckPYL5Hns3Kvp2hCknuJn3SIotl8FPaSxhGtuIsr7c+AziLySXuaJYCfg0Hl95i7muKMUxA2ZA782frwKePizjJzoYdz+WwQ0f46KFjDjW/exmyjotmlDAMFunTLp9GbP2fe8OZVfAebBcxiAb1U8qbfTFnQNewrj4QB0EmbzMzlMq/ugkbaRqbMF6imEQVvyuppB8daYBPPhOHAI5le0ZTcj4QCDgYpfqU4PEC55zCaC7fFsCtM7wf2ebsLKf4/m4rmo9Ei4NcWBpHNn2Xpm8DUV22XyQ4mO0PJpI8q4BVTBlei4wNq/7A0KnHkpUmL7a7tLsNjBqQzJraYoJPCP0Iicu0/lUXImqYCiPUvQTItNaq7J9aZby7c6ICXCOd4eta9M6l6gLva7xoxq5lpDra/mr7hY5pQIF2yHkHO3hcjwpzbyzh6++TkFHyt6l2bL2HYzPyENooaglgniEylEaY84tVpuovC4CeRrbPti4PwoPsNVq7Ui1OeUbhoo2f4Cl4cdzmp9iHyS2DdJf61XEq59ZbpAt6xN5bLqlW/PdhpdNcX9VtTLk8pA4vl6rF0GBlOWsLhG9nDbmjBA7Dipu4moAYh8hodplalidkY8QYqKkZSMXAi+eJ3D3LiMPXbxaBPK6MOEXthdnKuvROmMC3yXIhXPawSPPGX0l2sTZnRfwbyv8qpNGRN97+Xgp7nq8WS/pVVAd9bndDvmjT//Th28H2RnRWecMFiPVwTLMx7OC+fi8SPiEm5UnsrqovU7ia1m4l88dYqks1HsQyYZYiZAs95Z4Gj2+lPTT/3A6yC2OVXgIo0raSGf3DxCO+kj3tLaVfHqhzr3IA9BlYEeg4mUBhUebrEdBvAFdg4Y39TYxKYGHth7QRnwKidB0UAi6ZRS9G3vlQ9zQPWFFRtcza/G0KerEO80v6/181SugkG1gReoXgi1Vjjhq8kg6MCjsz+86Hy+LOb4BquB5XvTGlbu7dbtX8oeNHJHAvtPurHsFxEvL6jSovfrsaU6w/RVwEsO8TmgCOOpbhieMYFEbtv+5c8Hqv0IyegQSpUEOcNwVITK9Z2G70jI8z1AFddXy8BnM+xxbMTe4jOhPRe6zn//VRvWuPTc68r9y1U/a6dg0lfVMETc",
            "1; SN6PR07MB4973;\n\t6:NaeDtxG/lr6q+nMd3ej8i6dyQUbXkd/gIRyPaqSfXpIWVbEG8+wL5qjA9sFnQqueqdPM9PyR8QLg4sVnmQ/ns309MS12MmCMtN2zGC7JBzG1xLsE1F78gnyiiKxrLZJEwzXYL0ZbecuywVaX6AfAgBGy0p2eJ+Wibcdz5mCIkA4t2B1lMKxJihChl+nIXTL9kCK7eewjY/sRdmRd4npKNHmfFjI2EYoi1zPwWfBW7HxjqET4ji/iU4BPw6oyigqMrLqOk69kKh+KrzRz4ZTotOO9OOUg3cWEfKVKOv9+B0JzVCijLqnki0TJUsKWU7WL1q2cWTYodrCXAA4AnprD1H7BCV4LhD342W1+XIUe9PvtZ9uFYRjYaRwOqcOS09RlejbrHUBtxOlFjvo+QVX0tua6pLqLNWzyfkrBWgHHrqEfGWrhEo8RwY75U719V9Ko4KW4uACHJXs+e87WYd+Otg==;\n\t5:XgtnDMOyUPQEFMHkY4mrrjQ7mgKzL57VI1jXxuwZtmAfESlUcK+zkUFVDIGTsUsHy7BhswfRdrgib0qmtAWpNUDHG9I1IH/Yxv7SFoUk78fy6o3x6j35wn8kNh9y9mmE6CeN2gdaCN/0IrMhfHcfGU02D1Jf/P4EzrSXLG6RLQk=;\n\t7:kNtWSb3hPcslg1C0Jx7qvmH0SZKmGIzwV3SI7SUxbKe5Hmrsz1xaE5xwsGe/bF8zuB2lEIO0WzNs6gGm6rxRZV9OlHoZdN21eISb96BNLCH+SyCUeUwXQSg9Qw7wSFfRe9KY31a6YWorAOA8IJMsFzaphXHFk89coam5haKhudfNaqh+u8FlpZvYu4C+FRFLZEwrUeXyCJYxwtDd6q+l01k89TJHUkmahhZ8PkScWKc+lrdrvl/jZJoD0WjEn1bu"
        ],
        "X-MS-TrafficTypeDiagnostic": "SN6PR07MB4973:",
        "X-Microsoft-Antispam-PRVS": "<SN6PR07MB49731C954F6FDC39C93200B880170@SN6PR07MB4973.namprd07.prod.outlook.com>",
        "X-Exchange-Antispam-Report-Test": "UriScan:(21532816269658);",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(93006095)(10201501046)(3002001)(3231355)(944501410)(52105095)(149066)(150027)(6041310)(20161123560045)(20161123564045)(20161123562045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699051);\n\tSRVR:SN6PR07MB4973; BCL:0; PCL:0; RULEID:; SRVR:SN6PR07MB4973; ",
        "X-Forefront-PRVS": "0805EC9467",
        "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(6069001)(396003)(39860400002)(136003)(376002)(346002)(366004)(199004)(189003)(11346002)(8676002)(36756003)(2906002)(68736007)(6486002)(6666003)(81166006)(107886003)(478600001)(7736002)(48376002)(14444005)(97736004)(50466002)(81156014)(6636002)(106356001)(105586002)(5660300001)(25786009)(72206003)(47776003)(50226002)(8936002)(4326008)(305945005)(6116002)(3846002)(2616005)(956004)(52116002)(26005)(476003)(575784001)(42882007)(1076002)(1857600001)(53946003)(486006)(16526019)(76176011)(6512007)(53936002)(51416003)(66066001)(446003)(316002)(386003)(6506007)(69590400006)(16586007)(42262002)(579004);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR07MB4973; H:localhost.localdomain;\n\tFPR:; \n\tSPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; ",
        "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)",
        "X-Microsoft-Antispam-Message-Info": "cb5owMIPNj8MXBlPOCAIGT0dtVVsL5Hn7KMAM6gw+jfC9r10sTtGnLmCRrGErm4Zl6rjpx2qjWQ2jfb1IwA0MVOXHL6L8mgbQ+KpLznGZlKvbLww6VeN6IQD6E4WMpquAsEWsW4VAWhjFwIRCRpQTU7iFQ7G9GUjgmbGcxKMCBpI+OpJFrZHgNUJcmgiB4FlSajVwEP8IYXxSC6OWnuGgQAw7T5Qkad6sKPcxIAkuAqoZXMg6UcxZR9Tw5xXbGrybytl2XpkNqe4bNQnKd+dXlY6MtP5DESvah9EjQIO6AICANApURJQjNuI64Ga4+p+5QpO4TCydeho4teqJowh+6jlUwsUSzdq2sj8jyUPELk=",
        "SpamDiagnosticOutput": "1:99",
        "SpamDiagnosticMetadata": "NSPM",
        "X-OriginatorOrg": "caviumnetworks.com",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Sep 2018 08:02:57.3237\n\t(UTC)",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "814973c5-7ab6-4c33-816c-08d621f424dc",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted",
        "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN6PR07MB4973",
        "Subject": "[dpdk-dev] [PATCH v4 3/4] app/test-eventdev: add Tx adapter support",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Convert existing Tx service based pipeline to Tx adapter based APIs and\nsimplify worker functions.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>\nAcked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>\n---\n app/test-eventdev/test_pipeline_atq.c    | 271 ++++++++++++-----------\n app/test-eventdev/test_pipeline_common.c | 200 +++++------------\n app/test-eventdev/test_pipeline_common.h |  62 +++---\n app/test-eventdev/test_pipeline_queue.c  | 244 ++++++++++----------\n 4 files changed, 367 insertions(+), 410 deletions(-)",
    "diff": "diff --git a/app/test-eventdev/test_pipeline_atq.c b/app/test-eventdev/test_pipeline_atq.c\nindex f0b2f9015..c60635bf6 100644\n--- a/app/test-eventdev/test_pipeline_atq.c\n+++ b/app/test-eventdev/test_pipeline_atq.c\n@@ -15,7 +15,7 @@ pipeline_atq_nb_event_queues(struct evt_options *opt)\n \treturn rte_eth_dev_count_avail();\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_single_stage_tx(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n@@ -28,23 +28,18 @@ pipeline_atq_worker_single_stage_tx(void *arg)\n \t\t\tcontinue;\n \t\t}\n \n-\t\tif (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\t\t\tpipeline_tx_pkt(ev.mbuf);\n-\t\t\tw->processed_pkts++;\n-\t\t\tcontinue;\n-\t\t}\n-\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n-\t\tpipeline_event_enqueue(dev, port, &ev);\n+\t\tpipeline_event_tx(dev, port, &ev);\n+\t\tw->processed_pkts++;\n \t}\n \n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_single_stage_fwd(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -54,16 +49,16 @@ pipeline_atq_worker_single_stage_fwd(void *arg)\n \t\t\tcontinue;\n \t\t}\n \n-\t\tw->processed_pkts++;\n-\t\tev.queue_id = tx_queue;\n+\t\tev.queue_id = tx_queue[ev.mbuf->port];\n \t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n \t\tpipeline_event_enqueue(dev, port, &ev);\n+\t\tw->processed_pkts++;\n \t}\n \n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_single_stage_burst_tx(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n@@ -79,27 +74,21 @@ pipeline_atq_worker_single_stage_burst_tx(void *arg)\n \n \t\tfor (i = 0; i < nb_rx; i++) {\n \t\t\trte_prefetch0(ev[i + 1].mbuf);\n-\t\t\tif (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\tpipeline_tx_pkt(ev[i].mbuf);\n-\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n-\t\t\t\tw->processed_pkts++;\n-\t\t\t} else\n-\t\t\t\tpipeline_fwd_event(&ev[i],\n-\t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n \t\t}\n \n-\t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t\tpipeline_event_tx_burst(dev, port, ev, nb_rx);\n+\t\tw->processed_pkts += nb_rx;\n \t}\n \n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_single_stage_burst_fwd(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -112,23 +101,22 @@ pipeline_atq_worker_single_stage_burst_fwd(void *arg)\n \n \t\tfor (i = 0; i < nb_rx; i++) {\n \t\t\trte_prefetch0(ev[i + 1].mbuf);\n-\t\t\tev[i].queue_id = tx_queue;\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n+\t\t\tev[i].queue_id = tx_queue[ev[i].mbuf->port];\n \t\t\tpipeline_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);\n-\t\t\tw->processed_pkts++;\n \t\t}\n \n \t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t\tw->processed_pkts += nb_rx;\n \t}\n \n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_multi_stage_tx(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages;\n-\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -141,29 +129,24 @@ pipeline_atq_worker_multi_stage_tx(void *arg)\n \t\tcq_id = ev.sub_event_type % nb_stages;\n \n \t\tif (cq_id == last_queue) {\n-\t\t\tif (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\tpipeline_tx_pkt(ev.mbuf);\n-\t\t\t\tw->processed_pkts++;\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n-\t\t} else {\n-\t\t\tev.sub_event_type++;\n-\t\t\tpipeline_fwd_event(&ev, sched_type_list[cq_id]);\n+\t\t\tpipeline_event_tx(dev, port, &ev);\n+\t\t\tw->processed_pkts++;\n+\t\t\tcontinue;\n \t\t}\n \n+\t\tev.sub_event_type++;\n+\t\tpipeline_fwd_event(&ev, sched_type_list[cq_id]);\n \t\tpipeline_event_enqueue(dev, port, &ev);\n \t}\n+\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_multi_stage_fwd(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -176,9 +159,9 @@ pipeline_atq_worker_multi_stage_fwd(void *arg)\n \t\tcq_id = ev.sub_event_type % nb_stages;\n \n \t\tif (cq_id == last_queue) {\n-\t\t\tw->processed_pkts++;\n-\t\t\tev.queue_id = tx_queue;\n+\t\t\tev.queue_id = tx_queue[ev.mbuf->port];\n \t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n+\t\t\tw->processed_pkts++;\n \t\t} else {\n \t\t\tev.sub_event_type++;\n \t\t\tpipeline_fwd_event(&ev, sched_type_list[cq_id]);\n@@ -186,14 +169,14 @@ pipeline_atq_worker_multi_stage_fwd(void *arg)\n \n \t\tpipeline_event_enqueue(dev, port, &ev);\n \t}\n+\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_multi_stage_burst_tx(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -209,34 +192,27 @@ pipeline_atq_worker_multi_stage_burst_tx(void *arg)\n \t\t\tcq_id = ev[i].sub_event_type % nb_stages;\n \n \t\t\tif (cq_id == last_queue) {\n-\t\t\t\tif (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\t\tpipeline_tx_pkt(ev[i].mbuf);\n-\t\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n-\t\t\t\t\tw->processed_pkts++;\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n-\n-\t\t\t\tpipeline_fwd_event(&ev[i],\n-\t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n-\t\t\t} else {\n-\t\t\t\tev[i].sub_event_type++;\n-\t\t\t\tpipeline_fwd_event(&ev[i],\n-\t\t\t\t\t\tsched_type_list[cq_id]);\n+\t\t\t\tpipeline_event_tx(dev, port, &ev[i]);\n+\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n+\t\t\t\tw->processed_pkts++;\n+\t\t\t\tcontinue;\n \t\t\t}\n+\n+\t\t\tev[i].sub_event_type++;\n+\t\t\tpipeline_fwd_event(&ev[i], sched_type_list[cq_id]);\n \t\t}\n \n \t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n \t}\n+\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_atq_worker_multi_stage_burst_fwd(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -253,7 +229,7 @@ pipeline_atq_worker_multi_stage_burst_fwd(void *arg)\n \n \t\t\tif (cq_id == last_queue) {\n \t\t\t\tw->processed_pkts++;\n-\t\t\t\tev[i].queue_id = tx_queue;\n+\t\t\t\tev[i].queue_id = tx_queue[ev[i].mbuf->port];\n \t\t\t\tpipeline_fwd_event(&ev[i],\n \t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n \t\t\t} else {\n@@ -265,6 +241,7 @@ pipeline_atq_worker_multi_stage_burst_fwd(void *arg)\n \n \t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n \t}\n+\n \treturn 0;\n }\n \n@@ -274,39 +251,36 @@ worker_wrapper(void *arg)\n \tstruct worker_data *w  = arg;\n \tstruct evt_options *opt = w->t->opt;\n \tconst bool burst = evt_has_burst_mode(w->dev_id);\n-\tconst bool mt_safe = !w->t->mt_unsafe;\n+\tconst bool internal_port = w->t->internal_port;\n \tconst uint8_t nb_stages = opt->nb_stages;\n \tRTE_SET_USED(opt);\n \n \tif (nb_stages == 1) {\n-\t\tif (!burst && mt_safe)\n+\t\tif (!burst && internal_port)\n \t\t\treturn pipeline_atq_worker_single_stage_tx(arg);\n-\t\telse if (!burst && !mt_safe)\n+\t\telse if (!burst && !internal_port)\n \t\t\treturn pipeline_atq_worker_single_stage_fwd(arg);\n-\t\telse if (burst && mt_safe)\n+\t\telse if (burst && internal_port)\n \t\t\treturn pipeline_atq_worker_single_stage_burst_tx(arg);\n-\t\telse if (burst && !mt_safe)\n+\t\telse if (burst && !internal_port)\n \t\t\treturn pipeline_atq_worker_single_stage_burst_fwd(arg);\n \t} else {\n-\t\tif (!burst && mt_safe)\n+\t\tif (!burst && internal_port)\n \t\t\treturn pipeline_atq_worker_multi_stage_tx(arg);\n-\t\telse if (!burst && !mt_safe)\n+\t\telse if (!burst && !internal_port)\n \t\t\treturn pipeline_atq_worker_multi_stage_fwd(arg);\n-\t\tif (burst && mt_safe)\n+\t\tif (burst && internal_port)\n \t\t\treturn pipeline_atq_worker_multi_stage_burst_tx(arg);\n-\t\telse if (burst && !mt_safe)\n+\t\telse if (burst && !internal_port)\n \t\t\treturn pipeline_atq_worker_multi_stage_burst_fwd(arg);\n \t}\n+\n \trte_panic(\"invalid worker\\n\");\n }\n \n static int\n pipeline_atq_launch_lcores(struct evt_test *test, struct evt_options *opt)\n {\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\n-\tif (t->mt_unsafe)\n-\t\trte_service_component_runstate_set(t->tx_service.service_id, 1);\n \treturn pipeline_launch_lcores(test, opt, worker_wrapper);\n }\n \n@@ -317,34 +291,38 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \tint nb_ports;\n \tint nb_queues;\n \tuint8_t queue;\n-\tstruct rte_event_dev_info info;\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\tuint8_t tx_evqueue_id = 0;\n+\tuint8_t tx_evqueue_id[RTE_MAX_ETHPORTS];\n \tuint8_t queue_arr[RTE_EVENT_MAX_QUEUES_PER_DEV];\n \tuint8_t nb_worker_queues = 0;\n+\tuint8_t tx_evport_id = 0;\n+\tuint16_t prod = 0;\n+\tstruct rte_event_dev_info info;\n+\tstruct test_pipeline *t = evt_test_priv(test);\n \n \tnb_ports = evt_nr_active_lcores(opt->wlcores);\n \tnb_queues = rte_eth_dev_count_avail();\n \n-\t/* One extra port and queueu for Tx service */\n-\tif (t->mt_unsafe) {\n-\t\ttx_evqueue_id = nb_queues;\n-\t\tnb_ports++;\n-\t\tnb_queues++;\n+\tmemset(tx_evqueue_id, 0, sizeof(uint8_t) * RTE_MAX_ETHPORTS);\n+\tmemset(queue_arr, 0, sizeof(uint8_t) * RTE_EVENT_MAX_QUEUES_PER_DEV);\n+\t/* One queue for Tx adapter per port */\n+\tif (!t->internal_port) {\n+\t\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\t\ttx_evqueue_id[prod] = nb_queues;\n+\t\t\tnb_queues++;\n+\t\t}\n \t}\n \n-\n \trte_event_dev_info_get(opt->dev_id, &info);\n \n \tconst struct rte_event_dev_config config = {\n-\t\t\t.nb_event_queues = nb_queues,\n-\t\t\t.nb_event_ports = nb_ports,\n-\t\t\t.nb_events_limit  = info.max_num_events,\n-\t\t\t.nb_event_queue_flows = opt->nb_flows,\n-\t\t\t.nb_event_port_dequeue_depth =\n-\t\t\t\tinfo.max_event_port_dequeue_depth,\n-\t\t\t.nb_event_port_enqueue_depth =\n-\t\t\t\tinfo.max_event_port_enqueue_depth,\n+\t\t.nb_event_queues = nb_queues,\n+\t\t.nb_event_ports = nb_ports,\n+\t\t.nb_events_limit  = info.max_num_events,\n+\t\t.nb_event_queue_flows = opt->nb_flows,\n+\t\t.nb_event_port_dequeue_depth =\n+\t\t\tinfo.max_event_port_dequeue_depth,\n+\t\t.nb_event_port_enqueue_depth =\n+\t\t\tinfo.max_event_port_enqueue_depth,\n \t};\n \tret = rte_event_dev_configure(opt->dev_id, &config);\n \tif (ret) {\n@@ -353,21 +331,23 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t}\n \n \tstruct rte_event_queue_conf q_conf = {\n-\t\t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,\n-\t\t\t.nb_atomic_flows = opt->nb_flows,\n-\t\t\t.nb_atomic_order_sequences = opt->nb_flows,\n+\t\t.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,\n+\t\t.nb_atomic_flows = opt->nb_flows,\n+\t\t.nb_atomic_order_sequences = opt->nb_flows,\n \t};\n \t/* queue configurations */\n \tfor (queue = 0; queue < nb_queues; queue++) {\n \t\tq_conf.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;\n \n-\t\tif (t->mt_unsafe) {\n-\t\t\tif (queue == tx_evqueue_id) {\n-\t\t\t\tq_conf.event_queue_cfg =\n-\t\t\t\t\tRTE_EVENT_QUEUE_CFG_SINGLE_LINK;\n-\t\t\t} else {\n-\t\t\t\tqueue_arr[nb_worker_queues] = queue;\n-\t\t\t\tnb_worker_queues++;\n+\t\tif (!t->internal_port) {\n+\t\t\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\t\t\tif (queue == tx_evqueue_id[prod]) {\n+\t\t\t\t\tq_conf.event_queue_cfg =\n+\t\t\t\t\t\tRTE_EVENT_QUEUE_CFG_SINGLE_LINK;\n+\t\t\t\t} else {\n+\t\t\t\t\tqueue_arr[nb_worker_queues] = queue;\n+\t\t\t\t\tnb_worker_queues++;\n+\t\t\t\t}\n \t\t\t}\n \t\t}\n \n@@ -383,20 +363,15 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \n \t/* port configuration */\n \tconst struct rte_event_port_conf p_conf = {\n-\t\t\t.dequeue_depth = opt->wkr_deq_dep,\n-\t\t\t.enqueue_depth = info.max_event_port_dequeue_depth,\n-\t\t\t.new_event_threshold = info.max_num_events,\n+\t\t.dequeue_depth = opt->wkr_deq_dep,\n+\t\t.enqueue_depth = info.max_event_port_dequeue_depth,\n+\t\t.new_event_threshold = info.max_num_events,\n \t};\n \n-\tif (t->mt_unsafe) {\n+\tif (!t->internal_port)\n \t\tret = pipeline_event_port_setup(test, opt, queue_arr,\n \t\t\t\tnb_worker_queues, p_conf);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\n-\t\tret = pipeline_event_tx_service_setup(test, opt, tx_evqueue_id,\n-\t\t\t\tnb_ports - 1, p_conf);\n-\t} else\n+\telse\n \t\tret = pipeline_event_port_setup(test, opt, NULL, nb_queues,\n \t\t\t\tp_conf);\n \n@@ -408,30 +383,32 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t *\n \t * eth_dev_count = 2, nb_stages = 2, atq mode\n \t *\n-\t * Multi thread safe :\n+\t * eth0, eth1 have Internal port capability :\n \t *\tqueues = 2\n \t *\tstride = 1\n \t *\n \t *\tevent queue pipelines:\n-\t *\teth0 -> q0 ->tx\n-\t *\teth1 -> q1 ->tx\n+\t *\teth0 -> q0 ->Tx\n+\t *\teth1 -> q1 ->Tx\n \t *\n \t *\tq0, q1 are configured as ATQ so, all the different stages can\n \t *\tbe enqueued on the same queue.\n \t *\n-\t * Multi thread unsafe :\n-\t *\tqueues = 3\n+\t * eth0, eth1 use Tx adapters service core :\n+\t *\tqueues = 4\n \t *\tstride = 1\n \t *\n \t *\tevent queue pipelines:\n-\t *\teth0 -> q0\n-\t *\t\t  } (q3->tx) Tx service\n-\t *\teth1 -> q1\n+\t *\teth0 -> q0  -> q2 -> Tx\n+\t *\teth1 -> q1  -> q3 -> Tx\n \t *\n-\t *\tq0,q1 are configured as stated above.\n-\t *\tq3 configured as SINGLE_LINK|ATOMIC.\n+\t *\tq0, q1 are configured as stated above.\n+\t *\tq2, q3 configured as SINGLE_LINK.\n \t */\n \tret = pipeline_event_rx_adapter_setup(opt, 1, p_conf);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = pipeline_event_tx_adapter_setup(opt, p_conf);\n \tif (ret)\n \t\treturn ret;\n \n@@ -445,12 +422,58 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\t}\n \t}\n \n+\t/* Connect the tx_evqueue_id to the Tx adapter port */\n+\tif (!t->internal_port) {\n+\t\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\t\tret = rte_event_eth_tx_adapter_event_port_get(prod,\n+\t\t\t\t\t&tx_evport_id);\n+\t\t\tif (ret) {\n+\t\t\t\tevt_err(\"Unable to get Tx adapter[%d]\", prod);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tif (rte_event_port_link(opt->dev_id, tx_evport_id,\n+\t\t\t\t\t\t&tx_evqueue_id[prod],\n+\t\t\t\t\t\tNULL, 1) != 1) {\n+\t\t\t\tevt_err(\"Unable to link Tx adptr[%d] evprt[%d]\",\n+\t\t\t\t\t\tprod, tx_evport_id);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\tret = rte_eth_dev_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Ethernet dev [%d] failed to start.\"\n+\t\t\t\t\t\" Using synthetic producer\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n \tret = rte_event_dev_start(opt->dev_id);\n \tif (ret) {\n \t\tevt_err(\"failed to start eventdev %d\", opt->dev_id);\n \t\treturn ret;\n \t}\n \n+\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\tret = rte_event_eth_rx_adapter_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Rx adapter[%d] start failed\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret = rte_event_eth_tx_adapter_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Tx adapter[%d] start failed\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tmemcpy(t->tx_evqueue_id, tx_evqueue_id, sizeof(uint8_t) *\n+\t\t\tRTE_MAX_ETHPORTS);\n+\n \treturn 0;\n }\n \ndiff --git a/app/test-eventdev/test_pipeline_common.c b/app/test-eventdev/test_pipeline_common.c\nindex 832ab8b6e..752b5fded 100644\n--- a/app/test-eventdev/test_pipeline_common.c\n+++ b/app/test-eventdev/test_pipeline_common.c\n@@ -5,58 +5,6 @@\n \n #include \"test_pipeline_common.h\"\n \n-static int32_t\n-pipeline_event_tx_burst_service_func(void *args)\n-{\n-\n-\tint i;\n-\tstruct tx_service_data *tx = args;\n-\tconst uint8_t dev = tx->dev_id;\n-\tconst uint8_t port = tx->port_id;\n-\tstruct rte_event ev[BURST_SIZE + 1];\n-\n-\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);\n-\n-\tif (!nb_rx) {\n-\t\tfor (i = 0; i < tx->nb_ethports; i++)\n-\t\t\trte_eth_tx_buffer_flush(i, 0, tx->tx_buf[i]);\n-\t\treturn 0;\n-\t}\n-\n-\tfor (i = 0; i < nb_rx; i++) {\n-\t\tstruct rte_mbuf *m = ev[i].mbuf;\n-\t\trte_eth_tx_buffer(m->port, 0, tx->tx_buf[m->port], m);\n-\t}\n-\ttx->processed_pkts += nb_rx;\n-\n-\treturn 0;\n-}\n-\n-static int32_t\n-pipeline_event_tx_service_func(void *args)\n-{\n-\n-\tint i;\n-\tstruct tx_service_data *tx = args;\n-\tconst uint8_t dev = tx->dev_id;\n-\tconst uint8_t port = tx->port_id;\n-\tstruct rte_event ev;\n-\n-\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n-\n-\tif (!nb_rx) {\n-\t\tfor (i = 0; i < tx->nb_ethports; i++)\n-\t\t\trte_eth_tx_buffer_flush(i, 0, tx->tx_buf[i]);\n-\t\treturn 0;\n-\t}\n-\n-\tstruct rte_mbuf *m = ev.mbuf;\n-\trte_eth_tx_buffer(m->port, 0, tx->tx_buf[m->port], m);\n-\ttx->processed_pkts++;\n-\n-\treturn 0;\n-}\n-\n int\n pipeline_test_result(struct evt_test *test, struct evt_options *opt)\n {\n@@ -97,11 +45,8 @@ processed_pkts(struct test_pipeline *t)\n \tuint64_t total = 0;\n \n \trte_smp_rmb();\n-\tif (t->mt_unsafe)\n-\t\ttotal = t->tx_service.processed_pkts;\n-\telse\n-\t\tfor (i = 0; i < t->nb_workers; i++)\n-\t\t\ttotal += t->worker[i].processed_pkts;\n+\tfor (i = 0; i < t->nb_workers; i++)\n+\t\ttotal += t->worker[i].processed_pkts;\n \n \treturn total;\n }\n@@ -215,7 +160,6 @@ pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt)\n {\n \tuint16_t i;\n \tuint8_t nb_queues = 1;\n-\tuint8_t mt_state = 0;\n \tstruct test_pipeline *t = evt_test_priv(test);\n \tstruct rte_eth_rxconf rx_conf;\n \tstruct rte_eth_conf port_conf = {\n@@ -238,13 +182,17 @@ pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\treturn -ENODEV;\n \t}\n \n+\tt->internal_port = 1;\n \tRTE_ETH_FOREACH_DEV(i) {\n \t\tstruct rte_eth_dev_info dev_info;\n \t\tstruct rte_eth_conf local_port_conf = port_conf;\n+\t\tuint32_t caps = 0;\n+\n+\t\trte_event_eth_tx_adapter_caps_get(opt->dev_id, i, &caps);\n+\t\tif (!(caps & RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT))\n+\t\t\tt->internal_port = 0;\n \n \t\trte_eth_dev_info_get(i, &dev_info);\n-\t\tmt_state = !(dev_info.tx_offload_capa &\n-\t\t\t\tDEV_TX_OFFLOAD_MT_LOCKFREE);\n \t\trx_conf = dev_info.default_rxconf;\n \t\trx_conf.offloads = port_conf.rxmode.offloads;\n \n@@ -279,11 +227,6 @@ pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\t\treturn -EINVAL;\n \t\t}\n \n-\t\tt->mt_unsafe |= mt_state;\n-\t\tt->tx_service.tx_buf[i] =\n-\t\t\trte_malloc(NULL, RTE_ETH_TX_BUFFER_SIZE(BURST_SIZE), 0);\n-\t\tif (t->tx_service.tx_buf[i] == NULL)\n-\t\t\trte_panic(\"Unable to allocate Tx buffer memory.\");\n \t\trte_eth_promiscuous_enable(i);\n \t}\n \n@@ -295,7 +238,6 @@ pipeline_event_port_setup(struct evt_test *test, struct evt_options *opt,\n \t\tuint8_t *queue_arr, uint8_t nb_queues,\n \t\tconst struct rte_event_port_conf p_conf)\n {\n-\tint i;\n \tint ret;\n \tuint8_t port;\n \tstruct test_pipeline *t = evt_test_priv(test);\n@@ -316,23 +258,15 @@ pipeline_event_port_setup(struct evt_test *test, struct evt_options *opt,\n \t\t\treturn ret;\n \t\t}\n \n-\t\tif (queue_arr == NULL) {\n-\t\t\tif (rte_event_port_link(opt->dev_id, port, NULL, NULL,\n-\t\t\t\t\t\t0) != nb_queues)\n-\t\t\t\tgoto link_fail;\n-\t\t} else {\n-\t\t\tfor (i = 0; i < nb_queues; i++) {\n-\t\t\t\tif (rte_event_port_link(opt->dev_id, port,\n-\t\t\t\t\t\t&queue_arr[i], NULL, 1) != 1)\n-\t\t\t\t\tgoto link_fail;\n-\t\t\t}\n-\t\t}\n+\t\tif (rte_event_port_link(opt->dev_id, port, queue_arr, NULL,\n+\t\t\t\t\tnb_queues) != nb_queues)\n+\t\t\tgoto link_fail;\n \t}\n \n \treturn 0;\n \n link_fail:\n-\tevt_err(\"failed to link all queues to port %d\", port);\n+\tevt_err(\"failed to link queues to port %d\", port);\n \treturn -EINVAL;\n }\n \n@@ -385,79 +319,64 @@ pipeline_event_rx_adapter_setup(struct evt_options *opt, uint8_t stride,\n \t\t\t}\n \t\t}\n \n-\t\tret = rte_eth_dev_start(prod);\n-\t\tif (ret) {\n-\t\t\tevt_err(\"Ethernet dev [%d] failed to start.\"\n-\t\t\t\t\t\" Using synthetic producer\", prod);\n-\t\t\treturn ret;\n-\t\t}\n-\n-\t\tret = rte_event_eth_rx_adapter_start(prod);\n-\t\tif (ret) {\n-\t\t\tevt_err(\"Rx adapter[%d] start failed\", prod);\n-\t\t\treturn ret;\n-\t\t}\n-\t\tevt_info(\"Port[%d] using Rx adapter[%d] started\", prod, prod);\n+\t\tevt_info(\"Port[%d] using Rx adapter[%d] configured\", prod,\n+\t\t\t\tprod);\n \t}\n \n \treturn ret;\n }\n \n int\n-pipeline_event_tx_service_setup(struct evt_test *test, struct evt_options *opt,\n-\t\tuint8_t tx_queue_id, uint8_t tx_port_id,\n-\t\tconst struct rte_event_port_conf p_conf)\n+pipeline_event_tx_adapter_setup(struct evt_options *opt,\n+\t\tstruct rte_event_port_conf port_conf)\n {\n \tint ret;\n-\tstruct rte_service_spec serv;\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\tstruct tx_service_data *tx = &t->tx_service;\n+\tuint16_t consm;\n \n-\tret = rte_event_port_setup(opt->dev_id, tx_port_id, &p_conf);\n-\tif (ret) {\n-\t\tevt_err(\"failed to setup port %d\", tx_port_id);\n-\t\treturn ret;\n-\t}\n+\tRTE_ETH_FOREACH_DEV(consm) {\n+\t\tuint32_t cap;\n \n-\tif (rte_event_port_link(opt->dev_id, tx_port_id, &tx_queue_id,\n-\t\t\t\tNULL, 1) != 1) {\n-\t\tevt_err(\"failed to link queues to port %d\", tx_port_id);\n-\t\treturn -EINVAL;\n-\t}\n+\t\tret = rte_event_eth_tx_adapter_caps_get(opt->dev_id,\n+\t\t\t\tconsm, &cap);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"failed to get event tx adapter[%d] caps\",\n+\t\t\t\t\tconsm);\n+\t\t\treturn ret;\n+\t\t}\n \n-\ttx->dev_id = opt->dev_id;\n-\ttx->queue_id = tx_queue_id;\n-\ttx->port_id = tx_port_id;\n-\ttx->nb_ethports = rte_eth_dev_count_avail();\n-\ttx->t = t;\n-\n-\t/* Register Tx service */\n-\tmemset(&serv, 0, sizeof(struct rte_service_spec));\n-\tsnprintf(serv.name, sizeof(serv.name), \"Tx_service\");\n-\n-\tif (evt_has_burst_mode(opt->dev_id))\n-\t\tserv.callback = pipeline_event_tx_burst_service_func;\n-\telse\n-\t\tserv.callback = pipeline_event_tx_service_func;\n-\n-\tserv.callback_userdata = (void *)tx;\n-\tret = rte_service_component_register(&serv, &tx->service_id);\n-\tif (ret) {\n-\t\tevt_err(\"failed to register Tx service\");\n-\t\treturn ret;\n-\t}\n+\t\tret = rte_event_eth_tx_adapter_create(consm, opt->dev_id,\n+\t\t\t\t&port_conf);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"failed to create tx adapter[%d]\", consm);\n+\t\t\treturn ret;\n+\t\t}\n \n-\tret = evt_service_setup(tx->service_id);\n-\tif (ret) {\n-\t\tevt_err(\"Failed to setup service core for Tx service\\n\");\n-\t\treturn ret;\n-\t}\n+\t\tret = rte_event_eth_tx_adapter_queue_add(consm, consm, -1);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"failed to add tx queues to adapter[%d]\",\n+\t\t\t\t\tconsm);\n+\t\t\treturn ret;\n+\t\t}\n \n-\trte_service_runstate_set(tx->service_id, 1);\n+\t\tif (!(cap & RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT)) {\n+\t\t\tuint32_t service_id;\n \n-\treturn 0;\n-}\n+\t\t\trte_event_eth_tx_adapter_service_id_get(consm,\n+\t\t\t\t\t&service_id);\n+\t\t\tret = evt_service_setup(service_id);\n+\t\t\tif (ret) {\n+\t\t\t\tevt_err(\"Failed to setup service core\"\n+\t\t\t\t\t\t\" for Tx adapter\\n\");\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\tevt_info(\"Port[%d] using Tx adapter[%d] Configured\", consm,\n+\t\t\t\tconsm);\n+\t}\n \n+\treturn ret;\n+}\n \n void\n pipeline_ethdev_destroy(struct evt_test *test, struct evt_options *opt)\n@@ -465,16 +384,10 @@ pipeline_ethdev_destroy(struct evt_test *test, struct evt_options *opt)\n \tuint16_t i;\n \tRTE_SET_USED(test);\n \tRTE_SET_USED(opt);\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\n-\tif (t->mt_unsafe) {\n-\t\trte_service_component_runstate_set(t->tx_service.service_id, 0);\n-\t\trte_service_runstate_set(t->tx_service.service_id, 0);\n-\t\trte_service_component_unregister(t->tx_service.service_id);\n-\t}\n \n \tRTE_ETH_FOREACH_DEV(i) {\n \t\trte_event_eth_rx_adapter_stop(i);\n+\t\trte_event_eth_tx_adapter_stop(i);\n \t\trte_eth_dev_stop(i);\n \t}\n }\n@@ -484,7 +397,6 @@ pipeline_eventdev_destroy(struct evt_test *test, struct evt_options *opt)\n {\n \tRTE_SET_USED(test);\n \n-\trte_event_dev_stop(opt->dev_id);\n \trte_event_dev_close(opt->dev_id);\n }\n \ndiff --git a/app/test-eventdev/test_pipeline_common.h b/app/test-eventdev/test_pipeline_common.h\nindex 9cd6b905b..0440b9e29 100644\n--- a/app/test-eventdev/test_pipeline_common.h\n+++ b/app/test-eventdev/test_pipeline_common.h\n@@ -14,6 +14,7 @@\n #include <rte_ethdev.h>\n #include <rte_eventdev.h>\n #include <rte_event_eth_rx_adapter.h>\n+#include <rte_event_eth_tx_adapter.h>\n #include <rte_lcore.h>\n #include <rte_malloc.h>\n #include <rte_mempool.h>\n@@ -35,30 +36,19 @@ struct worker_data {\n \tstruct test_pipeline *t;\n } __rte_cache_aligned;\n \n-struct tx_service_data {\n-\tuint8_t dev_id;\n-\tuint8_t queue_id;\n-\tuint8_t port_id;\n-\tuint32_t service_id;\n-\tuint64_t processed_pkts;\n-\tuint16_t nb_ethports;\n-\tstruct rte_eth_dev_tx_buffer *tx_buf[RTE_MAX_ETHPORTS];\n-\tstruct test_pipeline *t;\n-} __rte_cache_aligned;\n-\n struct test_pipeline {\n \t/* Don't change the offset of \"done\". Signal handler use this memory\n \t * to terminate all lcores work.\n \t */\n \tint done;\n \tuint8_t nb_workers;\n-\tuint8_t mt_unsafe;\n+\tuint8_t internal_port;\n+\tuint8_t tx_evqueue_id[RTE_MAX_ETHPORTS];\n \tenum evt_test_result result;\n \tuint32_t nb_flows;\n \tuint64_t outstand_pkts;\n \tstruct rte_mempool *pool;\n \tstruct worker_data worker[EVT_MAX_PORTS];\n-\tstruct tx_service_data tx_service;\n \tstruct evt_options *opt;\n \tuint8_t sched_type_list[EVT_MAX_STAGES] __rte_cache_aligned;\n } __rte_cache_aligned;\n@@ -70,7 +60,7 @@ struct test_pipeline {\n \tstruct test_pipeline *t = w->t;   \\\n \tconst uint8_t dev = w->dev_id;    \\\n \tconst uint8_t port = w->port_id;  \\\n-\tstruct rte_event ev\n+\tstruct rte_event ev __rte_cache_aligned\n \n #define PIPELINE_WORKER_SINGLE_STAGE_BURST_INIT \\\n \tint i;                                  \\\n@@ -78,7 +68,7 @@ struct test_pipeline {\n \tstruct test_pipeline *t = w->t;         \\\n \tconst uint8_t dev = w->dev_id;          \\\n \tconst uint8_t port = w->port_id;        \\\n-\tstruct rte_event ev[BURST_SIZE + 1]\n+\tstruct rte_event ev[BURST_SIZE + 1] __rte_cache_aligned\n \n #define PIPELINE_WORKER_MULTI_STAGE_INIT                         \\\n \tstruct worker_data *w  = arg;                            \\\n@@ -88,10 +78,11 @@ struct test_pipeline {\n \tconst uint8_t port = w->port_id;                         \\\n \tconst uint8_t last_queue = t->opt->nb_stages - 1;        \\\n \tuint8_t *const sched_type_list = &t->sched_type_list[0]; \\\n-\tstruct rte_event ev\n+\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\t \\\n+\tstruct rte_event ev __rte_cache_aligned\n \n #define PIPELINE_WORKER_MULTI_STAGE_BURST_INIT                   \\\n-\tint i;                                  \\\n+\tint i;                                                   \\\n \tstruct worker_data *w  = arg;                            \\\n \tstruct test_pipeline *t = w->t;                          \\\n \tuint8_t cq_id;                                           \\\n@@ -99,7 +90,8 @@ struct test_pipeline {\n \tconst uint8_t port = w->port_id;                         \\\n \tconst uint8_t last_queue = t->opt->nb_stages - 1;        \\\n \tuint8_t *const sched_type_list = &t->sched_type_list[0]; \\\n-\tstruct rte_event ev[BURST_SIZE + 1]\n+\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\t \\\n+\tstruct rte_event ev[BURST_SIZE + 1] __rte_cache_aligned\n \n static __rte_always_inline void\n pipeline_fwd_event(struct rte_event *ev, uint8_t sched)\n@@ -109,6 +101,28 @@ pipeline_fwd_event(struct rte_event *ev, uint8_t sched)\n \tev->sched_type = sched;\n }\n \n+static __rte_always_inline void\n+pipeline_event_tx(const uint8_t dev, const uint8_t port,\n+\t\tstruct rte_event * const ev)\n+{\n+\trte_event_eth_tx_adapter_txq_set(ev->mbuf, 0);\n+\twhile (!rte_event_eth_tx_adapter_enqueue(dev, port, ev, 1))\n+\t\trte_pause();\n+}\n+\n+static __rte_always_inline void\n+pipeline_event_tx_burst(const uint8_t dev, const uint8_t port,\n+\t\tstruct rte_event *ev, const uint16_t nb_rx)\n+{\n+\tuint16_t enq;\n+\n+\tenq = rte_event_eth_tx_adapter_enqueue(dev, port, ev, nb_rx);\n+\twhile (enq < nb_rx) {\n+\t\tenq += rte_event_eth_tx_adapter_enqueue(dev, port,\n+\t\t\t\tev + enq, nb_rx - enq);\n+\t}\n+}\n+\n static __rte_always_inline void\n pipeline_event_enqueue(const uint8_t dev, const uint8_t port,\n \t\tstruct rte_event *ev)\n@@ -130,13 +144,6 @@ pipeline_event_enqueue_burst(const uint8_t dev, const uint8_t port,\n \t}\n }\n \n-static __rte_always_inline void\n-pipeline_tx_pkt(struct rte_mbuf *mbuf)\n-{\n-\twhile (rte_eth_tx_burst(mbuf->port, 0, &mbuf, 1) != 1)\n-\t\trte_pause();\n-}\n-\n static inline int\n pipeline_nb_event_ports(struct evt_options *opt)\n {\n@@ -149,9 +156,8 @@ int pipeline_test_setup(struct evt_test *test, struct evt_options *opt);\n int pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt);\n int pipeline_event_rx_adapter_setup(struct evt_options *opt, uint8_t stride,\n \t\tstruct rte_event_port_conf prod_conf);\n-int pipeline_event_tx_service_setup(struct evt_test *test,\n-\t\tstruct evt_options *opt, uint8_t tx_queue_id,\n-\t\tuint8_t tx_port_id, const struct rte_event_port_conf p_conf);\n+int pipeline_event_tx_adapter_setup(struct evt_options *opt,\n+\t\tstruct rte_event_port_conf prod_conf);\n int pipeline_mempool_setup(struct evt_test *test, struct evt_options *opt);\n int pipeline_event_port_setup(struct evt_test *test, struct evt_options *opt,\n \t\tuint8_t *queue_arr, uint8_t nb_queues,\ndiff --git a/app/test-eventdev/test_pipeline_queue.c b/app/test-eventdev/test_pipeline_queue.c\nindex 2e0d93d99..25217008c 100644\n--- a/app/test-eventdev/test_pipeline_queue.c\n+++ b/app/test-eventdev/test_pipeline_queue.c\n@@ -15,7 +15,7 @@ pipeline_queue_nb_event_queues(struct evt_options *opt)\n \treturn (eth_count * opt->nb_stages) + eth_count;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_single_stage_tx(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n@@ -29,7 +29,7 @@ pipeline_queue_worker_single_stage_tx(void *arg)\n \t\t}\n \n \t\tif (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\t\t\tpipeline_tx_pkt(ev.mbuf);\n+\t\t\tpipeline_event_tx(dev, port, &ev);\n \t\t\tw->processed_pkts++;\n \t\t} else {\n \t\t\tev.queue_id++;\n@@ -41,11 +41,11 @@ pipeline_queue_worker_single_stage_tx(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_single_stage_fwd(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -55,7 +55,8 @@ pipeline_queue_worker_single_stage_fwd(void *arg)\n \t\t\tcontinue;\n \t\t}\n \n-\t\tev.queue_id = tx_queue;\n+\t\tev.queue_id = tx_queue[ev.mbuf->port];\n+\t\trte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);\n \t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n \t\tpipeline_event_enqueue(dev, port, &ev);\n \t\tw->processed_pkts++;\n@@ -64,7 +65,7 @@ pipeline_queue_worker_single_stage_fwd(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_single_stage_burst_tx(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n@@ -81,8 +82,7 @@ pipeline_queue_worker_single_stage_burst_tx(void *arg)\n \t\tfor (i = 0; i < nb_rx; i++) {\n \t\t\trte_prefetch0(ev[i + 1].mbuf);\n \t\t\tif (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\tpipeline_tx_pkt(ev[i].mbuf);\n+\t\t\t\tpipeline_event_tx(dev, port, &ev[i]);\n \t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n \t\t\t\tw->processed_pkts++;\n \t\t\t} else {\n@@ -98,11 +98,11 @@ pipeline_queue_worker_single_stage_burst_tx(void *arg)\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_single_stage_burst_fwd(void *arg)\n {\n \tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -115,23 +115,24 @@ pipeline_queue_worker_single_stage_burst_fwd(void *arg)\n \n \t\tfor (i = 0; i < nb_rx; i++) {\n \t\t\trte_prefetch0(ev[i + 1].mbuf);\n-\t\t\tev[i].queue_id = tx_queue;\n+\t\t\tev[i].queue_id = tx_queue[ev[i].mbuf->port];\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n \t\t\tpipeline_fwd_event(&ev[i], RTE_SCHED_TYPE_ATOMIC);\n-\t\t\tw->processed_pkts++;\n \t\t}\n \n \t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t\tw->processed_pkts += nb_rx;\n \t}\n \n \treturn 0;\n }\n \n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_multi_stage_tx(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -143,31 +144,27 @@ pipeline_queue_worker_multi_stage_tx(void *arg)\n \n \t\tcq_id = ev.queue_id % nb_stages;\n \n-\t\tif (cq_id >= last_queue) {\n-\t\t\tif (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\tpipeline_tx_pkt(ev.mbuf);\n-\t\t\t\tw->processed_pkts++;\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t\tev.queue_id += (cq_id == last_queue) ? 1 : 0;\n-\t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n-\t\t} else {\n-\t\t\tev.queue_id++;\n-\t\t\tpipeline_fwd_event(&ev, sched_type_list[cq_id]);\n+\t\tif (ev.queue_id == tx_queue[ev.mbuf->port]) {\n+\t\t\tpipeline_event_tx(dev, port, &ev);\n+\t\t\tw->processed_pkts++;\n+\t\t\tcontinue;\n \t\t}\n \n+\t\tev.queue_id++;\n+\t\tpipeline_fwd_event(&ev, cq_id != last_queue ?\n+\t\t\t\tsched_type_list[cq_id] :\n+\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n \t\tpipeline_event_enqueue(dev, port, &ev);\n \t}\n+\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_multi_stage_fwd(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n@@ -180,7 +177,8 @@ pipeline_queue_worker_multi_stage_fwd(void *arg)\n \t\tcq_id = ev.queue_id % nb_stages;\n \n \t\tif (cq_id == last_queue) {\n-\t\t\tev.queue_id = tx_queue;\n+\t\t\tev.queue_id = tx_queue[ev.mbuf->port];\n+\t\t\trte_event_eth_tx_adapter_txq_set(ev.mbuf, 0);\n \t\t\tpipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC);\n \t\t\tw->processed_pkts++;\n \t\t} else {\n@@ -190,14 +188,15 @@ pipeline_queue_worker_multi_stage_fwd(void *arg)\n \n \t\tpipeline_event_enqueue(dev, port, &ev);\n \t}\n+\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_multi_stage_burst_tx(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -212,37 +211,30 @@ pipeline_queue_worker_multi_stage_burst_tx(void *arg)\n \t\t\trte_prefetch0(ev[i + 1].mbuf);\n \t\t\tcq_id = ev[i].queue_id % nb_stages;\n \n-\t\t\tif (cq_id >= last_queue) {\n-\t\t\t\tif (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\n-\t\t\t\t\tpipeline_tx_pkt(ev[i].mbuf);\n-\t\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n-\t\t\t\t\tw->processed_pkts++;\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n-\n-\t\t\t\tev[i].queue_id += (cq_id == last_queue) ? 1 : 0;\n-\t\t\t\tpipeline_fwd_event(&ev[i],\n-\t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n-\t\t\t} else {\n-\t\t\t\tev[i].queue_id++;\n-\t\t\t\tpipeline_fwd_event(&ev[i],\n-\t\t\t\t\t\tsched_type_list[cq_id]);\n+\t\t\tif (ev[i].queue_id == tx_queue[ev[i].mbuf->port]) {\n+\t\t\t\tpipeline_event_tx(dev, port, &ev[i]);\n+\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n+\t\t\t\tw->processed_pkts++;\n+\t\t\t\tcontinue;\n \t\t\t}\n \n+\t\t\tev[i].queue_id++;\n+\t\t\tpipeline_fwd_event(&ev[i], cq_id != last_queue ?\n+\t\t\t\t\tsched_type_list[cq_id] :\n+\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n \t\t}\n \n \t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n \t}\n+\n \treturn 0;\n }\n \n-static int\n+static __rte_noinline int\n pipeline_queue_worker_multi_stage_burst_fwd(void *arg)\n {\n \tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n-\tconst uint8_t nb_stages = t->opt->nb_stages + 1;\n-\tconst uint8_t tx_queue = t->tx_service.queue_id;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n \n \twhile (t->done == false) {\n \t\tuint16_t nb_rx = rte_event_dequeue_burst(dev, port, ev,\n@@ -258,7 +250,8 @@ pipeline_queue_worker_multi_stage_burst_fwd(void *arg)\n \t\t\tcq_id = ev[i].queue_id % nb_stages;\n \n \t\t\tif (cq_id == last_queue) {\n-\t\t\t\tev[i].queue_id = tx_queue;\n+\t\t\t\tev[i].queue_id = tx_queue[ev[i].mbuf->port];\n+\t\t\t\trte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0);\n \t\t\t\tpipeline_fwd_event(&ev[i],\n \t\t\t\t\t\tRTE_SCHED_TYPE_ATOMIC);\n \t\t\t\tw->processed_pkts++;\n@@ -271,6 +264,7 @@ pipeline_queue_worker_multi_stage_burst_fwd(void *arg)\n \n \t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n \t}\n+\n \treturn 0;\n }\n \n@@ -280,28 +274,28 @@ worker_wrapper(void *arg)\n \tstruct worker_data *w  = arg;\n \tstruct evt_options *opt = w->t->opt;\n \tconst bool burst = evt_has_burst_mode(w->dev_id);\n-\tconst bool mt_safe = !w->t->mt_unsafe;\n+\tconst bool internal_port = w->t->internal_port;\n \tconst uint8_t nb_stages = opt->nb_stages;\n \tRTE_SET_USED(opt);\n \n \tif (nb_stages == 1) {\n-\t\tif (!burst && mt_safe)\n+\t\tif (!burst && internal_port)\n \t\t\treturn pipeline_queue_worker_single_stage_tx(arg);\n-\t\telse if (!burst && !mt_safe)\n+\t\telse if (!burst && !internal_port)\n \t\t\treturn pipeline_queue_worker_single_stage_fwd(arg);\n-\t\telse if (burst && mt_safe)\n+\t\telse if (burst && internal_port)\n \t\t\treturn pipeline_queue_worker_single_stage_burst_tx(arg);\n-\t\telse if (burst && !mt_safe)\n+\t\telse if (burst && !internal_port)\n \t\t\treturn pipeline_queue_worker_single_stage_burst_fwd(\n \t\t\t\t\targ);\n \t} else {\n-\t\tif (!burst && mt_safe)\n+\t\tif (!burst && internal_port)\n \t\t\treturn pipeline_queue_worker_multi_stage_tx(arg);\n-\t\telse if (!burst && !mt_safe)\n+\t\telse if (!burst && !internal_port)\n \t\t\treturn pipeline_queue_worker_multi_stage_fwd(arg);\n-\t\telse if (burst && mt_safe)\n+\t\telse if (burst && internal_port)\n \t\t\treturn pipeline_queue_worker_multi_stage_burst_tx(arg);\n-\t\telse if (burst && !mt_safe)\n+\t\telse if (burst && !internal_port)\n \t\t\treturn pipeline_queue_worker_multi_stage_burst_fwd(arg);\n \n \t}\n@@ -311,10 +305,6 @@ worker_wrapper(void *arg)\n static int\n pipeline_queue_launch_lcores(struct evt_test *test, struct evt_options *opt)\n {\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\n-\tif (t->mt_unsafe)\n-\t\trte_service_component_runstate_set(t->tx_service.service_id, 1);\n \treturn pipeline_launch_lcores(test, opt, worker_wrapper);\n }\n \n@@ -326,25 +316,24 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \tint nb_queues;\n \tint nb_stages = opt->nb_stages;\n \tuint8_t queue;\n-\tstruct rte_event_dev_info info;\n-\tstruct test_pipeline *t = evt_test_priv(test);\n-\tuint8_t tx_evqueue_id = 0;\n+\tuint8_t tx_evport_id = 0;\n+\tuint8_t tx_evqueue_id[RTE_MAX_ETHPORTS];\n \tuint8_t queue_arr[RTE_EVENT_MAX_QUEUES_PER_DEV];\n \tuint8_t nb_worker_queues = 0;\n+\tuint16_t prod = 0;\n+\tstruct rte_event_dev_info info;\n+\tstruct test_pipeline *t = evt_test_priv(test);\n \n \tnb_ports = evt_nr_active_lcores(opt->wlcores);\n \tnb_queues = rte_eth_dev_count_avail() * (nb_stages);\n \n-\t/* Extra port for Tx service. */\n-\tif (t->mt_unsafe) {\n-\t\ttx_evqueue_id = nb_queues;\n-\t\tnb_ports++;\n-\t\tnb_queues++;\n-\t} else\n-\t\tnb_queues += rte_eth_dev_count_avail();\n+\t/* One queue for Tx adapter per port */\n+\tnb_queues += rte_eth_dev_count_avail();\n \n-\trte_event_dev_info_get(opt->dev_id, &info);\n+\tmemset(tx_evqueue_id, 0, sizeof(uint8_t) * RTE_MAX_ETHPORTS);\n+\tmemset(queue_arr, 0, sizeof(uint8_t) * RTE_EVENT_MAX_QUEUES_PER_DEV);\n \n+\trte_event_dev_info_get(opt->dev_id, &info);\n \tconst struct rte_event_dev_config config = {\n \t\t\t.nb_event_queues = nb_queues,\n \t\t\t.nb_event_ports = nb_ports,\n@@ -370,24 +359,19 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \tfor (queue = 0; queue < nb_queues; queue++) {\n \t\tuint8_t slot;\n \n-\t\tif (!t->mt_unsafe) {\n-\t\t\tslot = queue % (nb_stages + 1);\n-\t\t\tq_conf.schedule_type = slot == nb_stages ?\n-\t\t\t\tRTE_SCHED_TYPE_ATOMIC :\n-\t\t\t\topt->sched_type_list[slot];\n-\t\t} else {\n-\t\t\tslot = queue % nb_stages;\n-\n-\t\t\tif (queue == tx_evqueue_id) {\n-\t\t\t\tq_conf.schedule_type = RTE_SCHED_TYPE_ATOMIC;\n+\t\tq_conf.event_queue_cfg = 0;\n+\t\tslot = queue % (nb_stages + 1);\n+\t\tif (slot == nb_stages) {\n+\t\t\tq_conf.schedule_type = RTE_SCHED_TYPE_ATOMIC;\n+\t\t\tif (!t->internal_port) {\n \t\t\t\tq_conf.event_queue_cfg =\n \t\t\t\t\tRTE_EVENT_QUEUE_CFG_SINGLE_LINK;\n-\t\t\t} else {\n-\t\t\t\tq_conf.schedule_type =\n-\t\t\t\t\topt->sched_type_list[slot];\n-\t\t\t\tqueue_arr[nb_worker_queues] = queue;\n-\t\t\t\tnb_worker_queues++;\n \t\t\t}\n+\t\t\ttx_evqueue_id[prod++] = queue;\n+\t\t} else {\n+\t\t\tq_conf.schedule_type = opt->sched_type_list[slot];\n+\t\t\tqueue_arr[nb_worker_queues] = queue;\n+\t\t\tnb_worker_queues++;\n \t\t}\n \n \t\tret = rte_event_queue_setup(opt->dev_id, queue, &q_conf);\n@@ -407,19 +391,11 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\t\t.new_event_threshold = info.max_num_events,\n \t};\n \n-\t/*\n-\t * If tx is multi thread safe then allow workers to do Tx else use Tx\n-\t * service to Tx packets.\n-\t */\n-\tif (t->mt_unsafe) {\n+\tif (!t->internal_port) {\n \t\tret = pipeline_event_port_setup(test, opt, queue_arr,\n \t\t\t\tnb_worker_queues, p_conf);\n \t\tif (ret)\n \t\t\treturn ret;\n-\n-\t\tret = pipeline_event_tx_service_setup(test, opt, tx_evqueue_id,\n-\t\t\t\tnb_ports - 1, p_conf);\n-\n \t} else\n \t\tret = pipeline_event_port_setup(test, opt, NULL, nb_queues,\n \t\t\t\tp_conf);\n@@ -431,7 +407,6 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t *\n \t * eth_dev_count = 2, nb_stages = 2.\n \t *\n-\t * Multi thread safe :\n \t *\tqueues = 6\n \t *\tstride = 3\n \t *\n@@ -439,21 +414,14 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t *\teth0 -> q0 -> q1 -> (q2->tx)\n \t *\teth1 -> q3 -> q4 -> (q5->tx)\n \t *\n-\t *\tq2, q5 configured as ATOMIC\n-\t *\n-\t * Multi thread unsafe :\n-\t *\tqueues = 5\n-\t *\tstride = 2\n-\t *\n-\t *\tevent queue pipelines:\n-\t *\teth0 -> q0 -> q1\n-\t *\t\t\t} (q4->tx) Tx service\n-\t *\teth1 -> q2 -> q3\n+\t *\tq2, q5 configured as ATOMIC | SINGLE_LINK\n \t *\n-\t *\tq4 configured as SINGLE_LINK|ATOMIC\n \t */\n-\tret = pipeline_event_rx_adapter_setup(opt,\n-\t\t\tt->mt_unsafe ? nb_stages : nb_stages + 1, p_conf);\n+\tret = pipeline_event_rx_adapter_setup(opt, nb_stages + 1, p_conf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = pipeline_event_tx_adapter_setup(opt, p_conf);\n \tif (ret)\n \t\treturn ret;\n \n@@ -467,12 +435,60 @@ pipeline_queue_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\t}\n \t}\n \n+\t/* Connect the tx_evqueue_id to the Tx adapter port */\n+\tif (!t->internal_port) {\n+\t\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\t\tret = rte_event_eth_tx_adapter_event_port_get(prod,\n+\t\t\t\t\t&tx_evport_id);\n+\t\t\tif (ret) {\n+\t\t\t\tevt_err(\"Unable to get Tx adptr[%d] evprt[%d]\",\n+\t\t\t\t\t\tprod, tx_evport_id);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tif (rte_event_port_link(opt->dev_id, tx_evport_id,\n+\t\t\t\t\t\t&tx_evqueue_id[prod],\n+\t\t\t\t\t\tNULL, 1) != 1) {\n+\t\t\t\tevt_err(\"Unable to link Tx adptr[%d] evprt[%d]\",\n+\t\t\t\t\t\tprod, tx_evport_id);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\tret = rte_eth_dev_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Ethernet dev [%d] failed to start.\"\n+\t\t\t\t\t\" Using synthetic producer\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t}\n+\n \tret = rte_event_dev_start(opt->dev_id);\n \tif (ret) {\n \t\tevt_err(\"failed to start eventdev %d\", opt->dev_id);\n \t\treturn ret;\n \t}\n \n+\tRTE_ETH_FOREACH_DEV(prod) {\n+\t\tret = rte_event_eth_rx_adapter_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Rx adapter[%d] start failed\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret = rte_event_eth_tx_adapter_start(prod);\n+\t\tif (ret) {\n+\t\t\tevt_err(\"Tx adapter[%d] start failed\", prod);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tmemcpy(t->tx_evqueue_id, tx_evqueue_id, sizeof(uint8_t) *\n+\t\t\tRTE_MAX_ETHPORTS);\n+\n \treturn 0;\n }\n \n",
    "prefixes": [
        "v4",
        "3/4"
    ]
}