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{
    "id": 34061,
    "url": "https://patches.dpdk.org/api/patches/34061/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20180119004430.15305-9-yskoh@mellanox.com/",
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    "msgid": "<20180119004430.15305-9-yskoh@mellanox.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20180119004430.15305-9-yskoh@mellanox.com",
    "date": "2018-01-19T00:44:30",
    "name": "[dpdk-dev,v3,8/8] net/mlx5: fix synchonization on polling Rx completions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "1727a5a5cdf70206949b14469dc502d0358a707c",
    "submitter": {
        "id": 636,
        "url": "https://patches.dpdk.org/api/people/636/?format=api",
        "name": "Yongseok Koh",
        "email": "yskoh@mellanox.com"
    },
    "delegate": {
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        "url": "https://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20180119004430.15305-9-yskoh@mellanox.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/34061/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/34061/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Yongseok Koh <yskoh@mellanox.com>",
        "To": "adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com,\n\tbruce.richardson@intel.com, konstantin.ananyev@intel.com,\n\tchaozhu@linux.vnet.ibm.com, jerin.jacob@caviumnetworks.com,\n\tjianbo.liu@arm.com",
        "Cc": "dev@dpdk.org,\n\tYongseok Koh <yskoh@mellanox.com>,\n\tstable@dpdk.org",
        "Date": "Thu, 18 Jan 2018 16:44:30 -0800",
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        "Subject": "[dpdk-dev] [PATCH v3 8/8] net/mlx5: fix synchonization on polling\n\tRx completions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Polling a new packet is basically sensing the generation bit in a\ncompletion entry. For some processors not having strongly-ordered memory\nmodel, there has to be an IO memory barrier between reading the generation\nbit and other fields of the entry in order to guarantee data is not stale.\n\nFixes: 570acdb1da8a (\"net/mlx5: add vectorized Rx/Tx burst for ARM\")\nCc: stable@dpdk.org\n\nSigned-off-by: Yongseok Koh <yskoh@mellanox.com>\nAcked-by: Shahaf Shuler <shahafs@mellanox.com>\nAcked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>\n---\n drivers/net/mlx5/mlx5_rxtx.c          |  1 +\n drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 53 ++++++++++++++++++++---------------\n drivers/net/mlx5/mlx5_rxtx_vec_sse.h  |  2 +-\n 3 files changed, 32 insertions(+), 24 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 99a5f8681..8065d9d0b 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -1669,6 +1669,7 @@ mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,\n \t\t\treturn 0;\n \t\t++rxq->cq_ci;\n \t\top_own = cqe->op_own;\n+\t\trte_dma_rmb();\n \t\tif (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {\n \t\t\tvolatile struct mlx5_mini_cqe8 (*mc)[8] =\n \t\t\t\t(volatile struct mlx5_mini_cqe8 (*)[8])\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\nindex e11565f69..29ae933e7 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n@@ -814,6 +814,7 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,\n \t\tuint16x4_t mask;\n \t\tuint16x4_t byte_cnt;\n \t\tuint32x4_t ptype_info, flow_tag;\n+\t\tregister uint64x2_t c0, c1, c2, c3;\n \t\tuint8_t *p0, *p1, *p2, *p3;\n \t\tuint8_t *e0 = (void *)&elts[pos]->pkt_len;\n \t\tuint8_t *e1 = (void *)&elts[pos + 1]->pkt_len;\n@@ -830,6 +831,16 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,\n \t\tp1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe);\n \t\tp2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe);\n \t\tp3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe);\n+\t\t/* B.0 (CQE 3) load a block having op_own. */\n+\t\tc3 = vld1q_u64((uint64_t *)(p3 + 48));\n+\t\t/* B.0 (CQE 2) load a block having op_own. */\n+\t\tc2 = vld1q_u64((uint64_t *)(p2 + 48));\n+\t\t/* B.0 (CQE 1) load a block having op_own. */\n+\t\tc1 = vld1q_u64((uint64_t *)(p1 + 48));\n+\t\t/* B.0 (CQE 0) load a block having op_own. */\n+\t\tc0 = vld1q_u64((uint64_t *)(p0 + 48));\n+\t\t/* Synchronize for loading the rest of blocks. */\n+\t\trte_dma_rmb();\n \t\t/* Prefetch next 4 CQEs. */\n \t\tif (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {\n \t\t\tunsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;\n@@ -839,50 +850,46 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,\n \t\t\trte_prefetch_non_temporal(&cq[next + 3]);\n \t\t}\n \t\t__asm__ volatile (\n-\t\t/* B.1 (CQE 3) load a block having op_own. */\n-\t\t\"ld1 {v19.16b}, [%[p3]] \\n\\t\"\n-\t\t\"sub %[p3], %[p3], #48 \\n\\t\"\n-\t\t/* B.2 (CQE 3) load the rest blocks. */\n+\t\t/* B.1 (CQE 3) load the rest of blocks. */\n \t\t\"ld1 {v16.16b - v18.16b}, [%[p3]] \\n\\t\"\n+\t\t/* B.2 (CQE 3) move the block having op_own. */\n+\t\t\"mov v19.16b, %[c3].16b \\n\\t\"\n \t\t/* B.3 (CQE 3) extract 16B fields. */\n \t\t\"tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \\n\\t\"\n+\t\t/* B.1 (CQE 2) load the rest of blocks. */\n+\t\t\"ld1 {v16.16b - v18.16b}, [%[p2]] \\n\\t\"\n \t\t/* B.4 (CQE 3) adjust CRC length. */\n \t\t\"sub v23.8h, v23.8h, %[crc_adj].8h \\n\\t\"\n-\t\t/* B.1 (CQE 2) load a block having op_own. */\n-\t\t\"ld1 {v19.16b}, [%[p2]] \\n\\t\"\n-\t\t\"sub %[p2], %[p2], #48 \\n\\t\"\n \t\t/* C.1 (CQE 3) generate final structure for mbuf. */\n \t\t\"tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \\n\\t\"\n-\t\t/* B.2 (CQE 2) load the rest blocks. */\n-\t\t\"ld1 {v16.16b - v18.16b}, [%[p2]] \\n\\t\"\n+\t\t/* B.2 (CQE 2) move the block having op_own. */\n+\t\t\"mov v19.16b, %[c2].16b \\n\\t\"\n \t\t/* B.3 (CQE 2) extract 16B fields. */\n \t\t\"tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \\n\\t\"\n+\t\t/* B.1 (CQE 1) load the rest of blocks. */\n+\t\t\"ld1 {v16.16b - v18.16b}, [%[p1]] \\n\\t\"\n \t\t/* B.4 (CQE 2) adjust CRC length. */\n \t\t\"sub v22.8h, v22.8h, %[crc_adj].8h \\n\\t\"\n-\t\t/* B.1 (CQE 1) load a block having op_own. */\n-\t\t\"ld1 {v19.16b}, [%[p1]] \\n\\t\"\n-\t\t\"sub %[p1], %[p1], #48 \\n\\t\"\n \t\t/* C.1 (CQE 2) generate final structure for mbuf. */\n \t\t\"tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \\n\\t\"\n-\t\t/* B.2 (CQE 1) load the rest blocks. */\n-\t\t\"ld1 {v16.16b - v18.16b}, [%[p1]] \\n\\t\"\n+\t\t/* B.2 (CQE 1) move the block having op_own. */\n+\t\t\"mov v19.16b, %[c1].16b \\n\\t\"\n \t\t/* B.3 (CQE 1) extract 16B fields. */\n \t\t\"tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \\n\\t\"\n+\t\t/* B.1 (CQE 0) load the rest of blocks. */\n+\t\t\"ld1 {v16.16b - v18.16b}, [%[p0]] \\n\\t\"\n \t\t/* B.4 (CQE 1) adjust CRC length. */\n \t\t\"sub v21.8h, v21.8h, %[crc_adj].8h \\n\\t\"\n-\t\t/* B.1 (CQE 0) load a block having op_own. */\n-\t\t\"ld1 {v19.16b}, [%[p0]] \\n\\t\"\n-\t\t\"sub %[p0], %[p0], #48 \\n\\t\"\n \t\t/* C.1 (CQE 1) generate final structure for mbuf. */\n \t\t\"tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \\n\\t\"\n-\t\t/* B.2 (CQE 0) load the rest blocks. */\n-\t\t\"ld1 {v16.16b - v18.16b}, [%[p0]] \\n\\t\"\n+\t\t/* B.2 (CQE 0) move the block having op_own. */\n+\t\t\"mov v19.16b, %[c0].16b \\n\\t\"\n+\t\t/* A.1 load mbuf pointers. */\n+\t\t\"ld1 {v24.2d - v25.2d}, [%[elts_p]] \\n\\t\"\n \t\t/* B.3 (CQE 0) extract 16B fields. */\n \t\t\"tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \\n\\t\"\n \t\t/* B.4 (CQE 0) adjust CRC length. */\n \t\t\"sub v20.8h, v20.8h, %[crc_adj].8h \\n\\t\"\n-\t\t/* A.1 load mbuf pointers. */\n-\t\t\"ld1 {v24.2d - v25.2d}, [%[elts_p]] \\n\\t\"\n \t\t/* D.1 extract op_own byte. */\n \t\t\"tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \\n\\t\"\n \t\t/* C.2 (CQE 3) adjust flow mark. */\n@@ -917,9 +924,9 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,\n \t\t [byte_cnt]\"=&w\"(byte_cnt),\n \t\t [ptype_info]\"=&w\"(ptype_info),\n \t\t [flow_tag]\"=&w\"(flow_tag)\n-\t\t:[p3]\"r\"(p3 + 48), [p2]\"r\"(p2 + 48),\n-\t\t [p1]\"r\"(p1 + 48), [p0]\"r\"(p0 + 48),\n+\t\t:[p3]\"r\"(p3), [p2]\"r\"(p2), [p1]\"r\"(p1), [p0]\"r\"(p0),\n \t\t [e3]\"r\"(e3), [e2]\"r\"(e2), [e1]\"r\"(e1), [e0]\"r\"(e0),\n+\t\t [c3]\"w\"(c3), [c2]\"w\"(c2), [c1]\"w\"(c1), [c0]\"w\"(c0),\n \t\t [elts_p]\"r\"(elts_p),\n \t\t [pkts_p]\"r\"(pkts_p),\n \t\t [cqe_shuf_m]\"w\"(cqe_shuf_m),\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\nindex 559b0237e..6c4d1c3d5 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n@@ -833,7 +833,7 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,\n \t\t/* B.2 copy mbuf pointers. */\n \t\t_mm_storeu_si128((__m128i *)&pkts[pos], mbp1);\n \t\t_mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2);\n-\t\trte_compiler_barrier();\n+\t\trte_dma_rmb();\n \t\t/* C.1 load remained CQE data and extract necessary fields. */\n \t\tcqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]);\n \t\tcqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]);\n",
    "prefixes": [
        "dpdk-dev",
        "v3",
        "8/8"
    ]
}