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GET /api/patches/33047/?format=api
{ "id": 33047, "url": "https://patches.dpdk.org/api/patches/33047/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1515388414-16214-15-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1515388414-16214-15-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1515388414-16214-15-git-send-email-wenzhuo.lu@intel.com", "date": "2018-01-08T05:13:34", "name": "[dpdk-dev,v5,14/14] net/avf: enable Rx interrupt support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c96a57e4de64aedb027839406c1da580016acbb7", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1515388414-16214-15-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/33047/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/33047/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A8ADA1B22C;\n\tMon, 8 Jan 2018 06:12:06 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id E5B7B1B1D5\n\tfor <dev@dpdk.org>; Mon, 8 Jan 2018 06:11:55 +0100 (CET)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t07 Jan 2018 21:11:55 -0800", "from dpdk26.sh.intel.com ([10.67.110.152])\n\tby fmsmga008.fm.intel.com with ESMTP; 07 Jan 2018 21:11:54 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.46,329,1511856000\"; d=\"scan'208\";a=\"8086151\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Jingjing Wu <jingjing.wu@intel.com>", "Date": "Mon, 8 Jan 2018 13:13:34 +0800", "Message-Id": "<1515388414-16214-15-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1515388414-16214-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1515140505-38655-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1515388414-16214-1-git-send-email-wenzhuo.lu@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v5 14/14] net/avf: enable Rx interrupt support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jingjing Wu <jingjing.wu@intel.com>\n\nUpdate the doc for the AVF features either.\n\nSigned-off-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n doc/guides/nics/features/avf.ini | 1 +\n doc/guides/nics/features/avf_vec.ini | 1 +\n doc/guides/nics/intel_vf.rst | 20 +++-\n doc/guides/rel_notes/release_18_02.rst | 16 +++\n drivers/net/avf/avf_ethdev.c | 204 +++++++++++++++++++++++++++------\n 5 files changed, 204 insertions(+), 38 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/avf.ini b/doc/guides/nics/features/avf.ini\nindex da4d81b..ccb9edd 100644\n--- a/doc/guides/nics/features/avf.ini\n+++ b/doc/guides/nics/features/avf.ini\n@@ -7,6 +7,7 @@\n Speed capabilities = Y\n Link status = Y\n Link status event = Y\n+Rx interrupt = Y\n Queue start/stop = Y\n MTU update = Y\n Jumbo frame = Y\ndiff --git a/doc/guides/nics/features/avf_vec.ini b/doc/guides/nics/features/avf_vec.ini\nindex 45dd5e5..8924994 100644\n--- a/doc/guides/nics/features/avf_vec.ini\n+++ b/doc/guides/nics/features/avf_vec.ini\n@@ -7,6 +7,7 @@\n Speed capabilities = Y\n Link status = Y\n Link status event = Y\n+Rx interrupt = Y\n Queue start/stop = Y\n MTU update = Y\n Jumbo frame = Y\ndiff --git a/doc/guides/nics/intel_vf.rst b/doc/guides/nics/intel_vf.rst\nindex 1e83bf6..66f90b1 100644\n--- a/doc/guides/nics/intel_vf.rst\n+++ b/doc/guides/nics/intel_vf.rst\n@@ -28,8 +28,8 @@\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n \n-I40E/IXGBE/IGB Virtual Function Driver\n-======================================\n+Intel Virtual Function Driver\n+=============================\n \n Supported Intel® Ethernet Controllers (see the *DPDK Release Notes* for details)\n support the following modes of operation in a virtualized environment:\n@@ -93,6 +93,22 @@ and the Physical Function operates on the global resources on behalf of the Virt\n For this out-of-band communication, an SR-IOV enabled NIC provides a memory buffer for each Virtual Function,\n which is called a \"Mailbox\".\n \n+Intel® Ethernet Adaptive Virtual Function\n+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n+Adaptive Virtual Function (AVF) is a SR-IOV Virtual Function with the same device id (8086:1889) on different Intel Ethernet Controller.\n+AVF Driver is VF driver which supports for all future Intel devices without requiring a VM update. And since this happens to be an adaptive VF driver,\n+every new drop of the VF driver would add more and more advanced features that can be turned on in the VM if the underlying HW device supports those\n+advanced features based on a device agnostic way without ever compromising on the base functionality. AVF provides generic hardware interface and\n+interface between AVF driver and a compliant PF driver is specified.\n+\n+Intel products starting Ethernet Controller 710 Series to support Adaptive Virtual Function.\n+\n+The way to generate Virtual Function is like normal, and the resource of VF assignment depends on the NIC Infrastructure.\n+\n+For more detail on SR-IOV, please refer to the following documents:\n+\n+* `Intel® AVF HAS <https://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/ethernet-adaptive-virtual-function-hardware-spec.pdf>`_\n+\n The PCIE host-interface of Intel Ethernet Switch FM10000 Series VF infrastructure\n ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n \ndiff --git a/doc/guides/rel_notes/release_18_02.rst b/doc/guides/rel_notes/release_18_02.rst\nindex 24b67bb..0672b0e 100644\n--- a/doc/guides/rel_notes/release_18_02.rst\n+++ b/doc/guides/rel_notes/release_18_02.rst\n@@ -41,6 +41,22 @@ New Features\n Also, make sure to start the actual text at the margin.\n =========================================================\n \n+ * **Add AVF (Adaptive Virtual Function) net PMD.**\n+\n+ A new net PMD has been added, which supports Intel® Ethernet Adaptive\n+ Virtual Function (AVF) with features list below:\n+\n+ * Basic Rx/Tx burst\n+ * SSE vectorized Rx/Tx burst\n+ * Promiscuous mode\n+ * MAC/VLAN offload\n+ * Checksum offload\n+ * TSO offload\n+ * Jumbo frame and MTU setting\n+ * RSS configuration\n+ * stats\n+ * Rx/Tx descriptor status\n+ * Link status update/event\n \n API Changes\n -----------\ndiff --git a/drivers/net/avf/avf_ethdev.c b/drivers/net/avf/avf_ethdev.c\nindex d9f7cea..13f6329 100644\n--- a/drivers/net/avf/avf_ethdev.c\n+++ b/drivers/net/avf/avf_ethdev.c\n@@ -67,9 +67,14 @@ static int avf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n static int avf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n static void avf_dev_set_default_mac_addr(struct rte_eth_dev *dev,\n \t\t\t\t\t struct ether_addr *mac_addr);\n+static int avf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,\n+\t\t\t\t\tuint16_t queue_id);\n+static int avf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,\n+\t\t\t\t\t uint16_t queue_id);\n \n int avf_logtype_init;\n int avf_logtype_driver;\n+\n static const struct rte_pci_id pci_id_avf_map[] = {\n \t{ RTE_PCI_DEVICE(AVF_INTEL_VENDOR_ID, AVF_DEV_ID_ADAPTIVE_VF) },\n \t{ .vendor_id = 0, /* sentinel */ },\n@@ -111,6 +116,8 @@ static void avf_dev_set_default_mac_addr(struct rte_eth_dev *dev,\n \t.rx_descriptor_status = avf_dev_rx_desc_status,\n \t.tx_descriptor_status = avf_dev_tx_desc_status,\n \t.mtu_set = avf_dev_mtu_set,\n+\t.rx_queue_intr_enable = avf_dev_rx_queue_intr_enable,\n+\t.rx_queue_intr_disable = avf_dev_rx_queue_intr_disable,\n };\n \n static int\n@@ -275,6 +282,99 @@ static void avf_dev_set_default_mac_addr(struct rte_eth_dev *dev,\n \treturn ret;\n }\n \n+static int avf_config_rx_queues_irqs(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_intr_handle *intr_handle)\n+{\n+\tstruct avf_adapter *adapter =\n+\t\tAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tstruct avf_info *vf = AVF_DEV_PRIVATE_TO_VF(adapter);\n+\tstruct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(adapter);\n+\tuint16_t interval, i;\n+\tint vec;\n+\n+\tif (dev->data->dev_conf.intr_conf.rxq != 0) {\n+\t\tif (rte_intr_efd_enable(intr_handle, dev->data->nb_rx_queues))\n+\t\t\treturn -1;\n+\t}\n+\n+\tif (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {\n+\t\tintr_handle->intr_vec =\n+\t\t\trte_zmalloc(\"intr_vec\",\n+\t\t\t\t dev->data->nb_rx_queues * sizeof(int), 0);\n+\t\tif (!intr_handle->intr_vec) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate %d rx intr_vec\",\n+\t\t\t\t dev->data->nb_rx_queues);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tif (!dev->data->dev_conf.intr_conf.rxq) {\n+\t\t/* Rx interrupt disabled, Map interrupt only for writeback */\n+\t\tvf->nb_msix = 1;\n+\t\tif (vf->vf_res->vf_cap_flags &\n+\t\t VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {\n+\t\t\t/* If WB_ON_ITR supports, enable it */\n+\t\t\tvf->msix_base = AVF_RX_VEC_START;\n+\t\t\tAVF_WRITE_REG(hw, AVFINT_DYN_CTLN1(vf->msix_base - 1),\n+\t\t\t\t AVFINT_DYN_CTLN1_ITR_INDX_MASK |\n+\t\t\t\t AVFINT_DYN_CTLN1_WB_ON_ITR_MASK);\n+\t\t} else {\n+\t\t\t/* If no WB_ON_ITR offload flags, need to set\n+\t\t\t * interrupt for descriptor write back.\n+\t\t\t */\n+\t\t\tvf->msix_base = AVF_MISC_VEC_ID;\n+\n+\t\t\t/* set ITR to max */\n+\t\t\tinterval = avf_calc_itr_interval(\n+\t\t\t\t\tAVF_QUEUE_ITR_INTERVAL_MAX);\n+\t\t\tAVF_WRITE_REG(hw, AVFINT_DYN_CTL01,\n+\t\t\t\t AVFINT_DYN_CTL01_INTENA_MASK |\n+\t\t\t\t (AVF_ITR_INDEX_DEFAULT <<\n+\t\t\t\t AVFINT_DYN_CTL01_ITR_INDX_SHIFT) |\n+\t\t\t\t (interval <<\n+\t\t\t\t AVFINT_DYN_CTL01_INTERVAL_SHIFT));\n+\t\t}\n+\t\tAVF_WRITE_FLUSH(hw);\n+\t\t/* map all queues to the same interrupt */\n+\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n+\t\t\tvf->rxq_map[0] |= 1 << i;\n+\t} else {\n+\t\tif (!rte_intr_allow_others(intr_handle)) {\n+\t\t\tvf->nb_msix = 1;\n+\t\t\tvf->msix_base = AVF_MISC_VEC_ID;\n+\t\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\t\t\tvf->rxq_map[0] |= 1 << i;\n+\t\t\t\tintr_handle->intr_vec[i] = AVF_MISC_VEC_ID;\n+\t\t\t}\n+\t\t\tPMD_DRV_LOG(DEBUG,\n+\t\t\t\t \"vector 0 are mapping to all Rx queues\");\n+\t\t} else {\n+\t\t\t/* If Rx interrupt is reuquired, and we can use\n+\t\t\t * multi interrupts, then the vec is from 1\n+\t\t\t */\n+\t\t\tvf->nb_msix = RTE_MIN(vf->vf_res->max_vectors,\n+\t\t\t\t\t intr_handle->nb_efd);\n+\t\t\tvf->msix_base = AVF_RX_VEC_START;\n+\t\t\tvec = AVF_RX_VEC_START;\n+\t\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\t\t\tvf->rxq_map[vec] |= 1 << i;\n+\t\t\t\tintr_handle->intr_vec[i] = vec++;\n+\t\t\t\tif (vec >= vf->nb_msix)\n+\t\t\t\t\tvec = AVF_RX_VEC_START;\n+\t\t\t}\n+\t\t\tPMD_DRV_LOG(DEBUG,\n+\t\t\t\t \"%u vectors are mapping to %u Rx queues\",\n+\t\t\t\t vf->nb_msix, dev->data->nb_rx_queues);\n+\t\t}\n+\t}\n+\n+\tif (avf_config_irq_map(adapter)) {\n+\t\tPMD_DRV_LOG(ERR, \"config interrupt mapping failed\");\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n static int\n avf_start_queues(struct rte_eth_dev *dev)\n {\n@@ -314,8 +414,6 @@ static void avf_dev_set_default_mac_addr(struct rte_eth_dev *dev,\n \tstruct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = dev->intr_handle;\n-\tuint16_t interval;\n-\tint i;\n \n \tPMD_INIT_FUNC_TRACE();\n \n@@ -325,8 +423,6 @@ static void avf_dev_set_default_mac_addr(struct rte_eth_dev *dev,\n \tvf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,\n \t\t\t\t dev->data->nb_tx_queues);\n \n-\t/* TODO: Rx interrupt */\n-\n \tif (avf_init_queues(dev) != 0) {\n \t\tPMD_DRV_LOG(ERR, \"failed to do Queue init\");\n \t\treturn -1;\n@@ -344,36 +440,15 @@ static void avf_dev_set_default_mac_addr(struct rte_eth_dev *dev,\n \t\tgoto err_queue;\n \t}\n \n-\t/* Map interrupt for writeback */\n-\tvf->nb_msix = 1;\n-\tif (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {\n-\t\t/* If WB_ON_ITR supports, enable it */\n-\t\tvf->msix_base = AVF_RX_VEC_START;\n-\t\tAVF_WRITE_REG(hw, AVFINT_DYN_CTLN1(vf->msix_base - 1),\n-\t\t\t AVFINT_DYN_CTLN1_ITR_INDX_MASK |\n-\t\t\t AVFINT_DYN_CTLN1_WB_ON_ITR_MASK);\n-\t} else {\n-\t\t/* If no WB_ON_ITR offload flags, need to set interrupt for\n-\t\t * descriptor write back.\n-\t\t */\n-\t\tvf->msix_base = AVF_MISC_VEC_ID;\n-\n-\t\t/* set ITR to max */\n-\t\tinterval = avf_calc_itr_interval(AVF_QUEUE_ITR_INTERVAL_MAX);\n-\t\tAVF_WRITE_REG(hw, AVFINT_DYN_CTL01,\n-\t\t\t AVFINT_DYN_CTL01_INTENA_MASK |\n-\t\t\t (AVF_ITR_INDEX_DEFAULT <<\n-\t\t\t AVFINT_DYN_CTL01_ITR_INDX_SHIFT) |\n-\t\t\t (interval << AVFINT_DYN_CTL01_INTERVAL_SHIFT));\n-\t}\n-\tAVF_WRITE_FLUSH(hw);\n-\t/* map all queues to the same interrupt */\n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n-\t\tvf->rxq_map[0] |= 1 << i;\n-\tif (avf_config_irq_map(adapter)) {\n-\t\tPMD_DRV_LOG(ERR, \"config interrupt mapping failed\");\n+\tif (avf_config_rx_queues_irqs(dev, intr_handle) != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"configure irq failed\");\n \t\tgoto err_queue;\n \t}\n+\t/* re-enable intr again, because efd assign may change */\n+\tif (dev->data->dev_conf.intr_conf.rxq != 0) {\n+\t\trte_intr_disable(intr_handle);\n+\t\trte_intr_enable(intr_handle);\n+\t}\n \n \t/* Set all mac addrs */\n \tavf_add_del_all_mac_addr(adapter, TRUE);\n@@ -383,7 +458,6 @@ static void avf_dev_set_default_mac_addr(struct rte_eth_dev *dev,\n \t\tgoto err_mac;\n \t}\n \n-\t/* TODO: enable interrupt for RX interrupt */\n \treturn 0;\n \n err_mac:\n@@ -399,6 +473,8 @@ static void avf_dev_set_default_mac_addr(struct rte_eth_dev *dev,\n \tstruct avf_adapter *adapter =\n \t\tAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tstruct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct rte_intr_handle *intr_handle = dev->intr_handle;\n \tint ret, i;\n \n \tPMD_INIT_FUNC_TRACE();\n@@ -408,9 +484,13 @@ static void avf_dev_set_default_mac_addr(struct rte_eth_dev *dev,\n \n \tavf_stop_queues(dev);\n \n-\t/*TODO: Disable the interrupt for Rx*/\n-\n-\t/* TODO: Rx interrupt vector mapping free */\n+\t/* Disable the interrupt for Rx */\n+\trte_intr_efd_disable(intr_handle);\n+\t/* Rx interrupt vector mapping free */\n+\tif (intr_handle->intr_vec) {\n+\t\trte_free(intr_handle->intr_vec);\n+\t\tintr_handle->intr_vec = NULL;\n+\t}\n \n \t/* remove all mac addrs */\n \tavf_add_del_all_mac_addr(adapter, FALSE);\n@@ -913,6 +993,58 @@ static void avf_dev_set_default_mac_addr(struct rte_eth_dev *dev,\n }\n \n static int\n+avf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n+{\n+\tstruct avf_adapter *adapter =\n+\t\tAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(adapter);\n+\tuint16_t msix_intr;\n+\n+\tmsix_intr = pci_dev->intr_handle.intr_vec[queue_id];\n+\tif (msix_intr == AVF_MISC_VEC_ID) {\n+\t\tPMD_DRV_LOG(INFO, \"MISC is also enabled for control\");\n+\t\tAVF_WRITE_REG(hw, AVFINT_DYN_CTL01,\n+\t\t\t AVFINT_DYN_CTL01_INTENA_MASK |\n+\t\t\t AVFINT_DYN_CTL01_ITR_INDX_MASK);\n+\t} else {\n+\t\tAVF_WRITE_REG(hw,\n+\t\t\t AVFINT_DYN_CTLN1(msix_intr - AVF_RX_VEC_START),\n+\t\t\t AVFINT_DYN_CTLN1_INTENA_MASK |\n+\t\t\t AVFINT_DYN_CTLN1_ITR_INDX_MASK);\n+\t}\n+\n+\tAVF_WRITE_FLUSH(hw);\n+\n+\trte_intr_enable(&pci_dev->intr_handle);\n+\n+\treturn 0;\n+}\n+\n+static int\n+avf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n+{\n+\tstruct avf_adapter *adapter =\n+\t\tAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tstruct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint16_t msix_intr;\n+\n+\tmsix_intr = pci_dev->intr_handle.intr_vec[queue_id];\n+\tif (msix_intr == AVF_MISC_VEC_ID) {\n+\t\tPMD_DRV_LOG(ERR, \"MISC is used for control, cannot disable it\");\n+\t\treturn -EIO;\n+\t}\n+\n+\tAVF_WRITE_REG(hw,\n+\t\t AVFINT_DYN_CTLN1(msix_intr - AVF_RX_VEC_START),\n+\t\t 0);\n+\n+\tAVF_WRITE_FLUSH(hw);\n+\treturn 0;\n+}\n+\n+static int\n avf_check_vf_reset_done(struct avf_hw *hw)\n {\n \tint i, reset;\n", "prefixes": [ "dpdk-dev", "v5", "14/14" ] }