Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/30637/?format=api
{ "id": 30637, "url": "https://patches.dpdk.org/api/patches/30637/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20171020123136.10557-2-santosh.shukla@caviumnetworks.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20171020123136.10557-2-santosh.shukla@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20171020123136.10557-2-santosh.shukla@caviumnetworks.com", "date": "2017-10-20T12:31:31", "name": "[dpdk-dev,v3,1/6] eal: rename phys addr to iova addr", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ab744e4d77169ad17448a09797098179b705c310", "submitter": { "id": 480, "url": "https://patches.dpdk.org/api/people/480/?format=api", "name": "Santosh Shukla", "email": "santosh.shukla@caviumnetworks.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20171020123136.10557-2-santosh.shukla@caviumnetworks.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/30637/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/30637/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 373251B234;\n\tFri, 20 Oct 2017 14:32:21 +0200 (CEST)", "from NAM03-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam03on0089.outbound.protection.outlook.com [104.47.42.89])\n\tby dpdk.org (Postfix) with ESMTP id 20C9B1B205\n\tfor <dev@dpdk.org>; Fri, 20 Oct 2017 14:32:18 +0200 (CEST)", "from localhost.localdomain (14.140.2.178) by\n\tDM5PR07MB3100.namprd07.prod.outlook.com (10.172.85.10) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.156.4; Fri, 20 Oct 2017 12:32:13 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=3jo1NKMSG33Q++93GoeaelG7dm+OI6bAi+MJ8Oq4cYM=;\n\tb=LZ+4biKJcBDP11DvPj4XVSMahtgZsROZ3TShX1wPDEksKLj2Z6DC7HhvQymL0ctBqMsKQHo4I2/BjRJ+bS8C5dnYnW//tqG0bVb4JzTo1AzOr1bpxJ4DiOHsYJm6vk/9lRylnG5IAcHK4u+XAVD/ej7aZdn5cOYbki4P5vsH+7E=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Santosh.Shukla@cavium.com; ", "From": "Santosh Shukla <santosh.shukla@caviumnetworks.com>", "To": "dev@dpdk.org", "Cc": "olivier.matz@6wind.com, thomas@monjalon.net,\n\tjerin.jacob@caviumnetworks.com, hemant.agrawal@nxp.com,\n\tanatoly.burakov@intel.com,\n\tSantosh Shukla <santosh.shukla@caviumnetworks.com>", "Date": "Fri, 20 Oct 2017 18:01:31 +0530", "Message-Id": "<20171020123136.10557-2-santosh.shukla@caviumnetworks.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20171020123136.10557-1-santosh.shukla@caviumnetworks.com>", "References": "<20170905103119.20511-1-santosh.shukla@caviumnetworks.com>\n\t<20171020123136.10557-1-santosh.shukla@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[14.140.2.178]", "X-ClientProxiedBy": "BM1PR01CA0110.INDPRD01.PROD.OUTLOOK.COM (10.174.208.26) To\n\tDM5PR07MB3100.namprd07.prod.outlook.com (10.172.85.10)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "20912507-de89-4158-0e76-08d517b698c8", "X-Microsoft-Antispam": "UriScan:; BCL:0; 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"X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Oct 2017 12:32:13.0340\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "20912507-de89-4158-0e76-08d517b698c8", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR07MB3100", "Subject": "[dpdk-dev] [PATCH v3 1/6] eal: rename phys addr to iova addr", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Renamed data type from phys_addr_t to iova_addr_t.\n\nSigned-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>\nReviewed-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\nv2 --> v3:\n- Replaced __KERNEL__ with __clang__ in kni header (By Anatoly)\nRefer v2:\nhttp://dpdk.org/dev/patchwork/patch/28358/\n\n app/test-crypto-perf/cperf_test_common.c | 2 +-\n app/test-crypto-perf/cperf_test_vectors.h | 4 +--\n doc/guides/contributing/documentation.rst | 4 +--\n doc/guides/prog_guide/cryptodev_lib.rst | 6 ++--\n drivers/bus/dpaa/rte_dpaa_bus.h | 2 +-\n drivers/bus/fslmc/mc/fsl_mc_cmd.h | 2 +-\n drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 14 ++++----\n drivers/crypto/dpaa_sec/dpaa_sec.c | 18 +++++-----\n drivers/crypto/qat/qat_adf/qat_algs.h | 6 ++--\n drivers/crypto/qat/qat_crypto.c | 2 +-\n drivers/crypto/qat/qat_crypto.h | 2 +-\n drivers/mempool/dpaa2/dpaa2_hw_mempool.h | 2 +-\n drivers/mempool/octeontx/octeontx_fpavf.c | 2 +-\n drivers/mempool/octeontx/rte_mempool_octeontx.c | 2 +-\n drivers/net/ark/ark_ddm.c | 2 +-\n drivers/net/ark/ark_ddm.h | 4 +--\n drivers/net/ark/ark_ethdev_rx.c | 12 +++----\n drivers/net/ark/ark_ethdev_tx.c | 2 +-\n drivers/net/ark/ark_mpu.c | 2 +-\n drivers/net/ark/ark_mpu.h | 4 +--\n drivers/net/ark/ark_udm.c | 2 +-\n drivers/net/ark/ark_udm.h | 4 +--\n drivers/net/avp/avp_ethdev.c | 2 +-\n drivers/net/avp/rte_avp_common.h | 20 +++++------\n drivers/net/bnx2x/bnx2x.c | 40 +++++++++++-----------\n drivers/net/bnx2x/bnx2x.h | 22 ++++++------\n drivers/net/bnx2x/bnx2x_rxtx.c | 4 +--\n drivers/net/bnx2x/bnx2x_stats.c | 2 +-\n drivers/net/bnx2x/bnx2x_vfpf.c | 2 +-\n drivers/net/bnx2x/ecore_sp.h | 2 +-\n drivers/net/bnxt/bnxt.h | 10 +++---\n drivers/net/bnxt/bnxt_cpr.h | 4 +--\n drivers/net/bnxt/bnxt_ethdev.c | 2 +-\n drivers/net/bnxt/bnxt_hwrm.c | 6 ++--\n drivers/net/bnxt/bnxt_ring.c | 2 +-\n drivers/net/bnxt/bnxt_ring.h | 2 +-\n drivers/net/bnxt/bnxt_rxr.h | 4 +--\n drivers/net/bnxt/bnxt_txr.h | 2 +-\n drivers/net/bnxt/bnxt_vnic.c | 2 +-\n drivers/net/bnxt/bnxt_vnic.h | 6 ++--\n drivers/net/liquidio/lio_rxtx.c | 2 +-\n drivers/net/liquidio/lio_rxtx.h | 4 +--\n drivers/net/octeontx/base/octeontx_pkovf.c | 2 +-\n drivers/net/qede/base/bcm_osal.h | 2 +-\n drivers/net/sfc/efsys.h | 2 +-\n drivers/net/sfc/sfc_ef10_rx.c | 2 +-\n drivers/net/sfc/sfc_ef10_tx.c | 4 +--\n drivers/net/thunderx/base/nicvf_hw.c | 2 +-\n drivers/net/thunderx/base/nicvf_hw.h | 2 +-\n drivers/net/thunderx/base/nicvf_hw_defs.h | 6 ++--\n drivers/net/thunderx/nicvf_ethdev.c | 4 +--\n drivers/net/thunderx/nicvf_ethdev.h | 4 +--\n drivers/net/thunderx/nicvf_struct.h | 6 ++--\n drivers/net/virtio/virtio_rxtx.h | 4 +--\n drivers/net/virtio/virtqueue.h | 2 +-\n examples/l2fwd-crypto/main.c | 2 +-\n lib/librte_cryptodev/rte_crypto.h | 2 +-\n lib/librte_cryptodev/rte_crypto_sym.h | 6 ++--\n lib/librte_cryptodev/rte_cryptodev.h | 2 +-\n lib/librte_eal/bsdapp/eal/eal_memory.c | 4 +--\n lib/librte_eal/common/include/rte_malloc.h | 2 +-\n lib/librte_eal/common/include/rte_memory.h | 8 ++---\n lib/librte_eal/common/include/rte_memzone.h | 2 +-\n lib/librte_eal/common/rte_malloc.c | 4 +--\n lib/librte_eal/linuxapp/eal/eal_memory.c | 8 ++---\n .../linuxapp/eal/include/exec-env/rte_kni_common.h | 21 +++++++-----\n lib/librte_mbuf/rte_mbuf.h | 8 ++---\n lib/librte_mempool/rte_mempool.c | 18 +++++-----\n lib/librte_mempool/rte_mempool.h | 18 +++++-----\n lib/librte_mempool/rte_mempool_ops.c | 2 +-\n lib/librte_vhost/vhost.h | 2 +-\n test/test/test_cryptodev.h | 2 +-\n test/test/test_memzone.c | 8 ++---\n 73 files changed, 203 insertions(+), 198 deletions(-)", "diff": "diff --git a/app/test-crypto-perf/cperf_test_common.c b/app/test-crypto-perf/cperf_test_common.c\nindex 46e4a46ec..3f116da6e 100644\n--- a/app/test-crypto-perf/cperf_test_common.c\n+++ b/app/test-crypto-perf/cperf_test_common.c\n@@ -74,7 +74,7 @@ fill_multi_seg_mbuf(struct rte_mbuf *m, struct rte_mempool *mp,\n \tuint16_t mbuf_hdr_size = sizeof(struct rte_mbuf);\n \tuint16_t remaining_segments = segments_nb;\n \tstruct rte_mbuf *next_mbuf;\n-\tphys_addr_t next_seg_phys_addr = rte_mempool_virt2phy(mp, obj) +\n+\tiova_addr_t next_seg_phys_addr = rte_mempool_virt2phy(mp, obj) +\n \t\t\t mbuf_offset + mbuf_hdr_size;\n \n \tdo {\ndiff --git a/app/test-crypto-perf/cperf_test_vectors.h b/app/test-crypto-perf/cperf_test_vectors.h\nindex 85955703c..a203272cf 100644\n--- a/app/test-crypto-perf/cperf_test_vectors.h\n+++ b/app/test-crypto-perf/cperf_test_vectors.h\n@@ -78,13 +78,13 @@ struct cperf_test_vector {\n \n \tstruct {\n \t\tuint8_t *data;\n-\t\tphys_addr_t phys_addr;\n+\t\tiova_addr_t phys_addr;\n \t\tuint16_t length;\n \t} aad;\n \n \tstruct {\n \t\tuint8_t *data;\n-\t\tphys_addr_t phys_addr;\n+\t\tiova_addr_t phys_addr;\n \t\tuint16_t length;\n \t} digest;\n \ndiff --git a/doc/guides/contributing/documentation.rst b/doc/guides/contributing/documentation.rst\nindex 170dacdb7..274ab9888 100644\n--- a/doc/guides/contributing/documentation.rst\n+++ b/doc/guides/contributing/documentation.rst\n@@ -711,7 +711,7 @@ The following are some guidelines for use of Doxygen in the DPDK API documentati\n /**< Virtual address of the first mempool object. */\n uintptr_t elt_va_end;\n /**< Virtual address of the <size + 1> mempool object. */\n- phys_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];\n+ iova_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];\n /**< Array of physical page addresses for the mempool buffer. */\n \n This doesn't have an effect on the rendered documentation but it is confusing for the developer reading the code.\n@@ -730,7 +730,7 @@ The following are some guidelines for use of Doxygen in the DPDK API documentati\n /** Virtual address of the <size + 1> mempool object. */\n uintptr_t elt_va_end;\n /** Array of physical page addresses for the mempool buffer. */\n- phys_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];\n+ iova_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];\n \n * Check for Doxygen warnings in new code by checking the API documentation build::\n \ndiff --git a/doc/guides/prog_guide/cryptodev_lib.rst b/doc/guides/prog_guide/cryptodev_lib.rst\nindex 75ae085f6..248038f64 100644\n--- a/doc/guides/prog_guide/cryptodev_lib.rst\n+++ b/doc/guides/prog_guide/cryptodev_lib.rst\n@@ -539,12 +539,12 @@ chain.\n \n struct {\n uint8_t *data;\n- phys_addr_t phys_addr;\n+ iova_addr_t phys_addr;\n } digest; /**< Digest parameters */\n \n struct {\n uint8_t *data;\n- phys_addr_t phys_addr;\n+ iova_addr_t phys_addr;\n } aad;\n /**< Additional authentication parameters */\n } aead;\n@@ -566,7 +566,7 @@ chain.\n \n struct {\n uint8_t *data;\n- phys_addr_t phys_addr;\n+ iova_addr_t phys_addr;\n } digest; /**< Digest parameters */\n } auth;\n };\ndiff --git a/drivers/bus/dpaa/rte_dpaa_bus.h b/drivers/bus/dpaa/rte_dpaa_bus.h\nindex eafc944d0..dff13016d 100644\n--- a/drivers/bus/dpaa/rte_dpaa_bus.h\n+++ b/drivers/bus/dpaa/rte_dpaa_bus.h\n@@ -107,7 +107,7 @@ struct dpaa_portal {\n };\n \n /* TODO - this is costly, need to write a fast coversion routine */\n-static inline void *rte_dpaa_mem_ptov(phys_addr_t paddr)\n+static inline void *rte_dpaa_mem_ptov(iova_addr_t paddr)\n {\n \tconst struct rte_memseg *memseg = rte_eal_get_physmem_layout();\n \tint i;\ndiff --git a/drivers/bus/fslmc/mc/fsl_mc_cmd.h b/drivers/bus/fslmc/mc/fsl_mc_cmd.h\nindex 2cec29ea8..6c29b638b 100644\n--- a/drivers/bus/fslmc/mc/fsl_mc_cmd.h\n+++ b/drivers/bus/fslmc/mc/fsl_mc_cmd.h\n@@ -45,7 +45,7 @@\n \n #define MC_CMD_NUM_OF_PARAMS\t7\n \n-#define phys_addr_t\tuint64_t\n+#define iova_addr_t\tuint64_t\n \n #define u64\tuint64_t\n #define u32\tuint32_t\ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\nindex 8f39cfbbb..f69af88b5 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n@@ -272,9 +272,9 @@ enum qbman_fd_format {\n #define DPAA2_EQ_RESP_ALWAYS\t\t1\n \n #ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA\n-static void *dpaa2_mem_ptov(phys_addr_t paddr) __attribute__((unused));\n+static void *dpaa2_mem_ptov(iova_addr_t paddr) __attribute__((unused));\n /* todo - this is costly, need to write a fast coversion routine */\n-static void *dpaa2_mem_ptov(phys_addr_t paddr)\n+static void *dpaa2_mem_ptov(iova_addr_t paddr)\n {\n \tconst struct rte_memseg *memseg = rte_eal_get_physmem_layout();\n \tint i;\n@@ -288,8 +288,8 @@ static void *dpaa2_mem_ptov(phys_addr_t paddr)\n \treturn NULL;\n }\n \n-static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));\n-static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)\n+static iova_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));\n+static iova_addr_t dpaa2_mem_vtop(uint64_t vaddr)\n {\n \tconst struct rte_memseg *memseg = rte_eal_get_physmem_layout();\n \tint i;\n@@ -300,7 +300,7 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)\n \t\t\treturn memseg[i].phys_addr\n \t\t\t\t+ (vaddr - memseg[i].addr_64);\n \t}\n-\treturn (phys_addr_t)(NULL);\n+\treturn (iova_addr_t)(NULL);\n }\n \n /**\n@@ -321,13 +321,13 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)\n /**\n * macro to convert IOVA to Virtual address\n */\n-#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova))\n+#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((iova_addr_t)(_iova))\n \n /**\n * macro to convert modify the memory containing IOVA to Virtual address\n */\n #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \\\n-\t{_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); }\n+\t{_mem = (_type)(dpaa2_mem_ptov((iova_addr_t)(_mem))); }\n \n #else\t/* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */\n \ndiff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c\nindex 7b9a68356..b944b94e3 100644\n--- a/drivers/crypto/dpaa_sec/dpaa_sec.c\n+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c\n@@ -110,7 +110,7 @@ dpaa_sec_alloc_ctx(dpaa_sec_session *ses)\n \treturn ctx;\n }\n \n-static inline phys_addr_t\n+static inline iova_addr_t\n dpaa_mem_vtop(void *vaddr)\n {\n \tconst struct rte_memseg *memseg = rte_eal_get_physmem_layout();\n@@ -124,14 +124,14 @@ dpaa_mem_vtop(void *vaddr)\n \t\t\tpaddr = memseg[i].phys_addr +\n \t\t\t\t(vaddr_64 - memseg[i].addr_64);\n \n-\t\t\treturn (phys_addr_t)paddr;\n+\t\t\treturn (iova_addr_t)paddr;\n \t\t}\n \t}\n-\treturn (phys_addr_t)(NULL);\n+\treturn (iova_addr_t)(NULL);\n }\n \n static inline void *\n-dpaa_mem_ptov(phys_addr_t paddr)\n+dpaa_mem_ptov(iova_addr_t paddr)\n {\n \tconst struct rte_memseg *memseg = rte_eal_get_physmem_layout();\n \tint i;\n@@ -158,7 +158,7 @@ ern_sec_fq_handler(struct qman_portal *qm __rte_unused,\n * all the packets in this queue could be dispatched into caam\n */\n static int\n-dpaa_sec_init_rx(struct qman_fq *fq_in, phys_addr_t hwdesc,\n+dpaa_sec_init_rx(struct qman_fq *fq_in, iova_addr_t hwdesc,\n \t\t uint32_t fqid_out)\n {\n \tstruct qm_mcc_initfq fq_opts;\n@@ -566,7 +566,7 @@ build_auth_only(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \tstruct dpaa_sec_job *cf;\n \tstruct dpaa_sec_op_ctx *ctx;\n \tstruct qm_sg_entry *sg;\n-\tphys_addr_t start_addr;\n+\tiova_addr_t start_addr;\n \tuint8_t *old_digest;\n \n \tctx = dpaa_sec_alloc_ctx(ses);\n@@ -628,7 +628,7 @@ build_cipher_only(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \tstruct dpaa_sec_job *cf;\n \tstruct dpaa_sec_op_ctx *ctx;\n \tstruct qm_sg_entry *sg;\n-\tphys_addr_t start_addr;\n+\tiova_addr_t start_addr;\n \tuint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,\n \t\t\tses->iv.offset);\n \n@@ -678,7 +678,7 @@ build_cipher_auth_gcm(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \tstruct dpaa_sec_job *cf;\n \tstruct dpaa_sec_op_ctx *ctx;\n \tstruct qm_sg_entry *sg;\n-\tphys_addr_t start_addr;\n+\tiova_addr_t start_addr;\n \tuint32_t length = 0;\n \tuint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,\n \t\t\tses->iv.offset);\n@@ -787,7 +787,7 @@ build_cipher_auth(struct rte_crypto_op *op, dpaa_sec_session *ses)\n \tstruct dpaa_sec_job *cf;\n \tstruct dpaa_sec_op_ctx *ctx;\n \tstruct qm_sg_entry *sg;\n-\tphys_addr_t start_addr;\n+\tiova_addr_t start_addr;\n \tuint32_t length = 0;\n \tuint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,\n \t\t\tses->iv.offset);\ndiff --git a/drivers/crypto/qat/qat_adf/qat_algs.h b/drivers/crypto/qat/qat_adf/qat_algs.h\nindex 2c8e03c0a..c53ebd7ed 100644\n--- a/drivers/crypto/qat/qat_adf/qat_algs.h\n+++ b/drivers/crypto/qat/qat_adf/qat_algs.h\n@@ -104,8 +104,8 @@ struct qat_alg_buf_list {\n struct qat_crypto_op_cookie {\n \tstruct qat_alg_buf_list qat_sgl_list_src;\n \tstruct qat_alg_buf_list qat_sgl_list_dst;\n-\tphys_addr_t qat_sgl_src_phys_addr;\n-\tphys_addr_t qat_sgl_dst_phys_addr;\n+\tiova_addr_t qat_sgl_src_phys_addr;\n+\tiova_addr_t qat_sgl_dst_phys_addr;\n };\n \n /* Common content descriptor */\n@@ -124,7 +124,7 @@ struct qat_session {\n \tvoid *bpi_ctx;\n \tstruct qat_alg_cd cd;\n \tuint8_t *cd_cur_ptr;\n-\tphys_addr_t cd_paddr;\n+\tiova_addr_t cd_paddr;\n \tstruct icp_qat_fw_la_bulk_req fw_req;\n \tuint8_t aad_len;\n \tstruct qat_crypto_instance *inst;\ndiff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c\nindex ae73c78b5..afcce22c8 100644\n--- a/drivers/crypto/qat/qat_crypto.c\n+++ b/drivers/crypto/qat/qat_crypto.c\n@@ -1375,7 +1375,7 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,\n \t\t * This address may used for setting AAD physical pointer\n \t\t * into IV offset from op\n \t\t */\n-\t\tphys_addr_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;\n+\t\tiova_addr_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;\n \t\tif (ctx->qat_hash_alg ==\n \t\t\t\tICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||\n \t\t\t\tctx->qat_hash_alg ==\ndiff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h\nindex 0ebb08349..d9d3a5c87 100644\n--- a/drivers/crypto/qat/qat_crypto.h\n+++ b/drivers/crypto/qat/qat_crypto.h\n@@ -70,7 +70,7 @@ enum qat_device_gen {\n struct qat_queue {\n \tchar\t\tmemz_name[RTE_MEMZONE_NAMESIZE];\n \tvoid\t\t*base_addr;\t\t/* Base address */\n-\tphys_addr_t\tbase_phys_addr;\t\t/* Queue physical address */\n+\tiova_addr_t\tbase_phys_addr;\t\t/* Queue physical address */\n \tuint32_t\thead;\t\t\t/* Shadow copy of the head */\n \tuint32_t\ttail;\t\t\t/* Shadow copy of the tail */\n \tuint32_t\tmodulo;\ndiff --git a/drivers/mempool/dpaa2/dpaa2_hw_mempool.h b/drivers/mempool/dpaa2/dpaa2_hw_mempool.h\nindex 56b71bede..835fe9ef7 100644\n--- a/drivers/mempool/dpaa2/dpaa2_hw_mempool.h\n+++ b/drivers/mempool/dpaa2/dpaa2_hw_mempool.h\n@@ -39,7 +39,7 @@\n struct buf_pool_cfg {\n \tvoid *addr;\n \t/**< The address from where DPAA2 will carve out the buffers */\n-\tphys_addr_t phys_addr;\n+\tiova_addr_t phys_addr;\n \t/**< Physical address of the memory provided in addr */\n \tuint32_t num;\n \t/**< Number of buffers */\ndiff --git a/drivers/mempool/octeontx/octeontx_fpavf.c b/drivers/mempool/octeontx/octeontx_fpavf.c\nindex 8d5c2a689..4947f2dd5 100644\n--- a/drivers/mempool/octeontx/octeontx_fpavf.c\n+++ b/drivers/mempool/octeontx/octeontx_fpavf.c\n@@ -224,7 +224,7 @@ octeontx_fpapf_pool_setup(unsigned int gpool, unsigned int buf_size,\n \t\t\t signed short buf_offset, unsigned int max_buf_count)\n {\n \tvoid *memptr = NULL;\n-\tphys_addr_t phys_addr;\n+\tiova_addr_t phys_addr;\n \tunsigned int memsz;\n \tstruct fpavf_res *fpa = NULL;\n \tuint64_t reg;\ndiff --git a/drivers/mempool/octeontx/rte_mempool_octeontx.c b/drivers/mempool/octeontx/rte_mempool_octeontx.c\nindex 9f1c07f9d..c7bc6873c 100644\n--- a/drivers/mempool/octeontx/rte_mempool_octeontx.c\n+++ b/drivers/mempool/octeontx/rte_mempool_octeontx.c\n@@ -220,7 +220,7 @@ octeontx_fpavf_get_capabilities(const struct rte_mempool *mp,\n \n static int\n octeontx_fpavf_register_memory_area(const struct rte_mempool *mp,\n-\t\t\t\t char *vaddr, phys_addr_t paddr, size_t len)\n+\t\t\t\t char *vaddr, iova_addr_t paddr, size_t len)\n {\n \tstruct octeontx_pool_info *pool_info;\n \ndiff --git a/drivers/net/ark/ark_ddm.c b/drivers/net/ark/ark_ddm.c\nindex 221460c78..7c78ab75c 100644\n--- a/drivers/net/ark/ark_ddm.c\n+++ b/drivers/net/ark/ark_ddm.c\n@@ -93,7 +93,7 @@ ark_ddm_reset(struct ark_ddm_t *ddm)\n }\n \n void\n-ark_ddm_setup(struct ark_ddm_t *ddm, phys_addr_t cons_addr, uint32_t interval)\n+ark_ddm_setup(struct ark_ddm_t *ddm, iova_addr_t cons_addr, uint32_t interval)\n {\n \tddm->setup.cons_write_index_addr = cons_addr;\n \tddm->setup.write_index_interval = interval / 4;\t/* 4 ns period */\ndiff --git a/drivers/net/ark/ark_ddm.h b/drivers/net/ark/ark_ddm.h\nindex de61926c3..3381cb9e2 100644\n--- a/drivers/net/ark/ark_ddm.h\n+++ b/drivers/net/ark/ark_ddm.h\n@@ -127,7 +127,7 @@ struct ark_ddm_cpld_ps_t {\n \n #define ARK_DDM_SETUP 0x00e0\n struct ark_ddm_setup_t {\n-\tphys_addr_t cons_write_index_addr;\n+\tiova_addr_t cons_write_index_addr;\n \tuint32_t write_index_interval;\t/* 4ns each */\n \tvolatile uint32_t cons_index;\n };\n@@ -165,7 +165,7 @@ void ark_ddm_start(struct ark_ddm_t *ddm);\n int ark_ddm_stop(struct ark_ddm_t *ddm, const int wait);\n void ark_ddm_reset(struct ark_ddm_t *ddm);\n void ark_ddm_stats_reset(struct ark_ddm_t *ddm);\n-void ark_ddm_setup(struct ark_ddm_t *ddm, phys_addr_t cons_addr,\n+void ark_ddm_setup(struct ark_ddm_t *ddm, iova_addr_t cons_addr,\n \t\t uint32_t interval);\n void ark_ddm_dump_stats(struct ark_ddm_t *ddm, const char *msg);\n void ark_ddm_dump(struct ark_ddm_t *ddm, const char *msg);\ndiff --git a/drivers/net/ark/ark_ethdev_rx.c b/drivers/net/ark/ark_ethdev_rx.c\nindex f5d812a55..53e5d9b5c 100644\n--- a/drivers/net/ark/ark_ethdev_rx.c\n+++ b/drivers/net/ark/ark_ethdev_rx.c\n@@ -61,7 +61,7 @@ struct ark_rx_queue {\n \tstruct rte_mbuf **reserve_q;\n \t/* array of physical addresses of the mbuf data pointer */\n \t/* This point is a virtual address */\n-\tphys_addr_t *paddress_q;\n+\tiova_addr_t *paddress_q;\n \tstruct rte_mempool *mb_pool;\n \n \tstruct ark_udm_t *udm;\n@@ -95,9 +95,9 @@ eth_ark_rx_hw_setup(struct rte_eth_dev *dev,\n \t\t struct ark_rx_queue *queue,\n \t\t uint16_t rx_queue_id __rte_unused, uint16_t rx_queue_idx)\n {\n-\tphys_addr_t queue_base;\n-\tphys_addr_t phys_addr_q_base;\n-\tphys_addr_t phys_addr_prod_index;\n+\tiova_addr_t queue_base;\n+\tiova_addr_t phys_addr_q_base;\n+\tiova_addr_t phys_addr_prod_index;\n \n \tqueue_base = rte_malloc_virt2phy(queue);\n \tphys_addr_prod_index = queue_base +\n@@ -106,7 +106,7 @@ eth_ark_rx_hw_setup(struct rte_eth_dev *dev,\n \tphys_addr_q_base = rte_malloc_virt2phy(queue->paddress_q);\n \n \t/* Verify HW */\n-\tif (ark_mpu_verify(queue->mpu, sizeof(phys_addr_t))) {\n+\tif (ark_mpu_verify(queue->mpu, sizeof(iova_addr_t))) {\n \t\tPMD_DRV_LOG(ERR, \"Illegal configuration rx queue\\n\");\n \t\treturn -1;\n \t}\n@@ -204,7 +204,7 @@ eth_ark_dev_rx_queue_setup(struct rte_eth_dev *dev,\n \t\t\t\t socket_id);\n \tqueue->paddress_q =\n \t\trte_zmalloc_socket(\"Ark_rx_queue paddr\",\n-\t\t\t\t nb_desc * sizeof(phys_addr_t),\n+\t\t\t\t nb_desc * sizeof(iova_addr_t),\n \t\t\t\t 64,\n \t\t\t\t socket_id);\n \ndiff --git a/drivers/net/ark/ark_ethdev_tx.c b/drivers/net/ark/ark_ethdev_tx.c\nindex 0e2d60deb..8c4b50ea7 100644\n--- a/drivers/net/ark/ark_ethdev_tx.c\n+++ b/drivers/net/ark/ark_ethdev_tx.c\n@@ -310,7 +310,7 @@ eth_ark_tx_queue_setup(struct rte_eth_dev *dev,\n static int\n eth_ark_tx_hw_queue_config(struct ark_tx_queue *queue)\n {\n-\tphys_addr_t queue_base, ring_base, cons_index_addr;\n+\tiova_addr_t queue_base, ring_base, cons_index_addr;\n \tuint32_t write_interval_ns;\n \n \t/* Verify HW -- MPU */\ndiff --git a/drivers/net/ark/ark_mpu.c b/drivers/net/ark/ark_mpu.c\nindex cd2c0788f..23575c8e3 100644\n--- a/drivers/net/ark/ark_mpu.c\n+++ b/drivers/net/ark/ark_mpu.c\n@@ -118,7 +118,7 @@ ark_mpu_reset_stats(struct ark_mpu_t *mpu)\n }\n \n int\n-ark_mpu_configure(struct ark_mpu_t *mpu, phys_addr_t ring, uint32_t ring_size,\n+ark_mpu_configure(struct ark_mpu_t *mpu, iova_addr_t ring, uint32_t ring_size,\n \t\t int is_tx)\n {\n \tark_mpu_reset(mpu);\ndiff --git a/drivers/net/ark/ark_mpu.h b/drivers/net/ark/ark_mpu.h\nindex a0171dbd6..a42e242b7 100644\n--- a/drivers/net/ark/ark_mpu.h\n+++ b/drivers/net/ark/ark_mpu.h\n@@ -75,7 +75,7 @@ struct ark_mpu_hw_t {\n \n #define ARK_MPU_CFG 0x040\n struct ark_mpu_cfg_t {\n-\tphys_addr_t ring_base;\t/* phys_addr_t is a uint64_t */\n+\tiova_addr_t ring_base;\t/* iova_addr_t is a uint64_t */\n \tuint32_t ring_size;\n \tuint32_t ring_mask;\n \tuint32_t min_host_move;\n@@ -137,7 +137,7 @@ int ark_mpu_verify(struct ark_mpu_t *mpu, uint32_t obj_size);\n void ark_mpu_stop(struct ark_mpu_t *mpu);\n void ark_mpu_start(struct ark_mpu_t *mpu);\n int ark_mpu_reset(struct ark_mpu_t *mpu);\n-int ark_mpu_configure(struct ark_mpu_t *mpu, phys_addr_t ring,\n+int ark_mpu_configure(struct ark_mpu_t *mpu, iova_addr_t ring,\n \t\t uint32_t ring_size, int is_tx);\n \n void ark_mpu_dump(struct ark_mpu_t *mpu, const char *msg, uint16_t idx);\ndiff --git a/drivers/net/ark/ark_udm.c b/drivers/net/ark/ark_udm.c\nindex 1ba7d26d4..1c04d92d9 100644\n--- a/drivers/net/ark/ark_udm.c\n+++ b/drivers/net/ark/ark_udm.c\n@@ -122,7 +122,7 @@ ark_udm_configure(struct ark_udm_t *udm,\n }\n \n void\n-ark_udm_write_addr(struct ark_udm_t *udm, phys_addr_t addr)\n+ark_udm_write_addr(struct ark_udm_t *udm, iova_addr_t addr)\n {\n \tudm->rt_cfg.hw_prod_addr = addr;\n }\ndiff --git a/drivers/net/ark/ark_udm.h b/drivers/net/ark/ark_udm.h\nindex 29bf1e8f7..1be45e2d9 100644\n--- a/drivers/net/ark/ark_udm.h\n+++ b/drivers/net/ark/ark_udm.h\n@@ -137,7 +137,7 @@ struct ark_udm_tlp_ps_t {\n \n #define ARK_UDM_RT_CFG 0x00e0\n struct ark_udm_rt_cfg_t {\n-\tphys_addr_t hw_prod_addr;\n+\tiova_addr_t hw_prod_addr;\n \tuint32_t write_interval;\t/* 4ns cycles */\n \tvolatile uint32_t prod_idx;\t/* RO */\n };\n@@ -171,7 +171,7 @@ void ark_udm_configure(struct ark_udm_t *udm,\n \t\t uint32_t headroom,\n \t\t uint32_t dataroom,\n \t\t uint32_t write_interval_ns);\n-void ark_udm_write_addr(struct ark_udm_t *udm, phys_addr_t addr);\n+void ark_udm_write_addr(struct ark_udm_t *udm, iova_addr_t addr);\n void ark_udm_stats_reset(struct ark_udm_t *udm);\n void ark_udm_dump_stats(struct ark_udm_t *udm, const char *msg);\n void ark_udm_dump_queue_stats(struct ark_udm_t *udm, const char *msg,\ndiff --git a/drivers/net/avp/avp_ethdev.c b/drivers/net/avp/avp_ethdev.c\nindex b97a90cea..f946e6834 100644\n--- a/drivers/net/avp/avp_ethdev.c\n+++ b/drivers/net/avp/avp_ethdev.c\n@@ -387,7 +387,7 @@ avp_dev_translate_buffer(struct avp_dev *avp, void *host_mbuf_address)\n /* translate from host physical address to guest virtual address */\n static void *\n avp_dev_translate_address(struct rte_eth_dev *eth_dev,\n-\t\t\t phys_addr_t host_phys_addr)\n+\t\t\t iova_addr_t host_phys_addr)\n {\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n \tstruct rte_mem_resource *resource;\ndiff --git a/drivers/net/avp/rte_avp_common.h b/drivers/net/avp/rte_avp_common.h\nindex 488d72168..791d2f1b6 100644\n--- a/drivers/net/avp/rte_avp_common.h\n+++ b/drivers/net/avp/rte_avp_common.h\n@@ -243,7 +243,7 @@ struct rte_avp_desc {\n */\n struct rte_avp_memmap {\n \tvoid *addr;\n-\tphys_addr_t phys_addr;\n+\tiova_addr_t phys_addr;\n \tuint64_t length;\n };\n \n@@ -345,7 +345,7 @@ RTE_AVP_MAKE_VERSION(RTE_AVP_RELEASE_VERSION_1, \\\n */\n struct rte_avp_mempool_info {\n \tvoid *addr;\n-\tphys_addr_t phys_addr;\n+\tiova_addr_t phys_addr;\n \tuint64_t length;\n };\n \n@@ -359,10 +359,10 @@ struct rte_avp_device_info {\n \n \tchar ifname[RTE_AVP_NAMESIZE];\t/**< Network device name for AVP */\n \n-\tphys_addr_t tx_phys;\n-\tphys_addr_t rx_phys;\n-\tphys_addr_t alloc_phys;\n-\tphys_addr_t free_phys;\n+\tiova_addr_t tx_phys;\n+\tiova_addr_t rx_phys;\n+\tiova_addr_t alloc_phys;\n+\tiova_addr_t free_phys;\n \n \tuint32_t features; /**< Supported feature bitmap */\n \tuint8_t min_rx_queues; /**< Minimum supported receive/free queues */\n@@ -379,14 +379,14 @@ struct rte_avp_device_info {\n \tuint32_t free_size;\t/**< Size of each free queue */\n \n \t/* Used by Ethtool */\n-\tphys_addr_t req_phys;\n-\tphys_addr_t resp_phys;\n-\tphys_addr_t sync_phys;\n+\tiova_addr_t req_phys;\n+\tiova_addr_t resp_phys;\n+\tiova_addr_t sync_phys;\n \tvoid *sync_va;\n \n \t/* mbuf mempool (used when a single memory area is supported) */\n \tvoid *mbuf_va;\n-\tphys_addr_t mbuf_phys;\n+\tiova_addr_t mbuf_phys;\n \n \t/* mbuf mempools */\n \tstruct rte_avp_mempool_info pool[RTE_AVP_MAX_MEMPOOLS];\ndiff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c\nindex 44222af2f..0fc6f6510 100644\n--- a/drivers/net/bnx2x/bnx2x.c\n+++ b/drivers/net/bnx2x/bnx2x.c\n@@ -419,7 +419,7 @@ void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)\n }\n \n void\n-bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,\n+bnx2x_write_dmae(struct bnx2x_softc *sc, iova_addr_t dma_addr, uint32_t dst_addr,\n \t uint32_t len32)\n {\n \tstruct dmae_command dmae;\n@@ -447,7 +447,7 @@ bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr\n }\n \n static void\n-bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,\n+bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, iova_addr_t phys_addr,\n \t\t\tuint32_t addr, uint32_t len)\n {\n \tuint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);\n@@ -823,14 +823,14 @@ bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)\n \n static void\n __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,\n-\t\t\t phys_addr_t mapping)\n+\t\t\t iova_addr_t mapping)\n {\n \tREG_WR(sc, addr, U64_LO(mapping));\n \tREG_WR(sc, (addr + 4), U64_HI(mapping));\n }\n \n static void\n-storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,\n+storm_memset_spq_addr(struct bnx2x_softc *sc, iova_addr_t mapping,\n \t\t uint16_t abs_fid)\n {\n \tuint32_t addr = (XSEM_REG_FAST_MEMORY +\n@@ -1498,7 +1498,7 @@ bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,\n \n \tramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);\n \tramrod_param.rdata_mapping =\n-\t (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),\n+\t (iova_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),\n \t bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);\n \n \tramrod_param.ramrod_flags = ramrod_flags;\n@@ -4599,9 +4599,9 @@ static void bnx2x_init_func_obj(struct bnx2x_softc *sc)\n \tecore_init_func_obj(sc,\n \t\t\t &sc->func_obj,\n \t\t\t BNX2X_SP(sc, func_rdata),\n-\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),\n+\t\t\t (iova_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),\n \t\t\t BNX2X_SP(sc, func_afex_rdata),\n-\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),\n+\t\t\t (iova_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),\n \t\t\t &bnx2x_func_sp_drv);\n }\n \n@@ -4772,7 +4772,7 @@ static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)\n }\n \n static void\n-bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,\n+bnx2x_init_sb(struct bnx2x_softc *sc, iova_addr_t busaddr, int vfid,\n \t uint8_t vf_valid, int fw_sb_id, int igu_sb_id)\n {\n \tstruct hc_status_block_data_e2 sb_data_e2;\n@@ -4918,7 +4918,7 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)\n \t\t\t sc->max_cos,\n \t\t\t SC_FUNC(sc),\n \t\t\t BNX2X_SP(sc, q_rdata),\n-\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),\n+\t\t\t (iova_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),\n \t\t\t q_type);\n \n \t/* configure classification DBs */\n@@ -4928,7 +4928,7 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)\n \t\t\t idx,\n \t\t\t SC_FUNC(sc),\n \t\t\t BNX2X_SP(sc, mac_rdata),\n-\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),\n+\t\t\t (iova_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),\n \t\t\t ECORE_FILTER_MAC_PENDING, &sc->sp_state,\n \t\t\t ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);\n }\n@@ -5028,7 +5028,7 @@ static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)\n static void bnx2x_init_def_sb(struct bnx2x_softc *sc)\n {\n \tstruct host_sp_status_block *def_sb = sc->def_sb;\n-\tphys_addr_t mapping = sc->def_sb_dma.paddr;\n+\tiova_addr_t mapping = sc->def_sb_dma.paddr;\n \tint igu_sp_sb_index;\n \tint igu_seg_id;\n \tint port = SC_PORT(sc);\n@@ -5700,7 +5700,7 @@ static void bnx2x_init_objs(struct bnx2x_softc *sc)\n \t\t\t SC_FUNC(sc),\n \t\t\t SC_FUNC(sc),\n \t\t\t BNX2X_SP(sc, mcast_rdata),\n-\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),\n+\t\t\t (iova_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),\n \t\t\t ECORE_FILTER_MCAST_PENDING,\n \t\t\t &sc->sp_state, o_type);\n \n@@ -5724,7 +5724,7 @@ static void bnx2x_init_objs(struct bnx2x_softc *sc)\n \t\t\t\t SC_FUNC(sc),\n \t\t\t\t SC_FUNC(sc),\n \t\t\t\t BNX2X_SP(sc, rss_rdata),\n-\t\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),\n+\t\t\t\t (iova_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),\n \t\t\t\t ECORE_FILTER_RSS_CONF_PENDING,\n \t\t\t\t &sc->sp_state, ECORE_OBJ_TYPE_RX);\n }\n@@ -6445,9 +6445,9 @@ bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n \tpause->pri_map = 1;\n \n \t/* rxq setup */\n-\trxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;\n-\trxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;\n-\trxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +\n+\trxq_init->dscr_map = (iova_addr_t)rxq->rx_ring_phys_addr;\n+\trxq_init->rcq_map = (iova_addr_t)rxq->cq_ring_phys_addr;\n+\trxq_init->rcq_np_map = (iova_addr_t)(rxq->cq_ring_phys_addr +\n \t\t\t\t\t BNX2X_PAGE_SIZE);\n \n \t/*\n@@ -6486,7 +6486,7 @@ bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n \t\tPMD_TX_LOG(ERR, \"ERROR: TX queue is NULL\");\n \t\treturn;\n \t}\n-\ttxq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;\n+\ttxq_init->dscr_map = (iova_addr_t)txq->tx_ring_phys_addr;\n \ttxq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;\n \ttxq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;\n \ttxq_init->fw_sb_id = fp->fw_sb_id;\n@@ -11059,7 +11059,7 @@ static int bnx2x_init_hw_func(struct bnx2x_softc *sc)\n \tfor (i = 0; i < L2_ILT_LINES(sc); i++) {\n \t\tilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;\n \t\tilt->lines[cdu_ilt_start + i].page_mapping =\n-\t\t (phys_addr_t)sc->context[i].vcxt_dma.paddr;\n+\t\t (iova_addr_t)sc->context[i].vcxt_dma.paddr;\n \t\tilt->lines[cdu_ilt_start + i].size = sc->context[i].size;\n \t}\n \tecore_ilt_init_op(sc, INITOP_SET);\n@@ -11357,7 +11357,7 @@ static void bnx2x_reset_port(struct bnx2x_softc *sc)\n \t}\n }\n \n-static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)\n+static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, iova_addr_t addr)\n {\n \tint reg;\n \tuint32_t wb_write[2];\n@@ -11587,7 +11587,7 @@ static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)\n }\n \n static void\n-ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,\n+ecore_write_dmae_phys_len(struct bnx2x_softc *sc, iova_addr_t phys_addr,\n \t\t\t uint32_t addr, uint32_t len)\n {\n \tbnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);\ndiff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex 14e892c0e..440856335 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -317,7 +317,7 @@ struct bnx2x_bar {\n /* Used to manage DMA allocations. */\n struct bnx2x_dma {\n \tstruct bnx2x_softc *sc;\n-\tphys_addr_t paddr;\n+\tiova_addr_t paddr;\n \tvoid *vaddr;\n \tint nseg;\n \tchar msg[RTE_MEMZONE_NAMESIZE - 6];\n@@ -370,10 +370,10 @@ struct bnx2x_fastpath {\n \tstruct bnx2x_dma sb_dma;\n \tunion bnx2x_host_hc_status_block status_block;\n \n-\tphys_addr_t tx_desc_mapping;\n+\tiova_addr_t tx_desc_mapping;\n \n-\tphys_addr_t rx_desc_mapping;\n-\tphys_addr_t rx_comp_mapping;\n+\tiova_addr_t rx_desc_mapping;\n+\tiova_addr_t rx_comp_mapping;\n \n \tuint16_t *sb_index_values;\n \tuint16_t *sb_running_index;\n@@ -468,7 +468,7 @@ union cdu_context {\n struct hw_context {\n struct bnx2x_dma vcxt_dma;\n union cdu_context *vcxt;\n- //phys_addr_t cxt_mapping;\n+ //iova_addr_t cxt_mapping;\n size_t size;\n };\n \n@@ -1242,7 +1242,7 @@ struct bnx2x_softc {\n \tuint32_t gz_outlen;\n #define GUNZIP_BUF(sc) (sc->gz_buf)\n #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)\n-#define GUNZIP_PHYS(sc) (phys_addr_t)(sc->gz_buf_dma.paddr)\n+#define GUNZIP_PHYS(sc) (iova_addr_t)(sc->gz_buf_dma.paddr)\n #define FW_BUF_SIZE 0x40000\n \n \tstruct raw_op *init_ops;\n@@ -1310,14 +1310,14 @@ struct bnx2x_softc {\n \t */\n \tint fw_stats_req_size;\n \tstruct bnx2x_fw_stats_req *fw_stats_req;\n-\tphys_addr_t fw_stats_req_mapping;\n+\tiova_addr_t fw_stats_req_mapping;\n \t/*\n \t * FW statistics data shortcut (points at the beginning of fw_stats\n \t * buffer + fw_stats_req_size).\n \t */\n \tint fw_stats_data_size;\n \tstruct bnx2x_fw_stats_data *fw_stats_data;\n-\tphys_addr_t fw_stats_data_mapping;\n+\tiova_addr_t fw_stats_data_mapping;\n \n \t/* tracking a pending STAT_QUERY ramrod */\n \tuint16_t stats_pending;\n@@ -1402,8 +1402,8 @@ union bnx2x_stats_show_data {\n #define FUNC_FLG_LEADING 0x0020 /* PF only */\n \n struct bnx2x_func_init_params {\n- phys_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */\n- phys_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */\n+ iova_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */\n+ iova_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */\n uint16_t func_flgs;\n uint16_t func_id; /* abs function id */\n uint16_t pf_id;\n@@ -1748,7 +1748,7 @@ uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,\n \t\t\t uint8_t comp_type);\n void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);\n void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);\n-void bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr,\n+void bnx2x_write_dmae(struct bnx2x_softc *sc, iova_addr_t dma_addr,\n \t\t uint32_t dst_addr, uint32_t len32);\n void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,\n \t\t\t uint32_t cid);\ndiff --git a/drivers/net/bnx2x/bnx2x_rxtx.c b/drivers/net/bnx2x/bnx2x_rxtx.c\nindex 5dd4aee7f..7336124fc 100644\n--- a/drivers/net/bnx2x/bnx2x_rxtx.c\n+++ b/drivers/net/bnx2x/bnx2x_rxtx.c\n@@ -71,8 +71,8 @@ bnx2x_dev_rx_queue_setup(struct rte_eth_dev *dev,\n \tstruct bnx2x_softc *sc = dev->data->dev_private;\n \tstruct bnx2x_fastpath *fp = &sc->fp[queue_idx];\n \tstruct eth_rx_cqe_next_page *nextpg;\n-\tphys_addr_t *rx_bd;\n-\tphys_addr_t busaddr;\n+\tiova_addr_t *rx_bd;\n+\tiova_addr_t busaddr;\n \n \t/* First allocate the rx queue data structure */\n \trxq = rte_zmalloc_socket(\"ethdev RX queue\", sizeof(struct bnx2x_rx_queue),\ndiff --git a/drivers/net/bnx2x/bnx2x_stats.c b/drivers/net/bnx2x/bnx2x_stats.c\nindex 6223cfef1..03625810e 100644\n--- a/drivers/net/bnx2x/bnx2x_stats.c\n+++ b/drivers/net/bnx2x/bnx2x_stats.c\n@@ -1338,7 +1338,7 @@ bnx2x_prep_fw_stats_req(struct bnx2x_softc *sc)\n int i;\n int first_queue_query_index;\n struct stats_query_header *stats_hdr = &sc->fw_stats_req->hdr;\n- phys_addr_t cur_data_offset;\n+ iova_addr_t cur_data_offset;\n struct stats_query_entry *cur_query_entry;\n \n stats_hdr->cmd_num = sc->fw_stats_num;\ndiff --git a/drivers/net/bnx2x/bnx2x_vfpf.c b/drivers/net/bnx2x/bnx2x_vfpf.c\nindex 0ca0df876..855dafaa6 100644\n--- a/drivers/net/bnx2x/bnx2x_vfpf.c\n+++ b/drivers/net/bnx2x/bnx2x_vfpf.c\n@@ -113,7 +113,7 @@ bnx2x_vf_finalize(struct bnx2x_softc *sc,\n #define BNX2X_VF_CHANNEL_TRIES 100\n \n static int\n-bnx2x_do_req4pf(struct bnx2x_softc *sc, phys_addr_t phys_addr)\n+bnx2x_do_req4pf(struct bnx2x_softc *sc, iova_addr_t phys_addr)\n {\n \tuint8_t *status = &sc->vf2pf_mbox->resp.common_reply.status;\n \tuint8_t i;\ndiff --git a/drivers/net/bnx2x/ecore_sp.h b/drivers/net/bnx2x/ecore_sp.h\nindex 85ab4c28f..fed6f04a1 100644\n--- a/drivers/net/bnx2x/ecore_sp.h\n+++ b/drivers/net/bnx2x/ecore_sp.h\n@@ -36,7 +36,7 @@\n #include \"ecore_reg.h\"\n \n struct bnx2x_softc;\n-typedef phys_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */\n+typedef iova_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */\n typedef volatile int ecore_atomic_t;\n \n \ndiff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex 294a17466..42b0b1da0 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -132,7 +132,7 @@ struct bnxt_pf_info {\n \tuint16_t\t\tmax_vfs;\n \tuint32_t\t\tfunc_cfg_flags;\n \tvoid\t\t\t*vf_req_buf;\n-\tphys_addr_t\t\tvf_req_buf_dma_addr;\n+\tiova_addr_t\t\tvf_req_buf_dma_addr;\n \tuint32_t\t\tvf_req_fwd[8];\n \tuint16_t\t\ttotal_vnics;\n \tstruct bnxt_child_vf_info\t*vf_info;\n@@ -202,14 +202,14 @@ struct bnxt {\n \tstruct bnxt_rx_queue **rx_queues;\n \tconst void\t\t*rx_mem_zone;\n \tstruct rx_port_stats *hw_rx_port_stats;\n-\tphys_addr_t\t\thw_rx_port_stats_map;\n+\tiova_addr_t\t\thw_rx_port_stats_map;\n \n \tunsigned int\t\ttx_nr_rings;\n \tunsigned int\t\ttx_cp_nr_rings;\n \tstruct bnxt_tx_queue **tx_queues;\n \tconst void\t\t*tx_mem_zone;\n \tstruct tx_port_stats *hw_tx_port_stats;\n-\tphys_addr_t\t\thw_tx_port_stats_map;\n+\tiova_addr_t\t\thw_tx_port_stats_map;\n \n \t/* Default completion ring */\n \tstruct bnxt_cp_ring_info\t*def_cp_ring;\n@@ -235,9 +235,9 @@ struct bnxt {\n \n \tuint16_t\t\t\thwrm_cmd_seq;\n \tvoid\t\t\t\t*hwrm_cmd_resp_addr;\n-\tphys_addr_t\t\t\thwrm_cmd_resp_dma_addr;\n+\tiova_addr_t\t\t\thwrm_cmd_resp_dma_addr;\n \tvoid\t\t\t\t*hwrm_short_cmd_req_addr;\n-\tphys_addr_t\t\t\thwrm_short_cmd_req_dma_addr;\n+\tiova_addr_t\t\t\thwrm_short_cmd_req_dma_addr;\n \trte_spinlock_t\t\t\thwrm_lock;\n \tuint16_t\t\t\tmax_req_len;\n \tuint16_t\t\t\tmax_resp_len;\ndiff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h\nindex e8f048a3b..4e7f123ce 100644\n--- a/drivers/net/bnxt/bnxt_cpr.h\n+++ b/drivers/net/bnxt/bnxt_cpr.h\n@@ -86,10 +86,10 @@ struct bnxt_cp_ring_info {\n \n \tstruct cmpl_base\t*cp_desc_ring;\n \n-\tphys_addr_t\t\tcp_desc_mapping;\n+\tiova_addr_t\t\tcp_desc_mapping;\n \n \tstruct ctx_hw_stats\t*hw_stats;\n-\tphys_addr_t\t\thw_stats_map;\n+\tiova_addr_t\t\thw_stats_map;\n \tuint32_t\t\thw_stats_ctx_id;\n \n \tstruct bnxt_ring\t*cp_ring_struct;\ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex d3da30189..845bb03d9 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -2772,7 +2772,7 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev)\n \tconst struct rte_memzone *mz = NULL;\n \tstatic int version_printed;\n \tuint32_t total_alloc_len;\n-\tphys_addr_t mz_phys_addr;\n+\tiova_addr_t mz_phys_addr;\n \tstruct bnxt *bp;\n \tint rc;\n \ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 0e96d3c4d..10898e19a 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -3025,7 +3025,7 @@ int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)\n \tuint32_t entry_length;\n \tuint8_t *buf;\n \tsize_t buflen;\n-\tphys_addr_t dma_handle;\n+\tiova_addr_t dma_handle;\n \tstruct hwrm_nvm_get_dir_entries_input req = {0};\n \tstruct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;\n \n@@ -3070,7 +3070,7 @@ int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,\n {\n \tint rc;\n \tuint8_t *buf;\n-\tphys_addr_t dma_handle;\n+\tiova_addr_t dma_handle;\n \tstruct hwrm_nvm_read_input req = {0};\n \tstruct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;\n \n@@ -3124,7 +3124,7 @@ int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,\n \tint rc;\n \tstruct hwrm_nvm_write_input req = {0};\n \tstruct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;\n-\tphys_addr_t dma_handle;\n+\tiova_addr_t dma_handle;\n \tuint8_t *buf;\n \n \tHWRM_PREP(req, NVM_WRITE);\ndiff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c\nindex 9d0ae277e..8e83e4704 100644\n--- a/drivers/net/bnxt/bnxt_ring.c\n+++ b/drivers/net/bnxt/bnxt_ring.c\n@@ -98,7 +98,7 @@ int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,\n \tstruct rte_pci_device *pdev = bp->pdev;\n \tconst struct rte_memzone *mz = NULL;\n \tchar mz_name[RTE_MEMZONE_NAMESIZE];\n-\tphys_addr_t mz_phys_addr;\n+\tiova_addr_t mz_phys_addr;\n \tint sz;\n \n \tint stats_len = (tx_ring_info || rx_ring_info) ?\ndiff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h\nindex 6d1eb5888..09042cb80 100644\n--- a/drivers/net/bnxt/bnxt_ring.h\n+++ b/drivers/net/bnxt/bnxt_ring.h\n@@ -70,7 +70,7 @@\n \n struct bnxt_ring {\n \tvoid\t\t\t*bd;\n-\tphys_addr_t\t\tbd_dma;\n+\tiova_addr_t\t\tbd_dma;\n \tuint32_t\t\tring_size;\n \tuint32_t\t\tring_mask;\n \ndiff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h\nindex cb0cef303..6cb735b6b 100644\n--- a/drivers/net/bnxt/bnxt_rxr.h\n+++ b/drivers/net/bnxt/bnxt_rxr.h\n@@ -101,8 +101,8 @@ struct bnxt_rx_ring_info {\n \tstruct bnxt_sw_rx_bd\t*rx_buf_ring; /* sw ring */\n \tstruct bnxt_sw_rx_bd\t*ag_buf_ring; /* sw ring */\n \n-\tphys_addr_t\t\trx_desc_mapping;\n-\tphys_addr_t\t\tag_desc_mapping;\n+\tiova_addr_t\t\trx_desc_mapping;\n+\tiova_addr_t\t\tag_desc_mapping;\n \n \tstruct bnxt_ring\t*rx_ring_struct;\n \tstruct bnxt_ring\t*ag_ring_struct;\ndiff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h\nindex 3f3eb312b..7548c599c 100644\n--- a/drivers/net/bnxt/bnxt_txr.h\n+++ b/drivers/net/bnxt/bnxt_txr.h\n@@ -49,7 +49,7 @@ struct bnxt_tx_ring_info {\n \tstruct tx_bd_long\t*tx_desc_ring;\n \tstruct bnxt_sw_tx_bd\t*tx_buf_ring;\n \n-\tphys_addr_t\t\ttx_desc_mapping;\n+\tiova_addr_t\t\ttx_desc_mapping;\n \n #define BNXT_DEV_STATE_CLOSING\t0x1\n \tuint32_t\t\tdev_state;\ndiff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c\nindex 6f7c05bdf..76c9a35d7 100644\n--- a/drivers/net/bnxt/bnxt_vnic.c\n+++ b/drivers/net/bnxt/bnxt_vnic.c\n@@ -175,7 +175,7 @@ int bnxt_alloc_vnic_attributes(struct bnxt *bp)\n \t\t\t\tBNXT_MAX_MC_ADDRS * ETHER_ADDR_LEN);\n \tuint16_t max_vnics;\n \tint i;\n-\tphys_addr_t mz_phys_addr;\n+\tiova_addr_t mz_phys_addr;\n \n \tmax_vnics = bp->max_vnics;\n \tsnprintf(mz_name, RTE_MEMZONE_NAMESIZE,\ndiff --git a/drivers/net/bnxt/bnxt_vnic.h b/drivers/net/bnxt/bnxt_vnic.h\nindex 544390453..def6b42a1 100644\n--- a/drivers/net/bnxt/bnxt_vnic.h\n+++ b/drivers/net/bnxt/bnxt_vnic.h\n@@ -53,11 +53,11 @@ struct bnxt_vnic_info {\n \tuint16_t\tdflt_ring_grp;\n \tuint16_t\tmru;\n \tuint16_t\thash_type;\n-\tphys_addr_t\trss_table_dma_addr;\n+\tiova_addr_t\trss_table_dma_addr;\n \tuint16_t\t*rss_table;\n-\tphys_addr_t\trss_hash_key_dma_addr;\n+\tiova_addr_t\trss_hash_key_dma_addr;\n \tvoid\t\t*rss_hash_key;\n-\tphys_addr_t\tmc_list_dma_addr;\n+\tiova_addr_t\tmc_list_dma_addr;\n \tchar\t\t*mc_list;\n \tuint32_t\tmc_addr_cnt;\n #define BNXT_MAX_MC_ADDRS\t\t16\ndiff --git a/drivers/net/liquidio/lio_rxtx.c b/drivers/net/liquidio/lio_rxtx.c\nindex 2bbb893c2..5156ac08d 100644\n--- a/drivers/net/liquidio/lio_rxtx.c\n+++ b/drivers/net/liquidio/lio_rxtx.c\n@@ -1744,7 +1744,7 @@ lio_dev_xmit_pkts(void *tx_queue, struct rte_mbuf **pkts, uint16_t nb_pkts)\n \t\t} else {\n \t\t\tstruct lio_buf_free_info *finfo;\n \t\t\tstruct lio_gather *g;\n-\t\t\tphys_addr_t phyaddr;\n+\t\t\tiova_addr_t phyaddr;\n \t\t\tint i, frags;\n \n \t\t\tfinfo = (struct lio_buf_free_info *)rte_malloc(NULL,\ndiff --git a/drivers/net/liquidio/lio_rxtx.h b/drivers/net/liquidio/lio_rxtx.h\nindex 85685dc7d..b0977f17b 100644\n--- a/drivers/net/liquidio/lio_rxtx.h\n+++ b/drivers/net/liquidio/lio_rxtx.h\n@@ -686,7 +686,7 @@ lio_swap_8B_data(uint64_t *data, uint32_t blocks)\n static inline uint64_t\n lio_map_ring(void *buf)\n {\n-\tphys_addr_t dma_addr;\n+\tiova_addr_t dma_addr;\n \n \tdma_addr = rte_mbuf_data_dma_addr_default(((struct rte_mbuf *)buf));\n \n@@ -696,7 +696,7 @@ lio_map_ring(void *buf)\n static inline uint64_t\n lio_map_ring_info(struct lio_droq *droq, uint32_t i)\n {\n-\tphys_addr_t dma_addr;\n+\tiova_addr_t dma_addr;\n \n \tdma_addr = droq->info_list_dma + (i * LIO_DROQ_INFO_SIZE);\n \ndiff --git a/drivers/net/octeontx/base/octeontx_pkovf.c b/drivers/net/octeontx/base/octeontx_pkovf.c\nindex a8f6e5d36..5fefdffe3 100644\n--- a/drivers/net/octeontx/base/octeontx_pkovf.c\n+++ b/drivers/net/octeontx/base/octeontx_pkovf.c\n@@ -46,7 +46,7 @@\n \n struct octeontx_pko_iomem {\n \tuint8_t\t\t*va;\n-\tphys_addr_t\tiova;\n+\tiova_addr_t\tiova;\n \tsize_t\t\tsize;\n };\n \ndiff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\nindex 74e518821..9d945d218 100644\n--- a/drivers/net/qede/base/bcm_osal.h\n+++ b/drivers/net/qede/base/bcm_osal.h\n@@ -63,7 +63,7 @@ typedef u32 OSAL_BE32;\n \n #define osal_uintptr_t uintptr_t\n \n-typedef phys_addr_t dma_addr_t;\n+typedef iova_addr_t dma_addr_t;\n \n typedef rte_spinlock_t osal_spinlock_t;\n \ndiff --git a/drivers/net/sfc/efsys.h b/drivers/net/sfc/efsys.h\nindex 0405d02bb..5a6625008 100644\n--- a/drivers/net/sfc/efsys.h\n+++ b/drivers/net/sfc/efsys.h\n@@ -253,7 +253,7 @@ typedef struct __efsys_identifier_s efsys_identifier_t;\n \n /* DMA */\n \n-typedef phys_addr_t efsys_dma_addr_t;\n+typedef iova_addr_t efsys_dma_addr_t;\n \n typedef struct efsys_mem_s {\n \tconst struct rte_memzone\t*esm_mz;\ndiff --git a/drivers/net/sfc/sfc_ef10_rx.c b/drivers/net/sfc/sfc_ef10_rx.c\nindex 500d652a9..2cdc90c42 100644\n--- a/drivers/net/sfc/sfc_ef10_rx.c\n+++ b/drivers/net/sfc/sfc_ef10_rx.c\n@@ -177,7 +177,7 @@ sfc_ef10_rx_qrefill(struct sfc_ef10_rxq *rxq)\n \t\t ++i, ++id) {\n \t\t\tstruct rte_mbuf *m = objs[i];\n \t\t\tstruct sfc_ef10_rx_sw_desc *rxd;\n-\t\t\tphys_addr_t phys_addr;\n+\t\t\tiova_addr_t phys_addr;\n \n \t\t\tSFC_ASSERT((id & ~ptr_mask) == 0);\n \t\t\trxd = &rxq->sw_ring[id];\ndiff --git a/drivers/net/sfc/sfc_ef10_tx.c b/drivers/net/sfc/sfc_ef10_tx.c\nindex 9047b3e46..7f2732aef 100644\n--- a/drivers/net/sfc/sfc_ef10_tx.c\n+++ b/drivers/net/sfc/sfc_ef10_tx.c\n@@ -195,7 +195,7 @@ sfc_ef10_tx_reap(struct sfc_ef10_txq *txq)\n }\n \n static void\n-sfc_ef10_tx_qdesc_dma_create(phys_addr_t addr, uint16_t size, bool eop,\n+sfc_ef10_tx_qdesc_dma_create(iova_addr_t addr, uint16_t size, bool eop,\n \t\t\t efx_qword_t *edp)\n {\n \tEFX_POPULATE_QWORD_4(*edp,\n@@ -341,7 +341,7 @@ sfc_ef10_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \n \t\tpkt_len = m_seg->pkt_len;\n \t\tdo {\n-\t\t\tphys_addr_t seg_addr = rte_mbuf_data_dma_addr(m_seg);\n+\t\t\tiova_addr_t seg_addr = rte_mbuf_data_dma_addr(m_seg);\n \t\t\tunsigned int seg_len = rte_pktmbuf_data_len(m_seg);\n \t\t\tunsigned int id = added & ptr_mask;\n \ndiff --git a/drivers/net/thunderx/base/nicvf_hw.c b/drivers/net/thunderx/base/nicvf_hw.c\nindex 2634285eb..dc0af1ca0 100644\n--- a/drivers/net/thunderx/base/nicvf_hw.c\n+++ b/drivers/net/thunderx/base/nicvf_hw.c\n@@ -509,7 +509,7 @@ nicvf_qset_rbdr_precharge(void *dev, struct nicvf *nic,\n \tstruct rbdr_entry_t *desc, *desc0;\n \tstruct nicvf_rbdr *rbdr = nic->rbdr;\n \tuint32_t count;\n-\tnicvf_phys_addr_t phy;\n+\tnicvf_iova_addr_t phy;\n \n \tassert(rbdr != NULL);\n \tdesc = rbdr->desc;\ndiff --git a/drivers/net/thunderx/base/nicvf_hw.h b/drivers/net/thunderx/base/nicvf_hw.h\nindex b7d0a3dc5..698aa4878 100644\n--- a/drivers/net/thunderx/base/nicvf_hw.h\n+++ b/drivers/net/thunderx/base/nicvf_hw.h\n@@ -88,7 +88,7 @@ enum nicvf_err_e {\n \tNICVF_ERR_RSS_GET_SZ, /* -8171 */\n };\n \n-typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *dev, void *opaque);\n+typedef nicvf_iova_addr_t (*rbdr_pool_get_handler)(void *dev, void *opaque);\n \n struct nicvf_hw_rx_qstats {\n \tuint64_t q_rx_bytes;\ndiff --git a/drivers/net/thunderx/base/nicvf_hw_defs.h b/drivers/net/thunderx/base/nicvf_hw_defs.h\nindex 0fe673e6d..e7e092b61 100644\n--- a/drivers/net/thunderx/base/nicvf_hw_defs.h\n+++ b/drivers/net/thunderx/base/nicvf_hw_defs.h\n@@ -213,7 +213,7 @@\n #define NICVF_STATIC_ASSERT(s) _Static_assert(s, #s)\n #define assert_primary(nic) assert((nic)->sqs_mode == 0)\n \n-typedef uint64_t nicvf_phys_addr_t;\n+typedef uint64_t nicvf_iova_addr_t;\n \n /* vNIC HW Enumerations */\n \n@@ -840,7 +840,7 @@ struct rbdr_entry_t {\n \t\t\tuint64_t buf_addr:42;\n \t\t\tuint64_t cache_align:7;\n \t\t};\n-\t\tnicvf_phys_addr_t full_addr;\n+\t\tnicvf_iova_addr_t full_addr;\n \t};\n #else\n \tunion {\n@@ -849,7 +849,7 @@ struct rbdr_entry_t {\n \t\t\tuint64_t buf_addr:42;\n \t\t\tuint64_t rsvd0:15;\n \t\t};\n-\t\tnicvf_phys_addr_t full_addr;\n+\t\tnicvf_iova_addr_t full_addr;\n \t};\n #endif\n };\ndiff --git a/drivers/net/thunderx/nicvf_ethdev.c b/drivers/net/thunderx/nicvf_ethdev.c\nindex 551b371c5..45d7d8be8 100644\n--- a/drivers/net/thunderx/nicvf_ethdev.c\n+++ b/drivers/net/thunderx/nicvf_ethdev.c\n@@ -679,7 +679,7 @@ nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,\n \n static void\n nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,\n-\t\t\tnicvf_phys_addr_t phy)\n+\t\t\tnicvf_iova_addr_t phy)\n {\n \tuint16_t qidx;\n \tvoid *obj;\n@@ -1428,7 +1428,7 @@ nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t};\n }\n \n-static nicvf_phys_addr_t\n+static nicvf_iova_addr_t\n rbdr_rte_mempool_get(void *dev, void *opaque)\n {\n \tuint16_t qidx;\ndiff --git a/drivers/net/thunderx/nicvf_ethdev.h b/drivers/net/thunderx/nicvf_ethdev.h\nindex 3734430f5..6909082f5 100644\n--- a/drivers/net/thunderx/nicvf_ethdev.h\n+++ b/drivers/net/thunderx/nicvf_ethdev.h\n@@ -104,7 +104,7 @@ nicvf_netdev_qidx(struct nicvf *nic, uint8_t local_qidx)\n * P = V - offset\n */\n static inline uintptr_t\n-nicvf_mbuff_phy2virt(phys_addr_t phy, uint64_t mbuf_phys_off)\n+nicvf_mbuff_phy2virt(iova_addr_t phy, uint64_t mbuf_phys_off)\n {\n \treturn (uintptr_t)(phy + mbuf_phys_off);\n }\n@@ -112,7 +112,7 @@ nicvf_mbuff_phy2virt(phys_addr_t phy, uint64_t mbuf_phys_off)\n static inline uintptr_t\n nicvf_mbuff_virt2phy(uintptr_t virt, uint64_t mbuf_phys_off)\n {\n-\treturn (phys_addr_t)(virt - mbuf_phys_off);\n+\treturn (iova_addr_t)(virt - mbuf_phys_off);\n }\n \n static inline void\ndiff --git a/drivers/net/thunderx/nicvf_struct.h b/drivers/net/thunderx/nicvf_struct.h\nindex e54a96f8e..0f8208ef1 100644\n--- a/drivers/net/thunderx/nicvf_struct.h\n+++ b/drivers/net/thunderx/nicvf_struct.h\n@@ -46,7 +46,7 @@ struct nicvf_rbdr {\n \tuintptr_t rbdr_status;\n \tuintptr_t rbdr_door;\n \tstruct rbdr_entry_t *desc;\n-\tnicvf_phys_addr_t phys;\n+\tnicvf_iova_addr_t phys;\n \tuint32_t buffsz;\n \tuint32_t tail;\n \tuint32_t next_tail;\n@@ -56,7 +56,7 @@ struct nicvf_rbdr {\n \n struct nicvf_txq {\n \tunion sq_entry_t *desc;\n-\tnicvf_phys_addr_t phys;\n+\tnicvf_iova_addr_t phys;\n \tstruct rte_mbuf **txbuffs;\n \tuintptr_t sq_head;\n \tuintptr_t sq_door;\n@@ -87,7 +87,7 @@ struct nicvf_rxq {\n \tuintptr_t cq_status;\n \tuintptr_t cq_door;\n \tunion mbuf_initializer mbuf_initializer;\n-\tnicvf_phys_addr_t phys;\n+\tnicvf_iova_addr_t phys;\n \tunion cq_entry_t *desc;\n \tstruct nicvf_rbdr *shared_rbdr;\n \tstruct nicvf *nic;\ndiff --git a/drivers/net/virtio/virtio_rxtx.h b/drivers/net/virtio/virtio_rxtx.h\nindex 2a7c3ad3a..bc674afc7 100644\n--- a/drivers/net/virtio/virtio_rxtx.h\n+++ b/drivers/net/virtio/virtio_rxtx.h\n@@ -66,7 +66,7 @@ struct virtnet_tx {\n \tstruct virtqueue *vq;\n \t/**< memzone to populate hdr. */\n \tconst struct rte_memzone *virtio_net_hdr_mz;\n-\tphys_addr_t virtio_net_hdr_mem; /**< hdr for each xmit packet */\n+\tiova_addr_t virtio_net_hdr_mem; /**< hdr for each xmit packet */\n \n \tuint16_t queue_id; /**< DPDK queue index. */\n \tuint16_t port_id; /**< Device port identifier. */\n@@ -81,7 +81,7 @@ struct virtnet_ctl {\n \tstruct virtqueue *vq;\n \t/**< memzone to populate hdr. */\n \tconst struct rte_memzone *virtio_net_hdr_mz;\n-\tphys_addr_t virtio_net_hdr_mem; /**< hdr for each xmit packet */\n+\tiova_addr_t virtio_net_hdr_mem; /**< hdr for each xmit packet */\n \tuint16_t port_id; /**< Device port identifier. */\n \tconst struct rte_memzone *mz; /**< mem zone to populate CTL ring. */\n };\ndiff --git a/drivers/net/virtio/virtqueue.h b/drivers/net/virtio/virtqueue.h\nindex 9c4f96d2b..d8e4364f5 100644\n--- a/drivers/net/virtio/virtqueue.h\n+++ b/drivers/net/virtio/virtqueue.h\n@@ -204,7 +204,7 @@ struct virtqueue {\n \t\tstruct virtnet_ctl cq;\n \t};\n \n-\tphys_addr_t vq_ring_mem; /**< physical address of vring,\n+\tiova_addr_t vq_ring_mem; /**< physical address of vring,\n \t\t\t\t * or virtual address for virtio_user. */\n \n \t/**\ndiff --git a/examples/l2fwd-crypto/main.c b/examples/l2fwd-crypto/main.c\nindex 7dfcba421..96e5ed77f 100644\n--- a/examples/l2fwd-crypto/main.c\n+++ b/examples/l2fwd-crypto/main.c\n@@ -141,7 +141,7 @@ enum l2fwd_crypto_xform_chain {\n struct l2fwd_key {\n \tuint8_t *data;\n \tuint32_t length;\n-\tphys_addr_t phys_addr;\n+\tiova_addr_t phys_addr;\n };\n \n struct l2fwd_iv {\ndiff --git a/lib/librte_cryptodev/rte_crypto.h b/lib/librte_cryptodev/rte_crypto.h\nindex 10fe0804b..363d1a7e5 100644\n--- a/lib/librte_cryptodev/rte_crypto.h\n+++ b/lib/librte_cryptodev/rte_crypto.h\n@@ -117,7 +117,7 @@ struct rte_crypto_op {\n \tstruct rte_mempool *mempool;\n \t/**< crypto operation mempool which operation is allocated from */\n \n-\tphys_addr_t phys_addr;\n+\tiova_addr_t phys_addr;\n \t/**< physical address of crypto operation */\n \n \tRTE_STD_C11\ndiff --git a/lib/librte_cryptodev/rte_crypto_sym.h b/lib/librte_cryptodev/rte_crypto_sym.h\nindex 0a0ea59de..f4338d866 100644\n--- a/lib/librte_cryptodev/rte_crypto_sym.h\n+++ b/lib/librte_cryptodev/rte_crypto_sym.h\n@@ -546,7 +546,7 @@ struct rte_crypto_sym_op {\n \t\t\t\t * For GCM (@ref RTE_CRYPTO_AEAD_AES_GCM), for\n \t\t\t\t * \"digest result\" read \"authentication tag T\".\n \t\t\t\t */\n-\t\t\t\tphys_addr_t phys_addr;\n+\t\t\t\tiova_addr_t phys_addr;\n \t\t\t\t/**< Physical address of digest */\n \t\t\t} digest; /**< Digest parameters */\n \t\t\tstruct {\n@@ -581,7 +581,7 @@ struct rte_crypto_sym_op {\n \t\t\t\t * of the block size (16 bytes).\n \t\t\t\t *\n \t\t\t\t */\n-\t\t\t\tphys_addr_t phys_addr;\t/**< physical address */\n+\t\t\t\tiova_addr_t phys_addr;\t/**< physical address */\n \t\t\t} aad;\n \t\t\t/**< Additional authentication parameters */\n \t\t} aead;\n@@ -678,7 +678,7 @@ struct rte_crypto_sym_op {\n \t\t\t\t\t * will overwrite any data at this location.\n \t\t\t\t\t *\n \t\t\t\t\t */\n-\t\t\t\t\tphys_addr_t phys_addr;\n+\t\t\t\t\tiova_addr_t phys_addr;\n \t\t\t\t\t/**< Physical address of digest */\n \t\t\t\t} digest; /**< Digest parameters */\n \t\t\t} auth;\ndiff --git a/lib/librte_cryptodev/rte_cryptodev.h b/lib/librte_cryptodev/rte_cryptodev.h\nindex fd0e3f197..ce41829fc 100644\n--- a/lib/librte_cryptodev/rte_cryptodev.h\n+++ b/lib/librte_cryptodev/rte_cryptodev.h\n@@ -111,7 +111,7 @@ extern const char **rte_cyptodev_names;\n * to calculate address from.\n */\n #define rte_crypto_op_ctophys_offset(c, o)\t\\\n-\t(phys_addr_t)((c)->phys_addr + (o))\n+\t(iova_addr_t)((c)->phys_addr + (o))\n \n /**\n * Crypto parameters range description\ndiff --git a/lib/librte_eal/bsdapp/eal/eal_memory.c b/lib/librte_eal/bsdapp/eal/eal_memory.c\nindex 3614da8db..10c2e121f 100644\n--- a/lib/librte_eal/bsdapp/eal/eal_memory.c\n+++ b/lib/librte_eal/bsdapp/eal/eal_memory.c\n@@ -50,7 +50,7 @@\n /*\n * Get physical address of any mapped virtual address in the current process.\n */\n-phys_addr_t\n+iova_addr_t\n rte_mem_virt2phy(const void *virtaddr)\n {\n \t/* XXX not implemented. This function is only used by\n@@ -73,7 +73,7 @@ rte_eal_hugepage_init(void)\n \t/* for debug purposes, hugetlbfs can be disabled */\n \tif (internal_config.no_hugetlbfs) {\n \t\taddr = malloc(internal_config.memory);\n-\t\tmcfg->memseg[0].phys_addr = (phys_addr_t)(uintptr_t)addr;\n+\t\tmcfg->memseg[0].phys_addr = (iova_addr_t)(uintptr_t)addr;\n \t\tmcfg->memseg[0].addr = addr;\n \t\tmcfg->memseg[0].hugepage_sz = RTE_PGSIZE_4K;\n \t\tmcfg->memseg[0].len = internal_config.memory;\ndiff --git a/lib/librte_eal/common/include/rte_malloc.h b/lib/librte_eal/common/include/rte_malloc.h\nindex 3d37f79b8..491b479b1 100644\n--- a/lib/librte_eal/common/include/rte_malloc.h\n+++ b/lib/librte_eal/common/include/rte_malloc.h\n@@ -332,7 +332,7 @@ rte_malloc_set_limit(const char *type, size_t max);\n * RTE_BAD_PHYS_ADDR on error\n * otherwise return physical address of the buffer\n */\n-phys_addr_t\n+iova_addr_t\n rte_malloc_virt2phy(const void *addr);\n \n #ifdef __cplusplus\ndiff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h\nindex c545963c8..d05f53ad7 100644\n--- a/lib/librte_eal/common/include/rte_memory.h\n+++ b/lib/librte_eal/common/include/rte_memory.h\n@@ -94,14 +94,14 @@ enum rte_page_sizes {\n */\n #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)\n \n-typedef uint64_t phys_addr_t; /**< Physical address definition. */\n-#define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1)\n+typedef uint64_t iova_addr_t; /**< Physical address definition. */\n+#define RTE_BAD_PHYS_ADDR ((iova_addr_t)-1)\n \n /**\n * Physical memory segment descriptor.\n */\n struct rte_memseg {\n-\tphys_addr_t phys_addr; /**< Start physical address. */\n+\tiova_addr_t phys_addr; /**< Start physical address. */\n \tRTE_STD_C11\n \tunion {\n \t\tvoid *addr; /**< Start virtual address. */\n@@ -134,7 +134,7 @@ int rte_mem_lock_page(const void *virt);\n * @return\n * The physical address or RTE_BAD_PHYS_ADDR on error.\n */\n-phys_addr_t rte_mem_virt2phy(const void *virt);\n+iova_addr_t rte_mem_virt2phy(const void *virt);\n \n /**\n * Get the layout of the available physical memory.\ndiff --git a/lib/librte_eal/common/include/rte_memzone.h b/lib/librte_eal/common/include/rte_memzone.h\nindex 1d0827f46..89b2adb6e 100644\n--- a/lib/librte_eal/common/include/rte_memzone.h\n+++ b/lib/librte_eal/common/include/rte_memzone.h\n@@ -78,7 +78,7 @@ struct rte_memzone {\n #define RTE_MEMZONE_NAMESIZE 32 /**< Maximum length of memory zone name.*/\n \tchar name[RTE_MEMZONE_NAMESIZE]; /**< Name of the memory zone. */\n \n-\tphys_addr_t phys_addr; /**< Start physical address. */\n+\tiova_addr_t phys_addr; /**< Start physical address. */\n \tRTE_STD_C11\n \tunion {\n \t\tvoid *addr; /**< Start virtual address. */\ndiff --git a/lib/librte_eal/common/rte_malloc.c b/lib/librte_eal/common/rte_malloc.c\nindex d65c05a4d..e817d70ca 100644\n--- a/lib/librte_eal/common/rte_malloc.c\n+++ b/lib/librte_eal/common/rte_malloc.c\n@@ -248,10 +248,10 @@ rte_malloc_set_limit(__rte_unused const char *type,\n /*\n * Return the physical address of a virtual address obtained through rte_malloc\n */\n-phys_addr_t\n+iova_addr_t\n rte_malloc_virt2phy(const void *addr)\n {\n-\tphys_addr_t paddr;\n+\tiova_addr_t paddr;\n \tconst struct malloc_elem *elem = malloc_elem_from_data(addr);\n \tif (elem == NULL)\n \t\treturn RTE_BAD_PHYS_ADDR;\ndiff --git a/lib/librte_eal/linuxapp/eal/eal_memory.c b/lib/librte_eal/linuxapp/eal/eal_memory.c\nindex 187d3389e..9c94c4ca9 100644\n--- a/lib/librte_eal/linuxapp/eal/eal_memory.c\n+++ b/lib/librte_eal/linuxapp/eal/eal_memory.c\n@@ -97,7 +97,7 @@ static void\n test_phys_addrs_available(void)\n {\n \tuint64_t tmp;\n-\tphys_addr_t physaddr;\n+\tiova_addr_t physaddr;\n \n \tif (!rte_eal_has_hugepages()) {\n \t\tRTE_LOG(ERR, EAL,\n@@ -119,7 +119,7 @@ test_phys_addrs_available(void)\n /*\n * Get physical address of any mapped virtual address in the current process.\n */\n-phys_addr_t\n+iova_addr_t\n rte_mem_virt2phy(const void *virtaddr)\n {\n \tint fd, retval;\n@@ -188,7 +188,7 @@ static int\n find_physaddrs(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)\n {\n \tunsigned int i;\n-\tphys_addr_t addr;\n+\tiova_addr_t addr;\n \n \tfor (i = 0; i < hpi->num_pages[0]; i++) {\n \t\taddr = rte_mem_virt2phy(hugepg_tbl[i].orig_va);\n@@ -206,7 +206,7 @@ static int\n set_physaddrs(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)\n {\n \tunsigned int i;\n-\tstatic phys_addr_t addr;\n+\tstatic iova_addr_t addr;\n \n \tfor (i = 0; i < hpi->num_pages[0]; i++) {\n \t\thugepg_tbl[i].physaddr = addr;\ndiff --git a/lib/librte_eal/linuxapp/eal/include/exec-env/rte_kni_common.h b/lib/librte_eal/linuxapp/eal/include/exec-env/rte_kni_common.h\nindex 2ac879fdd..bf0ac31e7 100644\n--- a/lib/librte_eal/linuxapp/eal/include/exec-env/rte_kni_common.h\n+++ b/lib/librte_eal/linuxapp/eal/include/exec-env/rte_kni_common.h\n@@ -73,6 +73,11 @@\n \n #define RTE_CACHE_LINE_MIN_SIZE 64\n \n+#ifndef __clang__\n+typedef uint64_t iova_addr_t;\n+#endif\n+\n+\n /*\n * Request id.\n */\n@@ -138,20 +143,20 @@ struct rte_kni_mbuf {\n struct rte_kni_device_info {\n \tchar name[RTE_KNI_NAMESIZE]; /**< Network device name for KNI */\n \n-\tphys_addr_t tx_phys;\n-\tphys_addr_t rx_phys;\n-\tphys_addr_t alloc_phys;\n-\tphys_addr_t free_phys;\n+\tiova_addr_t tx_phys;\n+\tiova_addr_t rx_phys;\n+\tiova_addr_t alloc_phys;\n+\tiova_addr_t free_phys;\n \n \t/* Used by Ethtool */\n-\tphys_addr_t req_phys;\n-\tphys_addr_t resp_phys;\n-\tphys_addr_t sync_phys;\n+\tiova_addr_t req_phys;\n+\tiova_addr_t resp_phys;\n+\tiova_addr_t sync_phys;\n \tvoid * sync_va;\n \n \t/* mbuf mempool */\n \tvoid * mbuf_va;\n-\tphys_addr_t mbuf_phys;\n+\tiova_addr_t mbuf_phys;\n \n \t/* PCI info */\n \tuint16_t vendor_id; /**< Vendor ID or PCI_ANY_ID. */\ndiff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h\nindex cc380400d..85e1880bf 100644\n--- a/lib/librte_mbuf/rte_mbuf.h\n+++ b/lib/librte_mbuf/rte_mbuf.h\n@@ -411,7 +411,7 @@ struct rte_mbuf {\n \t * same mbuf cacheline0 layout for 32-bit and 64-bit. This makes\n \t * working on vector drivers easier.\n \t */\n-\tphys_addr_t buf_physaddr __rte_aligned(sizeof(phys_addr_t));\n+\tiova_addr_t buf_physaddr __rte_aligned(sizeof(iova_addr_t));\n \n \t/* next 8 bytes are initialised on RX descriptor rearm */\n \tMARKER64 rearm_data;\n@@ -594,7 +594,7 @@ static inline uint16_t rte_pktmbuf_priv_size(struct rte_mempool *mp);\n * @return\n * The physical address of the beginning of the mbuf data\n */\n-static inline phys_addr_t\n+static inline iova_addr_t\n rte_mbuf_data_dma_addr(const struct rte_mbuf *mb)\n {\n \treturn mb->buf_physaddr + mb->data_off;\n@@ -612,7 +612,7 @@ rte_mbuf_data_dma_addr(const struct rte_mbuf *mb)\n * @return\n * The physical address of the beginning of the mbuf data\n */\n-static inline phys_addr_t\n+static inline iova_addr_t\n rte_mbuf_data_dma_addr_default(const struct rte_mbuf *mb)\n {\n \treturn mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;\n@@ -1535,7 +1535,7 @@ static inline struct rte_mbuf *rte_pktmbuf_lastseg(struct rte_mbuf *m)\n * The offset into the data to calculate address from.\n */\n #define rte_pktmbuf_mtophys_offset(m, o) \\\n-\t(phys_addr_t)((m)->buf_physaddr + (m)->data_off + (o))\n+\t(iova_addr_t)((m)->buf_physaddr + (m)->data_off + (o))\n \n /**\n * A macro that returns the physical address that points to the start of the\ndiff --git a/lib/librte_mempool/rte_mempool.c b/lib/librte_mempool/rte_mempool.c\nindex 6357fd48e..a9b64fffe 100644\n--- a/lib/librte_mempool/rte_mempool.c\n+++ b/lib/librte_mempool/rte_mempool.c\n@@ -128,7 +128,7 @@ static unsigned optimize_object_size(unsigned obj_size)\n }\n \n static void\n-mempool_add_elem(struct rte_mempool *mp, void *obj, phys_addr_t physaddr)\n+mempool_add_elem(struct rte_mempool *mp, void *obj, iova_addr_t physaddr)\n {\n \tstruct rte_mempool_objhdr *hdr;\n \tstruct rte_mempool_objtlr *tlr __rte_unused;\n@@ -270,11 +270,11 @@ rte_mempool_xmem_size(uint32_t elt_num, size_t total_elt_sz, uint32_t pg_shift,\n */\n ssize_t\n rte_mempool_xmem_usage(__rte_unused void *vaddr, uint32_t elt_num,\n-\tsize_t total_elt_sz, const phys_addr_t paddr[], uint32_t pg_num,\n+\tsize_t total_elt_sz, const iova_addr_t paddr[], uint32_t pg_num,\n \tuint32_t pg_shift, unsigned int flags)\n {\n \tuint32_t elt_cnt = 0;\n-\tphys_addr_t start, end;\n+\tiova_addr_t start, end;\n \tuint32_t paddr_idx;\n \tsize_t pg_sz = (size_t)1 << pg_shift;\n \tunsigned int mask;\n@@ -358,7 +358,7 @@ rte_mempool_free_memchunks(struct rte_mempool *mp)\n */\n int\n rte_mempool_populate_phys(struct rte_mempool *mp, char *vaddr,\n-\tphys_addr_t paddr, size_t len, rte_mempool_memchunk_free_cb_t *free_cb,\n+\tiova_addr_t paddr, size_t len, rte_mempool_memchunk_free_cb_t *free_cb,\n \tvoid *opaque)\n {\n \tunsigned total_elt_sz;\n@@ -440,7 +440,7 @@ rte_mempool_populate_phys(struct rte_mempool *mp, char *vaddr,\n */\n int\n rte_mempool_populate_phys_tab(struct rte_mempool *mp, char *vaddr,\n-\tconst phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift,\n+\tconst iova_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift,\n \trte_mempool_memchunk_free_cb_t *free_cb, void *opaque)\n {\n \tuint32_t i, n;\n@@ -483,7 +483,7 @@ rte_mempool_populate_virt(struct rte_mempool *mp, char *addr,\n \tsize_t len, size_t pg_sz, rte_mempool_memchunk_free_cb_t *free_cb,\n \tvoid *opaque)\n {\n-\tphys_addr_t paddr;\n+\tiova_addr_t paddr;\n \tsize_t off, phys_len;\n \tint ret, cnt = 0;\n \n@@ -512,7 +512,7 @@ rte_mempool_populate_virt(struct rte_mempool *mp, char *addr,\n \n \t\t/* populate with the largest group of contiguous pages */\n \t\tfor (phys_len = pg_sz; off + phys_len < len; phys_len += pg_sz) {\n-\t\t\tphys_addr_t paddr_tmp;\n+\t\t\tiova_addr_t paddr_tmp;\n \n \t\t\tpaddr_tmp = rte_mem_virt2phy(addr + off + phys_len);\n \n@@ -547,7 +547,7 @@ rte_mempool_populate_default(struct rte_mempool *mp)\n \tchar mz_name[RTE_MEMZONE_NAMESIZE];\n \tconst struct rte_memzone *mz;\n \tsize_t size, total_elt_sz, align, pg_sz, pg_shift;\n-\tphys_addr_t paddr;\n+\tiova_addr_t paddr;\n \tunsigned mz_id, n;\n \tunsigned int mp_flags;\n \tint ret;\n@@ -958,7 +958,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,\n \t\trte_mempool_ctor_t *mp_init, void *mp_init_arg,\n \t\trte_mempool_obj_cb_t *obj_init, void *obj_init_arg,\n \t\tint socket_id, unsigned flags, void *vaddr,\n-\t\tconst phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift)\n+\t\tconst iova_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift)\n {\n \tstruct rte_mempool *mp = NULL;\n \tint ret;\ndiff --git a/lib/librte_mempool/rte_mempool.h b/lib/librte_mempool/rte_mempool.h\nindex c69841ec4..3139be4f5 100644\n--- a/lib/librte_mempool/rte_mempool.h\n+++ b/lib/librte_mempool/rte_mempool.h\n@@ -157,7 +157,7 @@ struct rte_mempool_objsz {\n struct rte_mempool_objhdr {\n \tSTAILQ_ENTRY(rte_mempool_objhdr) next; /**< Next in list. */\n \tstruct rte_mempool *mp; /**< The mempool owning the object. */\n-\tphys_addr_t physaddr; /**< Physical address of the object. */\n+\tiova_addr_t physaddr; /**< Physical address of the object. */\n #ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n \tuint64_t cookie; /**< Debug cookie. */\n #endif\n@@ -203,7 +203,7 @@ struct rte_mempool_memhdr {\n \tSTAILQ_ENTRY(rte_mempool_memhdr) next; /**< Next in list. */\n \tstruct rte_mempool *mp; /**< The mempool owning the chunk */\n \tvoid *addr; /**< Virtual address of the chunk */\n-\tphys_addr_t phys_addr; /**< Physical address of the chunk */\n+\tiova_addr_t phys_addr; /**< Physical address of the chunk */\n \tsize_t len; /**< length of the chunk */\n \trte_mempool_memchunk_free_cb_t *free_cb; /**< Free callback */\n \tvoid *opaque; /**< Argument passed to the free callback */\n@@ -417,7 +417,7 @@ typedef int (*rte_mempool_get_capabilities_t)(const struct rte_mempool *mp,\n * Notify new memory area to mempool.\n */\n typedef int (*rte_mempool_ops_register_memory_area_t)\n-(const struct rte_mempool *mp, char *vaddr, phys_addr_t paddr, size_t len);\n+(const struct rte_mempool *mp, char *vaddr, iova_addr_t paddr, size_t len);\n \n /** Structure defining mempool operations structure */\n struct rte_mempool_ops {\n@@ -581,7 +581,7 @@ rte_mempool_ops_get_capabilities(const struct rte_mempool *mp,\n */\n int\n rte_mempool_ops_register_memory_area(const struct rte_mempool *mp,\n-\t\t\t\tchar *vaddr, phys_addr_t paddr, size_t len);\n+\t\t\t\tchar *vaddr, iova_addr_t paddr, size_t len);\n \n /**\n * @internal wrapper for mempool_ops free callback.\n@@ -814,7 +814,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,\n \t\trte_mempool_ctor_t *mp_init, void *mp_init_arg,\n \t\trte_mempool_obj_cb_t *obj_init, void *obj_init_arg,\n \t\tint socket_id, unsigned flags, void *vaddr,\n-\t\tconst phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift);\n+\t\tconst iova_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift);\n \n /**\n * Create an empty mempool\n@@ -895,7 +895,7 @@ rte_mempool_free(struct rte_mempool *mp);\n * mempool and a negative errno is returned.\n */\n int rte_mempool_populate_phys(struct rte_mempool *mp, char *vaddr,\n-\tphys_addr_t paddr, size_t len, rte_mempool_memchunk_free_cb_t *free_cb,\n+\tiova_addr_t paddr, size_t len, rte_mempool_memchunk_free_cb_t *free_cb,\n \tvoid *opaque);\n \n /**\n@@ -926,7 +926,7 @@ int rte_mempool_populate_phys(struct rte_mempool *mp, char *vaddr,\n * mempool and a negative errno is returned.\n */\n int rte_mempool_populate_phys_tab(struct rte_mempool *mp, char *vaddr,\n-\tconst phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift,\n+\tconst iova_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift,\n \trte_mempool_memchunk_free_cb_t *free_cb, void *opaque);\n \n /**\n@@ -1456,7 +1456,7 @@ rte_mempool_empty(const struct rte_mempool *mp)\n * If the mempool was created with MEMPOOL_F_NO_PHYS_CONTIG, the\n * returned value is RTE_BAD_PHYS_ADDR.\n */\n-static inline phys_addr_t\n+static inline iova_addr_t\n rte_mempool_virt2phy(__rte_unused const struct rte_mempool *mp, const void *elt)\n {\n \tconst struct rte_mempool_objhdr *hdr;\n@@ -1589,7 +1589,7 @@ size_t rte_mempool_xmem_size(uint32_t elt_num, size_t total_elt_sz,\n * is the actual number of elements that can be stored in that buffer.\n */\n ssize_t rte_mempool_xmem_usage(void *vaddr, uint32_t elt_num,\n-\tsize_t total_elt_sz, const phys_addr_t paddr[], uint32_t pg_num,\n+\tsize_t total_elt_sz, const iova_addr_t paddr[], uint32_t pg_num,\n \tuint32_t pg_shift, unsigned int flags);\n \n /**\ndiff --git a/lib/librte_mempool/rte_mempool_ops.c b/lib/librte_mempool/rte_mempool_ops.c\nindex a6b5f2002..efa42ae97 100644\n--- a/lib/librte_mempool/rte_mempool_ops.c\n+++ b/lib/librte_mempool/rte_mempool_ops.c\n@@ -142,7 +142,7 @@ rte_mempool_ops_get_capabilities(const struct rte_mempool *mp,\n /* wrapper to notify new memory area to external mempool */\n int\n rte_mempool_ops_register_memory_area(const struct rte_mempool *mp, char *vaddr,\n-\t\t\t\t\tphys_addr_t paddr, size_t len)\n+\t\t\t\t\tiova_addr_t paddr, size_t len)\n {\n \tstruct rte_mempool_ops *ops;\n \ndiff --git a/lib/librte_vhost/vhost.h b/lib/librte_vhost/vhost.h\nindex 01b17ca72..108376689 100644\n--- a/lib/librte_vhost/vhost.h\n+++ b/lib/librte_vhost/vhost.h\n@@ -338,7 +338,7 @@ extern uint64_t VHOST_FEATURES;\n extern struct virtio_net *vhost_devices[MAX_VHOST_DEVICE];\n \n /* Convert guest physical address to host physical address */\n-static __rte_always_inline phys_addr_t\n+static __rte_always_inline iova_addr_t\n gpa_to_hpa(struct virtio_net *dev, uint64_t gpa, uint64_t size)\n {\n \tuint32_t i;\ndiff --git a/test/test/test_cryptodev.h b/test/test/test_cryptodev.h\nindex 2e9eb0b1c..3214a43ac 100644\n--- a/test/test/test_cryptodev.h\n+++ b/test/test/test_cryptodev.h\n@@ -153,7 +153,7 @@ pktmbuf_mtod_offset(struct rte_mbuf *mbuf, int offset) {\n \treturn rte_pktmbuf_mtod_offset(m, uint8_t *, offset);\n }\n \n-static inline phys_addr_t\n+static inline iova_addr_t\n pktmbuf_mtophys_offset(struct rte_mbuf *mbuf, int offset) {\n \tstruct rte_mbuf *m;\n \ndiff --git a/test/test/test_memzone.c b/test/test/test_memzone.c\nindex 7ae31cf74..0afb159e9 100644\n--- a/test/test/test_memzone.c\n+++ b/test/test/test_memzone.c\n@@ -78,7 +78,7 @@\n \n /* Test if memory overlaps: return 1 if true, or 0 if false. */\n static int\n-is_memory_overlap(phys_addr_t ptr1, size_t len1, phys_addr_t ptr2, size_t len2)\n+is_memory_overlap(iova_addr_t ptr1, size_t len1, iova_addr_t ptr2, size_t len2)\n {\n \tif (ptr2 >= ptr1 && (ptr2 - ptr1) < len1)\n \t\treturn 1;\n@@ -601,9 +601,9 @@ check_memzone_bounded(const char *name, uint32_t len, uint32_t align,\n \tuint32_t bound)\n {\n \tconst struct rte_memzone *mz;\n-\tphys_addr_t bmask;\n+\tiova_addr_t bmask;\n \n-\tbmask = ~((phys_addr_t)bound - 1);\n+\tbmask = ~((iova_addr_t)bound - 1);\n \n \tif ((mz = rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, 0,\n \t\t\talign, bound)) == NULL) {\n@@ -612,7 +612,7 @@ check_memzone_bounded(const char *name, uint32_t len, uint32_t align,\n \t\treturn -1;\n \t}\n \n-\tif ((mz->phys_addr & ((phys_addr_t)align - 1)) != 0) {\n+\tif ((mz->phys_addr & ((iova_addr_t)align - 1)) != 0) {\n \t\tprintf(\"%s(%s): invalid phys addr alignment\\n\",\n \t\t\t__func__, mz->name);\n \t\treturn -1;\n", "prefixes": [ "dpdk-dev", "v3", "1/6" ] }