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GET /api/patches/29625/?format=api
{ "id": 29625, "url": "https://patches.dpdk.org/api/patches/29625/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1507153746-31255-7-git-send-email-ophirmu@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1507153746-31255-7-git-send-email-ophirmu@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1507153746-31255-7-git-send-email-ophirmu@mellanox.com", "date": "2017-10-04T21:49:05", "name": "[dpdk-dev,v3,6/7] net/mlx4: get back Rx checksum offloads", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2547623c1b9cdaf14189d3c4ecf6a93d3d116b03", "submitter": { "id": 793, "url": "https://patches.dpdk.org/api/people/793/?format=api", "name": "Ophir Munk", "email": "ophirmu@mellanox.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1507153746-31255-7-git-send-email-ophirmu@mellanox.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/29625/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/29625/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9C8E31B65B;\n\tWed, 4 Oct 2017 23:49:53 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id C8ACA1B61F\n\tfor <dev@dpdk.org>; Wed, 4 Oct 2017 23:49:49 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n\tophirmu@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 4 Oct 2017 23:49:47 +0200", "from pegasus05.mtr.labs.mlnx (pegasus05.mtr.labs.mlnx\n\t[10.210.16.100])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v94LnlQj015907;\n\tThu, 5 Oct 2017 00:49:47 +0300", "from pegasus05.mtr.labs.mlnx (localhost [127.0.0.1])\n\tby pegasus05.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id\n\tv94LnlfQ031339; Wed, 4 Oct 2017 21:49:47 GMT", "(from root@localhost)\n\tby pegasus05.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id v94LnlI7031338; \n\tWed, 4 Oct 2017 21:49:47 GMT" ], "From": "Ophir Munk <ophirmu@mellanox.com>", "To": "Adrien Mazarguil <adrien.mazarguil@6wind.com>", "Cc": "dev@dpdk.org, Thomas Monjalon <thomas@monjalon.net>,\n\tOlga Shern <olgas@mellanox.com>, Matan Azrad <matan@mellanox.com>,\n\tMoti Haimovsky <motih@mellanox.com>,\n\tVasily Philipov <vasilyf@mellanox.com>", "Date": "Wed, 4 Oct 2017 21:49:05 +0000", "Message-Id": "<1507153746-31255-7-git-send-email-ophirmu@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1507153746-31255-1-git-send-email-ophirmu@mellanox.com>", "References": "<1507027711-879-1-git-send-email-matan@mellanox.com>\n\t<1507153746-31255-1-git-send-email-ophirmu@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v3 6/7] net/mlx4: get back Rx checksum offloads", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Moti Haimovsky <motih@mellanox.com>\n\nThis patch adds hardware offloading support for IPV4, UDP and TCP\nchecksum verification.\nThis commit also includes support for offloading IPV4, UDP and TCP tunnel\nchecksum verification to the hardware.\n\nSigned-off-by: Vasily Philipov <vasilyf@mellanox.com>\n---\n drivers/net/mlx4/mlx4.c | 2 +\n drivers/net/mlx4/mlx4_ethdev.c | 8 ++-\n drivers/net/mlx4/mlx4_prm.h | 19 +++++++\n drivers/net/mlx4/mlx4_rxq.c | 5 ++\n drivers/net/mlx4/mlx4_rxtx.c | 120 ++++++++++++++++++++++++++++++++++++++++-\n drivers/net/mlx4/mlx4_rxtx.h | 2 +\n 6 files changed, 152 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c\nindex a0e76ee..865ffdd 100644\n--- a/drivers/net/mlx4/mlx4.c\n+++ b/drivers/net/mlx4/mlx4.c\n@@ -535,6 +535,8 @@ struct mlx4_conf {\n \t\tpriv->vf = vf;\n \t\tpriv->hw_csum =\n \t\t !!(device_attr.device_cap_flags & IBV_DEVICE_RAW_IP_CSUM);\n+\t\tDEBUG(\"checksum offloading is %ssupported\",\n+\t\t (priv->hw_csum ? \"\" : \"not \"));\n \t\tpriv->hw_csum_l2tun = tunnel_en;\n \t\tDEBUG(\"L2 tunnel checksum offloads are %ssupported\",\n \t\t (priv->hw_csum_l2tun ? \"\" : \"not \"));\ndiff --git a/drivers/net/mlx4/mlx4_ethdev.c b/drivers/net/mlx4/mlx4_ethdev.c\nindex 95cc6e4..6dbf273 100644\n--- a/drivers/net/mlx4/mlx4_ethdev.c\n+++ b/drivers/net/mlx4/mlx4_ethdev.c\n@@ -553,10 +553,14 @@\n \tinfo->max_mac_addrs = 1;\n \tinfo->rx_offload_capa = 0;\n \tinfo->tx_offload_capa = 0;\n-\tif (priv->hw_csum)\n+\tif (priv->hw_csum) {\n \t\tinfo->tx_offload_capa |= (DEV_TX_OFFLOAD_IPV4_CKSUM |\n-\t\t\t\t\t DEV_TX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\t\t DEV_TX_OFFLOAD_UDP_CKSUM |\n \t\t\t\t\t DEV_TX_OFFLOAD_TCP_CKSUM);\n+\t\tinfo->rx_offload_capa |= (DEV_RX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\t\t DEV_RX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\t\t DEV_RX_OFFLOAD_TCP_CKSUM);\n+\t}\n \tif (priv->hw_csum_l2tun)\n \t\tinfo->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;\n \tif (mlx4_get_ifname(priv, &ifname) == 0)\ndiff --git a/drivers/net/mlx4/mlx4_prm.h b/drivers/net/mlx4/mlx4_prm.h\nindex 57f5a46..73c3d55 100644\n--- a/drivers/net/mlx4/mlx4_prm.h\n+++ b/drivers/net/mlx4/mlx4_prm.h\n@@ -70,6 +70,25 @@\n #define MLX4_SIZE_TO_TXBBS(size) \\\n \t\t(RTE_ALIGN((size), (MLX4_TXBB_SIZE)) >> (MLX4_TXBB_SHIFT))\n \n+/* Generic macro to convert MLX4 to IBV flags. */\n+#define MLX4_TRANSPOSE(val, from, to) \\\n+\t\t(__extension__({ \\\n+\t\t\ttypeof(val) _val = (val); \\\n+\t\t\ttypeof(from) _from = (from); \\\n+\t\t\ttypeof(to) _to = (to); \\\n+\t\t\t(((_from) >= (_to)) ? \\\n+\t\t\t(((_val) & (_from)) / ((_from) / (_to))) : \\\n+\t\t\t(((_val) & (_from)) * ((_to) / (_from)))); \\\n+\t\t}))\n+\n+/* CQE checksum flags */\n+enum {\n+\tMLX4_CQE_L2_TUNNEL_IPV4 = (int)(1U << 25),\n+\tMLX4_CQE_L2_TUNNEL_L4_CSUM = (int)(1U << 26),\n+\tMLX4_CQE_L2_TUNNEL = (int)(1U << 27),\n+\tMLX4_CQE_L2_TUNNEL_IPOK = (int)(1U << 31),\n+};\n+\n /* Send queue information. */\n struct mlx4_sq {\n \tchar *buf; /**< SQ buffer. */\ndiff --git a/drivers/net/mlx4/mlx4_rxq.c b/drivers/net/mlx4/mlx4_rxq.c\nindex 7d13121..889f05c 100644\n--- a/drivers/net/mlx4/mlx4_rxq.c\n+++ b/drivers/net/mlx4/mlx4_rxq.c\n@@ -267,6 +267,11 @@\n \tint ret;\n \n \t(void)conf; /* Thresholds configuration (ignored). */\n+\t/* Toggle Rx checksum offload if hardware supports it. */\n+\tif (priv->hw_csum)\n+\t\ttmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n+\tif (priv->hw_csum_l2tun)\n+\t\ttmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n \tmb_len = rte_pktmbuf_data_room_size(mp);\n \t/* Enable scattered packets support for this queue if necessary. */\n \tassert(mb_len >= RTE_PKTMBUF_HEADROOM);\ndiff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c\nindex ea92ebb..ca66b1d 100644\n--- a/drivers/net/mlx4/mlx4_rxtx.c\n+++ b/drivers/net/mlx4/mlx4_rxtx.c\n@@ -563,6 +563,110 @@ struct pv {\n }\n \n /**\n+ * Translate Rx completion flags to packet type.\n+ *\n+ * @param flags\n+ * Rx completion flags returned by poll_length_flags().\n+ *\n+ * @return\n+ * Packet type for struct rte_mbuf.\n+ */\n+static inline uint32_t\n+rxq_cq_to_pkt_type(uint32_t flags)\n+{\n+\tuint32_t pkt_type;\n+\n+\tif (flags & MLX4_CQE_L2_TUNNEL)\n+\t\tpkt_type =\n+\t\t\tMLX4_TRANSPOSE(flags,\n+\t\t\t (uint32_t)MLX4_CQE_L2_TUNNEL_IPV4,\n+\t\t\t (uint32_t)RTE_PTYPE_L3_IPV4_EXT_UNKNOWN) |\n+\t\t\tMLX4_TRANSPOSE(flags,\n+\t\t\t (uint32_t)MLX4_CQE_STATUS_IPV4_PKT,\n+\t\t\t (uint32_t)RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN);\n+\telse\n+\t\tpkt_type =\n+\t\t\tMLX4_TRANSPOSE(flags,\n+\t\t\t (uint32_t)MLX4_CQE_STATUS_IPV4_PKT,\n+\t\t\t (uint32_t)RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);\n+\tERROR(\"pkt_type 0x%x\", pkt_type); //\n+\treturn pkt_type;\n+}\n+\n+/**\n+ * Translate Rx completion flags to offload flags.\n+ *\n+ * @param flags\n+ * Rx completion flags returned by poll_length_flags().\n+ * @param csum\n+ * Rx checksum enable flag\n+ * @param csum_l2tun\n+ * Rx L2 tunnel checksum enable flag\n+ *\n+ * @return\n+ * Offload flags (ol_flags) for struct rte_mbuf.\n+ */\n+static inline uint32_t\n+rxq_cq_to_ol_flags(uint32_t flags, unsigned int csum, unsigned int csum_l2tun)\n+{\n+\tuint32_t ol_flags = 0;\n+\n+\tif (csum)\n+\t\tol_flags |=\n+\t\t\tMLX4_TRANSPOSE(flags,\n+\t\t\t\t(uint64_t)MLX4_CQE_STATUS_IP_HDR_CSUM_OK,\n+\t\t\t\tPKT_RX_IP_CKSUM_GOOD) |\n+\t\t\tMLX4_TRANSPOSE(flags,\n+\t\t\t\t(uint64_t)MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,\n+\t\t\t\tPKT_RX_L4_CKSUM_GOOD);\n+\tif ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)\n+\t\tol_flags |=\n+\t\t\tMLX4_TRANSPOSE(flags,\n+\t\t\t\t (uint64_t)MLX4_CQE_L2_TUNNEL_IPOK,\n+\t\t\t\t PKT_RX_IP_CKSUM_GOOD) |\n+\t\t\tMLX4_TRANSPOSE(flags,\n+\t\t\t\t (uint64_t)MLX4_CQE_L2_TUNNEL_L4_CSUM,\n+\t\t\t\t PKT_RX_L4_CKSUM_GOOD);\n+\treturn ol_flags;\n+}\n+\n+/**\n+ * Get Rx checksum CQE flags.\n+ *\n+ * @param cqe\n+ * Pointer to cqe structure.\n+ * @param csum\n+ * Rx checksum enable flag\n+ * @param csum_l2tun\n+ * RX L2 tunnel checksum enable flag\n+ *\n+ * @return\n+ * CQE flags in CPU order\n+ */\n+static inline uint32_t\n+mlx4_cqe_flags(struct mlx4_cqe *cqe,\n+\t int csum, unsigned int csum_l2tun)\n+{\n+\tuint32_t flags = 0;\n+\n+\t/*\n+\t * The relevant bits are in different locations on their\n+\t * CQE fields therefore we can join them in one 32-bit\n+\t * variable.\n+\t */\n+\tif (csum)\n+\t\tflags = rte_be_to_cpu_32(cqe->status) &\n+\t\t\tMLX4_CQE_STATUS_IPV4_CSUM_OK;\n+\tif (csum_l2tun)\n+\t\tflags |= rte_be_to_cpu_32(cqe->vlan_my_qpn) &\n+\t\t\t (MLX4_CQE_L2_TUNNEL |\n+\t\t\t MLX4_CQE_L2_TUNNEL_IPOK |\n+\t\t\t MLX4_CQE_L2_TUNNEL_L4_CSUM |\n+\t\t\t MLX4_CQE_L2_TUNNEL_IPV4);\n+\t\treturn flags;\n+}\n+\n+/**\n * Poll one CQE from CQ.\n *\n * @param rxq\n@@ -601,7 +705,7 @@ struct pv {\n }\n \n /**\n- * DPDK callback for RX with scattered packets support.\n+ * DPDK callback for Rx with scattered packets support.\n *\n * @param dpdk_rxq\n * Generic pointer to Rx queue structure.\n@@ -666,7 +770,7 @@ struct pv {\n \t\t\t\tbreak;\n \t\t\t}\n \t\t\tif (unlikely(len < 0)) {\n-\t\t\t\t/* RX error, packet is likely too large. */\n+\t\t\t\t/* Rx error, packet is likely too large. */\n \t\t\t\trte_mbuf_raw_free(rep);\n \t\t\t\t++rxq->stats.idropped;\n \t\t\t\tgoto skip;\n@@ -674,6 +778,18 @@ struct pv {\n \t\t\tpkt = seg;\n \t\t\tpkt->packet_type = 0;\n \t\t\tpkt->ol_flags = 0;\n+\t\t\tif (rxq->csum | rxq->csum_l2tun) {\n+\t\t\t\tuint32_t flags =\n+\t\t\t\t\tmlx4_cqe_flags(cqe, rxq->csum,\n+\t\t\t\t\t\t rxq->csum_l2tun);\n+\t\t\t\tpkt->ol_flags =\n+\t\t\t\t\trxq_cq_to_ol_flags(flags, rxq->csum,\n+\t\t\t\t\t\t\t rxq->csum_l2tun);\n+\t\t\t\tpkt->packet_type = rxq_cq_to_pkt_type(flags);\n+\t\t\t} else {\n+\t\t\t\tpkt->packet_type = 0;\n+\t\t\t\tpkt->ol_flags = 0;\n+\t\t\t}\n \t\t\tpkt->pkt_len = len;\n \t\t}\n \t\trep->nb_segs = 1;\ndiff --git a/drivers/net/mlx4/mlx4_rxtx.h b/drivers/net/mlx4/mlx4_rxtx.h\nindex dc283e1..75c98c1 100644\n--- a/drivers/net/mlx4/mlx4_rxtx.h\n+++ b/drivers/net/mlx4/mlx4_rxtx.h\n@@ -80,6 +80,8 @@ struct rxq {\n \t} hw;\n \tstruct mlx4_cq mcq; /**< Info for directly manipulating the CQ. */\n \tunsigned int sge_n; /**< Log 2 of SGEs number. */\n+\tunsigned int csum:1; /**< Enable checksum offloading. */\n+\tunsigned int csum_l2tun:1; /**< Enable checksum for L2 tunnels. */\n \tstruct mlx4_rxq_stats stats; /**< Rx queue counters. */\n \tunsigned int socket; /**< CPU socket ID for allocations. */\n };\n", "prefixes": [ "dpdk-dev", "v3", "6/7" ] }