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GET /api/patches/2847/?format=api
{ "id": 2847, "url": "https://patches.dpdk.org/api/patches/2847/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1422544846-10697-3-git-send-email-adrien.mazarguil@6wind.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1422544846-10697-3-git-send-email-adrien.mazarguil@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1422544846-10697-3-git-send-email-adrien.mazarguil@6wind.com", "date": "2015-01-29T15:20:46", "name": "[dpdk-dev,2/2] mlx4: new poll mode driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1a59fe2edce0a0bd7e4fd772bef15c60315ce5a8", "submitter": { "id": 165, "url": "https://patches.dpdk.org/api/people/165/?format=api", "name": "Adrien Mazarguil", "email": "adrien.mazarguil@6wind.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1422544846-10697-3-git-send-email-adrien.mazarguil@6wind.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/2847/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/2847/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<adrien.mazarguil@6wind.com>", "Received": [ "from mail-wi0-f170.google.com (mail-wi0-f170.google.com\n\t[209.85.212.170]) by dpdk.org (Postfix) with ESMTP id 2BDF3234\n\tfor <dev@dpdk.org>; Thu, 29 Jan 2015 16:21:35 +0100 (CET)", "by mail-wi0-f170.google.com with SMTP id bs8so11317953wib.1\n\tfor <dev@dpdk.org>; Thu, 29 Jan 2015 07:21:35 -0800 (PST)", "from 6wind.com (guy78-3-82-239-227-177.fbx.proxad.net.\n\t[82.239.227.177]) by mx.google.com with ESMTPSA id\n\te18sm10870932wjz.27.2015.01.29.07.21.25\n\t(version=TLSv1.2 cipher=RC4-SHA bits=128/128);\n\tThu, 29 Jan 2015 07:21:33 -0800 (PST)" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=QFvPNYd5GXpQFJWCTosrUNTN/I3CA+pxet01eQaIH5s=;\n\tb=NycyyWu1HH0010toyFNsfOo1JcaVKAq6RAsY3kC2MyzueTAe9S84Ngv2l96JmFU/HC\n\tewStSx52yIJ+734QbFEUqHkg8rU4jDSVdimPMeEKC6AqvJHbeR6WyoFZhLtWykzwMlx1\n\t3/E/pS5J/PwqmPDJ1bbMGOpoP46N2Pheg88lcr4j6UQ5qgAY06liIJnnzWEpGs9eg7g5\n\tiCPZAJ/qbe6zivg+8BoWq6Vg/4S+kj9FB9O6TOARvSn/4cfFMfPVELezXNIsj2yRH9zZ\n\thCoVJPCUZqBjLints9T/jEyAgnFw/KjnZbNaRySQz9RiBnPyQzAVKlOUwouL1l8OtQsp\n\tm0ig==", "X-Gm-Message-State": "ALoCoQllLh5ggk/gQ4x/k6K34j2EFeMKpIYmRhMNp8AIrlqKXXVrxym3vDPqdNZCj50lcHxdLpj9", "X-Received": "by 10.194.184.140 with SMTP id eu12mr1989989wjc.25.1422544894792;\n\tThu, 29 Jan 2015 07:21:34 -0800 (PST)", "From": "Adrien Mazarguil <adrien.mazarguil@6wind.com>", "To": "dev@dpdk.org", "Date": "Thu, 29 Jan 2015 16:20:46 +0100", "Message-Id": "<1422544846-10697-3-git-send-email-adrien.mazarguil@6wind.com>", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1422544846-10697-1-git-send-email-adrien.mazarguil@6wind.com>", "References": "<1422544846-10697-1-git-send-email-adrien.mazarguil@6wind.com>", "Subject": "[dpdk-dev] [PATCH 2/2] mlx4: new poll mode driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "X-List-Received-Date": "Thu, 29 Jan 2015 15:21:35 -0000" }, "content": "This PMD manages all variants of Mellanox ConnectX-3 (EN 40, EN 10, Pro EN\n40) as well as their virtual functions in SR-IOV context through IB Verbs\n(libibverbs) and the dedicated user-space driver (libmlx4).\n\nIt is disabled by default due to dependencies on these libraries and only\nsupports Linux userland at the moment partly because /sys (sysfs) support is\nrequired.\n\nSigned-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>\nSigned-off-by: Olga Shern <olgas@mellanox.com>\n---\n config/common_bsdapp | 11 +\n config/common_linuxapp | 11 +\n lib/Makefile | 1 +\n lib/librte_pmd_mlx4/Makefile | 119 ++\n lib/librte_pmd_mlx4/mlx4.c | 4739 ++++++++++++++++++++++++++++++++++++++++++\n lib/librte_pmd_mlx4/mlx4.h | 166 ++\n mk/rte.app.mk | 8 +\n 7 files changed, 5055 insertions(+)\n create mode 100755 lib/librte_pmd_mlx4/Makefile\n create mode 100755 lib/librte_pmd_mlx4/mlx4.c\n create mode 100644 lib/librte_pmd_mlx4/mlx4.h", "diff": "diff --git a/config/common_bsdapp b/config/common_bsdapp\nindex 9177db1..f7b3fe1 100644\n--- a/config/common_bsdapp\n+++ b/config/common_bsdapp\n@@ -182,6 +182,17 @@ CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM=4\n CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1\n \n #\n+# Compile burst-oriented Mellanox ConnectX-3 (MLX4) PMD\n+#\n+CONFIG_RTE_LIBRTE_MLX4_PMD=n\n+CONFIG_RTE_LIBRTE_MLX4_DEBUG=n\n+CONFIG_RTE_LIBRTE_MLX4_SGE_WR_N=4\n+CONFIG_RTE_LIBRTE_MLX4_MAX_INLINE=0\n+CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE=8\n+CONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS=1\n+CONFIG_RTE_LIBRTE_MLX4_COMPAT_VMWARE=1\n+\n+#\n # Compile burst-oriented Cisco ENIC PMD driver\n #\n CONFIG_RTE_LIBRTE_ENIC_PMD=y\ndiff --git a/config/common_linuxapp b/config/common_linuxapp\nindex 2f9643b..0cec157 100644\n--- a/config/common_linuxapp\n+++ b/config/common_linuxapp\n@@ -180,6 +180,17 @@ CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM=4\n CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1\n \n #\n+# Compile burst-oriented Mellanox ConnectX-3 (MLX4) PMD\n+#\n+CONFIG_RTE_LIBRTE_MLX4_PMD=n\n+CONFIG_RTE_LIBRTE_MLX4_DEBUG=n\n+CONFIG_RTE_LIBRTE_MLX4_SGE_WR_N=4\n+CONFIG_RTE_LIBRTE_MLX4_MAX_INLINE=0\n+CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE=8\n+CONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS=1\n+CONFIG_RTE_LIBRTE_MLX4_COMPAT_VMWARE=1\n+\n+#\n # Compile burst-oriented Cisco ENIC PMD driver\n #\n CONFIG_RTE_LIBRTE_ENIC_PMD=y\ndiff --git a/lib/Makefile b/lib/Makefile\nindex 0ffc982..9f1994d 100644\n--- a/lib/Makefile\n+++ b/lib/Makefile\n@@ -43,6 +43,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_ETHER) += librte_ether\n DIRS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += librte_pmd_e1000\n DIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += librte_pmd_ixgbe\n DIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += librte_pmd_i40e\n+DIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += librte_pmd_mlx4\n DIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += librte_pmd_enic\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += librte_pmd_bond\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_RING) += librte_pmd_ring\ndiff --git a/lib/librte_pmd_mlx4/Makefile b/lib/librte_pmd_mlx4/Makefile\nnew file mode 100755\nindex 0000000..9a6c891\n--- /dev/null\n+++ b/lib/librte_pmd_mlx4/Makefile\n@@ -0,0 +1,119 @@\n+# BSD LICENSE\n+#\n+# Copyright(c) 2012-2015 6WIND S.A.\n+# Copyright(c) 2012 Mellanox.\n+# All rights reserved.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of 6WIND S.A. nor the names of its\n+# contributors may be used to endorse or promote products derived\n+# from this software without specific prior written permission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+# Library name.\n+LIB = librte_pmd_mlx4.a\n+\n+# Sources.\n+SRCS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += mlx4.c\n+\n+# Dependencies.\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += lib/librte_ether\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += lib/librte_mbuf\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += lib/librte_eal\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += lib/librte_mempool\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += lib/librte_malloc\n+\n+# Basic CFLAGS.\n+CFLAGS += -O3\n+CFLAGS += -std=gnu99 -Wall -Wextra\n+CFLAGS += -g\n+CFLAGS += -I.\n+CFLAGS += -D_XOPEN_SOURCE=600\n+CFLAGS += $(WERROR_FLAGS)\n+\n+# A few warnings cannot be avoided in external headers.\n+CFLAGS += -Wno-error=cast-qual\n+\n+# DEBUG which is usually provided on the command-line may enable\n+# CONFIG_RTE_LIBRTE_MLX4_DEBUG.\n+ifeq ($(DEBUG),1)\n+CONFIG_RTE_LIBRTE_MLX4_DEBUG := y\n+endif\n+\n+# User-defined CFLAGS.\n+ifeq ($(CONFIG_RTE_LIBRTE_MLX4_DEBUG),y)\n+CFLAGS += -pedantic -UNDEBUG -DPEDANTIC\n+else\n+CFLAGS += -DNDEBUG -UPEDANTIC\n+endif\n+\n+ifdef CONFIG_RTE_LIBRTE_MLX4_SGE_WR_N\n+CFLAGS += -DMLX4_PMD_SGE_WR_N=$(CONFIG_RTE_LIBRTE_MLX4_SGE_WR_N)\n+endif\n+\n+ifdef CONFIG_RTE_LIBRTE_MLX4_MAX_INLINE\n+CFLAGS += -DMLX4_PMD_MAX_INLINE=$(CONFIG_RTE_LIBRTE_MLX4_MAX_INLINE)\n+endif\n+\n+ifdef CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE\n+CFLAGS += -DMLX4_PMD_TX_MP_CACHE=$(CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE)\n+endif\n+\n+ifdef CONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS\n+CFLAGS += -DMLX4_PMD_SOFT_COUNTERS=$(CONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS)\n+endif\n+\n+ifdef CONFIG_RTE_LIBRTE_MLX4_COMPAT_VMWARE\n+CFLAGS += -DMLX4_PMD_COMPAT_VMWARE=$(CONFIG_RTE_LIBRTE_MLX4_COMPAT_VMWARE)\n+endif\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\n+\n+# Generate and clean-up mlx4_autoconf.h.\n+\n+export CC CFLAGS CPPFLAGS EXTRA_CFLAGS EXTRA_CPPFLAGS\n+export AUTO_CONFIG_CFLAGS = -Wno-error\n+\n+mlx4_autoconf.h: $(RTE_SDK)/scripts/auto-config-h.sh\n+\t$Q $(RM) -f -- '$@'\n+\t$Q sh -- '$<' '$@' \\\n+\t\tRSS_SUPPORT \\\n+\t\tinfiniband/verbs.h \\\n+\t\tenum IBV_EXP_DEVICE_UD_RSS\n+\t$Q sh -- '$<' '$@' \\\n+\t\tINLINE_RECV \\\n+\t\tinfiniband/verbs.h \\\n+\t\tenum IBV_EXP_DEVICE_ATTR_INLINE_RECV_SZ\n+\t$Q sh -- '$<' '$@' \\\n+\t\tSEND_RAW_WR_SUPPORT \\\n+\t\tinfiniband/verbs.h \\\n+\t\ttype 'struct ibv_send_wr_raw'\n+\n+mlx4.o: mlx4_autoconf.h\n+\n+clean_mlx4: FORCE\n+\t$Q rm -f -- mlx4_autoconf.h\n+\n+clean: clean_mlx4\ndiff --git a/lib/librte_pmd_mlx4/mlx4.c b/lib/librte_pmd_mlx4/mlx4.c\nnew file mode 100755\nindex 0000000..71c75ad\n--- /dev/null\n+++ b/lib/librte_pmd_mlx4/mlx4.c\n@@ -0,0 +1,4739 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2012-2015 6WIND S.A.\n+ * Copyright(c) 2012 Mellanox.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of 6WIND S.A. nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+/*\n+ * Known limitations:\n+ * - Multiple RX VLAN filters can be configured, but only the first one\n+ * works properly.\n+ * - RSS hash key and options cannot be modified.\n+ * - Hardware counters aren't implemented.\n+ */\n+\n+/* System headers. */\n+#include <stddef.h>\n+#include <stdio.h>\n+#include <stdlib.h>\n+#include <stdint.h>\n+#include <inttypes.h>\n+#include <string.h>\n+#include <errno.h>\n+#include <unistd.h>\n+#include <limits.h>\n+#include <assert.h>\n+#include <arpa/inet.h>\n+#include <net/if.h>\n+#include <dirent.h>\n+#include <sys/ioctl.h>\n+#include <sys/socket.h>\n+#include <netinet/in.h>\n+#include <linux/if.h>\n+#include <linux/ethtool.h>\n+#include <linux/sockios.h>\n+\n+/* DPDK headers don't like -pedantic. */\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-pedantic\"\n+#endif\n+#include <rte_config.h>\n+#include <rte_ether.h>\n+#include <rte_ethdev.h>\n+#include <rte_dev.h>\n+#include <rte_mbuf.h>\n+#include <rte_errno.h>\n+#include <rte_mempool.h>\n+#include <rte_prefetch.h>\n+#include <rte_malloc.h>\n+#include <rte_spinlock.h>\n+#include <rte_atomic.h>\n+#include <rte_version.h>\n+#include <rte_log.h>\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-pedantic\"\n+#endif\n+\n+/* Verbs header. */\n+/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-pedantic\"\n+#endif\n+\n+#include <infiniband/verbs.h>\n+\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-pedantic\"\n+#endif\n+\n+/* Generated configuration header. */\n+#include \"mlx4_autoconf.h\"\n+\n+/* PMD header. */\n+#include \"mlx4.h\"\n+\n+/* Runtime logging through RTE_LOG() is enabled when not in debugging mode.\n+ * Intermediate LOG_*() macros add the required end-of-line characters. */\n+#ifndef NDEBUG\n+#define INFO(...) DEBUG(__VA_ARGS__)\n+#define WARN(...) DEBUG(__VA_ARGS__)\n+#define ERROR(...) DEBUG(__VA_ARGS__)\n+#else\n+#define LOG__(level, m, ...) \\\n+\tRTE_LOG(level, PMD, MLX4_DRIVER_NAME \": \" m \"%c\", __VA_ARGS__)\n+#define LOG_(level, ...) LOG__(level, __VA_ARGS__, '\\n')\n+#define INFO(...) LOG_(INFO, __VA_ARGS__)\n+#define WARN(...) LOG_(WARNING, __VA_ARGS__)\n+#define ERROR(...) LOG_(ERR, __VA_ARGS__)\n+#endif\n+\n+/* Convenience macros for accessing mbuf fields. */\n+#define NEXT(m) (m)->next\n+#define DATA_LEN(m) (m)->data_len\n+#define PKT_LEN(m) (m)->pkt_len\n+#define DATA_OFF(m) (m)->data_off\n+#define SET_DATA_OFF(m, o) ((m)->data_off = (o))\n+#define NB_SEGS(m) (m)->nb_segs\n+#define PORT(m) (m)->port\n+\n+/* Work Request ID data type (64 bit). */\n+typedef union {\n+\tstruct {\n+\t\tuint32_t id;\n+\t\tuint16_t offset;\n+\t} data;\n+\tuint64_t raw;\n+} wr_id_t;\n+\n+#define WR_ID(o) ((wr_id_t *)&(o))->data\n+\n+/* Compile-time check. */\n+static inline void wr_id_t_check(void)\n+{\n+\twr_id_t check[1 + (2 * -!(sizeof(wr_id_t) == sizeof(uint64_t)))];\n+\n+\t(void)check;\n+\t(void)wr_id_t_check;\n+}\n+\n+/* If raw send operations are available, use them since they are faster. */\n+#ifdef SEND_RAW_WR_SUPPORT\n+typedef struct ibv_send_wr_raw mlx4_send_wr_t;\n+#define mlx4_post_send ibv_post_send_raw\n+#else\n+typedef struct ibv_send_wr mlx4_send_wr_t;\n+#define mlx4_post_send ibv_post_send\n+#endif\n+\n+struct mlx4_rxq_stats {\n+\tunsigned int idx; /**< Mapping index. */\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\tuint64_t ipackets; /**< Total of successfully received packets. */\n+\tuint64_t ibytes; /**< Total of successfully received bytes. */\n+#endif\n+\tuint64_t idropped; /**< Total of packets dropped when RX ring full. */\n+\tuint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */\n+};\n+\n+struct mlx4_txq_stats {\n+\tunsigned int idx; /**< Mapping index. */\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\tuint64_t opackets; /**< Total of successfully sent packets. */\n+\tuint64_t obytes; /**< Total of successfully sent bytes. */\n+#endif\n+\tuint64_t odropped; /**< Total of packets not sent when TX ring full. */\n+};\n+\n+/* RX element (scattered packets). */\n+struct rxq_elt_sp {\n+\tstruct ibv_recv_wr wr; /* Work Request. */\n+\tstruct ibv_sge sges[MLX4_PMD_SGE_WR_N]; /* Scatter/Gather Elements. */\n+\tstruct rte_mbuf *bufs[MLX4_PMD_SGE_WR_N]; /* SGEs buffers. */\n+};\n+\n+/* RX element. */\n+struct rxq_elt {\n+\tstruct ibv_recv_wr wr; /* Work Request. */\n+\tstruct ibv_sge sge; /* Scatter/Gather Element. */\n+\t/* mbuf pointer is derived from WR_ID(wr.wr_id).offset. */\n+};\n+\n+/* RX queue descriptor. */\n+struct rxq {\n+\tstruct priv *priv; /* Back pointer to private data. */\n+\tstruct rte_mempool *mp; /* Memory Pool for allocations. */\n+\tstruct ibv_mr *mr; /* Memory Region (for mp). */\n+\tstruct ibv_cq *cq; /* Completion Queue. */\n+\tstruct ibv_qp *qp; /* Queue Pair. */\n+\t/*\n+\t * There is exactly one flow configured per MAC address. Each flow\n+\t * may contain several specifications, one per configured VLAN ID.\n+\t */\n+\tBITFIELD_DECLARE(mac_configured, uint32_t, MLX4_MAX_MAC_ADDRESSES);\n+\tstruct ibv_exp_flow *mac_flow[MLX4_MAX_MAC_ADDRESSES];\n+\tstruct ibv_exp_flow *promisc_flow; /* Promiscuous flow. */\n+\tstruct ibv_exp_flow *allmulti_flow; /* Multicast flow. */\n+\tunsigned int port_id; /* Port ID for incoming packets. */\n+\tunsigned int elts_n; /* (*elts)[] length. */\n+\tunion {\n+\t\tstruct rxq_elt_sp (*sp)[]; /* Scattered RX elements. */\n+\t\tstruct rxq_elt (*no_sp)[]; /* RX elements. */\n+\t} elts;\n+\tunsigned int sp:1; /* Use scattered RX elements. */\n+\tuint32_t mb_len; /* Length of a mp-issued mbuf. */\n+\tstruct mlx4_rxq_stats stats; /* RX queue counters. */\n+\tunsigned int socket; /* CPU socket ID for allocations. */\n+};\n+\n+/* TX element. */\n+struct txq_elt {\n+\tmlx4_send_wr_t wr; /* Work Request. */\n+\tstruct ibv_sge sges[MLX4_PMD_SGE_WR_N]; /* Scatter/Gather Elements. */\n+\t/* mbuf pointer is derived from WR_ID(wr.wr_id).offset. */\n+};\n+\n+/* Linear buffer type. It is used when transmitting buffers with too many\n+ * segments that do not fit the hardware queue (see max_send_sge).\n+ * Extra segments are copied (linearized) in such buffers, replacing the\n+ * last SGE during TX.\n+ * The size is arbitrary but large enough to hold a jumbo frame with\n+ * 8 segments considering mbuf.buf_len is about 2048 bytes. */\n+typedef uint8_t linear_t[16384];\n+\n+/* TX queue descriptor. */\n+struct txq {\n+\tstruct priv *priv; /* Back pointer to private data. */\n+\tstruct {\n+\t\tstruct rte_mempool *mp; /* Cached Memory Pool. */\n+\t\tstruct ibv_mr *mr; /* Memory Region (for mp). */\n+\t\tuint32_t lkey; /* mr->lkey */\n+\t} mp2mr[MLX4_PMD_TX_MP_CACHE]; /* MP to MR translation table. */\n+\tstruct ibv_cq *cq; /* Completion Queue. */\n+\tstruct ibv_qp *qp; /* Queue Pair. */\n+#if MLX4_PMD_MAX_INLINE > 0\n+\tuint32_t max_inline; /* Max inline send size <= MLX4_PMD_MAX_INLINE. */\n+#endif\n+\tunsigned int elts_n; /* (*elts)[] length. */\n+\tstruct txq_elt (*elts)[]; /* TX elements. */\n+\tunsigned int elts_head; /* Current index in (*elts)[]. */\n+\tunsigned int elts_tail; /* First element awaiting completion. */\n+\tunsigned int elts_comp; /* Number of completion requests. */\n+\tstruct mlx4_txq_stats stats; /* TX queue counters. */\n+\tlinear_t (*elts_linear)[]; /* Linearized buffers. */\n+\tstruct ibv_mr *mr_linear; /* Memory Region for linearized buffers. */\n+\tunsigned int socket; /* CPU socket ID for allocations. */\n+};\n+\n+struct priv {\n+\tstruct rte_eth_dev *dev; /* Ethernet device. */\n+\tstruct ibv_context *ctx; /* Verbs context. */\n+\tstruct ibv_device_attr device_attr; /* Device properties. */\n+\tstruct ibv_port_attr port_attr; /* Physical port properties. */\n+\tstruct ibv_pd *pd; /* Protection Domain. */\n+\t/*\n+\t * MAC addresses array and configuration bit-field.\n+\t * An extra entry that cannot be modified by the DPDK is reserved\n+\t * for broadcast frames (destination MAC address ff:ff:ff:ff:ff:ff).\n+\t */\n+\tstruct ether_addr mac[MLX4_MAX_MAC_ADDRESSES];\n+\tBITFIELD_DECLARE(mac_configured, uint32_t, MLX4_MAX_MAC_ADDRESSES);\n+\t/* VLAN filters. */\n+\tstruct {\n+\t\tunsigned int enabled:1; /* If enabled. */\n+\t\tunsigned int id:12; /* VLAN ID (0-4095). */\n+\t} vlan_filter[MLX4_MAX_VLAN_IDS]; /* VLAN filters table. */\n+\t/* Device properties. */\n+\tuint16_t mtu; /* Configured MTU. */\n+\tuint8_t port; /* Physical port number. */\n+\tunsigned int started:1; /* Device started, flows enabled. */\n+\tunsigned int promisc:1; /* Device in promiscuous mode. */\n+\tunsigned int promisc_ok:1; /* Promiscuous flow is supported. */\n+\tunsigned int allmulti:1; /* Device receives all multicast packets. */\n+\tunsigned int hw_qpg:1; /* QP groups are supported. */\n+\tunsigned int hw_tss:1; /* TSS is supported. */\n+\tunsigned int hw_rss:1; /* RSS is supported. */\n+\tunsigned int rss:1; /* RSS is enabled. */\n+#ifdef MLX4_COMPAT_VMWARE\n+\tunsigned int vmware:1; /* Use VMware compatibility. */\n+#endif\n+\tunsigned int vf:1; /* This is a VF device. */\n+#ifdef INLINE_RECV\n+\tunsigned int inl_recv_size; /* Inline recv size */\n+#endif\n+\tunsigned int max_rss_tbl_sz; /* Maximum number of RSS queues. */\n+\t/* RX/TX queues. */\n+\tstruct rxq rxq_parent; /* Parent queue when RSS is enabled. */\n+\tunsigned int rxqs_n; /* RX queues array size. */\n+\tunsigned int txqs_n; /* TX queues array size. */\n+\tstruct rxq *(*rxqs)[]; /* RX queues. */\n+\tstruct txq *(*txqs)[]; /* TX queues. */\n+\trte_spinlock_t lock; /* Lock for control functions. */\n+};\n+\n+/**\n+ * Lock private structure to protect it from concurrent access in the\n+ * control path.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ */\n+static void\n+priv_lock(struct priv *priv)\n+{\n+\trte_spinlock_lock(&priv->lock);\n+}\n+\n+/**\n+ * Unlock private structure.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ */\n+static void\n+priv_unlock(struct priv *priv)\n+{\n+\trte_spinlock_unlock(&priv->lock);\n+}\n+\n+/* Allocate a buffer on the stack and fill it with a printf format string. */\n+#define MKSTR(name, ...) \\\n+\tchar name[snprintf(NULL, 0, __VA_ARGS__) + 1]; \\\n+\t\\\n+\tsnprintf(name, sizeof(name), __VA_ARGS__)\n+\n+/**\n+ * Get interface name from private structure.\n+ *\n+ * @param[in] priv\n+ * Pointer to private structure.\n+ * @param[out] ifname\n+ * Interface name output buffer.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure and errno is set.\n+ */\n+static int\n+priv_get_ifname(const struct priv *priv, char (*ifname)[IF_NAMESIZE])\n+{\n+\tint ret = -1;\n+\tDIR *dir;\n+\tstruct dirent *dent;\n+\n+\t{\n+\t\tMKSTR(path, \"%s/device/net\", priv->ctx->device->ibdev_path);\n+\n+\t\tdir = opendir(path);\n+\t\tif (dir == NULL)\n+\t\t\treturn -1;\n+\t}\n+\twhile ((dent = readdir(dir)) != NULL) {\n+\t\tchar *name = dent->d_name;\n+\t\tFILE *file;\n+\t\tunsigned int dev_id;\n+\t\tint r;\n+\n+\t\tif ((name[0] == '.') &&\n+\t\t ((name[1] == '\\0') ||\n+\t\t ((name[1] == '.') && (name[2] == '\\0'))))\n+\t\t\tcontinue;\n+\n+\t\tMKSTR(path, \"%s/device/net/%s/dev_id\",\n+\t\t priv->ctx->device->ibdev_path, name);\n+\n+\t\tfile = fopen(path, \"rb\");\n+\t\tif (file == NULL)\n+\t\t\tcontinue;\n+\t\tr = fscanf(file, \"%x\", &dev_id);\n+\t\tfclose(file);\n+\t\tif ((r == 1) && (dev_id == (priv->port - 1u))) {\n+\t\t\tsnprintf(*ifname, sizeof(*ifname), \"%s\", name);\n+\t\t\tret = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tclosedir(dir);\n+\treturn ret;\n+}\n+\n+/**\n+ * Read from sysfs entry.\n+ *\n+ * @param[in] priv\n+ * Pointer to private structure.\n+ * @param[in] entry\n+ * Entry name relative to sysfs path.\n+ * @param[out] buf\n+ * Data output buffer.\n+ * @param size\n+ * Buffer size.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure and errno is set.\n+ */\n+static int\n+priv_sysfs_read(const struct priv *priv, const char *entry,\n+\t\tchar *buf, size_t size)\n+{\n+\tchar ifname[IF_NAMESIZE];\n+\tFILE *file;\n+\tint ret;\n+\tint err;\n+\n+\tif (priv_get_ifname(priv, &ifname))\n+\t\treturn -1;\n+\n+\tMKSTR(path, \"%s/device/net/%s/%s\", priv->ctx->device->ibdev_path,\n+\t ifname, entry);\n+\n+\tfile = fopen(path, \"rb\");\n+\tif (file == NULL)\n+\t\treturn -1;\n+\tret = fread(buf, 1, size, file);\n+\terr = errno;\n+\tif (((size_t)ret < size) && (ferror(file)))\n+\t\tret = -1;\n+\telse\n+\t\tret = size;\n+\tfclose(file);\n+\terrno = err;\n+\treturn ret;\n+}\n+\n+/**\n+ * Write to sysfs entry.\n+ *\n+ * @param[in] priv\n+ * Pointer to private structure.\n+ * @param[in] entry\n+ * Entry name relative to sysfs path.\n+ * @param[in] buf\n+ * Data buffer.\n+ * @param size\n+ * Buffer size.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure and errno is set.\n+ */\n+static int\n+priv_sysfs_write(const struct priv *priv, const char *entry,\n+\t\t char *buf, size_t size)\n+{\n+\tchar ifname[IF_NAMESIZE];\n+\tFILE *file;\n+\tint ret;\n+\tint err;\n+\n+\tif (priv_get_ifname(priv, &ifname))\n+\t\treturn -1;\n+\n+\tMKSTR(path, \"%s/device/net/%s/%s\", priv->ctx->device->ibdev_path,\n+\t ifname, entry);\n+\n+\tfile = fopen(path, \"wb\");\n+\tif (file == NULL)\n+\t\treturn -1;\n+\tret = fwrite(buf, 1, size, file);\n+\terr = errno;\n+\tif (((size_t)ret < size) || (ferror(file)))\n+\t\tret = -1;\n+\telse\n+\t\tret = size;\n+\tfclose(file);\n+\terrno = err;\n+\treturn ret;\n+}\n+\n+/**\n+ * Get unsigned long sysfs property.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ * @param[in] name\n+ * Entry name relative to sysfs path.\n+ * @param[out] value\n+ * Value output buffer.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure and errno is set.\n+ */\n+static int\n+priv_get_sysfs_ulong(struct priv *priv, const char *name, unsigned long *value)\n+{\n+\tint ret;\n+\tunsigned long value_ret;\n+\tchar value_str[32];\n+\n+\tret = priv_sysfs_read(priv, name, value_str, (sizeof(value_str) - 1));\n+\tif (ret == -1) {\n+\t\tDEBUG(\"cannot read %s value from sysfs: %s\",\n+\t\t name, strerror(errno));\n+\t\treturn -1;\n+\t}\n+\tvalue_str[ret] = '\\0';\n+\terrno = 0;\n+\tvalue_ret = strtoul(value_str, NULL, 0);\n+\tif (errno) {\n+\t\tDEBUG(\"invalid %s value `%s': %s\", name, value_str,\n+\t\t strerror(errno));\n+\t\treturn -1;\n+\t}\n+\t*value = value_ret;\n+\treturn 0;\n+}\n+\n+/**\n+ * Set unsigned long sysfs property.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ * @param[in] name\n+ * Entry name relative to sysfs path.\n+ * @param value\n+ * Value to set.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure and errno is set.\n+ */\n+static int\n+priv_set_sysfs_ulong(struct priv *priv, const char *name, unsigned long value)\n+{\n+\tint ret;\n+\tMKSTR(value_str, \"%lu\", value);\n+\n+\tret = priv_sysfs_write(priv, name, value_str, (sizeof(value_str) - 1));\n+\tif (ret == -1) {\n+\t\tDEBUG(\"cannot write %s `%s' (%lu) to sysfs: %s\",\n+\t\t name, value_str, value, strerror(errno));\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * Perform ifreq ioctl() on associated Ethernet device.\n+ *\n+ * @param[in] priv\n+ * Pointer to private structure.\n+ * @param req\n+ * Request number to pass to ioctl().\n+ * @param[out] ifr\n+ * Interface request structure output buffer.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure and errno is set.\n+ */\n+static int\n+priv_ifreq(const struct priv *priv, int req, struct ifreq *ifr)\n+{\n+\tint sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_IP);\n+\tint ret = -1;\n+\n+\tif (sock == -1)\n+\t\treturn ret;\n+\tif (priv_get_ifname(priv, &ifr->ifr_name) == 0)\n+\t\tret = ioctl(sock, req, ifr);\n+\tclose(sock);\n+\treturn ret;\n+}\n+\n+/**\n+ * Get device MTU.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ * @param[out] mtu\n+ * MTU value output buffer.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure and errno is set.\n+ */\n+static int\n+priv_get_mtu(struct priv *priv, uint16_t *mtu)\n+{\n+\tunsigned long ulong_mtu;\n+\n+\tif (priv_get_sysfs_ulong(priv, \"mtu\", &ulong_mtu) == -1)\n+\t\treturn -1;\n+\t*mtu = ulong_mtu;\n+\treturn 0;\n+}\n+\n+/**\n+ * Set device MTU.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ * @param mtu\n+ * MTU value to set.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure and errno is set.\n+ */\n+static int\n+priv_set_mtu(struct priv *priv, uint16_t mtu)\n+{\n+\treturn priv_set_sysfs_ulong(priv, \"mtu\", mtu);\n+}\n+\n+/**\n+ * Set device flags.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ * @param keep\n+ * Bitmask for flags that must remain untouched.\n+ * @param flags\n+ * Bitmask for flags to modify.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure and errno is set.\n+ */\n+static int\n+priv_set_flags(struct priv *priv, unsigned int keep, unsigned int flags)\n+{\n+\tunsigned long tmp;\n+\n+\tif (priv_get_sysfs_ulong(priv, \"flags\", &tmp) == -1)\n+\t\treturn -1;\n+\ttmp &= keep;\n+\ttmp |= flags;\n+\treturn priv_set_sysfs_ulong(priv, \"flags\", tmp);\n+}\n+\n+/* Device configuration. */\n+\n+static int\n+rxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc,\n+\t unsigned int socket, const struct rte_eth_rxconf *conf,\n+\t struct rte_mempool *mp);\n+\n+static void\n+rxq_cleanup(struct rxq *rxq);\n+\n+/**\n+ * Ethernet device configuration.\n+ *\n+ * Prepare the driver for a given number of TX and RX queues.\n+ * Allocate parent RSS queue when several RX queues are requested.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+dev_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tunsigned int rxqs_n = dev->data->nb_rx_queues;\n+\tunsigned int txqs_n = dev->data->nb_tx_queues;\n+\tunsigned int tmp;\n+\tint ret;\n+\n+\tpriv->rxqs = (void *)dev->data->rx_queues;\n+\tpriv->txqs = (void *)dev->data->tx_queues;\n+\tif (txqs_n != priv->txqs_n) {\n+\t\tINFO(\"%p: TX queues number update: %u -> %u\",\n+\t\t (void *)dev, priv->txqs_n, txqs_n);\n+\t\tpriv->txqs_n = txqs_n;\n+\t}\n+\tif (rxqs_n == priv->rxqs_n)\n+\t\treturn 0;\n+\tINFO(\"%p: RX queues number update: %u -> %u\",\n+\t (void *)dev, priv->rxqs_n, rxqs_n);\n+\t/* If RSS is enabled, disable it first. */\n+\tif (priv->rss) {\n+\t\tunsigned int i;\n+\n+\t\t/* Only if there are no remaining child RX queues. */\n+\t\tfor (i = 0; (i != priv->rxqs_n); ++i)\n+\t\t\tif ((*priv->rxqs)[i] != NULL)\n+\t\t\t\treturn EINVAL;\n+\t\trxq_cleanup(&priv->rxq_parent);\n+\t\tpriv->rss = 0;\n+\t\tpriv->rxqs_n = 0;\n+\t}\n+\tif (rxqs_n <= 1) {\n+\t\t/* Nothing else to do. */\n+\t\tpriv->rxqs_n = rxqs_n;\n+\t\treturn 0;\n+\t}\n+\t/* Allocate a new RSS parent queue if supported by hardware. */\n+\tif (!priv->hw_rss) {\n+\t\tERROR(\"%p: only a single RX queue can be configured when\"\n+\t\t \" hardware doesn't support RSS\",\n+\t\t (void *)dev);\n+\t\treturn EINVAL;\n+\t}\n+\t/* Fail if hardware doesn't support that many RSS queues. */\n+\tif (rxqs_n >= priv->max_rss_tbl_sz) {\n+\t\tERROR(\"%p: only %u RX queues can be configured for RSS\",\n+\t\t (void *)dev, priv->max_rss_tbl_sz);\n+\t\treturn EINVAL;\n+\t}\n+\tpriv->rss = 1;\n+\ttmp = priv->rxqs_n;\n+\tpriv->rxqs_n = rxqs_n;\n+\tret = rxq_setup(dev, &priv->rxq_parent, 0, 0, NULL, NULL);\n+\tif (!ret)\n+\t\treturn 0;\n+\t/* Failure, rollback. */\n+\tpriv->rss = 0;\n+\tpriv->rxqs_n = tmp;\n+\tassert(ret > 0);\n+\treturn ret;\n+}\n+\n+/**\n+ * DPDK callback for Ethernet device configuration.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ *\n+ * @return\n+ * 0 on success, negative errno value on failure.\n+ */\n+static int\n+mlx4_dev_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tint ret;\n+\n+\tpriv_lock(priv);\n+\tret = dev_configure(dev);\n+\tassert(ret >= 0);\n+\tpriv_unlock(priv);\n+\treturn -ret;\n+}\n+\n+/* TX queues handling. */\n+\n+/**\n+ * Allocate TX queue elements.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ * @param elts_n\n+ * Number of elements to allocate.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+txq_alloc_elts(struct txq *txq, unsigned int elts_n)\n+{\n+\tunsigned int i;\n+\tstruct txq_elt (*elts)[elts_n] =\n+\t\trte_calloc_socket(\"TXQ\", 1, sizeof(*elts), 0, txq->socket);\n+\tlinear_t (*elts_linear)[elts_n] =\n+\t\trte_calloc_socket(\"TXQ\", 1, sizeof(*elts_linear), 0,\n+\t\t\t\t txq->socket);\n+\tstruct ibv_mr *mr_linear = NULL;\n+\tint ret = 0;\n+\n+\tif ((elts == NULL) || (elts_linear == NULL)) {\n+\t\tERROR(\"%p: can't allocate packets array\", (void *)txq);\n+\t\tret = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tmr_linear =\n+\t\tibv_reg_mr(txq->priv->pd, elts_linear, sizeof(*elts_linear),\n+\t\t\t (IBV_ACCESS_LOCAL_WRITE | IBV_ACCESS_REMOTE_WRITE));\n+\tif (mr_linear == NULL) {\n+\t\tERROR(\"%p: unable to configure MR, ibv_reg_mr() failed\",\n+\t\t (void *)txq);\n+\t\tret = EINVAL;\n+\t\tgoto error;\n+\t}\n+\tfor (i = 0; (i != elts_n); ++i) {\n+\t\tstruct txq_elt *elt = &(*elts)[i];\n+\t\tmlx4_send_wr_t *wr = &elt->wr;\n+\n+\t\t/* Configure WR. */\n+\t\tWR_ID(wr->wr_id).id = i;\n+\t\tWR_ID(wr->wr_id).offset = 0;\n+\t\twr->sg_list = &elt->sges[0];\n+\t\twr->opcode = IBV_WR_SEND;\n+\t\t/* Other fields are updated during TX. */\n+\t}\n+\tDEBUG(\"%p: allocated and configured %u WRs\", (void *)txq, elts_n);\n+\ttxq->elts_n = elts_n;\n+\ttxq->elts = elts;\n+\ttxq->elts_head = 0;\n+\ttxq->elts_tail = 0;\n+\ttxq->elts_comp = 0;\n+\ttxq->elts_linear = elts_linear;\n+\ttxq->mr_linear = mr_linear;\n+\tassert(ret == 0);\n+\treturn 0;\n+error:\n+\tif (mr_linear != NULL)\n+\t\tclaim_zero(ibv_dereg_mr(mr_linear));\n+\tif (elts_linear != NULL)\n+\t\trte_free(elts_linear);\n+\tif (elts != NULL)\n+\t\trte_free(elts);\n+\tDEBUG(\"%p: failed, freed everything\", (void *)txq);\n+\tassert(ret > 0);\n+\treturn ret;\n+}\n+\n+/**\n+ * Free TX queue elements.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ */\n+static void\n+txq_free_elts(struct txq *txq)\n+{\n+\tunsigned int i;\n+\tunsigned int elts_n = txq->elts_n;\n+\tstruct txq_elt (*elts)[elts_n] = txq->elts;\n+\tlinear_t (*elts_linear)[elts_n] = txq->elts_linear;\n+\tstruct ibv_mr *mr_linear = txq->mr_linear;\n+\n+\tDEBUG(\"%p: freeing WRs\", (void *)txq);\n+\ttxq->elts_n = 0;\n+\ttxq->elts = NULL;\n+\ttxq->elts_linear = NULL;\n+\ttxq->mr_linear = NULL;\n+\tif (mr_linear != NULL)\n+\t\tclaim_zero(ibv_dereg_mr(mr_linear));\n+\tif (elts_linear != NULL)\n+\t\trte_free(elts_linear);\n+\tif (elts == NULL)\n+\t\treturn;\n+\tfor (i = 0; (i != elemof(*elts)); ++i) {\n+\t\tstruct txq_elt *elt = &(*elts)[i];\n+\n+\t\tif (WR_ID(elt->wr.wr_id).offset == 0)\n+\t\t\tcontinue;\n+\t\trte_pktmbuf_free((void *)(elt->sges[0].addr -\n+\t\t\t\t\t WR_ID(elt->wr.wr_id).offset));\n+\t}\n+\trte_free(elts);\n+}\n+\n+\n+/**\n+ * Clean up a TX queue.\n+ *\n+ * Destroy objects, free allocated memory and reset the structure for reuse.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ */\n+static void\n+txq_cleanup(struct txq *txq)\n+{\n+\tsize_t i;\n+\n+\tDEBUG(\"cleaning up %p\", (void *)txq);\n+\ttxq_free_elts(txq);\n+\tif (txq->qp != NULL)\n+\t\tclaim_zero(ibv_destroy_qp(txq->qp));\n+\tif (txq->cq != NULL)\n+\t\tclaim_zero(ibv_destroy_cq(txq->cq));\n+\tfor (i = 0; (i != elemof(txq->mp2mr)); ++i) {\n+\t\tif (txq->mp2mr[i].mp == NULL)\n+\t\t\tbreak;\n+\t\tassert(txq->mp2mr[i].mr != NULL);\n+\t\tclaim_zero(ibv_dereg_mr(txq->mp2mr[i].mr));\n+\t}\n+\tmemset(txq, 0, sizeof(*txq));\n+}\n+\n+/**\n+ * Manage TX completions.\n+ *\n+ * When sending a burst, mlx4_tx_burst() posts several WRs.\n+ * To improve performance, a completion event is only required for the last of\n+ * them. Doing so discards completion information for other WRs, but this\n+ * information would not be used anyway.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure.\n+ */\n+static int\n+txq_complete(struct txq *txq)\n+{\n+\tunsigned int elts_comp = txq->elts_comp;\n+\tunsigned int elts_tail;\n+\tconst unsigned int elts_n = txq->elts_n;\n+\tstruct ibv_wc wcs[elts_comp];\n+\tint wcs_n;\n+\n+\tif (unlikely(elts_comp == 0))\n+\t\treturn 0;\n+#ifdef DEBUG_SEND\n+\tDEBUG(\"%p: processing %u work requests completions\",\n+\t (void *)txq, elts_comp);\n+#endif\n+\twcs_n = ibv_poll_cq(txq->cq, elts_comp, wcs);\n+\tif (unlikely(wcs_n == 0))\n+\t\treturn 0;\n+\tif (unlikely(wcs_n < 0)) {\n+\t\tDEBUG(\"%p: ibv_poll_cq() failed (wcs_n=%d)\",\n+\t\t (void *)txq, wcs_n);\n+\t\treturn -1;\n+\t}\n+\telts_comp -= wcs_n;\n+\tassert(elts_comp <= txq->elts_comp);\n+\t/*\n+\t * Work Completion ID contains the associated element index in\n+\t * (*txq->elts)[]. Since WCs are returned in order, we only need to\n+\t * look at the last WC to clear older Work Requests.\n+\t *\n+\t * Assume WC status is successful as nothing can be done about it\n+\t * anyway.\n+\t */\n+\telts_tail = WR_ID(wcs[wcs_n - 1].wr_id).id;\n+\t/* Consume the last WC. */\n+\tif (++elts_tail >= elts_n)\n+\t\telts_tail = 0;\n+\ttxq->elts_tail = elts_tail;\n+\ttxq->elts_comp = elts_comp;\n+\treturn 0;\n+}\n+\n+/**\n+ * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].\n+ * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,\n+ * remove an entry first.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ * @param[in] mp\n+ * Memory Pool for which a Memory Region lkey must be returned.\n+ *\n+ * @return\n+ * mr->lkey on success, (uint32_t)-1 on failure.\n+ */\n+static uint32_t\n+txq_mp2mr(struct txq *txq, struct rte_mempool *mp)\n+{\n+\tunsigned int i;\n+\tstruct ibv_mr *mr;\n+\n+\tfor (i = 0; (i != elemof(txq->mp2mr)); ++i) {\n+\t\tif (unlikely(txq->mp2mr[i].mp == NULL)) {\n+\t\t\t/* Unknown MP, add a new MR for it. */\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (txq->mp2mr[i].mp == mp) {\n+\t\t\tassert(txq->mp2mr[i].lkey != (uint32_t)-1);\n+\t\t\tassert(txq->mp2mr[i].mr->lkey == txq->mp2mr[i].lkey);\n+\t\t\treturn txq->mp2mr[i].lkey;\n+\t\t}\n+\t}\n+\t/* Add a new entry, register MR first. */\n+\tDEBUG(\"%p: discovered new memory pool %p\", (void *)txq, (void *)mp);\n+\tmr = ibv_reg_mr(txq->priv->pd,\n+\t\t (void *)mp->elt_va_start,\n+\t\t (mp->elt_va_end - mp->elt_va_start),\n+\t\t\t(IBV_ACCESS_LOCAL_WRITE | IBV_ACCESS_REMOTE_WRITE));\n+\tif (unlikely(mr == NULL)) {\n+\t\tDEBUG(\"%p: unable to configure MR, ibv_reg_mr() failed.\",\n+\t\t (void *)txq);\n+\t\treturn (uint32_t)-1;\n+\t}\n+\tif (unlikely(i == elemof(txq->mp2mr))) {\n+\t\t/* Table is full, remove oldest entry. */\n+\t\tDEBUG(\"%p: MR <-> MP table full, dropping oldest entry.\",\n+\t\t (void *)txq);\n+\t\t--i;\n+\t\tclaim_zero(ibv_dereg_mr(txq->mp2mr[i].mr));\n+\t\tmemmove(&txq->mp2mr[0], &txq->mp2mr[1],\n+\t\t\t(sizeof(txq->mp2mr) - sizeof(txq->mp2mr[0])));\n+\t}\n+\t/* Store the new entry. */\n+\ttxq->mp2mr[i].mp = mp;\n+\ttxq->mp2mr[i].mr = mr;\n+\ttxq->mp2mr[i].lkey = mr->lkey;\n+\tDEBUG(\"%p: new MR lkey for MP %p: 0x%08\" PRIu32,\n+\t (void *)txq, (void *)mp, txq->mp2mr[i].lkey);\n+\treturn txq->mp2mr[i].lkey;\n+}\n+\n+/**\n+ * Copy scattered mbuf contents to a single linear buffer.\n+ *\n+ * @param[out] linear\n+ * Linear output buffer.\n+ * @param[in] buf\n+ * Scattered input buffer.\n+ *\n+ * @return\n+ * Number of bytes copied to the output buffer or 0 if not large enough.\n+ */\n+static unsigned int\n+linearize_mbuf(linear_t *linear, struct rte_mbuf *buf)\n+{\n+\tunsigned int size = 0;\n+\tunsigned int offset;\n+\n+\tdo {\n+\t\tunsigned int len = DATA_LEN(buf);\n+\n+\t\toffset = size;\n+\t\tsize += len;\n+\t\tif (unlikely(size > sizeof(*linear)))\n+\t\t\treturn 0;\n+\t\tmemcpy(&(*linear)[offset],\n+\t\t rte_pktmbuf_mtod(buf, uint8_t *),\n+\t\t len);\n+\t\tbuf = NEXT(buf);\n+\t}\n+\twhile (buf != NULL);\n+\treturn size;\n+}\n+\n+/**\n+ * DPDK callback for TX.\n+ *\n+ * @param dpdk_txq\n+ * Generic pointer to TX queue structure.\n+ * @param[in] pkts\n+ * Packets to transmit.\n+ * @param pkts_n\n+ * Number of packets in array.\n+ *\n+ * @return\n+ * Number of packets successfully transmitted (<= pkts_n).\n+ */\n+static uint16_t\n+mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n+{\n+\tstruct txq *txq = (struct txq *)dpdk_txq;\n+\tmlx4_send_wr_t head;\n+\tmlx4_send_wr_t **wr_next = &head.next;\n+\tmlx4_send_wr_t *bad_wr;\n+\tunsigned int elts_head = txq->elts_head;\n+\tconst unsigned int elts_tail = txq->elts_tail;\n+\tconst unsigned int elts_n = txq->elts_n;\n+\tunsigned int i;\n+\tunsigned int max;\n+\tint err;\n+\n+\ttxq_complete(txq);\n+\tmax = (elts_n - (elts_head - elts_tail));\n+\tif (max > elts_n)\n+\t\tmax -= elts_n;\n+\tassert(max >= 1);\n+\tassert(max <= elts_n);\n+\t/* Always leave one free entry in the ring. */\n+\t--max;\n+\tif (max == 0)\n+\t\treturn 0;\n+\tif (max > pkts_n)\n+\t\tmax = pkts_n;\n+\tfor (i = 0; (i != max); ++i) {\n+\t\tstruct rte_mbuf *buf = pkts[i];\n+\t\tstruct txq_elt *elt = &(*txq->elts)[elts_head];\n+\t\tmlx4_send_wr_t *wr = &elt->wr;\n+\t\tunsigned int segs = NB_SEGS(buf);\n+#if (MLX4_PMD_MAX_INLINE > 0) || defined(MLX4_PMD_SOFT_COUNTERS)\n+\t\tunsigned int sent_size = 0;\n+#endif\n+\t\tunsigned int j;\n+\t\tint linearize = 0;\n+\n+\t\t/* Clean up old buffer. */\n+\t\tif (likely(WR_ID(wr->wr_id).offset != 0)) {\n+\t\t\tstruct rte_mbuf *tmp = (void *)\n+\t\t\t\t(elt->sges[0].addr - WR_ID(wr->wr_id).offset);\n+\n+\t\t\t/* Faster than rte_pktmbuf_free(). */\n+\t\t\tdo {\n+\t\t\t\tstruct rte_mbuf *next = NEXT(tmp);\n+\n+\t\t\t\trte_pktmbuf_free_seg(tmp);\n+\t\t\t\ttmp = next;\n+\t\t\t}\n+\t\t\twhile (tmp != NULL);\n+\t\t}\n+#ifndef NDEBUG\n+\t\t/* For assert(). */\n+\t\tWR_ID(wr->wr_id).offset = 0;\n+\t\tfor (j = 0; ((int)j < wr->num_sge); ++j) {\n+\t\t\telt->sges[j].addr = 0;\n+\t\t\telt->sges[j].length = 0;\n+\t\t\telt->sges[j].lkey = 0;\n+\t\t}\n+\t\twr->next = NULL;\n+\t\twr->num_sge = 0;\n+#endif\n+\t\t/* Sanity checks, most of which are only relevant with\n+\t\t * debugging enabled. */\n+\t\tassert(WR_ID(wr->wr_id).id == elts_head);\n+\t\tassert(WR_ID(wr->wr_id).offset == 0);\n+\t\tassert(wr->next == NULL);\n+\t\tassert(wr->sg_list == &elt->sges[0]);\n+\t\tassert(wr->num_sge == 0);\n+\t\tassert(wr->opcode == IBV_WR_SEND);\n+\t\t/* When there are too many segments, extra segments are\n+\t\t * linearized in the last SGE. */\n+\t\tif (unlikely(segs > elemof(elt->sges))) {\n+\t\t\tsegs = (elemof(elt->sges) - 1);\n+\t\t\tlinearize = 1;\n+\t\t}\n+\t\t/* Set WR fields. */\n+\t\tassert(((uintptr_t)rte_pktmbuf_mtod(buf, char *) -\n+\t\t\t(uintptr_t)buf) <= 0xffff);\n+\t\tWR_ID(wr->wr_id).offset =\n+\t\t\t((uintptr_t)rte_pktmbuf_mtod(buf, char *) -\n+\t\t\t (uintptr_t)buf);\n+\t\twr->num_sge = segs;\n+\t\t/* Register segments as SGEs. */\n+\t\tfor (j = 0; (j != segs); ++j) {\n+\t\t\tstruct ibv_sge *sge = &elt->sges[j];\n+\t\t\tuint32_t lkey;\n+\n+\t\t\t/* Retrieve Memory Region key for this memory pool. */\n+\t\t\tlkey = txq_mp2mr(txq, buf->pool);\n+\t\t\tif (unlikely(lkey == (uint32_t)-1)) {\n+\t\t\t\t/* MR does not exist. */\n+\t\t\t\tDEBUG(\"%p: unable to get MP <-> MR\"\n+\t\t\t\t \" association\", (void *)txq);\n+\t\t\t\t/* Clean up TX element. */\n+\t\t\t\tWR_ID(elt->wr.wr_id).offset = 0;\n+#ifndef NDEBUG\n+\t\t\t\t/* For assert(). */\n+\t\t\t\twhile (j) {\n+\t\t\t\t\t--j;\n+\t\t\t\t\t--sge;\n+\t\t\t\t\tsge->addr = 0;\n+\t\t\t\t\tsge->length = 0;\n+\t\t\t\t\tsge->lkey = 0;\n+\t\t\t\t}\n+\t\t\t\twr->num_sge = 0;\n+#endif\n+\t\t\t\tgoto stop;\n+\t\t\t}\n+\t\t\t/* Sanity checks, only relevant with debugging\n+\t\t\t * enabled. */\n+\t\t\tassert(sge->addr == 0);\n+\t\t\tassert(sge->length == 0);\n+\t\t\tassert(sge->lkey == 0);\n+\t\t\t/* Update SGE. */\n+\t\t\tsge->addr = (uintptr_t)rte_pktmbuf_mtod(buf, char *);\n+\t\t\tif (txq->priv->vf)\n+\t\t\t\trte_prefetch0((volatile void *)sge->addr);\n+\t\t\tsge->length = DATA_LEN(buf);\n+\t\t\tsge->lkey = lkey;\n+#if (MLX4_PMD_MAX_INLINE > 0) || defined(MLX4_PMD_SOFT_COUNTERS)\n+\t\t\tsent_size += sge->length;\n+#endif\n+\t\t\tbuf = NEXT(buf);\n+\t\t}\n+\t\t/* If buf is not NULL here and is not going to be linearized,\n+\t\t * nb_segs is not valid. */\n+\t\tassert(j == segs);\n+\t\tassert((buf == NULL) || (linearize));\n+\t\t/* Linearize extra segments. */\n+\t\tif (linearize) {\n+\t\t\tstruct ibv_sge *sge = &elt->sges[segs];\n+\t\t\tlinear_t *linear = &(*txq->elts_linear)[elts_head];\n+\t\t\tunsigned int size = linearize_mbuf(linear, buf);\n+\n+\t\t\tassert(segs == (elemof(elt->sges) - 1));\n+\t\t\tif (size == 0) {\n+\t\t\t\t/* Invalid packet. */\n+\t\t\t\tDEBUG(\"%p: packet too large to be linearized.\",\n+\t\t\t\t (void *)txq);\n+\t\t\t\t/* Clean up TX element. */\n+\t\t\t\tWR_ID(elt->wr.wr_id).offset = 0;\n+#ifndef NDEBUG\n+\t\t\t\t/* For assert(). */\n+\t\t\t\twhile (j) {\n+\t\t\t\t\t--j;\n+\t\t\t\t\t--sge;\n+\t\t\t\t\tsge->addr = 0;\n+\t\t\t\t\tsge->length = 0;\n+\t\t\t\t\tsge->lkey = 0;\n+\t\t\t\t}\n+\t\t\t\twr->num_sge = 0;\n+#endif\n+\t\t\t\tgoto stop;\n+\t\t\t}\n+\t\t\t/* If MLX4_PMD_SGE_WR_N is 1, free mbuf immediately\n+\t\t\t * and clear offset from WR ID. */\n+\t\t\tif (elemof(elt->sges) == 1) {\n+\t\t\t\tdo {\n+\t\t\t\t\tstruct rte_mbuf *next = NEXT(buf);\n+\n+\t\t\t\t\trte_pktmbuf_free_seg(buf);\n+\t\t\t\t\tbuf = next;\n+\t\t\t\t}\n+\t\t\t\twhile (buf != NULL);\n+\t\t\t\tWR_ID(wr->wr_id).offset = 0;\n+\t\t\t}\n+\t\t\t/* Set WR fields and fill SGE with linear buffer. */\n+\t\t\t++wr->num_sge;\n+\t\t\t/* Sanity checks, only relevant with debugging\n+\t\t\t * enabled. */\n+\t\t\tassert(sge->addr == 0);\n+\t\t\tassert(sge->length == 0);\n+\t\t\tassert(sge->lkey == 0);\n+\t\t\t/* Update SGE. */\n+\t\t\tsge->addr = (uintptr_t)&(*linear)[0];\n+\t\t\tsge->length = size;\n+\t\t\tsge->lkey = txq->mr_linear->lkey;\n+#if (MLX4_PMD_MAX_INLINE > 0) || defined(MLX4_PMD_SOFT_COUNTERS)\n+\t\t\tsent_size += size;\n+#endif\n+\t\t}\n+\t\t/* Link WRs together for ibv_post_send(). */\n+\t\t*wr_next = wr;\n+\t\twr_next = &wr->next;\n+#if MLX4_PMD_MAX_INLINE > 0\n+\t\tif (sent_size <= txq->max_inline)\n+\t\t\twr->send_flags = IBV_SEND_INLINE;\n+\t\telse\n+#endif\n+\t\t\twr->send_flags = 0;\n+\t\tif (++elts_head >= elts_n)\n+\t\t\telts_head = 0;\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\t/* Increment sent bytes counter. */\n+\t\ttxq->stats.obytes += sent_size;\n+#endif\n+\t}\n+stop:\n+\t/* Take a shortcut if nothing must be sent. */\n+\tif (unlikely(i == 0))\n+\t\treturn 0;\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t/* Increment sent packets counter. */\n+\ttxq->stats.opackets += i;\n+#endif\n+\t*wr_next = NULL;\n+\t/* The last WR is the only one asking for a completion event. */\n+\tcontainerof(wr_next, mlx4_send_wr_t, next)->\n+\t\tsend_flags |= IBV_SEND_SIGNALED;\n+\terr = mlx4_post_send(txq->qp, head.next, &bad_wr);\n+\tif (unlikely(err)) {\n+\t\tunsigned int unsent = 0;\n+\n+\t\t/* An error occured, completion event is lost. Fix counters. */\n+\t\twhile (bad_wr != NULL) {\n+\t\t\tstruct txq_elt *elt =\n+\t\t\t\tcontainerof(bad_wr, struct txq_elt, wr);\n+\t\t\tmlx4_send_wr_t *wr = &elt->wr;\n+\t\t\tmlx4_send_wr_t *next = wr->next;\n+#if defined(MLX4_PMD_SOFT_COUNTERS) || !defined(NDEBUG)\n+\t\t\tunsigned int j;\n+#endif\n+\n+\t\t\tassert(wr == bad_wr);\n+\t\t\t/* Clean up TX element without freeing it, caller\n+\t\t\t * should take care of this. */\n+\t\t\tWR_ID(elt->wr.wr_id).offset = 0;\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\t\tfor (j = 0; ((int)j < wr->num_sge); ++j)\n+\t\t\t\ttxq->stats.obytes -= wr->sg_list[j].length;\n+#endif\n+\t\t\t++unsent;\n+#ifndef NDEBUG\n+\t\t\t/* For assert(). */\n+\t\t\tfor (j = 0; ((int)j < wr->num_sge); ++j) {\n+\t\t\t\telt->sges[j].addr = 0;\n+\t\t\t\telt->sges[j].length = 0;\n+\t\t\t\telt->sges[j].lkey = 0;\n+\t\t\t}\n+\t\t\twr->next = NULL;\n+\t\t\twr->num_sge = 0;\n+#endif\n+\t\t\tbad_wr = next;\n+\t\t}\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\ttxq->stats.opackets -= unsent;\n+#endif\n+\t\tassert(i >= unsent);\n+\t\ti -= unsent;\n+\t\t/* \"Unsend\" remaining packets. */\n+\t\telts_head -= unsent;\n+\t\tif (elts_head >= elts_n)\n+\t\t\telts_head += elts_n;\n+\t\tassert(elts_head < elts_n);\n+\t\tDEBUG(\"%p: mlx4_post_send() failed, %u unprocessed WRs: %s\",\n+\t\t (void *)txq, unsent,\n+\t\t ((err <= -1) ? \"Internal error\" : strerror(err)));\n+\t}\n+\telse\n+\t\t++txq->elts_comp;\n+\ttxq->elts_head = elts_head;\n+\treturn i;\n+}\n+\n+/**\n+ * Configure a TX queue.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ * @param desc\n+ * Number of descriptors to configure in queue.\n+ * @param socket\n+ * NUMA socket on which memory must be allocated.\n+ * @param[in] conf\n+ * Thresholds parameters.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+txq_setup(struct rte_eth_dev *dev, struct txq *txq, uint16_t desc,\n+\t unsigned int socket, const struct rte_eth_txconf *conf)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tstruct txq tmpl = {\n+\t\t.priv = priv,\n+\t\t.socket = socket\n+\t};\n+\tunion {\n+\t\tstruct ibv_qp_init_attr init;\n+\t\tstruct ibv_exp_qp_attr mod;\n+\t} attr;\n+\tint ret = 0;\n+\n+\t(void)conf; /* Thresholds configuration (ignored). */\n+\tif ((desc == 0) || (desc % MLX4_PMD_SGE_WR_N)) {\n+\t\tERROR(\"%p: invalid number of TX descriptors (must be a\"\n+\t\t \" multiple of %d)\", (void *)dev, desc);\n+\t\treturn EINVAL;\n+\t}\n+\tdesc /= MLX4_PMD_SGE_WR_N;\n+\t/* MRs will be registered in mp2mr[] later. */\n+\ttmpl.cq = ibv_create_cq(priv->ctx, desc, NULL, NULL, 0);\n+\tif (tmpl.cq == NULL) {\n+\t\tret = ENOMEM;\n+\t\tERROR(\"%p: CQ creation failure: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+\tDEBUG(\"priv->device_attr.max_qp_wr is %d\",\n+\t priv->device_attr.max_qp_wr);\n+\tDEBUG(\"priv->device_attr.max_sge is %d\",\n+\t priv->device_attr.max_sge);\n+\tattr.init = (struct ibv_qp_init_attr){\n+\t\t/* CQ to be associated with the send queue. */\n+\t\t.send_cq = tmpl.cq,\n+\t\t/* CQ to be associated with the receive queue. */\n+\t\t.recv_cq = tmpl.cq,\n+\t\t.cap = {\n+\t\t\t/* Max number of outstanding WRs. */\n+\t\t\t.max_send_wr = ((priv->device_attr.max_qp_wr < desc) ?\n+\t\t\t\t\tpriv->device_attr.max_qp_wr :\n+\t\t\t\t\tdesc),\n+\t\t\t/* Max number of scatter/gather elements in a WR. */\n+\t\t\t.max_send_sge = ((priv->device_attr.max_sge <\n+\t\t\t\t\t MLX4_PMD_SGE_WR_N) ?\n+\t\t\t\t\t priv->device_attr.max_sge :\n+\t\t\t\t\t MLX4_PMD_SGE_WR_N),\n+#if MLX4_PMD_MAX_INLINE > 0\n+\t\t\t.max_inline_data = MLX4_PMD_MAX_INLINE,\n+#endif\n+\t\t},\n+\t\t.qp_type = IBV_QPT_RAW_PACKET,\n+\t\t/* Do *NOT* enable this, completions events are managed per\n+\t\t * TX burst. */\n+\t\t.sq_sig_all = 0\n+\t};\n+\ttmpl.qp = ibv_create_qp(priv->pd, &attr.init);\n+\tif (tmpl.qp == NULL) {\n+\t\tret = (errno ? errno : EINVAL);\n+\t\tERROR(\"%p: QP creation failure: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+#if MLX4_PMD_MAX_INLINE > 0\n+\t/* ibv_create_qp() updates this value. */\n+\ttmpl.max_inline = attr.init.cap.max_inline_data;\n+#endif\n+\tattr.mod = (struct ibv_exp_qp_attr){\n+\t\t/* Move the QP to this state. */\n+\t\t.qp_state = IBV_QPS_INIT,\n+\t\t/* Primary port number. */\n+\t\t.port_num = priv->port\n+\t};\n+\tif ((ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod,\n+\t\t\t\t (IBV_EXP_QP_STATE | IBV_EXP_QP_PORT)))) {\n+\t\tERROR(\"%p: QP state to IBV_QPS_INIT failed: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+\tif ((ret = txq_alloc_elts(&tmpl, desc))) {\n+\t\tERROR(\"%p: TXQ allocation failed: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+\tattr.mod = (struct ibv_exp_qp_attr){\n+\t\t.qp_state = IBV_QPS_RTR\n+\t};\n+\tif ((ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE))) {\n+\t\tERROR(\"%p: QP state to IBV_QPS_RTR failed: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+\tattr.mod.qp_state = IBV_QPS_RTS;\n+\tif ((ret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE))) {\n+\t\tERROR(\"%p: QP state to IBV_QPS_RTS failed: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+\t/* Clean up txq in case we're reinitializing it. */\n+\tDEBUG(\"%p: cleaning-up old txq just in case\", (void *)txq);\n+\ttxq_cleanup(txq);\n+\t*txq = tmpl;\n+\tDEBUG(\"%p: txq updated with %p\", (void *)txq, (void *)&tmpl);\n+\tassert(ret == 0);\n+\treturn 0;\n+error:\n+\ttxq_cleanup(&tmpl);\n+\tassert(ret > 0);\n+\treturn ret;\n+}\n+\n+/**\n+ * DPDK callback to configure a TX queue.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param idx\n+ * TX queue index.\n+ * @param desc\n+ * Number of descriptors to configure in queue.\n+ * @param socket\n+ * NUMA socket on which memory must be allocated.\n+ * @param[in] conf\n+ * Thresholds parameters.\n+ *\n+ * @return\n+ * 0 on success, negative errno value on failure.\n+ */\n+static int\n+mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n+\t\t unsigned int socket, const struct rte_eth_txconf *conf)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tstruct txq *txq = (*priv->txqs)[idx];\n+\tint ret;\n+\n+\tpriv_lock(priv);\n+\tDEBUG(\"%p: configuring queue %u for %u descriptors\",\n+\t (void *)dev, idx, desc);\n+\tif (idx >= priv->txqs_n) {\n+\t\tERROR(\"%p: queue index out of range (%u >= %u)\",\n+\t\t (void *)dev, idx, priv->txqs_n);\n+\t\tpriv_unlock(priv);\n+\t\treturn -EOVERFLOW;\n+\t}\n+\tif (txq != NULL) {\n+\t\tDEBUG(\"%p: reusing already allocated queue index %u (%p)\",\n+\t\t (void *)dev, idx, (void *)txq);\n+\t\tif (priv->started) {\n+\t\t\tpriv_unlock(priv);\n+\t\t\treturn -EEXIST;\n+\t\t}\n+\t\t(*priv->txqs)[idx] = NULL;\n+\t\ttxq_cleanup(txq);\n+\t}\n+\telse {\n+\t\ttxq = rte_calloc_socket(\"TXQ\", 1, sizeof(*txq), 0, socket);\n+\t\tif (txq == NULL) {\n+\t\t\tERROR(\"%p: unable to allocate queue index %u\",\n+\t\t\t (void *)dev, idx);\n+\t\t\tpriv_unlock(priv);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\tret = txq_setup(dev, txq, desc, socket, conf);\n+\tif (ret)\n+\t\trte_free(txq);\n+\telse {\n+\t\ttxq->stats.idx = idx;\n+\t\tDEBUG(\"%p: adding TX queue %p to list\",\n+\t\t (void *)dev, (void *)txq);\n+\t\t(*priv->txqs)[idx] = txq;\n+\t\t/* Update send callback. */\n+\t\tdev->tx_pkt_burst = mlx4_tx_burst;\n+\t}\n+\tpriv_unlock(priv);\n+\treturn -ret;\n+}\n+\n+/**\n+ * DPDK callback to release a TX queue.\n+ *\n+ * @param dpdk_txq\n+ * Generic TX queue pointer.\n+ */\n+static void\n+mlx4_tx_queue_release(void *dpdk_txq)\n+{\n+\tstruct txq *txq = (struct txq *)dpdk_txq;\n+\tstruct priv *priv;\n+\tunsigned int i;\n+\n+\tif (txq == NULL)\n+\t\treturn;\n+\tpriv = txq->priv;\n+\tpriv_lock(priv);\n+\tfor (i = 0; (i != priv->txqs_n); ++i)\n+\t\tif ((*priv->txqs)[i] == txq) {\n+\t\t\tDEBUG(\"%p: removing TX queue %p from list\",\n+\t\t\t (void *)priv->dev, (void *)txq);\n+\t\t\t(*priv->txqs)[i] = NULL;\n+\t\t\tbreak;\n+\t\t}\n+\ttxq_cleanup(txq);\n+\trte_free(txq);\n+\tpriv_unlock(priv);\n+}\n+\n+/* RX queues handling. */\n+\n+/**\n+ * Allocate RX queue elements with scattered packets support.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ * @param elts_n\n+ * Number of elements to allocate.\n+ * @param[in] pool\n+ * If not NULL, fetch buffers from this array instead of allocating them\n+ * with rte_pktmbuf_alloc().\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+rxq_alloc_elts_sp(struct rxq *rxq, unsigned int elts_n,\n+\t\t struct rte_mbuf **pool)\n+{\n+\tunsigned int i;\n+\tstruct rxq_elt_sp (*elts)[elts_n] =\n+\t\trte_calloc_socket(\"RXQ elements\", 1, sizeof(*elts), 0,\n+\t\t\t\t rxq->socket);\n+\tint ret = 0;\n+\n+\tif (elts == NULL) {\n+\t\tERROR(\"%p: can't allocate packets array\", (void *)rxq);\n+\t\tret = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\t/* For each WR (packet). */\n+\tfor (i = 0; (i != elts_n); ++i) {\n+\t\tunsigned int j;\n+\t\tstruct rxq_elt_sp *elt = &(*elts)[i];\n+\t\tstruct ibv_recv_wr *wr = &elt->wr;\n+\t\tstruct ibv_sge (*sges)[(elemof(elt->sges))] = &elt->sges;\n+\n+\t\t/* These two arrays must have the same size. */\n+\t\tassert(elemof(elt->sges) == elemof(elt->bufs));\n+\t\t/* Configure WR. */\n+\t\twr->wr_id = i;\n+\t\twr->next = &(*elts)[(i + 1)].wr;\n+\t\twr->sg_list = &(*sges)[0];\n+\t\twr->num_sge = elemof(*sges);\n+\t\t/* For each SGE (segment). */\n+\t\tfor (j = 0; (j != elemof(elt->bufs)); ++j) {\n+\t\t\tstruct ibv_sge *sge = &(*sges)[j];\n+\t\t\tstruct rte_mbuf *buf;\n+\n+\t\t\tif (pool != NULL) {\n+\t\t\t\tbuf = *(pool++);\n+\t\t\t\tassert(buf != NULL);\n+\t\t\t\trte_pktmbuf_reset(buf);\n+\t\t\t}\n+\t\t\telse\n+\t\t\t\tbuf = rte_pktmbuf_alloc(rxq->mp);\n+\t\t\tif (buf == NULL) {\n+\t\t\t\tassert(pool == NULL);\n+\t\t\t\tERROR(\"%p: empty mbuf pool\", (void *)rxq);\n+\t\t\t\tret = ENOMEM;\n+\t\t\t\tgoto error;\n+\t\t\t}\n+\t\t\telt->bufs[j] = buf;\n+\t\t\t/* Headroom is reserved by rte_pktmbuf_alloc(). */\n+\t\t\tassert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);\n+\t\t\t/* Buffer is supposed to be empty. */\n+\t\t\tassert(rte_pktmbuf_data_len(buf) == 0);\n+\t\t\tassert(rte_pktmbuf_pkt_len(buf) == 0);\n+\t\t\t/* sge->addr must be able to store a pointer. */\n+\t\t\tassert(sizeof(sge->addr) >= sizeof(uintptr_t));\n+\t\t\tif (j == 0) {\n+\t\t\t\t/* The first SGE keeps its headroom. */\n+\t\t\t\tsge->addr = (uintptr_t)rte_pktmbuf_mtod(buf,\n+\t\t\t\t\t\t\t\t\tchar *);\n+\t\t\t\tsge->length = (buf->buf_len -\n+\t\t\t\t\t RTE_PKTMBUF_HEADROOM);\n+\t\t\t}\n+\t\t\telse {\n+\t\t\t\t/* Subsequent SGEs lose theirs. */\n+\t\t\t\tassert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);\n+\t\t\t\tSET_DATA_OFF(buf, 0);\n+\t\t\t\tsge->addr = (uintptr_t)buf->buf_addr;\n+\t\t\t\tsge->length = buf->buf_len;\n+\t\t\t}\n+\t\t\tsge->lkey = rxq->mr->lkey;\n+\t\t\t/* Redundant check for tailroom. */\n+\t\t\tassert(sge->length == rte_pktmbuf_tailroom(buf));\n+\t\t}\n+\t}\n+\t/* The last WR pointer must be NULL. */\n+\t(*elts)[(i - 1)].wr.next = NULL;\n+\tDEBUG(\"%p: allocated and configured %u WRs (%zu segments)\",\n+\t (void *)rxq, elts_n, (elts_n * elemof((*elts)[0].sges)));\n+\trxq->elts_n = elts_n;\n+\trxq->elts.sp = elts;\n+\tassert(ret == 0);\n+\treturn 0;\n+error:\n+\tif (elts != NULL) {\n+\t\tassert(pool == NULL);\n+\t\tfor (i = 0; (i != elemof(*elts)); ++i) {\n+\t\t\tunsigned int j;\n+\t\t\tstruct rxq_elt_sp *elt = &(*elts)[i];\n+\n+\t\t\tfor (j = 0; (j != elemof(elt->bufs)); ++j) {\n+\t\t\t\tstruct rte_mbuf *buf = elt->bufs[j];\n+\n+\t\t\t\tif (buf != NULL)\n+\t\t\t\t\trte_pktmbuf_free_seg(buf);\n+\t\t\t}\n+\t\t}\n+\t\trte_free(elts);\n+\t}\n+\tDEBUG(\"%p: failed, freed everything\", (void *)rxq);\n+\tassert(ret > 0);\n+\treturn ret;\n+}\n+\n+/**\n+ * Free RX queue elements with scattered packets support.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ */\n+static void\n+rxq_free_elts_sp(struct rxq *rxq)\n+{\n+\tunsigned int i;\n+\tunsigned int elts_n = rxq->elts_n;\n+\tstruct rxq_elt_sp (*elts)[elts_n] = rxq->elts.sp;\n+\n+\tDEBUG(\"%p: freeing WRs\", (void *)rxq);\n+\trxq->elts_n = 0;\n+\trxq->elts.sp = NULL;\n+\tif (elts == NULL)\n+\t\treturn;\n+\tfor (i = 0; (i != elemof(*elts)); ++i) {\n+\t\tunsigned int j;\n+\t\tstruct rxq_elt_sp *elt = &(*elts)[i];\n+\n+\t\tfor (j = 0; (j != elemof(elt->bufs)); ++j) {\n+\t\t\tstruct rte_mbuf *buf = elt->bufs[j];\n+\n+\t\t\tif (buf != NULL)\n+\t\t\t\trte_pktmbuf_free_seg(buf);\n+\t\t}\n+\t}\n+\trte_free(elts);\n+}\n+\n+/**\n+ * Allocate RX queue elements.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ * @param elts_n\n+ * Number of elements to allocate.\n+ * @param[in] pool\n+ * If not NULL, fetch buffers from this array instead of allocating them\n+ * with rte_pktmbuf_alloc().\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+rxq_alloc_elts(struct rxq *rxq, unsigned int elts_n, struct rte_mbuf **pool)\n+{\n+\tunsigned int i;\n+\tstruct rxq_elt (*elts)[elts_n] =\n+\t\trte_calloc_socket(\"RXQ elements\", 1, sizeof(*elts), 0,\n+\t\t\t\t rxq->socket);\n+\tint ret = 0;\n+\n+\tif (elts == NULL) {\n+\t\tERROR(\"%p: can't allocate packets array\", (void *)rxq);\n+\t\tret = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\t/* For each WR (packet). */\n+\tfor (i = 0; (i != elts_n); ++i) {\n+\t\tstruct rxq_elt *elt = &(*elts)[i];\n+\t\tstruct ibv_recv_wr *wr = &elt->wr;\n+\t\tstruct ibv_sge *sge = &(*elts)[i].sge;\n+\t\tstruct rte_mbuf *buf;\n+\n+\t\tif (pool != NULL) {\n+\t\t\tbuf = *(pool++);\n+\t\t\tassert(buf != NULL);\n+\t\t\trte_pktmbuf_reset(buf);\n+\t\t}\n+\t\telse\n+\t\t\tbuf = rte_pktmbuf_alloc(rxq->mp);\n+\t\tif (buf == NULL) {\n+\t\t\tassert(pool == NULL);\n+\t\t\tERROR(\"%p: empty mbuf pool\", (void *)rxq);\n+\t\t\tret = ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n+\t\t/* Configure WR. Work request ID contains its own index in\n+\t\t * the elts array and the offset between SGE buffer header and\n+\t\t * its data. */\n+\t\tWR_ID(wr->wr_id).id = i;\n+\t\tWR_ID(wr->wr_id).offset =\n+\t\t\t(((uintptr_t)buf->buf_addr + RTE_PKTMBUF_HEADROOM) -\n+\t\t\t (uintptr_t)buf);\n+\t\twr->next = &(*elts)[(i + 1)].wr;\n+\t\twr->sg_list = sge;\n+\t\twr->num_sge = 1;\n+\t\t/* Headroom is reserved by rte_pktmbuf_alloc(). */\n+\t\tassert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);\n+\t\t/* Buffer is supposed to be empty. */\n+\t\tassert(rte_pktmbuf_data_len(buf) == 0);\n+\t\tassert(rte_pktmbuf_pkt_len(buf) == 0);\n+\t\t/* sge->addr must be able to store a pointer. */\n+\t\tassert(sizeof(sge->addr) >= sizeof(uintptr_t));\n+\t\t/* SGE keeps its headroom. */\n+\t\tsge->addr = (uintptr_t)\n+\t\t\t((uint8_t *)buf->buf_addr + RTE_PKTMBUF_HEADROOM);\n+\t\tsge->length = (buf->buf_len - RTE_PKTMBUF_HEADROOM);\n+\t\tsge->lkey = rxq->mr->lkey;\n+\t\t/* Redundant check for tailroom. */\n+\t\tassert(sge->length == rte_pktmbuf_tailroom(buf));\n+\t\t/* Make sure elts index and SGE mbuf pointer can be deduced\n+\t\t * from WR ID. */\n+\t\tif ((WR_ID(wr->wr_id).id != i) ||\n+\t\t ((void *)(sge->addr - WR_ID(wr->wr_id).offset) != buf)) {\n+\t\t\tERROR(\"%p: cannot store index and offset in WR ID\",\n+\t\t\t (void *)rxq);\n+\t\t\tsge->addr = 0;\n+\t\t\trte_pktmbuf_free(buf);\n+\t\t\tret = EOVERFLOW;\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n+\t/* The last WR pointer must be NULL. */\n+\t(*elts)[(i - 1)].wr.next = NULL;\n+\tDEBUG(\"%p: allocated and configured %u single-segment WRs\",\n+\t (void *)rxq, elts_n);\n+\trxq->elts_n = elts_n;\n+\trxq->elts.no_sp = elts;\n+\tassert(ret == 0);\n+\treturn 0;\n+error:\n+\tif (elts != NULL) {\n+\t\tassert(pool == NULL);\n+\t\tfor (i = 0; (i != elemof(*elts)); ++i) {\n+\t\t\tstruct rxq_elt *elt = &(*elts)[i];\n+\t\t\tstruct rte_mbuf *buf;\n+\n+\t\t\tif (elt->sge.addr == 0)\n+\t\t\t\tcontinue;\n+\t\t\tassert(WR_ID(elt->wr.wr_id).id == i);\n+\t\t\tbuf = (void *)\n+\t\t\t\t(elt->sge.addr - WR_ID(elt->wr.wr_id).offset);\n+\t\t\trte_pktmbuf_free_seg(buf);\n+\t\t}\n+\t\trte_free(elts);\n+\t}\n+\tDEBUG(\"%p: failed, freed everything\", (void *)rxq);\n+\tassert(ret > 0);\n+\treturn ret;\n+}\n+\n+/**\n+ * Free RX queue elements.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ */\n+static void\n+rxq_free_elts(struct rxq *rxq)\n+{\n+\tunsigned int i;\n+\tunsigned int elts_n = rxq->elts_n;\n+\tstruct rxq_elt (*elts)[elts_n] = rxq->elts.no_sp;\n+\n+\tDEBUG(\"%p: freeing WRs\", (void *)rxq);\n+\trxq->elts_n = 0;\n+\trxq->elts.no_sp = NULL;\n+\tif (elts == NULL)\n+\t\treturn;\n+\tfor (i = 0; (i != elemof(*elts)); ++i) {\n+\t\tstruct rxq_elt *elt = &(*elts)[i];\n+\t\tstruct rte_mbuf *buf;\n+\n+\t\tif (elt->sge.addr == 0)\n+\t\t\tcontinue;\n+\t\tassert(WR_ID(elt->wr.wr_id).id == i);\n+\t\tbuf = (void *)(elt->sge.addr - WR_ID(elt->wr.wr_id).offset);\n+\t\trte_pktmbuf_free_seg(buf);\n+\t}\n+\trte_free(elts);\n+}\n+\n+/**\n+ * Unregister a MAC address from a RX queue.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ * @param mac_index\n+ * MAC address index.\n+ */\n+static void\n+rxq_mac_addr_del(struct rxq *rxq, unsigned int mac_index)\n+{\n+#if defined(NDEBUG) || defined(MLX4_COMPAT_VMWARE)\n+\tstruct priv *priv = rxq->priv;\n+\tconst uint8_t (*mac)[ETHER_ADDR_LEN] =\n+\t\t(const uint8_t (*)[ETHER_ADDR_LEN])\n+\t\tpriv->mac[mac_index].addr_bytes;\n+#endif\n+\n+\tassert(mac_index < elemof(priv->mac));\n+\tif (!BITFIELD_ISSET(rxq->mac_configured, mac_index)) {\n+\t\tassert(rxq->mac_flow[mac_index] == NULL);\n+\t\treturn;\n+\t}\n+\tDEBUG(\"%p: removing MAC address %02x:%02x:%02x:%02x:%02x:%02x\"\n+\t \" index %u\",\n+\t (void *)rxq,\n+\t (*mac)[0], (*mac)[1], (*mac)[2], (*mac)[3], (*mac)[4], (*mac)[5],\n+\t mac_index);\n+#ifdef MLX4_COMPAT_VMWARE\n+\tif (priv->vmware) {\n+\t\tunion ibv_gid gid = { .raw = { 0 } };\n+\n+\t\tmemcpy(&gid.raw[10], *mac, sizeof(*mac));\n+\t\tclaim_zero(ibv_detach_mcast(rxq->qp, &gid, 0));\n+\t\tBITFIELD_RESET(rxq->mac_configured, mac_index);\n+\t\treturn;\n+\t}\n+#endif\n+\tassert(rxq->mac_flow[mac_index] != NULL);\n+\tclaim_zero(ibv_exp_destroy_flow(rxq->mac_flow[mac_index]));\n+\trxq->mac_flow[mac_index] = NULL;\n+\tBITFIELD_RESET(rxq->mac_configured, mac_index);\n+}\n+\n+/**\n+ * Unregister all MAC addresses from a RX queue.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ */\n+static void\n+rxq_mac_addrs_del(struct rxq *rxq)\n+{\n+\tstruct priv *priv = rxq->priv;\n+\tunsigned int i;\n+\n+\tfor (i = 0; (i != elemof(priv->mac)); ++i)\n+\t\trxq_mac_addr_del(rxq, i);\n+}\n+\n+static int rxq_promiscuous_enable(struct rxq *);\n+static void rxq_promiscuous_disable(struct rxq *);\n+\n+/**\n+ * Register a MAC address in a RX queue.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ * @param mac_index\n+ * MAC address index to register.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+rxq_mac_addr_add(struct rxq *rxq, unsigned int mac_index)\n+{\n+\tstruct priv *priv = rxq->priv;\n+\tconst uint8_t (*mac)[ETHER_ADDR_LEN] =\n+\t\t(const uint8_t (*)[ETHER_ADDR_LEN])\n+\t\tpriv->mac[mac_index].addr_bytes;\n+\tunsigned int vlans = 0;\n+\tunsigned int specs = 0;\n+\tunsigned int i, j;\n+\tstruct ibv_exp_flow *flow;\n+\n+\tassert(mac_index < elemof(priv->mac));\n+\tif (BITFIELD_ISSET(rxq->mac_configured, mac_index))\n+\t\trxq_mac_addr_del(rxq, mac_index);\n+\t/* Number of configured VLANs. */\n+\tfor (i = 0; (i != elemof(priv->vlan_filter)); ++i)\n+\t\tif (priv->vlan_filter[i].enabled)\n+\t\t\t++vlans;\n+\tspecs = (vlans ? vlans : 1);\n+\n+\t/* Allocate flow specification on the stack. */\n+\tstruct ibv_exp_flow_attr data[1 +\n+\t\t\t\t (sizeof(struct ibv_exp_flow_spec_eth[specs]) /\n+\t\t\t\t sizeof(struct ibv_exp_flow_attr)) +\n+\t\t\t\t !!(sizeof(struct ibv_exp_flow_spec_eth[specs]) %\n+\t\t\t\t sizeof(struct ibv_exp_flow_attr))];\n+\n+\tstruct ibv_exp_flow_attr *attr = (void *)&data[0];\n+\tstruct ibv_exp_flow_spec_eth *spec = (void *)&data[1];\n+\n+\t/*\n+\t * No padding must be inserted by the compiler between attr and spec.\n+\t * This layout is expected by libibverbs.\n+\t */\n+\tassert(((uint8_t *)attr + sizeof(*attr)) == (uint8_t *)spec);\n+\t*attr = (struct ibv_exp_flow_attr){\n+\t\t.type = IBV_EXP_FLOW_ATTR_NORMAL,\n+\t\t.num_of_specs = specs,\n+\t\t.port = priv->port,\n+\t\t.flags = 0\n+\t};\n+\t*spec = (struct ibv_exp_flow_spec_eth){\n+\t\t.type = IBV_EXP_FLOW_SPEC_ETH,\n+\t\t.size = sizeof(*spec),\n+\t\t.val = {\n+\t\t\t.dst_mac = {\n+\t\t\t\t(*mac)[0], (*mac)[1], (*mac)[2],\n+\t\t\t\t(*mac)[3], (*mac)[4], (*mac)[5]\n+\t\t\t}\n+\t\t},\n+\t\t.mask = {\n+\t\t\t.dst_mac = \"\\xff\\xff\\xff\\xff\\xff\\xff\",\n+\t\t\t.vlan_tag = (vlans ? 0xfff : 0)\n+\t\t}\n+\t};\n+\t/* Fill VLAN specifications. */\n+\tfor (i = 0, j = 0; (i != elemof(priv->vlan_filter)); ++i) {\n+\t\tif (!priv->vlan_filter[i].enabled)\n+\t\t\tcontinue;\n+\t\tassert(j != vlans);\n+\t\tif (j)\n+\t\t\tspec[j] = spec[0];\n+\t\tspec[j].val.vlan_tag = priv->vlan_filter[i].id;\n+\t\t++j;\n+\t}\n+\tDEBUG(\"%p: adding MAC address %02x:%02x:%02x:%02x:%02x:%02x index %u\"\n+\t \" (%u VLAN(s) configured)\",\n+\t (void *)rxq,\n+\t (*mac)[0], (*mac)[1], (*mac)[2], (*mac)[3], (*mac)[4], (*mac)[5],\n+\t mac_index,\n+\t vlans);\n+#ifdef MLX4_COMPAT_VMWARE\n+\tif (priv->vmware) {\n+\t\tunion ibv_gid gid = { .raw = { 0 } };\n+\n+\t\t/* Call multicast attach with unicast mac to get traffic. */\n+\t\tmemcpy(&gid.raw[10], *mac, sizeof(*mac));\n+\t\terrno = 0;\n+\t\tif (ibv_attach_mcast(rxq->qp, &gid, 0)) {\n+\t\t\tif (errno)\n+\t\t\t\treturn errno;\n+\t\t\treturn EINVAL;\n+\t\t}\n+\t\tBITFIELD_SET(rxq->mac_configured, mac_index);\n+\t\treturn 0;\n+\t}\n+#endif\n+\t/* Create related flow. */\n+\terrno = 0;\n+\tif ((flow = ibv_exp_create_flow(rxq->qp, attr)) == NULL) {\n+\t\tint err = errno;\n+\t\tint disable = 0;\n+\n+\t\t/* Flow creation failure is not fatal when in DMFS A0 mode.\n+\t\t * Ignore error if promiscuity is already enabled or can be\n+\t\t * enabled. */\n+\t\tif (priv->promisc_ok)\n+\t\t\treturn 0;\n+\t\tif ((rxq->promisc_flow != NULL) ||\n+\t\t (disable = 1, rxq_promiscuous_enable(rxq) == 0)) {\n+\t\t\tif (disable)\n+\t\t\t\trxq_promiscuous_disable(rxq);\n+\t\t\tWARN(\"cannot configure normal flow but promiscuous\"\n+\t\t\t \" mode is fine, assuming promiscuous optimization\"\n+\t\t\t \" is enabled\"\n+\t\t\t \" (options mlx4_core log_num_mgm_entry_size=-7)\");\n+\t\t\tpriv->promisc_ok = 1;\n+\t\t\treturn 0;\n+\t\t}\n+\t\terrno = err;\n+\t\t/* It's not clear whether errno is always set in this case. */\n+\t\tERROR(\"%p: flow configuration failed, errno=%d: %s\",\n+\t\t (void *)rxq, errno,\n+\t\t (errno ? strerror(errno) : \"Unknown error\"));\n+\t\tif (errno)\n+\t\t\treturn errno;\n+\t\treturn EINVAL;\n+\t}\n+\tassert(rxq->mac_flow[mac_index] == NULL);\n+\trxq->mac_flow[mac_index] = flow;\n+\tBITFIELD_SET(rxq->mac_configured, mac_index);\n+\treturn 0;\n+}\n+\n+/**\n+ * Register all MAC addresses in a RX queue.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+rxq_mac_addrs_add(struct rxq *rxq)\n+{\n+\tstruct priv *priv = rxq->priv;\n+\tunsigned int i;\n+\tint ret;\n+\n+\tfor (i = 0; (i != elemof(priv->mac)); ++i) {\n+\t\tif (!BITFIELD_ISSET(priv->mac_configured, i))\n+\t\t\tcontinue;\n+\t\tret = rxq_mac_addr_add(rxq, i);\n+\t\tif (!ret)\n+\t\t\tcontinue;\n+\t\t/* Failure, rollback. */\n+\t\twhile (i != 0)\n+\t\t\trxq_mac_addr_del(rxq, --i);\n+\t\tassert(ret > 0);\n+\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * Unregister a MAC address.\n+ *\n+ * In RSS mode, the MAC address is unregistered from the parent queue,\n+ * otherwise it is unregistered from each queue directly.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ * @param mac_index\n+ * MAC address index.\n+ */\n+static void\n+priv_mac_addr_del(struct priv *priv, unsigned int mac_index)\n+{\n+\tunsigned int i;\n+\n+\tassert(mac_index < elemof(priv->mac));\n+\tif (!BITFIELD_ISSET(priv->mac_configured, mac_index))\n+\t\treturn;\n+\tif (priv->rss) {\n+\t\trxq_mac_addr_del(&priv->rxq_parent, mac_index);\n+\t\tgoto end;\n+\t}\n+\tfor (i = 0; (i != priv->dev->data->nb_rx_queues); ++i)\n+\t\trxq_mac_addr_del((*priv->rxqs)[i], mac_index);\n+end:\n+\tBITFIELD_RESET(priv->mac_configured, mac_index);\n+}\n+\n+/**\n+ * Register a MAC address.\n+ *\n+ * In RSS mode, the MAC address is registered in the parent queue,\n+ * otherwise it is registered in each queue directly.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ * @param mac_index\n+ * MAC address index to use.\n+ * @param mac\n+ * MAC address to register.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+priv_mac_addr_add(struct priv *priv, unsigned int mac_index,\n+\t\t const uint8_t (*mac)[ETHER_ADDR_LEN])\n+{\n+\tunsigned int i;\n+\tint ret;\n+\n+\tassert(mac_index < elemof(priv->mac));\n+\t/* First, make sure this address isn't already configured. */\n+\tfor (i = 0; (i != elemof(priv->mac)); ++i) {\n+\t\t/* Skip this index, it's going to be reconfigured. */\n+\t\tif (i == mac_index)\n+\t\t\tcontinue;\n+\t\tif (!BITFIELD_ISSET(priv->mac_configured, i))\n+\t\t\tcontinue;\n+\t\tif (memcmp(priv->mac[i].addr_bytes, *mac, sizeof(*mac)))\n+\t\t\tcontinue;\n+\t\t/* Address already configured elsewhere, return with error. */\n+\t\treturn EADDRINUSE;\n+\t}\n+\tif (BITFIELD_ISSET(priv->mac_configured, mac_index))\n+\t\tpriv_mac_addr_del(priv, mac_index);\n+\tpriv->mac[mac_index] = (struct ether_addr){\n+\t\t{\n+\t\t\t(*mac)[0], (*mac)[1], (*mac)[2],\n+\t\t\t(*mac)[3], (*mac)[4], (*mac)[5]\n+\t\t}\n+\t};\n+\t/* If device isn't started, this is all we need to do. */\n+\tif (!priv->started) {\n+#ifndef NDEBUG\n+\t\t/* Verify that all queues have this index disabled. */\n+\t\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n+\t\t\tif ((*priv->rxqs)[i] == NULL)\n+\t\t\t\tcontinue;\n+\t\t\tassert(!BITFIELD_ISSET\n+\t\t\t ((*priv->rxqs)[i]->mac_configured, mac_index));\n+\t\t}\n+#endif\n+\t\tgoto end;\n+\t}\n+\tif (priv->rss) {\n+\t\tret = rxq_mac_addr_add(&priv->rxq_parent, mac_index);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tgoto end;\n+\t}\n+\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n+\t\tif ((*priv->rxqs)[i] == NULL)\n+\t\t\tcontinue;\n+\t\tret = rxq_mac_addr_add((*priv->rxqs)[i], mac_index);\n+\t\tif (!ret)\n+\t\t\tcontinue;\n+\t\t/* Failure, rollback. */\n+\t\twhile (i != 0)\n+\t\t\tif ((*priv->rxqs)[(--i)] != NULL)\n+\t\t\t\trxq_mac_addr_del((*priv->rxqs)[i], mac_index);\n+\t\treturn ret;\n+\t}\n+end:\n+\tBITFIELD_SET(priv->mac_configured, mac_index);\n+\treturn 0;\n+}\n+\n+/**\n+ * Enable allmulti mode in a RX queue.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+rxq_allmulticast_enable(struct rxq *rxq)\n+{\n+\tstruct ibv_exp_flow *flow;\n+\tstruct ibv_exp_flow_attr attr = {\n+\t\t.type = IBV_EXP_FLOW_ATTR_MC_DEFAULT,\n+\t\t.num_of_specs = 0,\n+\t\t.port = rxq->priv->port,\n+\t\t.flags = 0\n+\t};\n+\n+#ifdef MLX4_COMPAT_VMWARE\n+\tif (rxq->priv->vmware) {\n+\t\tERROR(\"%p: allmulticast mode is not supported in VMware\",\n+\t\t (void *)rxq);\n+\t\treturn EINVAL;\n+\t}\n+#endif\n+\tDEBUG(\"%p: enabling allmulticast mode\", (void *)rxq);\n+\tif (rxq->allmulti_flow != NULL)\n+\t\treturn EBUSY;\n+\terrno = 0;\n+\tif ((flow = ibv_exp_create_flow(rxq->qp, &attr)) == NULL) {\n+\t\t/* It's not clear whether errno is always set in this case. */\n+\t\tERROR(\"%p: flow configuration failed, errno=%d: %s\",\n+\t\t (void *)rxq, errno,\n+\t\t (errno ? strerror(errno) : \"Unknown error\"));\n+\t\tif (errno)\n+\t\t\treturn errno;\n+\t\treturn EINVAL;\n+\t}\n+\trxq->allmulti_flow = flow;\n+\tDEBUG(\"%p: allmulticast mode enabled\", (void *)rxq);\n+\treturn 0;\n+}\n+\n+/**\n+ * Disable allmulti mode in a RX queue.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ */\n+static void\n+rxq_allmulticast_disable(struct rxq *rxq)\n+{\n+#ifdef MLX4_COMPAT_VMWARE\n+\tif (rxq->priv->vmware) {\n+\t\tERROR(\"%p: allmulticast mode is not supported in VMware\",\n+\t\t (void *)rxq);\n+\t\treturn;\n+\t}\n+#endif\n+\tDEBUG(\"%p: disabling allmulticast mode\", (void *)rxq);\n+\tif (rxq->allmulti_flow == NULL)\n+\t\treturn;\n+\tclaim_zero(ibv_exp_destroy_flow(rxq->allmulti_flow));\n+\trxq->allmulti_flow = NULL;\n+\tDEBUG(\"%p: allmulticast mode disabled\", (void *)rxq);\n+}\n+\n+/**\n+ * Enable promiscuous mode in a RX queue.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+rxq_promiscuous_enable(struct rxq *rxq)\n+{\n+\tstruct ibv_exp_flow *flow;\n+\tstruct ibv_exp_flow_attr attr = {\n+\t\t.type = IBV_EXP_FLOW_ATTR_ALL_DEFAULT,\n+\t\t.num_of_specs = 0,\n+\t\t.port = rxq->priv->port,\n+\t\t.flags = 0\n+\t};\n+\n+#ifdef MLX4_COMPAT_VMWARE\n+\tif (rxq->priv->vmware) {\n+\t\tERROR(\"%p: promiscuous mode is not supported in VMware\",\n+\t\t (void *)rxq);\n+\t\treturn EINVAL;\n+\t}\n+#endif\n+\tif (rxq->priv->vf)\n+\t\treturn 0;\n+\tDEBUG(\"%p: enabling promiscuous mode\", (void *)rxq);\n+\tif (rxq->promisc_flow != NULL)\n+\t\treturn EBUSY;\n+\terrno = 0;\n+\tif ((flow = ibv_exp_create_flow(rxq->qp, &attr)) == NULL) {\n+\t\t/* It's not clear whether errno is always set in this case. */\n+\t\tERROR(\"%p: flow configuration failed, errno=%d: %s\",\n+\t\t (void *)rxq, errno,\n+\t\t (errno ? strerror(errno) : \"Unknown error\"));\n+\t\tif (errno)\n+\t\t\treturn errno;\n+\t\treturn EINVAL;\n+\t}\n+\trxq->promisc_flow = flow;\n+\tDEBUG(\"%p: promiscuous mode enabled\", (void *)rxq);\n+\treturn 0;\n+}\n+\n+/**\n+ * Disable promiscuous mode in a RX queue.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ */\n+static void\n+rxq_promiscuous_disable(struct rxq *rxq)\n+{\n+#ifdef MLX4_COMPAT_VMWARE\n+\tif (rxq->priv->vmware) {\n+\t\tERROR(\"%p: promiscuous mode is not supported in VMware\",\n+\t\t (void *)rxq);\n+\t\treturn;\n+\t}\n+#endif\n+\tif (rxq->priv->vf)\n+\t\treturn;\n+\tDEBUG(\"%p: disabling promiscuous mode\", (void *)rxq);\n+\tif (rxq->promisc_flow == NULL)\n+\t\treturn;\n+\tclaim_zero(ibv_exp_destroy_flow(rxq->promisc_flow));\n+\trxq->promisc_flow = NULL;\n+\tDEBUG(\"%p: promiscuous mode disabled\", (void *)rxq);\n+}\n+\n+/**\n+ * Clean up a RX queue.\n+ *\n+ * Destroy objects, free allocated memory and reset the structure for reuse.\n+ *\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ */\n+static void\n+rxq_cleanup(struct rxq *rxq)\n+{\n+\tDEBUG(\"cleaning up %p\", (void *)rxq);\n+\tif (rxq->sp)\n+\t\trxq_free_elts_sp(rxq);\n+\telse\n+\t\trxq_free_elts(rxq);\n+\tif (rxq->qp != NULL) {\n+\t\trxq_promiscuous_disable(rxq);\n+\t\trxq_allmulticast_disable(rxq);\n+\t\trxq_mac_addrs_del(rxq);\n+\t\tclaim_zero(ibv_destroy_qp(rxq->qp));\n+\t}\n+\tif (rxq->cq != NULL)\n+\t\tclaim_zero(ibv_destroy_cq(rxq->cq));\n+\tif (rxq->mr != NULL)\n+\t\tclaim_zero(ibv_dereg_mr(rxq->mr));\n+\tmemset(rxq, 0, sizeof(*rxq));\n+}\n+\n+static uint16_t\n+mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);\n+\n+/**\n+ * DPDK callback for RX with scattered packets support.\n+ *\n+ * @param dpdk_rxq\n+ * Generic pointer to RX queue structure.\n+ * @param[out] pkts\n+ * Array to store received packets.\n+ * @param pkts_n\n+ * Maximum number of packets in array.\n+ *\n+ * @return\n+ * Number of packets successfully received (<= pkts_n).\n+ */\n+static uint16_t\n+mlx4_rx_burst_sp(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n+{\n+\tstruct rxq *rxq = (struct rxq *)dpdk_rxq;\n+\tstruct rxq_elt_sp (*elts)[rxq->elts_n] = rxq->elts.sp;\n+\tstruct ibv_wc wcs[pkts_n];\n+\tstruct ibv_recv_wr head;\n+\tstruct ibv_recv_wr **next = &head.next;\n+\tstruct ibv_recv_wr *bad_wr;\n+\tint ret = 0;\n+\tint wcs_n;\n+\tint i;\n+\n+\tif (unlikely(!rxq->sp))\n+\t\treturn mlx4_rx_burst(dpdk_rxq, pkts, pkts_n);\n+\tif (unlikely(elts == NULL)) /* See RTE_DEV_CMD_SET_MTU. */\n+\t\treturn 0;\n+\twcs_n = ibv_poll_cq(rxq->cq, pkts_n, wcs);\n+\tif (unlikely(wcs_n == 0))\n+\t\treturn 0;\n+\tif (unlikely(wcs_n < 0)) {\n+\t\tDEBUG(\"rxq=%p, ibv_poll_cq() failed (wc_n=%d)\",\n+\t\t (void *)rxq, wcs_n);\n+\t\treturn 0;\n+\t}\n+\tassert(wcs_n <= (int)pkts_n);\n+\t/* For each work completion. */\n+\tfor (i = 0; (i != wcs_n); ++i) {\n+\t\tstruct ibv_wc *wc = &wcs[i];\n+\t\tuint64_t wr_id = wc->wr_id;\n+\t\tuint32_t len = wc->byte_len;\n+\t\tstruct rxq_elt_sp *elt = &(*elts)[wr_id];\n+\t\tstruct ibv_recv_wr *wr = &elt->wr;\n+\t\tstruct rte_mbuf *pkt_buf = NULL; /* Buffer returned in pkts. */\n+\t\tstruct rte_mbuf **pkt_buf_next = &pkt_buf;\n+\t\tunsigned int seg_headroom = RTE_PKTMBUF_HEADROOM;\n+\t\tunsigned int j = 0;\n+\n+\t\t/* Sanity checks. */\n+\t\tassert(wr_id < rxq->elts_n);\n+\t\tassert(wr_id == wr->wr_id);\n+\t\tassert(wr->sg_list == elt->sges);\n+\t\tassert(wr->num_sge == elemof(elt->sges));\n+\t\t/* Link completed WRs together for repost. */\n+\t\t*next = wr;\n+\t\tnext = &wr->next;\n+\t\tif (unlikely(wc->status != IBV_WC_SUCCESS)) {\n+\t\t\t/* Whatever, just repost the offending WR. */\n+\t\t\tDEBUG(\"rxq=%p, wr_id=%\" PRIu64 \": bad work completion\"\n+\t\t\t \" status (%d): %s\",\n+\t\t\t (void *)rxq, wc->wr_id, wc->status,\n+\t\t\t ibv_wc_status_str(wc->status));\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\t\t/* Increase dropped packets counter. */\n+\t\t\t++rxq->stats.idropped;\n+#endif\n+\t\t\tgoto repost;\n+\t\t}\n+\t\t/*\n+\t\t * Replace spent segments with new ones, concatenate and\n+\t\t * return them as pkt_buf.\n+\t\t */\n+\t\twhile (1) {\n+\t\t\tstruct ibv_sge *sge = &elt->sges[j];\n+\t\t\tstruct rte_mbuf *seg = elt->bufs[j];\n+\t\t\tstruct rte_mbuf *rep;\n+\t\t\tunsigned int seg_tailroom;\n+\n+\t\t\t/*\n+\t\t\t * Fetch initial bytes of packet descriptor into a\n+\t\t\t * cacheline while allocating rep.\n+\t\t\t */\n+\t\t\trte_prefetch0(seg);\n+\t\t\trep = __rte_mbuf_raw_alloc(rxq->mp);\n+\t\t\tif (unlikely(rep == NULL)) {\n+\t\t\t\t/*\n+\t\t\t\t * Unable to allocate a replacement mbuf,\n+\t\t\t\t * repost WR.\n+\t\t\t\t */\n+\t\t\t\tDEBUG(\"rxq=%p, wr_id=%\" PRIu64 \":\"\n+\t\t\t\t \" can't allocate a new mbuf\",\n+\t\t\t\t (void *)rxq, wr_id);\n+\t\t\t\tif (pkt_buf != NULL)\n+\t\t\t\t\trte_pktmbuf_free(pkt_buf);\n+\t\t\t\t/* Increase out of memory counters. */\n+\t\t\t\t++rxq->stats.rx_nombuf;\n+\t\t\t\t++rxq->priv->dev->data->rx_mbuf_alloc_failed;\n+\t\t\t\tgoto repost;\n+\t\t\t}\n+#ifndef NDEBUG\n+\t\t\t/* Poison user-modifiable fields in rep. */\n+\t\t\tNEXT(rep) = (void *)((uintptr_t)-1);\n+\t\t\tSET_DATA_OFF(rep, 0xdead);\n+\t\t\tDATA_LEN(rep) = 0xd00d;\n+\t\t\tPKT_LEN(rep) = 0xdeadd00d;\n+\t\t\tNB_SEGS(rep) = 0x2a;\n+\t\t\tPORT(rep) = 0x2a;\n+\t\t\trep->ol_flags = -1;\n+#endif\n+\t\t\tassert(rep->buf_len == seg->buf_len);\n+\t\t\tassert(rep->buf_len == rxq->mb_len);\n+\t\t\t/* Reconfigure sge to use rep instead of seg. */\n+\t\t\tassert(sge->lkey == rxq->mr->lkey);\n+\t\t\tsge->addr = ((uintptr_t)rep->buf_addr + seg_headroom);\n+\t\t\telt->bufs[j] = rep;\n+\t\t\t++j;\n+\t\t\t/* Update pkt_buf if it's the first segment, or link\n+\t\t\t * seg to the previous one and update pkt_buf_next. */\n+\t\t\t*pkt_buf_next = seg;\n+\t\t\tpkt_buf_next = &NEXT(seg);\n+\t\t\t/* Update seg information. */\n+\t\t\tseg_tailroom = (seg->buf_len - seg_headroom);\n+\t\t\tassert(sge->length == seg_tailroom);\n+\t\t\tSET_DATA_OFF(seg, seg_headroom);\n+\t\t\tif (likely(len <= seg_tailroom)) {\n+\t\t\t\t/* Last segment. */\n+\t\t\t\tDATA_LEN(seg) = len;\n+\t\t\t\tPKT_LEN(seg) = len;\n+\t\t\t\t/* Sanity check. */\n+\t\t\t\tassert(rte_pktmbuf_headroom(seg) ==\n+\t\t\t\t seg_headroom);\n+\t\t\t\tassert(rte_pktmbuf_tailroom(seg) ==\n+\t\t\t\t (seg_tailroom - len));\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tDATA_LEN(seg) = seg_tailroom;\n+\t\t\tPKT_LEN(seg) = seg_tailroom;\n+\t\t\t/* Sanity check. */\n+\t\t\tassert(rte_pktmbuf_headroom(seg) == seg_headroom);\n+\t\t\tassert(rte_pktmbuf_tailroom(seg) == 0);\n+\t\t\t/* Fix len and clear headroom for next segments. */\n+\t\t\tlen -= seg_tailroom;\n+\t\t\tseg_headroom = 0;\n+\t\t}\n+\t\t/* Update head and tail segments. */\n+\t\t*pkt_buf_next = NULL;\n+\t\tassert(pkt_buf != NULL);\n+\t\tassert(j != 0);\n+\t\tNB_SEGS(pkt_buf) = j;\n+\t\tPORT(pkt_buf) = rxq->port_id;\n+\t\tPKT_LEN(pkt_buf) = wc->byte_len;\n+\t\tpkt_buf->ol_flags = 0;\n+\n+\t\t/* Return packet. */\n+\t\t*(pkts++) = pkt_buf;\n+\t\t++ret;\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\t/* Increase bytes counter. */\n+\t\trxq->stats.ibytes += wc->byte_len;\n+#endif\n+\trepost:\n+\t\tcontinue;\n+\t}\n+\t*next = NULL;\n+\t/* Repost WRs. */\n+#ifdef DEBUG_RECV\n+\tDEBUG(\"%p: reposting %d WRs starting from %\" PRIu64 \" (%p)\",\n+\t (void *)rxq, wcs_n, wcs[0].wr_id, (void *)head.next);\n+#endif\n+\ti = ibv_post_recv(rxq->qp, head.next, &bad_wr);\n+\tif (unlikely(i)) {\n+\t\t/* Inability to repost WRs is fatal. */\n+\t\tDEBUG(\"%p: ibv_post_recv(): failed for WR %p: %s\",\n+\t\t (void *)rxq->priv,\n+\t\t (void *)bad_wr,\n+\t\t strerror(i));\n+\t\tabort();\n+\t}\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t/* Increase packets counter. */\n+\trxq->stats.ipackets += ret;\n+#endif\n+\treturn ret;\n+}\n+\n+/**\n+ * DPDK callback for RX.\n+ *\n+ * The following function is the same as mlx4_rx_burst_sp(), except it doesn't\n+ * manage scattered packets. Improves performance when MRU is lower than the\n+ * size of the first segment.\n+ *\n+ * @param dpdk_rxq\n+ * Generic pointer to RX queue structure.\n+ * @param[out] pkts\n+ * Array to store received packets.\n+ * @param pkts_n\n+ * Maximum number of packets in array.\n+ *\n+ * @return\n+ * Number of packets successfully received (<= pkts_n).\n+ */\n+static uint16_t\n+mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n+{\n+\tstruct rxq *rxq = (struct rxq *)dpdk_rxq;\n+\tstruct rxq_elt (*elts)[rxq->elts_n] = rxq->elts.no_sp;\n+\tstruct ibv_wc wcs[pkts_n];\n+\tstruct ibv_recv_wr head;\n+\tstruct ibv_recv_wr **next = &head.next;\n+\tstruct ibv_recv_wr *bad_wr;\n+\tint ret = 0;\n+\tint wcs_n;\n+\tint i;\n+\n+\tif (unlikely(rxq->sp))\n+\t\treturn mlx4_rx_burst_sp(dpdk_rxq, pkts, pkts_n);\n+\twcs_n = ibv_poll_cq(rxq->cq, pkts_n, wcs);\n+\tif (unlikely(wcs_n == 0))\n+\t\treturn 0;\n+\tif (unlikely(wcs_n < 0)) {\n+\t\tDEBUG(\"rxq=%p, ibv_poll_cq() failed (wc_n=%d)\",\n+\t\t (void *)rxq, wcs_n);\n+\t\treturn 0;\n+\t}\n+\tassert(wcs_n <= (int)pkts_n);\n+\t/* For each work completion. */\n+\tfor (i = 0; (i != wcs_n); ++i) {\n+\t\tstruct ibv_wc *wc = &wcs[i];\n+\t\tuint64_t wr_id = wc->wr_id;\n+\t\tuint32_t len = wc->byte_len;\n+\t\tstruct rxq_elt *elt = &(*elts)[WR_ID(wr_id).id];\n+\t\tstruct ibv_recv_wr *wr = &elt->wr;\n+\t\tstruct rte_mbuf *seg =\n+\t\t\t(void *)(elt->sge.addr - WR_ID(wr_id).offset);\n+\t\tstruct rte_mbuf *rep;\n+\n+\t\t/* Sanity checks. */\n+\t\tassert(WR_ID(wr_id).id < rxq->elts_n);\n+\t\tassert(wr_id == wr->wr_id);\n+\t\tassert(wr->sg_list == &elt->sge);\n+\t\tassert(wr->num_sge == 1);\n+\t\t/* Link completed WRs together for repost. */\n+\t\t*next = wr;\n+\t\tnext = &wr->next;\n+\t\tif (unlikely(wc->status != IBV_WC_SUCCESS)) {\n+\t\t\t/* Whatever, just repost the offending WR. */\n+\t\t\tDEBUG(\"rxq=%p, wr_id=%\" PRIu32 \": bad work completion\"\n+\t\t\t \" status (%d): %s\",\n+\t\t\t (void *)rxq, WR_ID(wr_id).id, wc->status,\n+\t\t\t ibv_wc_status_str(wc->status));\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\t\t/* Increase dropped packets counter. */\n+\t\t\t++rxq->stats.idropped;\n+#endif\n+\t\t\tgoto repost;\n+\t\t}\n+\t\t/*\n+\t\t * Fetch initial bytes of packet descriptor into a\n+\t\t * cacheline while allocating rep.\n+\t\t */\n+\t\trte_prefetch0(seg);\n+\t\trep = __rte_mbuf_raw_alloc(rxq->mp);\n+\t\tif (unlikely(rep == NULL)) {\n+\t\t\t/*\n+\t\t\t * Unable to allocate a replacement mbuf,\n+\t\t\t * repost WR.\n+\t\t\t */\n+\t\t\tDEBUG(\"rxq=%p, wr_id=%\" PRIu32 \":\"\n+\t\t\t \" can't allocate a new mbuf\",\n+\t\t\t (void *)rxq, WR_ID(wr_id).id);\n+\t\t\t/* Increase out of memory counters. */\n+\t\t\t++rxq->stats.rx_nombuf;\n+\t\t\t++rxq->priv->dev->data->rx_mbuf_alloc_failed;\n+\t\t\tgoto repost;\n+\t\t}\n+\n+\t\t/* Reconfigure sge to use rep instead of seg. */\n+\t\telt->sge.addr = (uintptr_t)rep->buf_addr + RTE_PKTMBUF_HEADROOM;\n+\t\tassert(elt->sge.lkey == rxq->mr->lkey);\n+\t\tWR_ID(wr->wr_id).offset =\n+\t\t\t(((uintptr_t)rep->buf_addr + RTE_PKTMBUF_HEADROOM) -\n+\t\t\t (uintptr_t)rep);\n+\t\tassert(WR_ID(wr->wr_id).id == WR_ID(wr_id).id);\n+\n+\t\t/* Update seg information. */\n+\t\tSET_DATA_OFF(seg, RTE_PKTMBUF_HEADROOM);\n+\t\tNB_SEGS(seg) = 1;\n+\t\tPORT(seg) = rxq->port_id;\n+\t\tNEXT(seg) = NULL;\n+\t\tPKT_LEN(seg) = len;\n+\t\tDATA_LEN(seg) = len;\n+\t\tseg->ol_flags = 0;\n+\n+\t\t/* Return packet. */\n+\t\t*(pkts++) = seg;\n+\t\t++ret;\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\t/* Increase bytes counter. */\n+\t\trxq->stats.ibytes += wc->byte_len;\n+#endif\n+\trepost:\n+\t\tcontinue;\n+\t}\n+\t*next = NULL;\n+\t/* Repost WRs. */\n+#ifdef DEBUG_RECV\n+\tDEBUG(\"%p: reposting %d WRs starting from %\" PRIu32 \" (%p)\",\n+\t (void *)rxq, wcs_n, WR_ID(wcs[0].wr_id).id, (void *)head.next);\n+#endif\n+\ti = ibv_post_recv(rxq->qp, head.next, &bad_wr);\n+\tif (unlikely(i)) {\n+\t\t/* Inability to repost WRs is fatal. */\n+\t\tDEBUG(\"%p: ibv_post_recv(): failed for WR %p: %s\",\n+\t\t (void *)rxq->priv,\n+\t\t (void *)bad_wr,\n+\t\t strerror(i));\n+\t\tabort();\n+\t}\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t/* Increase packets counter. */\n+\trxq->stats.ipackets += ret;\n+#endif\n+\treturn ret;\n+}\n+\n+#ifdef INLINE_RECV\n+\n+/**\n+ * Allocate a Queue Pair in case inline receive is supported.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ * @param cq\n+ * Completion queue to associate with QP.\n+ * @param desc\n+ * Number of descriptors in QP (hint only).\n+ *\n+ * @return\n+ * QP pointer or NULL in case of error.\n+ */\n+static struct ibv_qp *\n+rxq_setup_qp(struct priv *priv, struct ibv_cq *cq, uint16_t desc)\n+{\n+\tstruct ibv_exp_qp_init_attr attr = {\n+\t\t/* CQ to be associated with the send queue. */\n+\t\t.send_cq = cq,\n+\t\t/* CQ to be associated with the receive queue. */\n+\t\t.recv_cq = cq,\n+\t\t.max_inl_recv = priv->inl_recv_size,\n+\t\t.cap = {\n+\t\t\t/* Max number of outstanding WRs. */\n+\t\t\t.max_recv_wr = ((priv->device_attr.max_qp_wr < desc) ?\n+\t\t\t\t\tpriv->device_attr.max_qp_wr :\n+\t\t\t\t\tdesc),\n+\t\t\t/* Max number of scatter/gather elements in a WR. */\n+\t\t\t.max_recv_sge = ((priv->device_attr.max_sge <\n+\t\t\t\t\t MLX4_PMD_SGE_WR_N) ?\n+\t\t\t\t\t priv->device_attr.max_sge :\n+\t\t\t\t\t MLX4_PMD_SGE_WR_N),\n+\t\t},\n+\t\t.qp_type = IBV_QPT_RAW_PACKET,\n+\t\t.pd = priv->pd\n+\t};\n+\n+\tattr.comp_mask = IBV_EXP_QP_INIT_ATTR_PD;\n+\tattr.comp_mask |= IBV_EXP_QP_INIT_ATTR_INL_RECV;\n+\n+\treturn ibv_exp_create_qp(priv->ctx, &attr);\n+}\n+\n+#else /* INLINE_RECV */\n+\n+/**\n+ * Allocate a Queue Pair.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ * @param cq\n+ * Completion queue to associate with QP.\n+ * @param desc\n+ * Number of descriptors in QP (hint only).\n+ *\n+ * @return\n+ * QP pointer or NULL in case of error.\n+ */\n+static struct ibv_qp *\n+rxq_setup_qp(struct priv *priv, struct ibv_cq *cq, uint16_t desc)\n+{\n+\tstruct ibv_qp_init_attr attr = {\n+\t\t/* CQ to be associated with the send queue. */\n+\t\t.send_cq = cq,\n+\t\t/* CQ to be associated with the receive queue. */\n+\t\t.recv_cq = cq,\n+\t\t.cap = {\n+\t\t\t/* Max number of outstanding WRs. */\n+\t\t\t.max_recv_wr = ((priv->device_attr.max_qp_wr < desc) ?\n+\t\t\t\t\tpriv->device_attr.max_qp_wr :\n+\t\t\t\t\tdesc),\n+\t\t\t/* Max number of scatter/gather elements in a WR. */\n+\t\t\t.max_recv_sge = ((priv->device_attr.max_sge <\n+\t\t\t\t\t MLX4_PMD_SGE_WR_N) ?\n+\t\t\t\t\t priv->device_attr.max_sge :\n+\t\t\t\t\t MLX4_PMD_SGE_WR_N),\n+\t\t},\n+\t\t.qp_type = IBV_QPT_RAW_PACKET\n+\t};\n+\n+\treturn ibv_create_qp(priv->pd, &attr);\n+}\n+\n+#endif /* INLINE_RECV */\n+\n+#ifdef RSS_SUPPORT\n+\n+/**\n+ * Allocate a RSS Queue Pair.\n+ *\n+ * @param priv\n+ * Pointer to private structure.\n+ * @param cq\n+ * Completion queue to associate with QP.\n+ * @param desc\n+ * Number of descriptors in QP (hint only).\n+ * @param parent\n+ * If nonzero, create a parent QP, otherwise a child.\n+ *\n+ * @return\n+ * QP pointer or NULL in case of error.\n+ */\n+static struct ibv_qp *\n+rxq_setup_qp_rss(struct priv *priv, struct ibv_cq *cq, uint16_t desc,\n+\t\t int parent)\n+{\n+\tstruct ibv_exp_qp_init_attr attr = {\n+\t\t/* CQ to be associated with the send queue. */\n+\t\t.send_cq = cq,\n+\t\t/* CQ to be associated with the receive queue. */\n+\t\t.recv_cq = cq,\n+#ifdef INLINE_RECV\n+\t\t.max_inl_recv = priv->inl_recv_size,\n+#endif\n+\t\t.cap = {\n+\t\t\t/* Max number of outstanding WRs. */\n+\t\t\t.max_recv_wr = ((priv->device_attr.max_qp_wr < desc) ?\n+\t\t\t\t\tpriv->device_attr.max_qp_wr :\n+\t\t\t\t\tdesc),\n+\t\t\t/* Max number of scatter/gather elements in a WR. */\n+\t\t\t.max_recv_sge = ((priv->device_attr.max_sge <\n+\t\t\t\t\t MLX4_PMD_SGE_WR_N) ?\n+\t\t\t\t\t priv->device_attr.max_sge :\n+\t\t\t\t\t MLX4_PMD_SGE_WR_N),\n+\t\t},\n+\t\t.qp_type = IBV_QPT_RAW_PACKET,\n+\t\t.comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |\n+\t\t\t IBV_EXP_QP_INIT_ATTR_QPG),\n+\t\t.pd = priv->pd\n+\t};\n+\n+#ifdef INLINE_RECV\n+\tattr.comp_mask |= IBV_EXP_QP_INIT_ATTR_INL_RECV;\n+#endif\n+\tif (parent) {\n+\t\tattr.qpg.qpg_type = IBV_EXP_QPG_PARENT;\n+\t\t/* TSS isn't necessary. */\n+\t\tattr.qpg.parent_attrib.tss_child_count = 0;\n+\t\tattr.qpg.parent_attrib.rss_child_count = priv->rxqs_n;\n+\t\tDEBUG(\"initializing parent RSS queue\");\n+\t}\n+\telse {\n+\t\tattr.qpg.qpg_type = IBV_EXP_QPG_CHILD_RX;\n+\t\tattr.qpg.qpg_parent = priv->rxq_parent.qp;\n+\t\tDEBUG(\"initializing child RSS queue\");\n+\t}\n+\treturn ibv_exp_create_qp(priv->ctx, &attr);\n+}\n+\n+#endif /* RSS_SUPPORT */\n+\n+/**\n+ * Reconfigure a RX queue with new parameters.\n+ *\n+ * rxq_rehash() does not allocate mbufs, which, if not done from the right\n+ * thread (such as a control thread), may corrupt the pool.\n+ * In case of failure, the queue is left untouched.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param rxq\n+ * RX queue pointer.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+rxq_rehash(struct rte_eth_dev *dev, struct rxq *rxq)\n+{\n+\tstruct priv *priv = rxq->priv;\n+\tstruct rxq tmpl = *rxq;\n+\tunsigned int mbuf_n;\n+\tunsigned int desc_n;\n+\tstruct rte_mbuf **pool;\n+\tunsigned int i, k;\n+\tstruct ibv_exp_qp_attr mod;\n+\tstruct ibv_recv_wr *bad_wr;\n+\tint err;\n+\tint parent = (rxq == &priv->rxq_parent);\n+\n+\tif (parent) {\n+\t\tERROR(\"%p: cannot rehash parent queue %p\",\n+\t\t (void *)dev, (void *)rxq);\n+\t\treturn EINVAL;\n+\t}\n+\tDEBUG(\"%p: rehashing queue %p\", (void *)dev, (void *)rxq);\n+\t/* Number of descriptors and mbufs currently allocated. */\n+\tdesc_n = (tmpl.elts_n * (tmpl.sp ? MLX4_PMD_SGE_WR_N : 1));\n+\tmbuf_n = desc_n;\n+\t/* Enable scattered packets support for this queue if necessary. */\n+\tif ((dev->data->dev_conf.rxmode.jumbo_frame) &&\n+\t (dev->data->dev_conf.rxmode.max_rx_pkt_len >\n+\t (tmpl.mb_len - RTE_PKTMBUF_HEADROOM))) {\n+\t\ttmpl.sp = 1;\n+\t\tdesc_n /= MLX4_PMD_SGE_WR_N;\n+\t}\n+\telse\n+\t\ttmpl.sp = 0;\n+\tDEBUG(\"%p: %s scattered packets support (%u WRs)\",\n+\t (void *)dev, (tmpl.sp ? \"enabling\" : \"disabling\"), desc_n);\n+\t/* If scatter mode is the same as before, nothing to do. */\n+\tif (tmpl.sp == rxq->sp) {\n+\t\tDEBUG(\"%p: nothing to do\", (void *)dev);\n+\t\treturn 0;\n+\t}\n+\t/* Remove attached flows if RSS is disabled (no parent queue). */\n+\tif (!priv->rss) {\n+\t\trxq_allmulticast_disable(&tmpl);\n+\t\trxq_promiscuous_disable(&tmpl);\n+\t\trxq_mac_addrs_del(&tmpl);\n+\t\t/* Update original queue in case of failure. */\n+\t\trxq->allmulti_flow = tmpl.allmulti_flow;\n+\t\trxq->promisc_flow = tmpl.promisc_flow;\n+\t\tmemcpy(rxq->mac_configured, tmpl.mac_configured,\n+\t\t sizeof(rxq->mac_configured));\n+\t\tmemcpy(rxq->mac_flow, tmpl.mac_flow, sizeof(rxq->mac_flow));\n+\t}\n+\t/* From now on, any failure will render the queue unusable.\n+\t * Reinitialize QP. */\n+\tmod = (struct ibv_exp_qp_attr){ .qp_state = IBV_QPS_RESET };\n+\tif ((err = ibv_exp_modify_qp(tmpl.qp, &mod, IBV_EXP_QP_STATE))) {\n+\t\tERROR(\"%p: cannot reset QP: %s\", (void *)dev, strerror(err));\n+\t\tassert(err > 0);\n+\t\treturn err;\n+\t}\n+\tif ((err = ibv_resize_cq(tmpl.cq, desc_n))) {\n+\t\tERROR(\"%p: cannot resize CQ: %s\", (void *)dev, strerror(err));\n+\t\tassert(err > 0);\n+\t\treturn err;\n+\t}\n+\tmod = (struct ibv_exp_qp_attr){\n+\t\t/* Move the QP to this state. */\n+\t\t.qp_state = IBV_QPS_INIT,\n+\t\t/* Primary port number. */\n+\t\t.port_num = priv->port\n+\t};\n+\tif ((err = ibv_exp_modify_qp(tmpl.qp, &mod,\n+\t\t\t\t (IBV_EXP_QP_STATE |\n+#ifdef RSS_SUPPORT\n+\t\t\t\t (parent ? IBV_EXP_QP_GROUP_RSS : 0) |\n+#endif /* RSS_SUPPORT */\n+\t\t\t\t IBV_EXP_QP_PORT)))) {\n+\t\tERROR(\"%p: QP state to IBV_QPS_INIT failed: %s\",\n+\t\t (void *)dev, strerror(err));\n+\t\tassert(err > 0);\n+\t\treturn err;\n+\t};\n+\t/* Reconfigure flows. Do not care for errors. */\n+\tif (!priv->rss) {\n+\t\trxq_mac_addrs_add(&tmpl);\n+\t\tif (priv->promisc)\n+\t\t\trxq_promiscuous_enable(&tmpl);\n+\t\tif (priv->allmulti)\n+\t\t\trxq_allmulticast_enable(&tmpl);\n+\t\t/* Update original queue in case of failure. */\n+\t\trxq->allmulti_flow = tmpl.allmulti_flow;\n+\t\trxq->promisc_flow = tmpl.promisc_flow;\n+\t\tmemcpy(rxq->mac_configured, tmpl.mac_configured,\n+\t\t sizeof(rxq->mac_configured));\n+\t\tmemcpy(rxq->mac_flow, tmpl.mac_flow, sizeof(rxq->mac_flow));\n+\t}\n+\t/* Allocate pool. */\n+\tpool = rte_malloc(__func__, (mbuf_n * sizeof(*pool)), 0);\n+\tif (pool == NULL) {\n+\t\tERROR(\"%p: cannot allocate memory\", (void *)dev);\n+\t\treturn ENOBUFS;\n+\t}\n+\t/* Snatch mbufs from original queue. */\n+\tk = 0;\n+\tif (rxq->sp) {\n+\t\tstruct rxq_elt_sp (*elts)[rxq->elts_n] = rxq->elts.sp;\n+\n+\t\tfor (i = 0; (i != elemof(*elts)); ++i) {\n+\t\t\tstruct rxq_elt_sp *elt = &(*elts)[i];\n+\t\t\tunsigned int j;\n+\n+\t\t\tfor (j = 0; (j != elemof(elt->bufs)); ++j) {\n+\t\t\t\tassert(elt->bufs[j] != NULL);\n+\t\t\t\tpool[k++] = elt->bufs[j];\n+\t\t\t}\n+\t\t}\n+\t}\n+\telse {\n+\t\tstruct rxq_elt (*elts)[rxq->elts_n] = rxq->elts.no_sp;\n+\n+\t\tfor (i = 0; (i != elemof(*elts)); ++i) {\n+\t\t\tstruct rxq_elt *elt = &(*elts)[i];\n+\t\t\tstruct rte_mbuf *buf = (void *)\n+\t\t\t\t(elt->sge.addr - WR_ID(elt->wr.wr_id).offset);\n+\n+\t\t\tassert(WR_ID(elt->wr.wr_id).id == i);\n+\t\t\tpool[k++] = buf;\n+\t\t}\n+ }\n+\tassert(k == mbuf_n);\n+\ttmpl.elts_n = 0;\n+\ttmpl.elts.sp = NULL;\n+\tassert((void *)&tmpl.elts.sp == (void *)&tmpl.elts.no_sp);\n+\terr = ((tmpl.sp) ?\n+\t rxq_alloc_elts_sp(&tmpl, desc_n, pool) :\n+\t rxq_alloc_elts(&tmpl, desc_n, pool));\n+\tif (err) {\n+\t\tERROR(\"%p: cannot reallocate WRs, aborting\", (void *)dev);\n+\t\trte_free(pool);\n+\t\tassert(err > 0);\n+\t\treturn err;\n+\t}\n+\tassert(tmpl.elts_n == desc_n);\n+\tassert(tmpl.elts.sp != NULL);\n+\trte_free(pool);\n+\t/* Clean up original data. */\n+\trxq->elts_n = 0;\n+\trte_free(rxq->elts.sp);\n+\trxq->elts.sp = NULL;\n+\t/* Post WRs. */\n+\tif ((err = ibv_post_recv(tmpl.qp,\n+\t\t\t\t (tmpl.sp ?\n+\t\t\t\t &(*tmpl.elts.sp)[0].wr :\n+\t\t\t\t &(*tmpl.elts.no_sp)[0].wr),\n+\t\t\t\t &bad_wr))) {\n+\t\tERROR(\"%p: ibv_post_recv() failed for WR %p: %s\",\n+\t\t (void *)dev,\n+\t\t (void *)bad_wr,\n+\t\t strerror(err));\n+\t\tgoto skip_rtr;\n+\t}\n+\tmod = (struct ibv_exp_qp_attr){\n+\t\t.qp_state = IBV_QPS_RTR\n+\t};\n+\tif ((err = ibv_exp_modify_qp(tmpl.qp, &mod, IBV_EXP_QP_STATE)))\n+\t\tERROR(\"%p: QP state to IBV_QPS_RTR failed: %s\",\n+\t\t (void *)dev, strerror(err));\n+skip_rtr:\n+\t*rxq = tmpl;\n+\tassert(err >= 0);\n+\treturn err;\n+}\n+\n+/**\n+ * Configure a RX queue.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param rxq\n+ * Pointer to RX queue structure.\n+ * @param desc\n+ * Number of descriptors to configure in queue.\n+ * @param socket\n+ * NUMA socket on which memory must be allocated.\n+ * @param[in] conf\n+ * Thresholds parameters.\n+ * @param mp\n+ * Memory pool for buffer allocations.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+rxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc,\n+\t unsigned int socket, const struct rte_eth_rxconf *conf,\n+\t struct rte_mempool *mp)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tstruct rxq tmpl = {\n+\t\t.priv = priv,\n+\t\t.mp = mp,\n+\t\t.socket = socket\n+\t};\n+\tstruct ibv_exp_qp_attr mod;\n+\tstruct ibv_recv_wr *bad_wr;\n+\tstruct rte_mbuf *buf;\n+\tint ret = 0;\n+\tint parent = (rxq == &priv->rxq_parent);\n+\n+\t(void)conf; /* Thresholds configuration (ignored). */\n+\t/*\n+\t * If this is a parent queue, hardware must support RSS and\n+\t * RSS must be enabled.\n+\t */\n+\tassert((!parent) || ((priv->hw_rss) && (priv->rss)));\n+\tif (parent) {\n+\t\t/* Even if unused, ibv_create_cq() requires at least one\n+\t\t * descriptor. */\n+\t\tdesc = 1;\n+\t\tgoto skip_mr;\n+\t}\n+\tif ((desc == 0) || (desc % MLX4_PMD_SGE_WR_N)) {\n+\t\tERROR(\"%p: invalid number of RX descriptors (must be a\"\n+\t\t \" multiple of %d)\", (void *)dev, desc);\n+\t\treturn EINVAL;\n+\t}\n+\t/* Get mbuf length. */\n+\tbuf = rte_pktmbuf_alloc(mp);\n+\tif (buf == NULL) {\n+\t\tERROR(\"%p: unable to allocate mbuf\", (void *)dev);\n+\t\treturn ENOMEM;\n+\t}\n+\ttmpl.mb_len = buf->buf_len;\n+\tassert((rte_pktmbuf_headroom(buf) +\n+\t\trte_pktmbuf_tailroom(buf)) == tmpl.mb_len);\n+\tassert(rte_pktmbuf_headroom(buf) == RTE_PKTMBUF_HEADROOM);\n+\trte_pktmbuf_free(buf);\n+\t/* Enable scattered packets support for this queue if necessary. */\n+\tif ((dev->data->dev_conf.rxmode.jumbo_frame) &&\n+\t (dev->data->dev_conf.rxmode.max_rx_pkt_len >\n+\t (tmpl.mb_len - RTE_PKTMBUF_HEADROOM))) {\n+\t\ttmpl.sp = 1;\n+\t\tdesc /= MLX4_PMD_SGE_WR_N;\n+\t}\n+\tDEBUG(\"%p: %s scattered packets support (%u WRs)\",\n+\t (void *)dev, (tmpl.sp ? \"enabling\" : \"disabling\"), desc);\n+\t/* Use the entire RX mempool as the memory region. */\n+\ttmpl.mr = ibv_reg_mr(priv->pd,\n+\t\t (void *)mp->elt_va_start,\n+\t\t\t (mp->elt_va_end - mp->elt_va_start),\n+\t\t\t (IBV_ACCESS_LOCAL_WRITE |\n+\t\t\t IBV_ACCESS_REMOTE_WRITE));\n+\tif (tmpl.mr == NULL) {\n+\t\tret = EINVAL;\n+\t\tERROR(\"%p: MR creation failure: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+skip_mr:\n+\ttmpl.cq = ibv_create_cq(priv->ctx, desc, NULL, NULL, 0);\n+\tif (tmpl.cq == NULL) {\n+\t\tret = ENOMEM;\n+\t\tERROR(\"%p: CQ creation failure: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+\tDEBUG(\"priv->device_attr.max_qp_wr is %d\",\n+\t priv->device_attr.max_qp_wr);\n+\tDEBUG(\"priv->device_attr.max_sge is %d\",\n+\t priv->device_attr.max_sge);\n+#ifdef RSS_SUPPORT\n+\tif (priv->rss)\n+\t\ttmpl.qp = rxq_setup_qp_rss(priv, tmpl.cq, desc, parent);\n+\telse\n+#endif /* RSS_SUPPORT */\n+\t\ttmpl.qp = rxq_setup_qp(priv, tmpl.cq, desc);\n+\tif (tmpl.qp == NULL) {\n+\t\tret = (errno ? errno : EINVAL);\n+\t\tERROR(\"%p: QP creation failure: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+\tmod = (struct ibv_exp_qp_attr){\n+\t\t/* Move the QP to this state. */\n+\t\t.qp_state = IBV_QPS_INIT,\n+\t\t/* Primary port number. */\n+\t\t.port_num = priv->port\n+\t};\n+\tif ((ret = ibv_exp_modify_qp(tmpl.qp, &mod,\n+\t\t\t\t (IBV_EXP_QP_STATE |\n+#ifdef RSS_SUPPORT\n+\t\t\t\t (parent ? IBV_EXP_QP_GROUP_RSS : 0) |\n+#endif /* RSS_SUPPORT */\n+\t\t\t\t IBV_EXP_QP_PORT)))) {\n+\t\tERROR(\"%p: QP state to IBV_QPS_INIT failed: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+\tif ((parent) || (!priv->rss)) {\n+\t\t/* Configure MAC and broadcast addresses. */\n+\t\tif ((ret = rxq_mac_addrs_add(&tmpl))) {\n+\t\t\tERROR(\"%p: QP flow attachment failed: %s\",\n+\t\t\t (void *)dev, strerror(ret));\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n+\t/* Allocate descriptors for RX queues, except for the RSS parent. */\n+\tif (parent)\n+\t\tgoto skip_alloc;\n+\tif (tmpl.sp)\n+\t\tret = rxq_alloc_elts_sp(&tmpl, desc, NULL);\n+\telse\n+\t\tret = rxq_alloc_elts(&tmpl, desc, NULL);\n+\tif (ret) {\n+\t\tERROR(\"%p: RXQ allocation failed: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+\tif ((ret = ibv_post_recv(tmpl.qp,\n+\t\t\t\t (tmpl.sp ?\n+\t\t\t\t &(*tmpl.elts.sp)[0].wr :\n+\t\t\t\t &(*tmpl.elts.no_sp)[0].wr),\n+\t\t\t\t &bad_wr))) {\n+\t\tERROR(\"%p: ibv_post_recv() failed for WR %p: %s\",\n+\t\t (void *)dev,\n+\t\t (void *)bad_wr,\n+\t\t strerror(ret));\n+\t\tgoto error;\n+\t}\n+skip_alloc:\n+\tmod = (struct ibv_exp_qp_attr){\n+\t\t.qp_state = IBV_QPS_RTR\n+\t};\n+\tif ((ret = ibv_exp_modify_qp(tmpl.qp, &mod, IBV_EXP_QP_STATE))) {\n+\t\tERROR(\"%p: QP state to IBV_QPS_RTR failed: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\tgoto error;\n+\t}\n+\t/* Save port ID. */\n+\ttmpl.port_id = dev->data->port_id;\n+\tDEBUG(\"%p: RTE port ID: %u\", (void *)rxq, tmpl.port_id);\n+\t/* Clean up rxq in case we're reinitializing it. */\n+\tDEBUG(\"%p: cleaning-up old rxq just in case\", (void *)rxq);\n+\trxq_cleanup(rxq);\n+\t*rxq = tmpl;\n+\tDEBUG(\"%p: rxq updated with %p\", (void *)rxq, (void *)&tmpl);\n+\tassert(ret == 0);\n+\treturn 0;\n+error:\n+\trxq_cleanup(&tmpl);\n+\tassert(ret > 0);\n+\treturn ret;\n+}\n+\n+/**\n+ * DPDK callback to configure a RX queue.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param idx\n+ * RX queue index.\n+ * @param desc\n+ * Number of descriptors to configure in queue.\n+ * @param socket\n+ * NUMA socket on which memory must be allocated.\n+ * @param[in] conf\n+ * Thresholds parameters.\n+ * @param mp\n+ * Memory pool for buffer allocations.\n+ *\n+ * @return\n+ * 0 on success, negative errno value on failure.\n+ */\n+static int\n+mlx4_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n+\t\t unsigned int socket, const struct rte_eth_rxconf *conf,\n+\t\t struct rte_mempool *mp)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tstruct rxq *rxq = (*priv->rxqs)[idx];\n+\tint ret;\n+\n+\tpriv_lock(priv);\n+\tDEBUG(\"%p: configuring queue %u for %u descriptors\",\n+\t (void *)dev, idx, desc);\n+\tif (idx >= priv->rxqs_n) {\n+\t\tERROR(\"%p: queue index out of range (%u >= %u)\",\n+\t\t (void *)dev, idx, priv->rxqs_n);\n+\t\tpriv_unlock(priv);\n+\t\treturn -EOVERFLOW;\n+\t}\n+\tif (rxq != NULL) {\n+\t\tDEBUG(\"%p: reusing already allocated queue index %u (%p)\",\n+\t\t (void *)dev, idx, (void *)rxq);\n+\t\tif (priv->started) {\n+\t\t\tpriv_unlock(priv);\n+\t\t\treturn -EEXIST;\n+\t\t}\n+\t\t(*priv->rxqs)[idx] = NULL;\n+\t\trxq_cleanup(rxq);\n+\t}\n+\telse {\n+\t\trxq = rte_calloc_socket(\"RXQ\", 1, sizeof(*rxq), 0, socket);\n+\t\tif (rxq == NULL) {\n+\t\t\tERROR(\"%p: unable to allocate queue index %u\",\n+\t\t\t (void *)dev, idx);\n+\t\t\tpriv_unlock(priv);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\tret = rxq_setup(dev, rxq, desc, socket, conf, mp);\n+\tif (ret)\n+\t\trte_free(rxq);\n+\telse {\n+\t\trxq->stats.idx = idx;\n+\t\tDEBUG(\"%p: adding RX queue %p to list\",\n+\t\t (void *)dev, (void *)rxq);\n+\t\t(*priv->rxqs)[idx] = rxq;\n+\t\t/* Update receive callback. */\n+\t\tif (rxq->sp)\n+\t\t\tdev->rx_pkt_burst = mlx4_rx_burst_sp;\n+\t\telse\n+\t\t\tdev->rx_pkt_burst = mlx4_rx_burst;\n+\t}\n+\tpriv_unlock(priv);\n+\treturn -ret;\n+}\n+\n+/**\n+ * DPDK callback to release a RX queue.\n+ *\n+ * @param dpdk_rxq\n+ * Generic RX queue pointer.\n+ */\n+static void\n+mlx4_rx_queue_release(void *dpdk_rxq)\n+{\n+\tstruct rxq *rxq = (struct rxq *)dpdk_rxq;\n+\tstruct priv *priv;\n+\tunsigned int i;\n+\n+\tif (rxq == NULL)\n+\t\treturn;\n+\tpriv = rxq->priv;\n+\tpriv_lock(priv);\n+\tassert(rxq != &priv->rxq_parent);\n+\tfor (i = 0; (i != priv->rxqs_n); ++i)\n+\t\tif ((*priv->rxqs)[i] == rxq) {\n+\t\t\tDEBUG(\"%p: removing RX queue %p from list\",\n+\t\t\t (void *)priv->dev, (void *)rxq);\n+\t\t\t(*priv->rxqs)[i] = NULL;\n+\t\t\tbreak;\n+\t\t}\n+\trxq_cleanup(rxq);\n+\trte_free(rxq);\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * DPDK callback to start the device.\n+ *\n+ * Simulate device start by attaching all configured flows.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ *\n+ * @return\n+ * 0 on success, negative errno value on failure.\n+ */\n+static int\n+mlx4_dev_start(struct rte_eth_dev *dev)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tunsigned int i = 0;\n+\tunsigned int r;\n+\tstruct rxq *rxq;\n+\n+\tpriv_lock(priv);\n+\tif (priv->started) {\n+\t\tpriv_unlock(priv);\n+\t\treturn 0;\n+\t}\n+\tDEBUG(\"%p: attaching configured flows to all RX queues\", (void *)dev);\n+\tpriv->started = 1;\n+\tif (priv->rss) {\n+\t\trxq = &priv->rxq_parent;\n+\t\tr = 1;\n+\t}\n+\telse {\n+\t\trxq = (*priv->rxqs)[0];\n+\t\tr = priv->rxqs_n;\n+\t}\n+\t/* Iterate only once when RSS is enabled. */\n+\tdo {\n+\t\tint ret;\n+\n+\t\t/* Ignore nonexistent RX queues. */\n+\t\tif (rxq == NULL)\n+\t\t\tcontinue;\n+\t\tif (((ret = rxq_mac_addrs_add(rxq)) == 0) &&\n+\t\t ((!priv->promisc) ||\n+\t\t ((ret = rxq_promiscuous_enable(rxq)) == 0)) &&\n+\t\t ((!priv->allmulti) ||\n+\t\t ((ret = rxq_allmulticast_enable(rxq)) == 0)))\n+\t\t\tcontinue;\n+\t\tWARN(\"%p: QP flow attachment failed: %s\",\n+\t\t (void *)dev, strerror(ret));\n+\t\t/* Rollback. */\n+\t\twhile (i != 0)\n+\t\t\tif ((rxq = (*priv->rxqs)[--i]) != NULL) {\n+\t\t\t\trxq_allmulticast_disable(rxq);\n+\t\t\t\trxq_promiscuous_disable(rxq);\n+\t\t\t\trxq_mac_addrs_del(rxq);\n+\t\t\t}\n+\t\tpriv->started = 0;\n+\t\treturn -ret;\n+\t}\n+\twhile ((--r) && ((rxq = (*priv->rxqs)[++i]), i));\n+\tpriv_unlock(priv);\n+\treturn 0;\n+}\n+\n+/**\n+ * DPDK callback to stop the device.\n+ *\n+ * Simulate device stop by detaching all configured flows.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ */\n+static void\n+mlx4_dev_stop(struct rte_eth_dev *dev)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tunsigned int i = 0;\n+\tunsigned int r;\n+\tstruct rxq *rxq;\n+\n+\tpriv_lock(priv);\n+\tif (!priv->started) {\n+\t\tpriv_unlock(priv);\n+\t\treturn;\n+\t}\n+\tDEBUG(\"%p: detaching flows from all RX queues\", (void *)dev);\n+\tpriv->started = 0;\n+\tif (priv->rss) {\n+\t\trxq = &priv->rxq_parent;\n+\t\tr = 1;\n+\t}\n+\telse {\n+\t\trxq = (*priv->rxqs)[0];\n+\t\tr = priv->rxqs_n;\n+\t}\n+\t/* Iterate only once when RSS is enabled. */\n+\tdo {\n+\t\t/* Ignore nonexistent RX queues. */\n+\t\tif (rxq == NULL)\n+\t\t\tcontinue;\n+\t\trxq_allmulticast_disable(rxq);\n+\t\trxq_promiscuous_disable(rxq);\n+\t\trxq_mac_addrs_del(rxq);\n+\t}\n+\twhile ((--r) && ((rxq = (*priv->rxqs)[++i]), i));\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * Dummy DPDK callback for TX.\n+ *\n+ * This function is used to temporarily replace the real callback during\n+ * unsafe control operations on the queue, or in case of error.\n+ *\n+ * @param dpdk_txq\n+ * Generic pointer to TX queue structure.\n+ * @param[in] pkts\n+ * Packets to transmit.\n+ * @param pkts_n\n+ * Number of packets in array.\n+ *\n+ * @return\n+ * Number of packets successfully transmitted (<= pkts_n).\n+ */\n+static uint16_t\n+removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n+{\n+\t(void)dpdk_txq;\n+\t(void)pkts;\n+\t(void)pkts_n;\n+\treturn 0;\n+}\n+\n+/**\n+ * Dummy DPDK callback for RX.\n+ *\n+ * This function is used to temporarily replace the real callback during\n+ * unsafe control operations on the queue, or in case of error.\n+ *\n+ * @param dpdk_rxq\n+ * Generic pointer to RX queue structure.\n+ * @param[out] pkts\n+ * Array to store received packets.\n+ * @param pkts_n\n+ * Maximum number of packets in array.\n+ *\n+ * @return\n+ * Number of packets successfully received (<= pkts_n).\n+ */\n+static uint16_t\n+removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n+{\n+\t(void)dpdk_rxq;\n+\t(void)pkts;\n+\t(void)pkts_n;\n+\treturn 0;\n+}\n+\n+/**\n+ * DPDK callback to close the device.\n+ *\n+ * Destroy all queues and objects, free memory.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ */\n+static void\n+mlx4_dev_close(struct rte_eth_dev *dev)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tvoid *tmp;\n+\tunsigned int i;\n+\n+\tpriv_lock(priv);\n+\tDEBUG(\"%p: closing device \\\"%s\\\"\",\n+\t (void *)dev,\n+\t ((priv->ctx != NULL) ? priv->ctx->device->name : \"\"));\n+\t/* Prevent crashes when queues are still in use. This is unfortunately\n+\t * still required for DPDK 1.3 because some programs (such as testpmd)\n+\t * never release them before closing the device. */\n+\tdev->rx_pkt_burst = removed_rx_burst;\n+\tdev->tx_pkt_burst = removed_tx_burst;\n+\tif (priv->rxqs != NULL) {\n+\t\t/* XXX race condition if mlx4_rx_burst() is still running. */\n+\t\tusleep(1000);\n+\t\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n+\t\t\ttmp = (*priv->rxqs)[i];\n+\t\t\tif (tmp == NULL)\n+\t\t\t\tcontinue;\n+\t\t\t(*priv->rxqs)[i] = NULL;\n+\t\t\trxq_cleanup(tmp);\n+\t\t\trte_free(tmp);\n+\t\t}\n+\t\tpriv->rxqs_n = 0;\n+\t\tpriv->rxqs = NULL;\n+\t}\n+\tif (priv->txqs != NULL) {\n+\t\t/* XXX race condition if mlx4_tx_burst() is still running. */\n+\t\tusleep(1000);\n+\t\tfor (i = 0; (i != priv->txqs_n); ++i) {\n+\t\t\ttmp = (*priv->txqs)[i];\n+\t\t\tif (tmp == NULL)\n+\t\t\t\tcontinue;\n+\t\t\t(*priv->txqs)[i] = NULL;\n+\t\t\ttxq_cleanup(tmp);\n+\t\t\trte_free(tmp);\n+\t\t}\n+\t\tpriv->txqs_n = 0;\n+\t\tpriv->txqs = NULL;\n+\t}\n+\tif (priv->rss)\n+\t\trxq_cleanup(&priv->rxq_parent);\n+\tif (priv->pd != NULL) {\n+\t\tassert(priv->ctx != NULL);\n+\t\tclaim_zero(ibv_dealloc_pd(priv->pd));\n+\t\tclaim_zero(ibv_close_device(priv->ctx));\n+\t}\n+\telse\n+\t\tassert(priv->ctx == NULL);\n+\tpriv_unlock(priv);\n+\tmemset(priv, 0, sizeof(*priv));\n+}\n+\n+/**\n+ * DPDK callback to get information about the device.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param[out] info\n+ * Info structure output buffer.\n+ */\n+static void\n+mlx4_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tunsigned int max;\n+\n+\tpriv_lock(priv);\n+\t/* FIXME: we should ask the device for these values. */\n+\tinfo->min_rx_bufsize = 32;\n+\tinfo->max_rx_pktlen = 65536;\n+\t/*\n+\t * Since we need one CQ per QP, the limit is the minimum number\n+\t * between the two values.\n+\t */\n+\tmax = ((priv->device_attr.max_cq > priv->device_attr.max_qp) ?\n+\t priv->device_attr.max_qp : priv->device_attr.max_cq);\n+\t/* If max >= 65535 then max = 0, max_rx_queues is uint16_t. */\n+\tif (max >= 65535) {\n+\t\tmax = 65535;\n+\t}\n+\tinfo->max_rx_queues = max;\n+\tinfo->max_tx_queues = max;\n+\tinfo->max_mac_addrs = elemof(priv->mac);\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * DPDK callback to get device statistics.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param[out] stats\n+ * Stats structure output buffer.\n+ */\n+static void\n+mlx4_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tstruct rte_eth_stats tmp = { .ipackets = 0 };\n+\tunsigned int i;\n+\tunsigned int idx;\n+\n+\tpriv_lock(priv);\n+\t/* Add software counters. */\n+\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n+\t\tstruct rxq *rxq = (*priv->rxqs)[i];\n+\n+\t\tif (rxq == NULL)\n+\t\t\tcontinue;\n+\t\tidx = rxq->stats.idx;\n+\t\tif (idx < RTE_ETHDEV_QUEUE_STAT_CNTRS) {\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\t\ttmp.q_ipackets[idx] += rxq->stats.ipackets;\n+\t\t\ttmp.q_ibytes[idx] += rxq->stats.ibytes;\n+#endif\n+\t\t\ttmp.q_errors[idx] += (rxq->stats.idropped +\n+\t\t\t\t\t rxq->stats.rx_nombuf);\n+\t\t}\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\ttmp.ipackets += rxq->stats.ipackets;\n+\t\ttmp.ibytes += rxq->stats.ibytes;\n+#endif\n+\t\ttmp.ierrors += rxq->stats.idropped;\n+\t\ttmp.rx_nombuf += rxq->stats.rx_nombuf;\n+\t}\n+\tfor (i = 0; (i != priv->txqs_n); ++i) {\n+\t\tstruct txq *txq = (*priv->txqs)[i];\n+\n+\t\tif (txq == NULL)\n+\t\t\tcontinue;\n+\t\tidx = txq->stats.idx;\n+\t\tif (idx < RTE_ETHDEV_QUEUE_STAT_CNTRS) {\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\t\ttmp.q_opackets[idx] += txq->stats.opackets;\n+\t\t\ttmp.q_obytes[idx] += txq->stats.obytes;\n+#endif\n+\t\t\ttmp.q_errors[idx] += txq->stats.odropped;\n+\t\t}\n+#ifdef MLX4_PMD_SOFT_COUNTERS\n+\t\ttmp.opackets += txq->stats.opackets;\n+\t\ttmp.obytes += txq->stats.obytes;\n+#endif\n+\t\ttmp.oerrors += txq->stats.odropped;\n+\t}\n+#ifndef MLX4_PMD_SOFT_COUNTERS\n+\t/* FIXME: retrieve and add hardware counters. */\n+#endif\n+\t*stats = tmp;\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * DPDK callback to clear device statistics.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ */\n+static void\n+mlx4_stats_reset(struct rte_eth_dev *dev)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tunsigned int i;\n+\tunsigned int idx;\n+\n+\tpriv_lock(priv);\n+\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n+\t\tif ((*priv->rxqs)[i] == NULL)\n+\t\t\tcontinue;\n+\t\tidx = (*priv->rxqs)[i]->stats.idx;\n+\t\t(*priv->rxqs)[i]->stats =\n+\t\t\t(struct mlx4_rxq_stats){ .idx = idx };\n+\t}\n+\tfor (i = 0; (i != priv->txqs_n); ++i) {\n+\t\tif ((*priv->txqs)[i] == NULL)\n+\t\t\tcontinue;\n+\t\tidx = (*priv->rxqs)[i]->stats.idx;\n+\t\t(*priv->txqs)[i]->stats =\n+\t\t\t(struct mlx4_txq_stats){ .idx = idx };\n+\t}\n+#ifndef MLX4_PMD_SOFT_COUNTERS\n+\t/* FIXME: reset hardware counters. */\n+#endif\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * DPDK callback to remove a MAC address.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param index\n+ * MAC address index.\n+ */\n+static void\n+mlx4_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\n+\tpriv_lock(priv);\n+\tDEBUG(\"%p: removing MAC address from index %\" PRIu32,\n+\t (void *)dev, index);\n+\tif (index >= MLX4_MAX_MAC_ADDRESSES)\n+\t\tgoto end;\n+\t/* Refuse to remove the broadcast address, this one is special. */\n+\tif (!memcmp(priv->mac[index].addr_bytes, \"\\xff\\xff\\xff\\xff\\xff\\xff\",\n+\t\t ETHER_ADDR_LEN))\n+\t\tgoto end;\n+\tpriv_mac_addr_del(priv, index);\n+end:\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * DPDK callback to add a MAC address.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param mac_addr\n+ * MAC address to register.\n+ * @param index\n+ * MAC address index.\n+ * @param vmdq\n+ * VMDq pool index to associate address with (ignored).\n+ */\n+static void\n+mlx4_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n+\t\t uint32_t index, uint32_t vmdq)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\n+\t(void)vmdq;\n+\tpriv_lock(priv);\n+\tDEBUG(\"%p: adding MAC address at index %\" PRIu32,\n+\t (void *)dev, index);\n+\tif (index >= MLX4_MAX_MAC_ADDRESSES)\n+\t\tgoto end;\n+\t/* Refuse to add the broadcast address, this one is special. */\n+\tif (!memcmp(mac_addr->addr_bytes, \"\\xff\\xff\\xff\\xff\\xff\\xff\",\n+\t\t ETHER_ADDR_LEN))\n+\t\tgoto end;\n+\tpriv_mac_addr_add(priv, index,\n+\t\t\t (const uint8_t (*)[ETHER_ADDR_LEN])\n+\t\t\t mac_addr->addr_bytes);\n+end:\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * DPDK callback to enable promiscuous mode.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ */\n+static void\n+mlx4_promiscuous_enable(struct rte_eth_dev *dev)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tunsigned int i;\n+\tint ret;\n+\n+\tpriv_lock(priv);\n+\tif (priv->promisc) {\n+\t\tpriv_unlock(priv);\n+\t\treturn;\n+\t}\n+\t/* If device isn't started, this is all we need to do. */\n+\tif (!priv->started)\n+\t\tgoto end;\n+\tif (priv->rss) {\n+\t\tret = rxq_promiscuous_enable(&priv->rxq_parent);\n+\t\tif (ret) {\n+\t\t\tpriv_unlock(priv);\n+\t\t\treturn;\n+\t\t}\n+\t\tgoto end;\n+\t}\n+\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n+\t\tif ((*priv->rxqs)[i] == NULL)\n+\t\t\tcontinue;\n+\t\tret = rxq_promiscuous_enable((*priv->rxqs)[i]);\n+\t\tif (!ret)\n+\t\t\tcontinue;\n+\t\t/* Failure, rollback. */\n+\t\twhile (i != 0)\n+\t\t\tif ((*priv->rxqs)[--i] != NULL)\n+\t\t\t\trxq_promiscuous_disable((*priv->rxqs)[i]);\n+\t\tpriv_unlock(priv);\n+\t\treturn;\n+\t}\n+end:\n+\tpriv->promisc = 1;\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * DPDK callback to disable promiscuous mode.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ */\n+static void\n+mlx4_promiscuous_disable(struct rte_eth_dev *dev)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tunsigned int i;\n+\n+\tpriv_lock(priv);\n+\tif (!priv->promisc) {\n+\t\tpriv_unlock(priv);\n+\t\treturn;\n+\t}\n+\tif (priv->rss) {\n+\t\trxq_promiscuous_disable(&priv->rxq_parent);\n+\t\tgoto end;\n+\t}\n+\tfor (i = 0; (i != priv->rxqs_n); ++i)\n+\t\tif ((*priv->rxqs)[i] != NULL)\n+\t\t\trxq_promiscuous_disable((*priv->rxqs)[i]);\n+end:\n+\tpriv->promisc = 0;\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * DPDK callback to enable allmulti mode.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ */\n+static void\n+mlx4_allmulticast_enable(struct rte_eth_dev *dev)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tunsigned int i;\n+\tint ret;\n+\n+\tpriv_lock(priv);\n+\tif (priv->allmulti) {\n+\t\tpriv_unlock(priv);\n+\t\treturn;\n+\t}\n+\t/* If device isn't started, this is all we need to do. */\n+\tif (!priv->started)\n+\t\tgoto end;\n+\tif (priv->rss) {\n+\t\tret = rxq_allmulticast_enable(&priv->rxq_parent);\n+\t\tif (ret) {\n+\t\t\tpriv_unlock(priv);\n+\t\t\treturn;\n+\t\t}\n+\t\tgoto end;\n+\t}\n+\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n+\t\tif ((*priv->rxqs)[i] == NULL)\n+\t\t\tcontinue;\n+\t\tret = rxq_allmulticast_enable((*priv->rxqs)[i]);\n+\t\tif (!ret)\n+\t\t\tcontinue;\n+\t\t/* Failure, rollback. */\n+\t\twhile (i != 0)\n+\t\t\tif ((*priv->rxqs)[--i] != NULL)\n+\t\t\t\trxq_allmulticast_disable((*priv->rxqs)[i]);\n+\t\tpriv_unlock(priv);\n+\t\treturn;\n+\t}\n+end:\n+\tpriv->allmulti = 1;\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * DPDK callback to disable allmulti mode.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ */\n+static void\n+mlx4_allmulticast_disable(struct rte_eth_dev *dev)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tunsigned int i;\n+\n+\tpriv_lock(priv);\n+\tif (!priv->allmulti) {\n+\t\tpriv_unlock(priv);\n+\t\treturn;\n+\t}\n+\tif (priv->rss) {\n+\t\trxq_allmulticast_disable(&priv->rxq_parent);\n+\t\tgoto end;\n+\t}\n+\tfor (i = 0; (i != priv->rxqs_n); ++i)\n+\t\tif ((*priv->rxqs)[i] != NULL)\n+\t\t\trxq_allmulticast_disable((*priv->rxqs)[i]);\n+end:\n+\tpriv->allmulti = 0;\n+\tpriv_unlock(priv);\n+}\n+\n+/**\n+ * DPDK callback to retrieve physical link information (unlocked version).\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param wait_to_complete\n+ * Wait for request completion (ignored).\n+ */\n+static int\n+mlx4_link_update_unlocked(struct rte_eth_dev *dev, int wait_to_complete)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tstruct ibv_port_attr port_attr;\n+\tstatic const uint8_t width_mult[] = {\n+\t\t/* Multiplier values taken from devinfo.c in libibverbs. */\n+\t\t0, 1, 4, 0, 8, 0, 0, 0, 12, 0\n+\t};\n+\n+\t(void)wait_to_complete;\n+\tif ((errno = ibv_query_port(priv->ctx, priv->port, &port_attr))) {\n+\t\tWARN(\"port query failed: %s\", strerror(errno));\n+\t\treturn -1;\n+\t}\n+\tdev->data->dev_link = (struct rte_eth_link){\n+\t\t.link_speed = (ibv_rate_to_mbps(mult_to_ibv_rate\n+\t\t\t\t\t\t(port_attr.active_speed)) *\n+\t\t\t width_mult[(port_attr.active_width %\n+\t\t\t\t\t sizeof(width_mult))]),\n+\t\t.link_duplex = ETH_LINK_FULL_DUPLEX,\n+\t\t.link_status = (port_attr.state == IBV_PORT_ACTIVE)\n+\t};\n+\tif (memcmp(&port_attr, &priv->port_attr, sizeof(port_attr))) {\n+\t\t/* Link status changed. */\n+\t\tpriv->port_attr = port_attr;\n+\t\treturn 0;\n+\t}\n+\t/* Link status is still the same. */\n+\treturn -1;\n+}\n+\n+/**\n+ * DPDK callback to retrieve physical link information.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param wait_to_complete\n+ * Wait for request completion (ignored).\n+ */\n+static int\n+mlx4_link_update(struct rte_eth_dev *dev, int wait_to_complete)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tint ret;\n+\n+\tpriv_lock(priv);\n+\tret = mlx4_link_update_unlocked(dev, wait_to_complete);\n+\tpriv_unlock(priv);\n+\treturn ret;\n+}\n+\n+/**\n+ * DPDK callback to change the MTU.\n+ *\n+ * Setting the MTU affects hardware MRU (packets larger than the MTU cannot be\n+ * received). Use this as a hint to enable/disable scattered packets support\n+ * and improve performance when not needed.\n+ * Since failure is not an option, reconfiguring queues on the fly is not\n+ * recommended.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param in_mtu\n+ * New MTU.\n+ *\n+ * @return\n+ * 0 on success, negative errno value on failure.\n+ */\n+static int\n+mlx4_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tint ret = 0;\n+\tunsigned int i;\n+\tuint16_t (*rx_func)(void *, struct rte_mbuf **, uint16_t) =\n+\t\tmlx4_rx_burst;\n+\n+\tpriv_lock(priv);\n+\t/* Set kernel interface MTU first. */\n+\tif (priv_set_mtu(priv, mtu)) {\n+\t\tret = errno;\n+\t\tWARN(\"cannot set port %u MTU to %u: %s\", priv->port, mtu,\n+\t\t strerror(ret));\n+\t\tgoto out;\n+\t}\n+\telse\n+\t\tDEBUG(\"adapter port %u MTU set to %u\", priv->port, mtu);\n+\tpriv->mtu = mtu;\n+\t/* Temporarily replace RX handler with a fake one, assuming it has not\n+\t * been copied elsewhere. */\n+\tdev->rx_pkt_burst = removed_rx_burst;\n+\t/* Make sure everyone has left mlx4_rx_burst() and uses\n+\t * removed_rx_burst() instead. */\n+\trte_wmb();\n+\tusleep(1000);\n+\t/* Reconfigure each RX queue. */\n+\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n+\t\tstruct rxq *rxq = (*priv->rxqs)[i];\n+\t\tunsigned int max_frame_len;\n+\t\tint sp;\n+\n+\t\tif (rxq == NULL)\n+\t\t\tcontinue;\n+\t\t/* Calculate new maximum frame length according to MTU and\n+\t\t * toggle scattered support (sp) if necessary. */\n+\t\tmax_frame_len = (priv->mtu + ETHER_HDR_LEN +\n+\t\t\t\t (ETHER_MAX_VLAN_FRAME_LEN - ETHER_MAX_LEN));\n+\t\tsp = (max_frame_len > (rxq->mb_len - RTE_PKTMBUF_HEADROOM));\n+\t\t/* Provide new values to rxq_setup(). */\n+\t\tdev->data->dev_conf.rxmode.jumbo_frame = sp;\n+\t\tdev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame_len;\n+\t\tif ((ret = rxq_rehash(dev, rxq))) {\n+\t\t\t/* Force SP RX if that queue requires it and abort. */\n+\t\t\tif (rxq->sp)\n+\t\t\t\trx_func = mlx4_rx_burst_sp;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* Reenable non-RSS queue attributes. No need to check\n+\t\t * for errors at this stage. */\n+\t\tif (!priv->rss) {\n+\t\t\trxq_mac_addrs_add(rxq);\n+\t\t\tif (priv->promisc)\n+\t\t\t\trxq_promiscuous_enable(rxq);\n+\t\t\tif (priv->allmulti)\n+\t\t\t\trxq_allmulticast_enable(rxq);\n+\t\t}\n+\t\t/* Scattered burst function takes priority. */\n+\t\tif (rxq->sp)\n+\t\t\trx_func = mlx4_rx_burst_sp;\n+\t}\n+\t/* Burst functions can now be called again. */\n+\trte_wmb();\n+\tdev->rx_pkt_burst = rx_func;\n+out:\n+\tpriv_unlock(priv);\n+\tassert(ret >= 0);\n+\treturn -ret;\n+}\n+\n+/**\n+ * DPDK callback to get flow control status.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param[out] fc_conf\n+ * Flow control output buffer.\n+ *\n+ * @return\n+ * 0 on success, negative errno value on failure.\n+ */\n+static int\n+mlx4_dev_get_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tstruct ifreq ifr;\n+\tstruct ethtool_pauseparam ethpause = {\n+\t\t.cmd = ETHTOOL_GPAUSEPARAM\n+\t};\n+\tint ret;\n+\n+\tifr.ifr_data = ðpause;\n+\tpriv_lock(priv);\n+\tif (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {\n+\t\tret = errno;\n+\t\tWARN(\"ioctl(SIOCETHTOOL, ETHTOOL_GPAUSEPARAM)\"\n+\t\t \" failed: %s\",\n+\t\t strerror(ret));\n+\t\tgoto out;\n+\t}\n+\n+\tfc_conf->autoneg = ethpause.autoneg;\n+\tif (ethpause.rx_pause && ethpause.tx_pause)\n+\t\tfc_conf->mode = RTE_FC_FULL;\n+\telse if (ethpause.rx_pause)\n+\t\tfc_conf->mode = RTE_FC_RX_PAUSE;\n+\telse if (ethpause.tx_pause)\n+\t\tfc_conf->mode = RTE_FC_TX_PAUSE;\n+\telse\n+\t\tfc_conf->mode = RTE_FC_NONE;\n+\tret = 0;\n+\n+out:\n+\tpriv_unlock(priv);\n+\tassert(ret >= 0);\n+\treturn -ret;\n+}\n+\n+/**\n+ * DPDK callback to modify flow control parameters.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param[in] fc_conf\n+ * Flow control parameters.\n+ *\n+ * @return\n+ * 0 on success, negative errno value on failure.\n+ */\n+static int\n+mlx4_dev_set_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tstruct ifreq ifr;\n+\tstruct ethtool_pauseparam ethpause = {\n+\t\t.cmd = ETHTOOL_SPAUSEPARAM\n+\t};\n+\tint ret;\n+\n+\tifr.ifr_data = ðpause;\n+\tethpause.autoneg = fc_conf->autoneg;\n+\tif (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||\n+\t (fc_conf->mode & RTE_FC_RX_PAUSE))\n+\t\tethpause.rx_pause = 1;\n+\telse\n+\t\tethpause.rx_pause = 0;\n+\n+\tif (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||\n+\t (fc_conf->mode & RTE_FC_TX_PAUSE))\n+\t\tethpause.tx_pause = 1;\n+\telse\n+\t\tethpause.tx_pause = 0;\n+\n+\tpriv_lock(priv);\n+\tif (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {\n+\t\tret = errno;\n+\t\tWARN(\"ioctl(SIOCETHTOOL, ETHTOOL_SPAUSEPARAM)\"\n+\t\t \" failed: %s\",\n+\t\t strerror(ret));\n+\t\tgoto out;\n+\t}\n+\tret = 0;\n+\n+out:\n+\tpriv_unlock(priv);\n+\tassert(ret >= 0);\n+\treturn -ret;\n+}\n+\n+/**\n+ * Configure a VLAN filter.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param vlan_id\n+ * VLAN ID to filter.\n+ * @param on\n+ * Toggle filter.\n+ *\n+ * @return\n+ * 0 on success, errno value on failure.\n+ */\n+static int\n+vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tunsigned int i;\n+\tunsigned int j = -1;\n+\n+\tDEBUG(\"%p: %s VLAN filter ID %\" PRIu16,\n+\t (void *)dev, (on ? \"enable\" : \"disable\"), vlan_id);\n+\tfor (i = 0; (i != elemof(priv->vlan_filter)); ++i) {\n+\t\tif (!priv->vlan_filter[i].enabled) {\n+\t\t\t/* Unused index, remember it. */\n+\t\t\tj = i;\n+\t\t\tcontinue;\n+\t\t}\n+\t\tif (priv->vlan_filter[i].id != vlan_id)\n+\t\t\tcontinue;\n+\t\t/* This VLAN ID is already known, use its index. */\n+\t\tj = i;\n+\t\tbreak;\n+\t}\n+\t/* Check if there's room for another VLAN filter. */\n+\tif (j == (unsigned int)-1)\n+\t\treturn ENOMEM;\n+\t/*\n+\t * VLAN filters apply to all configured MAC addresses, flow\n+\t * specifications must be reconfigured accordingly.\n+\t */\n+\tpriv->vlan_filter[j].id = vlan_id;\n+\tif ((on) && (!priv->vlan_filter[j].enabled)) {\n+\t\t/*\n+\t\t * Filter is disabled, enable it.\n+\t\t * Rehashing flows in all RX queues is necessary.\n+\t\t */\n+\t\tif (priv->rss)\n+\t\t\trxq_mac_addrs_del(&priv->rxq_parent);\n+\t\telse\n+\t\t\tfor (i = 0; (i != priv->rxqs_n); ++i)\n+\t\t\t\tif ((*priv->rxqs)[i] != NULL)\n+\t\t\t\t\trxq_mac_addrs_del((*priv->rxqs)[i]);\n+\t\tpriv->vlan_filter[j].enabled = 1;\n+\t\tif (priv->started) {\n+\t\t\tif (priv->rss)\n+\t\t\t\trxq_mac_addrs_add(&priv->rxq_parent);\n+\t\t\telse\n+\t\t\t\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n+\t\t\t\t\tif ((*priv->rxqs)[i] == NULL)\n+\t\t\t\t\t\tcontinue;\n+\t\t\t\t\trxq_mac_addrs_add((*priv->rxqs)[i]);\n+\t\t\t\t}\n+\t\t}\n+\t}\n+\telse if ((!on) && (priv->vlan_filter[j].enabled)) {\n+\t\t/*\n+\t\t * Filter is enabled, disable it.\n+\t\t * Rehashing flows in all RX queues is necessary.\n+\t\t */\n+\t\tif (priv->rss)\n+\t\t\trxq_mac_addrs_del(&priv->rxq_parent);\n+\t\telse\n+\t\t\tfor (i = 0; (i != priv->rxqs_n); ++i)\n+\t\t\t\tif ((*priv->rxqs)[i] != NULL)\n+\t\t\t\t\trxq_mac_addrs_del((*priv->rxqs)[i]);\n+\t\tpriv->vlan_filter[j].enabled = 0;\n+\t\tif (priv->started) {\n+\t\t\tif (priv->rss)\n+\t\t\t\trxq_mac_addrs_add(&priv->rxq_parent);\n+\t\t\telse\n+\t\t\t\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n+\t\t\t\t\tif ((*priv->rxqs)[i] == NULL)\n+\t\t\t\t\t\tcontinue;\n+\t\t\t\t\trxq_mac_addrs_add((*priv->rxqs)[i]);\n+\t\t\t\t}\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * DPDK callback to configure a VLAN filter.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device structure.\n+ * @param vlan_id\n+ * VLAN ID to filter.\n+ * @param on\n+ * Toggle filter.\n+ *\n+ * @return\n+ * 0 on success, negative errno value on failure.\n+ */\n+static int\n+mlx4_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n+{\n+\tstruct priv *priv = dev->data->dev_private;\n+\tint ret;\n+\n+\tpriv_lock(priv);\n+\tret = vlan_filter_set(dev, vlan_id, on);\n+\tpriv_unlock(priv);\n+\tassert(ret >= 0);\n+\treturn -ret;\n+}\n+\n+static struct eth_dev_ops mlx4_dev_ops = {\n+\t.dev_configure = mlx4_dev_configure,\n+\t.dev_start = mlx4_dev_start,\n+\t.dev_stop = mlx4_dev_stop,\n+\t.dev_close = mlx4_dev_close,\n+\t.promiscuous_enable = mlx4_promiscuous_enable,\n+\t.promiscuous_disable = mlx4_promiscuous_disable,\n+\t.allmulticast_enable = mlx4_allmulticast_enable,\n+\t.allmulticast_disable = mlx4_allmulticast_disable,\n+\t.link_update = mlx4_link_update,\n+\t.stats_get = mlx4_stats_get,\n+\t.stats_reset = mlx4_stats_reset,\n+\t.queue_stats_mapping_set = NULL,\n+\t.dev_infos_get = mlx4_dev_infos_get,\n+\t.vlan_filter_set = mlx4_vlan_filter_set,\n+\t.vlan_tpid_set = NULL,\n+\t.vlan_strip_queue_set = NULL,\n+\t.vlan_offload_set = NULL,\n+\t.rx_queue_setup = mlx4_rx_queue_setup,\n+\t.tx_queue_setup = mlx4_tx_queue_setup,\n+\t.rx_queue_release = mlx4_rx_queue_release,\n+\t.tx_queue_release = mlx4_tx_queue_release,\n+\t.dev_led_on = NULL,\n+\t.dev_led_off = NULL,\n+\t.flow_ctrl_get = mlx4_dev_get_flow_ctrl,\n+\t.flow_ctrl_set = mlx4_dev_set_flow_ctrl,\n+\t.priority_flow_ctrl_set = NULL,\n+\t.mac_addr_remove = mlx4_mac_addr_remove,\n+\t.mac_addr_add = mlx4_mac_addr_add,\n+\t.mtu_set = mlx4_dev_set_mtu,\n+\t.fdir_add_signature_filter = NULL,\n+\t.fdir_update_signature_filter = NULL,\n+\t.fdir_remove_signature_filter = NULL,\n+\t.fdir_add_perfect_filter = NULL,\n+\t.fdir_update_perfect_filter = NULL,\n+\t.fdir_remove_perfect_filter = NULL,\n+\t.fdir_set_masks = NULL\n+};\n+\n+/**\n+ * Get PCI information from struct ibv_device.\n+ *\n+ * @param device\n+ * Pointer to Ethernet device structure.\n+ * @param[out] pci_addr\n+ * PCI bus address output buffer.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure and errno is set.\n+ */\n+static int\n+mlx4_ibv_device_to_pci_addr(const struct ibv_device *device,\n+\t\t\t struct rte_pci_addr *pci_addr)\n+{\n+\tFILE *file;\n+\tchar line[32];\n+\tMKSTR(path, \"%s/device/uevent\", device->ibdev_path);\n+\n+\tfile = fopen(path, \"rb\");\n+\tif (file == NULL)\n+\t\treturn -1;\n+\twhile (fgets(line, sizeof(line), file) == line) {\n+\t\tsize_t len = strlen(line);\n+\t\tint ret;\n+\n+\t\t/* Truncate long lines. */\n+\t\tif (len == (sizeof(line) - 1))\n+\t\t\twhile (line[(len - 1)] != '\\n') {\n+\t\t\t\tret = fgetc(file);\n+\t\t\t\tif (ret == EOF)\n+\t\t\t\t\tbreak;\n+\t\t\t\tline[(len - 1)] = ret;\n+\t\t\t}\n+\t\t/* Extract information. */\n+\t\tif (sscanf(line,\n+\t\t\t \"PCI_SLOT_NAME=\"\n+\t\t\t \"%\" SCNx16 \":%\" SCNx8 \":%\" SCNx8 \".%\" SCNx8 \"\\n\",\n+\t\t\t &pci_addr->domain,\n+\t\t\t &pci_addr->bus,\n+\t\t\t &pci_addr->devid,\n+\t\t\t &pci_addr->function) == 4) {\n+\t\t\tret = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tfclose(file);\n+\treturn 0;\n+}\n+\n+/**\n+ * Derive MAC address from port GID.\n+ *\n+ * @param[out] mac\n+ * MAC address output buffer.\n+ * @param port\n+ * Physical port number.\n+ * @param[in] gid\n+ * Port GID.\n+ */\n+static void\n+mac_from_gid(uint8_t (*mac)[ETHER_ADDR_LEN], uint32_t port, uint8_t *gid)\n+{\n+\tmemcpy(&(*mac)[0], gid + 8, 3);\n+\tmemcpy(&(*mac)[3], gid + 13, 3);\n+\tif (port == 1)\n+\t\t(*mac)[0] ^= 2;\n+}\n+\n+/* Support up to 32 adapters. */\n+static struct {\n+\tstruct rte_pci_addr pci_addr; /* associated PCI address */\n+\tuint32_t ports; /* physical ports bitfield. */\n+} mlx4_dev[32];\n+\n+/**\n+ * Get device index in mlx4_dev[] from PCI bus address.\n+ *\n+ * @param[in] pci_addr\n+ * PCI bus address to look for.\n+ *\n+ * @return\n+ * mlx4_dev[] index on success, -1 on failure.\n+ */\n+static int\n+mlx4_dev_idx(struct rte_pci_addr *pci_addr)\n+{\n+\tunsigned int i;\n+\tint ret = -1;\n+\n+\tassert(pci_addr != NULL);\n+\tfor (i = 0; (i != elemof(mlx4_dev)); ++i) {\n+\t\tif ((mlx4_dev[i].pci_addr.domain == pci_addr->domain) &&\n+\t\t (mlx4_dev[i].pci_addr.bus == pci_addr->bus) &&\n+\t\t (mlx4_dev[i].pci_addr.devid == pci_addr->devid) &&\n+\t\t (mlx4_dev[i].pci_addr.function == pci_addr->function))\n+\t\t\treturn i;\n+\t\tif ((mlx4_dev[i].ports == 0) && (ret == -1))\n+\t\t\tret = i;\n+\t}\n+\treturn ret;\n+}\n+\n+/**\n+ * Retrieve integer value from environment variable.\n+ *\n+ * @param[in] name\n+ * Environment variable name.\n+ *\n+ * @return\n+ * Integer value, 0 if the variable is not set.\n+ */\n+static int\n+mlx4_getenv_int(const char *name)\n+{\n+\tconst char *val = getenv(name);\n+\n+\tif (val == NULL)\n+\t\treturn 0;\n+\treturn atoi(val);\n+}\n+\n+static struct eth_driver mlx4_driver;\n+\n+/**\n+ * DPDK callback to register a PCI device.\n+ *\n+ * This function creates an Ethernet device for each port of a given\n+ * PCI device.\n+ *\n+ * @param[in] pci_drv\n+ * PCI driver structure (mlx4_driver).\n+ * @param[in] pci_dev\n+ * PCI device information.\n+ *\n+ * @return\n+ * 0 on success, negative errno value on failure.\n+ */\n+static int\n+mlx4_pci_devinit(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n+{\n+\tstruct ibv_device **list;\n+\tstruct ibv_device *ibv_dev;\n+\tint err = 0;\n+\tstruct ibv_context *attr_ctx = NULL;\n+\tstruct ibv_device_attr device_attr;\n+\tunsigned int vf;\n+\tint idx;\n+\tint i;\n+\n+\t(void)pci_drv;\n+\tassert(pci_drv == &mlx4_driver.pci_drv);\n+\t/* Get mlx4_dev[] index. */\n+\tidx = mlx4_dev_idx(&pci_dev->addr);\n+\tif (idx == -1) {\n+\t\tERROR(\"this driver cannot support any more adapters\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tDEBUG(\"using driver device index %d\", idx);\n+\n+\t/* Save PCI address. */\n+\tmlx4_dev[idx].pci_addr = pci_dev->addr;\n+\tlist = ibv_get_device_list(&i);\n+\tif (list == NULL) {\n+\t\tassert(errno);\n+\t\treturn -errno;\n+\t}\n+\tassert(i >= 0);\n+\t/*\n+\t * For each listed device, check related sysfs entry against\n+\t * the provided PCI ID.\n+\t */\n+\twhile (i != 0) {\n+\t\tstruct rte_pci_addr pci_addr;\n+\n+\t\t--i;\n+\t\tDEBUG(\"checking device \\\"%s\\\"\", list[i]->name);\n+\t\tif (mlx4_ibv_device_to_pci_addr(list[i], &pci_addr))\n+\t\t\tcontinue;\n+\t\tif ((pci_dev->addr.domain != pci_addr.domain) ||\n+\t\t (pci_dev->addr.bus != pci_addr.bus) ||\n+\t\t (pci_dev->addr.devid != pci_addr.devid) ||\n+\t\t (pci_dev->addr.function != pci_addr.function))\n+\t\t\tcontinue;\n+\t\tvf = (pci_dev->id.device_id ==\n+\t\t PCI_DEVICE_ID_MELLANOX_CONNECTX3VF);\n+\t\tINFO(\"PCI information matches, using device \\\"%s\\\" (VF: %s)\",\n+\t\t list[i]->name, (vf ? \"true\" : \"false\"));\n+\t\tattr_ctx = ibv_open_device(list[i]);\n+\t\terr = errno;\n+\t\tbreak;\n+\t}\n+\tif (attr_ctx == NULL) {\n+\t\tif (err == 0)\n+\t\t\terr = ENODEV;\n+\t\tibv_free_device_list(list);\n+\t\tassert(err > 0);\n+\t\treturn -err;\n+\t}\n+\tibv_dev = list[i];\n+\n+\tDEBUG(\"device opened\");\n+\tif (ibv_query_device(attr_ctx, &device_attr))\n+\t\tgoto error;\n+\tINFO(\"%u port(s) detected\", device_attr.phys_port_cnt);\n+\n+\tfor (i = 0; i < device_attr.phys_port_cnt; i++) {\n+\t\tuint32_t port = i + 1; /* ports are indexed from one */\n+\t\tuint32_t test = (1 << i);\n+\t\tstruct ibv_context *ctx = NULL;\n+\t\tstruct ibv_port_attr port_attr;\n+\t\tstruct ibv_pd *pd = NULL;\n+\t\tstruct priv *priv = NULL;\n+\t\tstruct rte_eth_dev *eth_dev;\n+#if defined(INLINE_RECV) || defined(RSS_SUPPORT)\n+\t\tstruct ibv_exp_device_attr exp_device_attr;\n+#endif\n+\t\tstruct ether_addr mac;\n+\t\tunion ibv_gid temp_gid;\n+\n+#ifdef RSS_SUPPORT\n+\t\texp_device_attr.comp_mask =\n+\t\t\t(IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS |\n+\t\t\t IBV_EXP_DEVICE_ATTR_RSS_TBL_SZ);\n+#endif /* RSS_SUPPORT */\n+\n+\t\tDEBUG(\"using port %u (%08\" PRIx32 \")\", port, test);\n+\n+\t\tctx = ibv_open_device(ibv_dev);\n+\t\tif (ctx == NULL)\n+\t\t\tgoto port_error;\n+\n+\t\t/* Check port status. */\n+\t\tif ((err = ibv_query_port(ctx, port, &port_attr))) {\n+\t\t\tERROR(\"port query failed: %s\", strerror(err));\n+\t\t\tgoto port_error;\n+\t\t}\n+\t\tif (port_attr.state != IBV_PORT_ACTIVE)\n+\t\t\tWARN(\"bad state for port %d: \\\"%s\\\" (%d)\",\n+\t\t\t port, ibv_port_state_str(port_attr.state),\n+\t\t\t port_attr.state);\n+\n+\t\t/* Allocate protection domain. */\n+\t\tpd = ibv_alloc_pd(ctx);\n+\t\tif (pd == NULL) {\n+\t\t\tERROR(\"PD allocation failure\");\n+\t\t\terr = ENOMEM;\n+\t\t\tgoto port_error;\n+\t\t}\n+\n+\t\tmlx4_dev[idx].ports |= test;\n+\n+\t\t/* from rte_ethdev.c */\n+\t\tpriv = rte_zmalloc(\"ethdev private structure\",\n+\t\t sizeof(*priv),\n+\t\t RTE_CACHE_LINE_SIZE);\n+\t\tif (priv == NULL) {\n+\t\t\tERROR(\"priv allocation failure\");\n+\t\t\terr = ENOMEM;\n+\t\t\tgoto port_error;\n+\t\t}\n+\n+\t\tpriv->ctx = ctx;\n+\t\tpriv->device_attr = device_attr;\n+\t\tpriv->port_attr = port_attr;\n+\t\tpriv->port = port;\n+\t\tpriv->pd = pd;\n+\t\tpriv->mtu = ETHER_MTU;\n+#ifdef RSS_SUPPORT\n+\t\tif (ibv_exp_query_device(ctx, &exp_device_attr)) {\n+\t\t\tINFO(\"experimental ibv_exp_query_device\");\n+\t\t\tgoto port_error;\n+\t\t}\n+\t\tif ((exp_device_attr.exp_device_cap_flags & IBV_EXP_DEVICE_QPG) &&\n+\t\t (exp_device_attr.exp_device_cap_flags & IBV_EXP_DEVICE_UD_RSS) &&\n+\t\t (exp_device_attr.comp_mask & IBV_EXP_DEVICE_ATTR_RSS_TBL_SZ) &&\n+\t\t (exp_device_attr.max_rss_tbl_sz > 0)) {\n+\t\t\tpriv->hw_qpg = 1;\n+\t\t\tpriv->hw_rss = 1;\n+\t\t\tpriv->max_rss_tbl_sz = exp_device_attr.max_rss_tbl_sz;\n+\t\t}\n+\t\telse {\n+\t\t\tpriv->hw_qpg = 0;\n+\t\t\tpriv->hw_rss = 0;\n+\t\t\tpriv->max_rss_tbl_sz = 0;\n+\t\t}\n+\t\tpriv->hw_tss = !!(exp_device_attr.exp_device_cap_flags &\n+\t\t\t\t IBV_EXP_DEVICE_UD_TSS);\n+\t\tDEBUG(\"device flags: %s%s%s\",\n+\t\t (priv->hw_qpg ? \"IBV_DEVICE_QPG \" : \"\"),\n+\t\t (priv->hw_tss ? \"IBV_DEVICE_TSS \" : \"\"),\n+\t\t (priv->hw_rss ? \"IBV_DEVICE_RSS \" : \"\"));\n+\t\tif (priv->hw_rss)\n+\t\t\tDEBUG(\"maximum RSS indirection table size: %u\",\n+\t\t\t exp_device_attr.max_rss_tbl_sz);\n+#endif /* RSS_SUPPORT */\n+\n+#ifdef INLINE_RECV\n+\t\tpriv->inl_recv_size = mlx4_getenv_int(\"MLX4_INLINE_RECV_SIZE\");\n+\n+\t\tif (priv->inl_recv_size) {\n+\t\t\texp_device_attr.comp_mask = IBV_EXP_DEVICE_ATTR_INLINE_RECV_SZ;\n+\t\t\tif (ibv_exp_query_device(ctx, &exp_device_attr)) {\n+\t\t\t\tINFO(\"Couldn't query device for inline-receive capabilities.\");\n+\t\t\t\tpriv->inl_recv_size = 0;\n+\t\t\t} else {\n+\t\t\t\tif ((unsigned int)exp_device_attr.inline_recv_sz < priv->inl_recv_size) {\n+\t\t\t\t\tINFO(\"Max inline-receive(%d) < Requested inline-receive(%u)\",\n+\t\t\t\t\t\t\texp_device_attr.inline_recv_sz, priv->inl_recv_size);\n+\t\t\t\t\tpriv->inl_recv_size = exp_device_attr.inline_recv_sz;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tINFO(\"Set inline receive size to %u\", priv->inl_recv_size);\n+\t\t}\n+#endif /* INLINE_RECV */\n+\n+#ifdef MLX4_COMPAT_VMWARE\n+\t\tif (mlx4_getenv_int(\"MLX4_COMPAT_VMWARE\"))\n+\t\t\tpriv->vmware = 1;\n+#else /* MLX4_COMPAT_VMWARE */\n+\t\t(void)mlx4_getenv_int;\n+#endif /* MLX4_COMPAT_VMWARE */\n+\t\tpriv->vf = vf;\n+\t\tif (ibv_query_gid(ctx, port, 0, &temp_gid)) {\n+\t\t\tERROR(\"ibv_query_gid() failure\");\n+\t\t\tgoto port_error;\n+\t\t}\n+\t\t/* Configure the first MAC address by default. */\n+\t\tmac_from_gid(&mac.addr_bytes, port, temp_gid.raw);\n+\t\tINFO(\"port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x\",\n+\t\t priv->port,\n+\t\t mac.addr_bytes[0], mac.addr_bytes[1],\n+\t\t mac.addr_bytes[2], mac.addr_bytes[3],\n+\t\t mac.addr_bytes[4], mac.addr_bytes[5]);\n+\t\t/* Register MAC and broadcast addresses. */\n+\t\tclaim_zero(priv_mac_addr_add(priv, 0,\n+\t\t\t\t\t (const uint8_t (*)[ETHER_ADDR_LEN])\n+\t\t\t\t\t mac.addr_bytes));\n+\t\tclaim_zero(priv_mac_addr_add(priv, 1,\n+\t\t\t\t\t &(const uint8_t [ETHER_ADDR_LEN])\n+\t\t\t\t\t { \"\\xff\\xff\\xff\\xff\\xff\\xff\" }));\n+#ifndef NDEBUG\n+\t\t{\n+\t\t\tchar ifname[IF_NAMESIZE];\n+\n+\t\t\tif (priv_get_ifname(priv, &ifname) == 0)\n+\t\t\t\tDEBUG(\"port %u ifname is \\\"%s\\\"\", priv->port, ifname);\n+\t\t\telse\n+\t\t\t\tDEBUG(\"port %u ifname is unknown\", priv->port);\n+\t\t}\n+#endif\n+\t\t/* Get actual MTU if possible. */\n+\t\tpriv_get_mtu(priv, &priv->mtu);\n+\t\tDEBUG(\"port %u MTU is %u\", priv->port, priv->mtu);\n+\n+\t\t/* from rte_ethdev.c */\n+#if RTE_VERSION >= RTE_VERSION_NUM(1, 7, 0, 0)\n+\t\t{\n+\t\t\tchar name[RTE_ETH_NAME_MAX_LEN];\n+\n+\t\t\tsnprintf(name, sizeof(name), \"%s port %u\",\n+\t\t\t\t ibv_get_device_name(ibv_dev), port);\n+\t\t\teth_dev = rte_eth_dev_allocate(name);\n+\t\t}\n+#else\n+\t\teth_dev = rte_eth_dev_allocate();\n+#endif\n+\t\tif (eth_dev == NULL) {\n+\t\t\tERROR(\"can not allocate rte ethdev\");\n+\t\t\terr = ENOMEM;\n+\t\t\tgoto port_error;\n+\t\t}\n+\n+\t\teth_dev->data->dev_private = priv;\n+\t\teth_dev->pci_dev = pci_dev;\n+\t\teth_dev->driver = &mlx4_driver;\n+\t\teth_dev->data->rx_mbuf_alloc_failed = 0;\n+#if RTE_VERSION >= RTE_VERSION_NUM(1, 7, 0, 0)\n+\t\teth_dev->data->mtu = ETHER_MTU;\n+#else\n+\t\teth_dev->data->max_frame_size = ETHER_MAX_LEN;\n+#endif\n+\n+\t\tpriv->dev = eth_dev;\n+\t\teth_dev->dev_ops = &mlx4_dev_ops;\n+\t\teth_dev->data->mac_addrs = priv->mac;\n+\n+\t\t/* Bring Ethernet device up. */\n+\t\tDEBUG(\"forcing Ethernet interface up\");\n+\t\tpriv_set_flags(priv, ~IFF_UP, IFF_UP);\n+\t\tcontinue;\n+\n+port_error:\n+\t\tif (priv)\n+\t\t\trte_free(priv);\n+\t\tif (pd)\n+\t\t\tclaim_zero(ibv_dealloc_pd(pd));\n+\t\tif (ctx)\n+\t\t\tclaim_zero(ibv_close_device(ctx));\n+\t\tbreak;\n+\t}\n+\n+\t/*\n+\t * XXX if something went wrong in the loop above, there is a resource\n+\t * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as\n+\t * long as the dpdk does not provide a way to deallocate a ethdev and a\n+\t * way to enumerate the registered ethdevs to free the previous ones.\n+\t */\n+\n+\t/* no port found, complain */\n+\tif (!mlx4_dev[idx].ports) {\n+\t\terr = ENODEV;\n+\t\tgoto error;\n+\t}\n+\n+error:\n+\tif (attr_ctx)\n+\t\tclaim_zero(ibv_close_device(attr_ctx));\n+\tif (list)\n+\t\tibv_free_device_list(list);\n+\tassert(err >= 0);\n+\treturn -err;\n+}\n+\n+static struct rte_pci_id mlx4_pci_id_map[] = {\n+\t{\n+\t\t.vendor_id = PCI_VENDOR_ID_MELLANOX,\n+\t\t.device_id = PCI_DEVICE_ID_MELLANOX_CONNECTX3,\n+\t\t.subsystem_vendor_id = PCI_ANY_ID,\n+\t\t.subsystem_device_id = PCI_ANY_ID\n+\t},\n+\t{\n+\t\t.vendor_id = PCI_VENDOR_ID_MELLANOX,\n+\t\t.device_id = PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO,\n+\t\t.subsystem_vendor_id = PCI_ANY_ID,\n+\t\t.subsystem_device_id = PCI_ANY_ID\n+\t},\n+\t{\n+\t\t.vendor_id = PCI_VENDOR_ID_MELLANOX,\n+\t\t.device_id = PCI_DEVICE_ID_MELLANOX_CONNECTX3VF,\n+\t\t.subsystem_vendor_id = PCI_ANY_ID,\n+\t\t.subsystem_device_id = PCI_ANY_ID\n+\t},\n+\t{\n+\t\t.vendor_id = 0\n+\t}\n+};\n+\n+static struct eth_driver mlx4_driver = {\n+\t.pci_drv = {\n+\t\t.name = MLX4_DRIVER_NAME,\n+\t\t.id_table = mlx4_pci_id_map,\n+\t\t.devinit = mlx4_pci_devinit,\n+\t},\n+\t.dev_private_size = sizeof(struct priv)\n+};\n+\n+/**\n+ * Driver initialization routine.\n+ */\n+static int\n+rte_mlx4_pmd_init(const char *name, const char *args)\n+{\n+\t(void)name;\n+\t(void)args;\n+\trte_eal_pci_register(&mlx4_driver.pci_drv);\n+\treturn 0;\n+}\n+\n+static struct rte_driver rte_mlx4_driver = {\n+\t.type = PMD_PDEV,\n+\t.name = MLX4_DRIVER_NAME,\n+\t.init = rte_mlx4_pmd_init,\n+};\n+\n+PMD_REGISTER_DRIVER(rte_mlx4_driver)\ndiff --git a/lib/librte_pmd_mlx4/mlx4.h b/lib/librte_pmd_mlx4/mlx4.h\nnew file mode 100644\nindex 0000000..4743a64\n--- /dev/null\n+++ b/lib/librte_pmd_mlx4/mlx4.h\n@@ -0,0 +1,166 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2012-2015 6WIND S.A.\n+ * Copyright(c) 2012 Mellanox.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of 6WIND S.A. nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef RTE_PMD_MLX4_H_\n+#define RTE_PMD_MLX4_H_\n+\n+#include <stddef.h>\n+#include <stdint.h>\n+#include <limits.h>\n+\n+/*\n+ * Maximum number of simultaneous MAC addresses supported.\n+ *\n+ * According to ConnectX's Programmer Reference Manual:\n+ * The L2 Address Match is implemented by comparing a MAC/VLAN combination\n+ * of 128 MAC addresses and 127 VLAN values, comprising 128x127 possible\n+ * L2 addresses.\n+ */\n+#define MLX4_MAX_MAC_ADDRESSES 128\n+\n+/* Maximum number of simultaneous VLAN filters supported. See above. */\n+#define MLX4_MAX_VLAN_IDS 127\n+\n+/* Maximum number of Scatter/Gather Elements per Work Request. */\n+#ifndef MLX4_PMD_SGE_WR_N\n+#define MLX4_PMD_SGE_WR_N 4\n+#endif\n+\n+/* Maximum size for inline data. */\n+#ifndef MLX4_PMD_MAX_INLINE\n+#define MLX4_PMD_MAX_INLINE 0\n+#endif\n+\n+/*\n+ * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP\n+ * from which buffers are to be transmitted will have to be mapped by this\n+ * driver to their own Memory Region (MR). This is a slow operation.\n+ *\n+ * This value is always 1 for RX queues.\n+ */\n+#ifndef MLX4_PMD_TX_MP_CACHE\n+#define MLX4_PMD_TX_MP_CACHE 8\n+#endif\n+\n+/*\n+ * If defined, only use software counters. The PMD will never ask the hardware\n+ * for these, and many of them won't be available.\n+ */\n+#ifndef MLX4_PMD_SOFT_COUNTERS\n+#define MLX4_PMD_SOFT_COUNTERS 1\n+#endif\n+\n+/*\n+ * If defined, enable VMware compatibility code. It also requires the\n+ * environment variable MLX4_COMPAT_VMWARE set to a nonzero value at runtime.\n+ */\n+#ifndef MLX4_COMPAT_VMWARE\n+#define MLX4_COMPAT_VMWARE 1\n+#endif\n+\n+enum {\n+\tPCI_VENDOR_ID_MELLANOX = 0x15b3,\n+};\n+\n+enum {\n+\tPCI_DEVICE_ID_MELLANOX_CONNECTX3 = 0x1003,\n+\tPCI_DEVICE_ID_MELLANOX_CONNECTX3VF = 0x1004,\n+\tPCI_DEVICE_ID_MELLANOX_CONNECTX3PRO = 0x1007,\n+};\n+\n+#define MLX4_DRIVER_NAME \"librte_pmd_mlx4\"\n+\n+/* Bit-field manipulation. */\n+#define BITFIELD_DECLARE(bf, type, size)\t\t\t\t\\\n+\ttype bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) +\t\t\\\n+\t\t !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]\n+#define BITFIELD_DEFINE(bf, type, size)\t\t\t\t\t\\\n+\tBITFIELD_DECLARE((bf), type, (size)) = { 0 }\n+#define BITFIELD_SET(bf, b)\t\t\t\t\t\t\\\n+\t(assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)),\t\t\t\\\n+\t (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |=\t\t\\\n+\t\t((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))\n+#define BITFIELD_RESET(bf, b)\t\t\t\t\t\t\\\n+\t(assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)),\t\t\t\\\n+\t (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &=\t\t\\\n+\t\t~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))\n+#define BITFIELD_ISSET(bf, b)\t\t\t\t\t\t\\\n+\t(assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)),\t\t\t\\\n+\t !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &\t\t\\\n+\t ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))))\n+\n+/* Number of elements in array. */\n+#define elemof(a) (sizeof(a) / sizeof((a)[0]))\n+\n+/* Cast pointer p to structure member m to its parent structure of type t. */\n+#define containerof(p, t, m) ((t *)((uint8_t *)(p) - offsetof(t, m)))\n+\n+/* Branch prediction helpers. */\n+#ifndef likely\n+#define likely(c) __builtin_expect(!!(c), 1)\n+#endif\n+#ifndef unlikely\n+#define unlikely(c) __builtin_expect(!!(c), 0)\n+#endif\n+\n+/* Debugging */\n+#ifndef NDEBUG\n+#include <stdio.h>\n+#define DEBUG__(m, ...)\t\t\t\t\t\t\\\n+\t(fprintf(stderr, \"%s:%d: %s(): \" m \"%c\",\t\t\\\n+\t\t __FILE__, __LINE__, __func__, __VA_ARGS__),\t\\\n+\t fflush(stderr),\t\t\t\t\t\\\n+\t (void)0)\n+/*\n+ * Save/restore errno around DEBUG__().\n+ * XXX somewhat undefined behavior, but works.\n+ */\n+#define DEBUG_(...)\t\t\t\t\\\n+\t(errno = ((int []){\t\t\t\\\n+\t\t*(volatile int *)&errno,\t\\\n+\t\t(DEBUG__(__VA_ARGS__), 0)\t\\\n+\t})[0])\n+#define DEBUG(...) DEBUG_(__VA_ARGS__, '\\n')\n+#define claim_zero(...) assert((__VA_ARGS__) == 0)\n+#define claim_nonzero(...) assert((__VA_ARGS__) != 0)\n+#define claim_positive(...) assert((__VA_ARGS__) >= 0)\n+#else /* NDEBUG */\n+/* No-ops. */\n+#define DEBUG(...) (void)0\n+#define claim_zero(...) (__VA_ARGS__)\n+#define claim_nonzero(...) (__VA_ARGS__)\n+#define claim_positive(...) (__VA_ARGS__)\n+#endif /* NDEBUG */\n+\n+#endif /* RTE_PMD_MLX4_H_ */\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 4294d9a..07a1ebb 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -135,6 +135,10 @@ ifeq ($(CONFIG_RTE_LIBRTE_VHOST),y)\n LDLIBS += -lfuse\n endif\n \n+ifeq ($(CONFIG_RTE_LIBRTE_MLX4_PMD),y)\n+LDLIBS += -libverbs\n+endif\n+\n LDLIBS += --start-group\n \n ifeq ($(CONFIG_RTE_BUILD_COMBINE_LIBS),n)\n@@ -219,6 +223,10 @@ ifeq ($(CONFIG_RTE_LIBRTE_E1000_PMD),y)\n LDLIBS += -lrte_pmd_e1000\n endif\n \n+ifeq ($(CONFIG_RTE_LIBRTE_MLX4_PMD),y)\n+LDLIBS += -lrte_pmd_mlx4\n+endif\n+\n ifeq ($(CONFIG_RTE_LIBRTE_PMD_RING),y)\n LDLIBS += -lrte_pmd_ring\n endif\n", "prefixes": [ "dpdk-dev", "2/2" ] }