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GET /api/patches/28368/?format=api
HTTP 200 OK
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{
    "id": 28368,
    "url": "https://patches.dpdk.org/api/patches/28368/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1504611516-27404-3-git-send-email-pbhagavatula@caviumnetworks.com/",
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    "date": "2017-09-05T11:38:36",
    "name": "[dpdk-dev,v5,3/3] test: add tests for reciprocal based division",
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        "name": "Pavan Nikhilesh",
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        "Cc": "dev@dpdk.org,\n\tPavan Bhagavatula <pbhagavatula@caviumnetworks.com>",
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        "Subject": "[dpdk-dev] [PATCH v5 3/3] test: add tests for reciprocal based\n\tdivision",
        "X-BeenThere": "dev@dpdk.org",
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    "content": "From: Pavan Bhagavatula <pbhagavatula@caviumnetworks.com>\n\nThis commit provides a set of tests for verifying the correctness and\nperformance of both unsigned 32 and 64bit reciprocal based division.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>\n---\n test/test/Makefile                        |   2 +\n test/test/test_reciprocal_division.c      | 109 +++++++++++++++++\n test/test/test_reciprocal_division_perf.c | 193 ++++++++++++++++++++++++++++++\n 3 files changed, 304 insertions(+)\n create mode 100644 test/test/test_reciprocal_division.c\n create mode 100644 test/test/test_reciprocal_division_perf.c",
    "diff": "diff --git a/test/test/Makefile b/test/test/Makefile\nindex 42d9a49..6017862 100644\n--- a/test/test/Makefile\n+++ b/test/test/Makefile\n@@ -94,6 +94,8 @@ SRCS-y += test_cycles.c\n SRCS-y += test_spinlock.c\n SRCS-y += test_memory.c\n SRCS-y += test_memzone.c\n+SRCS-y += test_reciprocal_division.c\n+SRCS-y += test_reciprocal_division_perf.c\n \n SRCS-y += test_ring.c\n SRCS-y += test_ring_perf.c\ndiff --git a/test/test/test_reciprocal_division.c b/test/test/test_reciprocal_division.c\nnew file mode 100644\nindex 0000000..771ea64\n--- /dev/null\n+++ b/test/test/test_reciprocal_division.c\n@@ -0,0 +1,109 @@\n+/*\n+ *   BSD LICENSE\n+ *\n+ *   Copyright (C) Cavium, Inc. 2017.\n+ *\n+ *   Redistribution and use in source and binary forms, with or without\n+ *   modification, are permitted provided that the following conditions\n+ *   are met:\n+ *\n+ *     * Redistributions of source code must retain the above copyright\n+ *       notice, this list of conditions and the following disclaimer.\n+ *     * Redistributions in binary form must reproduce the above copyright\n+ *       notice, this list of conditions and the following disclaimer in\n+ *       the documentation and/or other materials provided with the\n+ *       distribution.\n+ *     * Neither the name of Cavium, Inc nor the names of its\n+ *       contributors may be used to endorse or promote products derived\n+ *       from this software without specific prior written permission.\n+ *\n+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include \"test.h\"\n+\n+#include <stdio.h>\n+#include <unistd.h>\n+#include <inttypes.h>\n+\n+#include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_random.h>\n+#include <rte_reciprocal.h>\n+\n+#define MAX_ITERATIONS\t1000000\n+#define DIVIDE_ITER\t\t100\n+\n+static int\n+test_reciprocal_division(void)\n+{\n+\tint i;\n+\tint result = 0;\n+\tuint32_t divisor_u32 = 0;\n+\tuint32_t dividend_u32;\n+\tuint32_t nresult_u32;\n+\tuint32_t rresult_u32;\n+\tuint64_t divisor_u64 = 0;\n+\tuint64_t dividend_u64;\n+\tuint64_t nresult_u64;\n+\tuint64_t rresult_u64;\n+\tstruct rte_reciprocal_u32 reci_u32;\n+\tstruct rte_reciprocal_u64 reci_u64;\n+\n+\trte_srand(rte_rdtsc());\n+\tprintf(\"Validating unsigned 32bit division.\\n\");\n+\tfor (i = 0; i < MAX_ITERATIONS; i++) {\n+\t\t/* Change divisor every DIVIDE_ITER iterations. */\n+\t\tif (i % DIVIDE_ITER == 0) {\n+\t\t\tdivisor_u32 = rte_rand();\n+\t\t\treci_u32 = rte_reciprocal_value_u32(divisor_u32);\n+\t\t}\n+\n+\t\tdividend_u32 = rte_rand();\n+\t\tnresult_u32 = dividend_u32 / divisor_u32;\n+\t\trresult_u32 = rte_reciprocal_divide_u32(dividend_u32,\n+\t\t\t\t&reci_u32);\n+\t\tif (nresult_u32 != rresult_u32) {\n+\t\t\tprintf(\"Division failed, expected %\"PRIu32\" \"\n+\t\t\t\t   \"result %\"PRIu32\"\",\n+\t\t\t\t\tnresult_u32, rresult_u32);\n+\t\t\tresult = 1;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tprintf(\"Validating unsigned 64bit division.\\n\");\n+\tfor (i = 0; i < MAX_ITERATIONS; i++) {\n+\t\t/* Change divisor every DIVIDE_ITER iterations. */\n+\t\tif (i % DIVIDE_ITER == 0) {\n+\t\t\tdivisor_u64 = rte_rand();\n+\t\t\treci_u64 = rte_reciprocal_value_u64(divisor_u64);\n+\t\t}\n+\n+\t\tdividend_u64 = rte_rand();\n+\t\tnresult_u64 = dividend_u64 / divisor_u64;\n+\t\trresult_u64 = rte_reciprocal_divide_u64(dividend_u64,\n+\t\t\t\t&reci_u64);\n+\t\tif (nresult_u64 != rresult_u64) {\n+\t\t\tprintf(\"Division failed, expected %\"PRIu64\" \"\n+\t\t\t\t   \"result %\"PRIu64\"\",\n+\t\t\t\t\tnresult_u64, rresult_u64);\n+\t\t\tresult = 1;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn result;\n+}\n+\n+REGISTER_TEST_COMMAND(reciprocal_division, test_reciprocal_division);\ndiff --git a/test/test/test_reciprocal_division_perf.c b/test/test/test_reciprocal_division_perf.c\nnew file mode 100644\nindex 0000000..3eaf575\n--- /dev/null\n+++ b/test/test/test_reciprocal_division_perf.c\n@@ -0,0 +1,193 @@\n+/*\n+ *   BSD LICENSE\n+ *\n+ *   Copyright (C) Cavium, Inc. 2017.\n+ *\n+ *   Redistribution and use in source and binary forms, with or without\n+ *   modification, are permitted provided that the following conditions\n+ *   are met:\n+ *\n+ *     * Redistributions of source code must retain the above copyright\n+ *       notice, this list of conditions and the following disclaimer.\n+ *     * Redistributions in binary form must reproduce the above copyright\n+ *       notice, this list of conditions and the following disclaimer in\n+ *       the documentation and/or other materials provided with the\n+ *       distribution.\n+ *     * Neither the name of Cavium, Inc nor the names of its\n+ *       contributors may be used to endorse or promote products derived\n+ *       from this software without specific prior written permission.\n+ *\n+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include \"test.h\"\n+\n+#include <stdio.h>\n+#include <unistd.h>\n+#include <inttypes.h>\n+\n+#include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_random.h>\n+#include <rte_reciprocal.h>\n+\n+#define MAX_ITERATIONS\t1000000\n+#define DIVIDE_ITER\t\t100\n+\n+static int\n+test_reciprocal_division_perf(void)\n+{\n+\tint result = 0;\n+\tuint32_t divisor_u32 = 0;\n+\tvolatile uint32_t dividend_u32;\n+\tuint32_t nresult_u32;\n+\tuint32_t rresult_u32;\n+\tuint64_t divisor_u64 = 0;\n+\tvolatile uint64_t dividend_u64;\n+\tuint64_t nresult_u64;\n+\tuint64_t rresult_u64;\n+\tuint64_t start_cyc;\n+\tuint64_t split_cyc;\n+\tuint64_t end_cyc;\n+\tuint64_t tot_cyc_n = 0;\n+\tuint64_t tot_cyc_r = 0;\n+\tuint64_t i;\n+\tstruct rte_reciprocal_u32 reci_u32 = {0};\n+\tstruct rte_reciprocal_u64 reci_u64 = {0};\n+\n+\trte_srand(rte_rdtsc());\n+\n+\tprintf(\"Validating unsigned 32bit division.\\n\");\n+\n+\tfor (i = 0; i < MAX_ITERATIONS; i++) {\n+\t\t/* Change divisor every DIVIDE_ITER iterations. */\n+\t\tif (i % DIVIDE_ITER == 0) {\n+\t\t\tdivisor_u32 = rte_rand();\n+\t\t\treci_u32 = rte_reciprocal_value_u32(divisor_u32);\n+\t\t}\n+\n+\t\tdividend_u32 = rte_rand();\n+\n+\t\tstart_cyc = rte_rdtsc();\n+\t\tnresult_u32 = dividend_u32 / divisor_u32;\n+\t\tsplit_cyc = rte_rdtsc();\n+\t\trresult_u32 = rte_reciprocal_divide_u32(dividend_u32,\n+\t\t\t\t&reci_u32);\n+\t\tend_cyc = rte_rdtsc();\n+\n+\t\ttot_cyc_n += split_cyc - start_cyc;\n+\t\ttot_cyc_r += end_cyc - split_cyc;\n+\t\tif (nresult_u32 != rresult_u32) {\n+\t\t\tprintf(\"Division failed, expected %\"PRIu32\" \"\n+\t\t\t\t\t\"result %\"PRIu32\"\",\n+\t\t\t\t\tnresult_u32, rresult_u32);\n+\t\t\tresult = 1;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tprintf(\"32bit Division results:\\n\");\n+\tprintf(\"Total number of cycles normal division     : %\"PRIu64\"\\n\",\n+\t\t\ttot_cyc_n);\n+\tprintf(\"Total number of cycles reciprocal division : %\"PRIu64\"\\n\",\n+\t\t\ttot_cyc_r);\n+\tprintf(\"Cycles per division(normal) : %3.2f\\n\",\n+\t\t\t((double)tot_cyc_n)/i);\n+\tprintf(\"Cycles per division(reciprocal) : %3.2f\\n\\n\",\n+\t\t\t((double)tot_cyc_r)/i);\n+\n+\ttot_cyc_n = 0;\n+\ttot_cyc_r = 0;\n+\n+\tprintf(\"Validating unsigned 64bit division.\\n\");\n+\n+\tfor (i = 0; i < MAX_ITERATIONS; i++) {\n+\t\t/* Change divisor every DIVIDE_ITER iterations. */\n+\t\tif (i % DIVIDE_ITER == 0) {\n+\t\t\tdivisor_u64 = rte_rand();\n+\t\t\treci_u64 = rte_reciprocal_value_u64(divisor_u64);\n+\t\t}\n+\n+\t\tdividend_u64 = rte_rand();\n+\n+\t\tstart_cyc = rte_rdtsc();\n+\t\tnresult_u64 = dividend_u64 / divisor_u64;\n+\t\tsplit_cyc = rte_rdtsc();\n+\t\trresult_u64 = rte_reciprocal_divide_u64(dividend_u64,\n+\t\t\t\t&reci_u64);\n+\t\tend_cyc = rte_rdtsc();\n+\n+\t\ttot_cyc_n += split_cyc - start_cyc;\n+\t\ttot_cyc_r += end_cyc - split_cyc;\n+\t\tif (nresult_u64 != rresult_u64) {\n+\t\t\tprintf(\"Division failed, expected %\"PRIu64\" \"\n+\t\t\t\t\t\"result %\"PRIu64\"\",\n+\t\t\t\t\tnresult_u64, rresult_u64);\n+\t\t\tresult = 1;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tprintf(\"64bit Division results:\\n\");\n+\tprintf(\"Total number of cycles normal division     : %\"PRIu64\"\\n\",\n+\t\t\ttot_cyc_n);\n+\tprintf(\"Total number of cycles reciprocal division : %\"PRIu64\"\\n\",\n+\t\t\ttot_cyc_r);\n+\tprintf(\"Cycles per division(normal) : %3.2f\\n\",\n+\t\t\t((double)tot_cyc_n)/i);\n+\tprintf(\"Cycles per division(reciprocal) : %3.2f\\n\\n\",\n+\t\t\t((double)tot_cyc_r)/i);\n+\n+\ttot_cyc_n = 0;\n+\ttot_cyc_r = 0;\n+\n+\tprintf(\"Validating unsigned 64bit division with 32bit divisor.\\n\");\n+\n+\tfor (i = 0; i < MAX_ITERATIONS; i++) {\n+\t\t/* Change divisor every DIVIDE_ITER iterations. */\n+\t\tif (i % DIVIDE_ITER == 0) {\n+\t\t\tdivisor_u64 = rte_rand() >> 32;\n+\t\t\treci_u64 = rte_reciprocal_value_u64(divisor_u64);\n+\t\t}\n+\n+\t\tdividend_u64 = rte_rand();\n+\n+\t\tstart_cyc = rte_rdtsc();\n+\t\tnresult_u64 = dividend_u64 / divisor_u64;\n+\t\tsplit_cyc = rte_rdtsc();\n+\t\trresult_u64 = rte_reciprocal_divide_u64(dividend_u64,\n+\t\t\t\t&reci_u64);\n+\t\tend_cyc = rte_rdtsc();\n+\n+\t\ttot_cyc_n += split_cyc - start_cyc;\n+\t\ttot_cyc_r += end_cyc - split_cyc;\n+\t\tif (nresult_u64 != rresult_u64) {\n+\t\t\tprintf(\"Division failed, expected %\"PRIu64\" \"\n+\t\t\t\t\t\"result %\"PRIu64\"\",\n+\t\t\t\t\tnresult_u64, rresult_u64);\n+\t\t\tresult = 1;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tprintf(\"64bit Division results:\\n\");\n+\tprintf(\"Total number of cycles normal division     : %\"PRIu64\"\\n\",\n+\t\t\ttot_cyc_n);\n+\tprintf(\"Total number of cycles reciprocal division : %\"PRIu64\"\\n\",\n+\t\t\ttot_cyc_r);\n+\tprintf(\"Cycles per division(normal) : %3.2f\\n\",\n+\t\t\t((double)tot_cyc_n)/i);\n+\tprintf(\"Cycles per division(reciprocal) : %3.2f\\n\",\n+\t\t\t((double)tot_cyc_r)/i);\n+\n+\treturn result;\n+}\n+\n+REGISTER_TEST_COMMAND(reciprocal_division_perf, test_reciprocal_division_perf);\n",
    "prefixes": [
        "dpdk-dev",
        "v5",
        "3/3"
    ]
}