Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/26384/?format=api
{ "id": 26384, "url": "https://patches.dpdk.org/api/patches/26384/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1499179471-19145-4-git-send-email-shreyansh.jain@nxp.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1499179471-19145-4-git-send-email-shreyansh.jain@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1499179471-19145-4-git-send-email-shreyansh.jain@nxp.com", "date": "2017-07-04T14:43:54", "name": "[dpdk-dev,v2,03/40] bus/dpaa: add compatibility and helper macros", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f441b94db05ea2de6911d836933f0c69b3a2cc22", "submitter": { "id": 497, "url": "https://patches.dpdk.org/api/people/497/?format=api", "name": "Shreyansh Jain", "email": "shreyansh.jain@nxp.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1499179471-19145-4-git-send-email-shreyansh.jain@nxp.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/26384/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/26384/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 032FB7CB1;\n\tTue, 4 Jul 2017 16:35:37 +0200 (CEST)", "from NAM03-DM3-obe.outbound.protection.outlook.com\n\t(mail-dm3nam03on0064.outbound.protection.outlook.com [104.47.41.64])\n\tby dpdk.org (Postfix) with ESMTP id F0CA97CA9\n\tfor <dev@dpdk.org>; Tue, 4 Jul 2017 16:35:34 +0200 (CEST)", "from BN6PR03CA0070.namprd03.prod.outlook.com (10.173.137.32) by\n\tBN1PR0301MB0595.namprd03.prod.outlook.com (10.160.170.22) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n\t15.1.1220.11; Tue, 4 Jul 2017 14:35:32 +0000", "from BL2FFO11FD052.protection.gbl (2a01:111:f400:7c09::157) by\n\tBN6PR03CA0070.outlook.office365.com (2603:10b6:404:4c::32) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1220.11\n\tvia Frontend Transport; Tue, 4 Jul 2017 14:35:32 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBL2FFO11FD052.mail.protection.outlook.com (10.173.161.214) with\n\tMicrosoft\n\tSMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id\n\t15.1.1199.9 via Frontend Transport; Tue, 4 Jul 2017 14:35:31 +0000", "from Tophie.ap.freescale.net ([10.232.14.39])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv64EZM6l016426; Tue, 4 Jul 2017 07:35:29 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "From": "Shreyansh Jain <shreyansh.jain@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>, <hemant.agrawal@nxp.com>", "Date": "Tue, 4 Jul 2017 20:13:54 +0530", "Message-ID": "<1499179471-19145-4-git-send-email-shreyansh.jain@nxp.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1499179471-19145-1-git-send-email-shreyansh.jain@nxp.com>", "References": "<1497591668-3320-1-git-send-email-shreyansh.jain@nxp.com>\n\t<1499179471-19145-1-git-send-email-shreyansh.jain@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131436525320542418;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BN1PR0301MB0595; ", "X-Forefront-PRVS": "0358535363", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Jul 2017 14:35:31.6798\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.158.2]; \n\tHelo=[az84smr01.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN1PR0301MB0595", "Subject": "[dpdk-dev] [PATCH v2 03/40] bus/dpaa: add compatibility and helper\n\tmacros", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Hemant Agrawal <hemant.agrawal@nxp.com>\n\nLinked list, bit operations and compatibility macros.\n\nSigned-off-by: Geoff Thorpe <geoff.thorpe@nxp.com>\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n drivers/bus/dpaa/include/compat.h | 383 +++++++++++++++++++++++++++++++++++\n drivers/bus/dpaa/include/dpaa_bits.h | 65 ++++++\n drivers/bus/dpaa/include/dpaa_list.h | 101 +++++++++\n 3 files changed, 549 insertions(+)\n create mode 100644 drivers/bus/dpaa/include/compat.h\n create mode 100644 drivers/bus/dpaa/include/dpaa_bits.h\n create mode 100644 drivers/bus/dpaa/include/dpaa_list.h", "diff": "diff --git a/drivers/bus/dpaa/include/compat.h b/drivers/bus/dpaa/include/compat.h\nnew file mode 100644\nindex 0000000..3d46232\n--- /dev/null\n+++ b/drivers/bus/dpaa/include/compat.h\n@@ -0,0 +1,383 @@\n+/*-\n+ * This file is provided under a dual BSD/GPLv2 license. When using or\n+ * redistributing this file, you may do so under either license.\n+ *\n+ * BSD LICENSE\n+ *\n+ * Copyright 2011 Freescale Semiconductor, Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ * GPL LICENSE SUMMARY\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __COMPAT_H\n+#define __COMPAT_H\n+\n+#include <sched.h>\n+\n+#ifndef _GNU_SOURCE\n+#define _GNU_SOURCE\n+#endif\n+#include <stdint.h>\n+#include <stdlib.h>\n+#include <stddef.h>\n+#include <stdio.h>\n+#include <errno.h>\n+#include <string.h>\n+#include <pthread.h>\n+#include <linux/types.h>\n+#include <stdbool.h>\n+#include <ctype.h>\n+#include <malloc.h>\n+#include <sys/types.h>\n+#include <sys/stat.h>\n+#include <fcntl.h>\n+#include <unistd.h>\n+#include <sys/mman.h>\n+#include <limits.h>\n+#include <assert.h>\n+#include <dirent.h>\n+#include <inttypes.h>\n+#include <error.h>\n+#include <rte_byteorder.h>\n+#include <rte_atomic.h>\n+#include <rte_spinlock.h>\n+#include <rte_common.h>\n+#include <rte_debug.h>\n+\n+/* The following definitions are primarily to allow the single-source driver\n+ * interfaces to be included by arbitrary program code. Ie. for interfaces that\n+ * are also available in kernel-space, these definitions provide compatibility\n+ * with certain attributes and types used in those interfaces.\n+ */\n+\n+/* Required compiler attributes */\n+#define __maybe_unused\t__rte_unused\n+#define __always_unused\t__rte_unused\n+#define __packed\t__rte_packed\n+#define noinline\t__attribute__((noinline))\n+\n+#define L1_CACHE_BYTES 64\n+#define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))\n+#define __stringify_1(x) #x\n+#define __stringify(x)\t__stringify_1(x)\n+\n+#ifdef ARRAY_SIZE\n+#undef ARRAY_SIZE\n+#endif\n+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))\n+\n+/* Debugging */\n+#define prflush(fmt, args...) \\\n+\tdo { \\\n+\t\tprintf(fmt, ##args); \\\n+\t\tfflush(stdout); \\\n+\t} while (0)\n+\n+#define pr_crit(fmt, args...)\t prflush(\"CRIT:\" fmt, ##args)\n+#define pr_err(fmt, args...)\t prflush(\"ERR:\" fmt, ##args)\n+#define pr_warn(fmt, args...)\t prflush(\"WARN:\" fmt, ##args)\n+#define pr_info(fmt, args...)\t prflush(fmt, ##args)\n+\n+#define ASSERT(x) do {\\\n+\tif (!(x)) \\\n+\t\trte_panic(\"DPAA: x\"); \\\n+} while (0)\n+#define BUG_ON(x) ASSERT(!(x))\n+\n+/* Required types */\n+typedef uint8_t\t\tu8;\n+typedef uint16_t\tu16;\n+typedef uint32_t\tu32;\n+typedef uint64_t\tu64;\n+typedef uint64_t\tdma_addr_t;\n+typedef cpu_set_t\tcpumask_t;\n+typedef uint32_t\tphandle;\n+typedef uint32_t\tgfp_t;\n+typedef uint32_t\tirqreturn_t;\n+\n+#define IRQ_HANDLED\t0\n+#define request_irq\tqbman_request_irq\n+#define free_irq\tqbman_free_irq\n+\n+#define __iomem\n+#define GFP_KERNEL\t0\n+#define __raw_readb(p)\t(*(const volatile unsigned char *)(p))\n+#define __raw_readl(p)\t(*(const volatile unsigned int *)(p))\n+#define __raw_writel(v, p) {*(volatile unsigned int *)(p) = (v); }\n+\n+/* SMP stuff */\n+#define DEFINE_PER_CPU(t, x)\t__thread t per_cpu__##x\n+#define get_cpu_var(x)\t\tper_cpu__##x\n+/* to be used as an upper-limit only */\n+#define NR_CPUS\t\t\t64\n+\n+/* Waitqueue stuff */\n+typedef struct { }\t\twait_queue_head_t;\n+#define DECLARE_WAIT_QUEUE_HEAD(x) int dummy_##x __always_unused\n+#define wake_up(x)\t\tdo { } while (0)\n+\n+/* I/O operations */\n+static inline u32 in_be32(volatile void *__p)\n+{\n+\tvolatile u32 *p = __p;\n+\treturn rte_be_to_cpu_32(*p);\n+}\n+\n+static inline void out_be32(volatile void *__p, u32 val)\n+{\n+\tvolatile u32 *p = __p;\n+\t*p = rte_cpu_to_be_32(val);\n+}\n+\n+#define dcbt_ro(p) __builtin_prefetch(p, 0)\n+#define dcbt_rw(p) __builtin_prefetch(p, 1)\n+\n+#define dcbz(p) { asm volatile(\"dc zva, %0\" : : \"r\" (p) : \"memory\"); }\n+#define dcbz_64(p) dcbz(p)\n+#define hwsync() rte_rmb()\n+#define lwsync() rte_wmb()\n+#define dcbf(p) { asm volatile(\"dc cvac, %0\" : : \"r\"(p) : \"memory\"); }\n+#define dcbf_64(p) dcbf(p)\n+#define dccivac(p) { asm volatile(\"dc civac, %0\" : : \"r\"(p) : \"memory\"); }\n+\n+#define dcbit_ro(p) \\\n+\tdo { \\\n+\t\tdccivac(p);\t\t\t\t\t\t\\\n+\t\tasm volatile(\"prfm pldl1keep, [%0, #64]\" : : \"r\" (p));\t\\\n+\t} while (0)\n+\n+#define barrier() { asm volatile (\"\" : : : \"memory\"); }\n+#define cpu_relax barrier\n+\n+static inline uint64_t mfatb(void)\n+{\n+\tuint64_t ret, ret_new, timeout = 200;\n+\n+\tasm volatile (\"mrs %0, cntvct_el0\" : \"=r\" (ret));\n+\tasm volatile (\"mrs %0, cntvct_el0\" : \"=r\" (ret_new));\n+\twhile (ret != ret_new && timeout--) {\n+\t\tret = ret_new;\n+\t\tasm volatile (\"mrs %0, cntvct_el0\" : \"=r\" (ret_new));\n+\t}\n+\tBUG_ON(!timeout && (ret != ret_new));\n+\treturn ret * 64;\n+}\n+\n+/* Spin for a few cycles without bothering the bus */\n+static inline void cpu_spin(int cycles)\n+{\n+\tuint64_t now = mfatb();\n+\n+\twhile (mfatb() < (now + cycles))\n+\t\t;\n+}\n+\n+/* Qman/Bman API inlines and macros; */\n+#ifdef lower_32_bits\n+#undef lower_32_bits\n+#endif\n+#define lower_32_bits(x) ((u32)(x))\n+\n+#ifdef upper_32_bits\n+#undef upper_32_bits\n+#endif\n+#define upper_32_bits(x) ((u32)(((x) >> 16) >> 16))\n+\n+/*\n+ * Swap bytes of a 48-bit value.\n+ */\n+static inline uint64_t\n+__bswap_48(uint64_t x)\n+{\n+\treturn ((x & 0x0000000000ffULL) << 40) |\n+\t\t((x & 0x00000000ff00ULL) << 24) |\n+\t\t((x & 0x000000ff0000ULL) << 8) |\n+\t\t((x & 0x0000ff000000ULL) >> 8) |\n+\t\t((x & 0x00ff00000000ULL) >> 24) |\n+\t\t((x & 0xff0000000000ULL) >> 40);\n+}\n+\n+/*\n+ * Swap bytes of a 40-bit value.\n+ */\n+static inline uint64_t\n+__bswap_40(uint64_t x)\n+{\n+\treturn ((x & 0x00000000ffULL) << 32) |\n+\t\t((x & 0x000000ff00ULL) << 16) |\n+\t\t((x & 0x0000ff0000ULL)) |\n+\t\t((x & 0x00ff000000ULL) >> 16) |\n+\t\t((x & 0xff00000000ULL) >> 32);\n+}\n+\n+/*\n+ * Swap bytes of a 24-bit value.\n+ */\n+static inline uint32_t\n+__bswap_24(uint32_t x)\n+{\n+\treturn ((x & 0x0000ffULL) << 16) |\n+\t\t((x & 0x00ff00ULL)) |\n+\t\t((x & 0xff0000ULL) >> 16);\n+}\n+\n+#define be64_to_cpu(x) rte_be_to_cpu_64(x)\n+#define be32_to_cpu(x) rte_be_to_cpu_32(x)\n+#define be16_to_cpu(x) rte_be_to_cpu_16(x)\n+\n+#define cpu_to_be64(x) rte_cpu_to_be_64(x)\n+#define cpu_to_be32(x) rte_cpu_to_be_32(x)\n+#define cpu_to_be16(x) rte_cpu_to_be_16(x)\n+\n+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+\n+#define cpu_to_be48(x) __bswap_48(x)\n+#define be48_to_cpu(x) __bswap_48(x)\n+\n+#define cpu_to_be40(x) __bswap_40(x)\n+#define be40_to_cpu(x) __bswap_40(x)\n+\n+#define cpu_to_be24(x) __bswap_24(x)\n+#define be24_to_cpu(x) __bswap_24(x)\n+\n+#else /* RTE_BIG_ENDIAN */\n+\n+#define cpu_to_be48(x) (x)\n+#define be48_to_cpu(x) (x)\n+\n+#define cpu_to_be40(x) (x)\n+#define be40_to_cpu(x) (x)\n+\n+#define cpu_to_be24(x) (x)\n+#define be24_to_cpu(x) (x)\n+\n+#endif /* RTE_BIG_ENDIAN */\n+\n+/* When copying aligned words or shorts, try to avoid memcpy() */\n+/* memcpy() stuff - when you know alignments in advance */\n+#define CONFIG_TRY_BETTER_MEMCPY\n+\n+#ifdef CONFIG_TRY_BETTER_MEMCPY\n+static inline void copy_words(void *dest, const void *src, size_t sz)\n+{\n+\tu32 *__dest = dest;\n+\tconst u32 *__src = src;\n+\tsize_t __sz = sz >> 2;\n+\n+\tBUG_ON((unsigned long)dest & 0x3);\n+\tBUG_ON((unsigned long)src & 0x3);\n+\tBUG_ON(sz & 0x3);\n+\twhile (__sz--)\n+\t\t*(__dest++) = *(__src++);\n+}\n+\n+static inline void copy_shorts(void *dest, const void *src, size_t sz)\n+{\n+\tu16 *__dest = dest;\n+\tconst u16 *__src = src;\n+\tsize_t __sz = sz >> 1;\n+\n+\tBUG_ON((unsigned long)dest & 0x1);\n+\tBUG_ON((unsigned long)src & 0x1);\n+\tBUG_ON(sz & 0x1);\n+\twhile (__sz--)\n+\t\t*(__dest++) = *(__src++);\n+}\n+\n+static inline void copy_bytes(void *dest, const void *src, size_t sz)\n+{\n+\tu8 *__dest = dest;\n+\tconst u8 *__src = src;\n+\n+\twhile (sz--)\n+\t\t*(__dest++) = *(__src++);\n+}\n+#else\n+#define copy_words memcpy\n+#define copy_shorts memcpy\n+#define copy_bytes memcpy\n+#endif\n+\n+/* Allocator stuff */\n+#define kmalloc(sz, t)\tmalloc(sz)\n+#define vmalloc(sz)\tmalloc(sz)\n+#define kfree(p)\t{ if (p) free(p); }\n+static inline void *kzalloc(size_t sz, gfp_t __foo __rte_unused)\n+{\n+\tvoid *ptr = malloc(sz);\n+\n+\tif (ptr)\n+\t\tmemset(ptr, 0, sz);\n+\treturn ptr;\n+}\n+\n+static inline unsigned long get_zeroed_page(gfp_t __foo __rte_unused)\n+{\n+\tvoid *p;\n+\n+\tif (posix_memalign(&p, 4096, 4096))\n+\t\treturn 0;\n+\tmemset(p, 0, 4096);\n+\treturn (unsigned long)p;\n+}\n+\n+/* Spinlock stuff */\n+#define spinlock_t\t\trte_spinlock_t\n+#define __SPIN_LOCK_UNLOCKED(x)\tRTE_SPINLOCK_INITIALIZER\n+#define DEFINE_SPINLOCK(x)\tspinlock_t x = __SPIN_LOCK_UNLOCKED(x)\n+#define spin_lock_init(x)\trte_spinlock_init(x)\n+#define spin_lock_destroy(x)\n+#define spin_lock(x)\t\trte_spinlock_lock(x)\n+#define spin_unlock(x)\t\trte_spinlock_unlock(x)\n+#define spin_lock_irq(x)\tspin_lock(x)\n+#define spin_unlock_irq(x)\tspin_unlock(x)\n+#define spin_lock_irqsave(x, f) spin_lock_irq(x)\n+#define spin_unlock_irqrestore(x, f) spin_unlock_irq(x)\n+\n+#define atomic_t rte_atomic32_t\n+#define atomic_read(v) rte_atomic32_read(v)\n+#define atomic_set(v, i) rte_atomic32_set(v, i)\n+\n+#define atomic_inc(v) rte_atomic32_add(v, 1)\n+#define atomic_dec(v) rte_atomic32_sub(v, 1)\n+\n+#define atomic_inc_and_test(v) rte_atomic32_inc_and_test(v)\n+#define atomic_dec_and_test(v) rte_atomic32_dec_and_test(v)\n+\n+#define atomic_inc_return(v) rte_atomic32_add_return(v, 1)\n+#define atomic_dec_return(v) rte_atomic32_sub_return(v, 1)\n+#define atomic_sub_and_test(i, v) (rte_atomic32_sub_return(v, i) == 0)\n+\n+#include <dpaa_list.h>\n+#include <dpaa_bits.h>\n+\n+#endif /* __COMPAT_H */\ndiff --git a/drivers/bus/dpaa/include/dpaa_bits.h b/drivers/bus/dpaa/include/dpaa_bits.h\nnew file mode 100644\nindex 0000000..e29019b\n--- /dev/null\n+++ b/drivers/bus/dpaa/include/dpaa_bits.h\n@@ -0,0 +1,65 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright 2017 NXP. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of NXP nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __DPAA_BITS_H\n+#define __DPAA_BITS_H\n+\n+/* Bitfield stuff. */\n+#define BITS_PER_ULONG\t(sizeof(unsigned long) << 3)\n+#define SHIFT_PER_ULONG\t(((1 << 5) == BITS_PER_ULONG) ? 5 : 6)\n+#define BITS_MASK(idx)\t(1UL << ((idx) & (BITS_PER_ULONG - 1)))\n+#define BITS_IDX(idx)\t((idx) >> SHIFT_PER_ULONG)\n+\n+static inline void dpaa_set_bits(unsigned long mask,\n+\t\t\t\t volatile unsigned long *p)\n+{\n+\t*p |= mask;\n+}\n+\n+static inline void dpaa_set_bit(int idx, volatile unsigned long *bits)\n+{\n+\tdpaa_set_bits(BITS_MASK(idx), bits + BITS_IDX(idx));\n+}\n+\n+static inline void dpaa_clear_bits(unsigned long mask,\n+\t\t\t\t volatile unsigned long *p)\n+{\n+\t*p &= ~mask;\n+}\n+\n+static inline void dpaa_clear_bit(int idx,\n+\t\t\t\t volatile unsigned long *bits)\n+{\n+\tdpaa_clear_bits(BITS_MASK(idx), bits + BITS_IDX(idx));\n+}\n+\n+#endif /* __DPAA_BITS_H */\ndiff --git a/drivers/bus/dpaa/include/dpaa_list.h b/drivers/bus/dpaa/include/dpaa_list.h\nnew file mode 100644\nindex 0000000..7ad0f14\n--- /dev/null\n+++ b/drivers/bus/dpaa/include/dpaa_list.h\n@@ -0,0 +1,101 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright 2017 NXP. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of NXP nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __DPAA_LIST_H\n+#define __DPAA_LIST_H\n+\n+/****************/\n+/* Linked-lists */\n+/****************/\n+\n+struct list_head {\n+\tstruct list_head *prev;\n+\tstruct list_head *next;\n+};\n+\n+#define COMPAT_LIST_HEAD(n) \\\n+struct list_head n = { \\\n+\t.prev = &n, \\\n+\t.next = &n \\\n+}\n+\n+#define INIT_LIST_HEAD(p) \\\n+do { \\\n+\tstruct list_head *__p298 = (p); \\\n+\t__p298->next = __p298; \\\n+\t__p298->prev = __p298->next; \\\n+} while (0)\n+#define list_entry(node, type, member) \\\n+\t(type *)((void *)node - offsetof(type, member))\n+#define list_empty(p) \\\n+({ \\\n+\tconst struct list_head *__p298 = (p); \\\n+\t((__p298->next == __p298) && (__p298->prev == __p298)); \\\n+})\n+#define list_add(p, l) \\\n+do { \\\n+\tstruct list_head *__p298 = (p); \\\n+\tstruct list_head *__l298 = (l); \\\n+\t__p298->next = __l298->next; \\\n+\t__p298->prev = __l298; \\\n+\t__l298->next->prev = __p298; \\\n+\t__l298->next = __p298; \\\n+} while (0)\n+#define list_add_tail(p, l) \\\n+do { \\\n+\tstruct list_head *__p298 = (p); \\\n+\tstruct list_head *__l298 = (l); \\\n+\t__p298->prev = __l298->prev; \\\n+\t__p298->next = __l298; \\\n+\t__l298->prev->next = __p298; \\\n+\t__l298->prev = __p298; \\\n+} while (0)\n+#define list_for_each(i, l)\t\t\t\t\\\n+\tfor (i = (l)->next; i != (l); i = i->next)\n+#define list_for_each_safe(i, j, l)\t\t\t\\\n+\tfor (i = (l)->next, j = i->next; i != (l);\t\\\n+\t i = j, j = i->next)\n+#define list_for_each_entry(i, l, name) \\\n+\tfor (i = list_entry((l)->next, typeof(*i), name); &i->name != (l); \\\n+\t\ti = list_entry(i->name.next, typeof(*i), name))\n+#define list_for_each_entry_safe(i, j, l, name) \\\n+\tfor (i = list_entry((l)->next, typeof(*i), name), \\\n+\t\tj = list_entry(i->name.next, typeof(*j), name); \\\n+\t\t&i->name != (l); \\\n+\t\ti = j, j = list_entry(j->name.next, typeof(*j), name))\n+#define list_del(i) \\\n+do { \\\n+\t(i)->next->prev = (i)->prev; \\\n+\t(i)->prev->next = (i)->next; \\\n+} while (0)\n+\n+#endif /* __DPAA_LIST_H */\n", "prefixes": [ "dpdk-dev", "v2", "03/40" ] }