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GET /api/patches/2460/?format=api
{ "id": 2460, "url": "https://patches.dpdk.org/api/patches/2460/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1421912219-1946-5-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1421912219-1946-5-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1421912219-1946-5-git-send-email-helin.zhang@intel.com", "date": "2015-01-22T07:36:58", "name": "[dpdk-dev,v9,4/5] i40e: support of controlling hash functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9679b1b9afb1b92058ade6a92300e27ac2cc88b1", "submitter": { "id": 14, "url": "https://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1421912219-1946-5-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/2460/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/2460/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id EBF0F5AA9;\n\tThu, 22 Jan 2015 08:37:21 +0100 (CET)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id EEE9A5AA6\n\tfor <dev@dpdk.org>; Thu, 22 Jan 2015 08:37:15 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga101.fm.intel.com with ESMTP; 21 Jan 2015 23:37:13 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga002.fm.intel.com with ESMTP; 21 Jan 2015 23:37:12 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t0M7bBeZ010313;\n\tThu, 22 Jan 2015 15:37:11 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t0M7b9a5002010; Thu, 22 Jan 2015 15:37:11 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t0M7b8EX002006; \n\tThu, 22 Jan 2015 15:37:08 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.09,447,1418112000\"; d=\"scan'208\";a=\"665671659\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 22 Jan 2015 15:36:58 +0800", "Message-Id": "<1421912219-1946-5-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1421912219-1946-1-git-send-email-helin.zhang@intel.com>", "References": "<1417486760-24459-1-git-send-email-helin.zhang@intel.com>\n\t<1421912219-1946-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v9 4/5] i40e: support of controlling hash\n\tfunctions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Hash filter control has been implemented for i40e. It includes\ngetting/setting,\n- global hash configurations (hash function type, and symmetric\n hash enable per flow type)\n- symmetric hash enable per port\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.c | 294 +++++++++++++++++++++++++++++++++++++-\n 1 file changed, 292 insertions(+), 2 deletions(-)\n\nv5 changes:\n* Integrated with filter API defined recently.\n\nv6 changes:\n* Implemented the mapping function to convert RSS offload types to Packet\n Classification Types, to isolate the real hardware specific things.\n* Removed initialization of global registers in i40e PMD, as global registers\n shouldn't be initialized per port.\n* Added more annotations to get code more understandable.\n* Corrected annotation format for documenation.\n\nv7 changes:\n* Removed swap configurations, as it is not allowed by hardware design.\n* Put symmetric hash per flow type and hash function type into\n 'RTE_ETH_HASH_FILTER_GLOBAL_CONFIG', as they are controlling global registers\n which will affects all the ports of the same NIC.\n\nv8 changes:\n* Removed redundant return value checks of i40e_flowtype_to_pctype(), as it\n should always be correct.\n* Fixed the compile issue on ICC, of \"error #188: enumerated type mixed with\n another type\".\n\nv9 changes:\n* Splitted the patch, one is for i40e only.", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex 48bc34d..9fa6bec 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -93,6 +93,18 @@\n \t\tI40E_PFINT_ICR0_ENA_VFLR_MASK | \\\n \t\tI40E_PFINT_ICR0_ENA_ADMINQ_MASK)\n \n+#define I40E_FLOW_TYPES ( \\\n+\t(1UL << RTE_ETH_FLOW_TYPE_UDPV4) | \\\n+\t(1UL << RTE_ETH_FLOW_TYPE_TCPV4) | \\\n+\t(1UL << RTE_ETH_FLOW_TYPE_SCTPV4) | \\\n+\t(1UL << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \\\n+\t(1UL << RTE_ETH_FLOW_TYPE_FRAG_IPV4) | \\\n+\t(1UL << RTE_ETH_FLOW_TYPE_UDPV6) | \\\n+\t(1UL << RTE_ETH_FLOW_TYPE_TCPV6) | \\\n+\t(1UL << RTE_ETH_FLOW_TYPE_SCTPV6) | \\\n+\t(1UL << RTE_ETH_FLOW_TYPE_IPV6_OTHER) | \\\n+\t(1UL << RTE_ETH_FLOW_TYPE_FRAG_IPV6))\n+\n static int eth_i40e_dev_init(\\\n \t\t\t__attribute__((unused)) struct eth_driver *eth_drv,\n \t\t\tstruct rte_eth_dev *eth_dev);\n@@ -199,6 +211,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n \t\t\t\tenum rte_filter_op filter_op,\n \t\t\t\tvoid *arg);\n static void i40e_configure_registers(struct i40e_hw *hw);\n+static void i40e_hw_init(struct i40e_hw *hw);\n \n static struct rte_pci_id pci_id_i40e_map[] = {\n #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n@@ -398,6 +411,9 @@ eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,\n \t/* Make sure all is clean before doing PF reset */\n \ti40e_clear_hw(hw);\n \n+\t/* Initialize the hardware */\n+\ti40e_hw_init(hw);\n+\n \t/* Reset here to make sure all is clean for each PF */\n \tret = i40e_pf_reset(hw);\n \tif (ret) {\n@@ -5136,6 +5152,260 @@ i40e_pf_config_mq_rx(struct i40e_pf *pf)\n \treturn ret;\n }\n \n+/* Get the symmetric hash enable configurations per port */\n+static void\n+i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)\n+{\n+\tuint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);\n+\n+\t*enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;\n+}\n+\n+/* Set the symmetric hash enable configurations per port */\n+static void\n+i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)\n+{\n+\tuint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);\n+\n+\tif (enable > 0) {\n+\t\tif (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {\n+\t\t\tPMD_DRV_LOG(INFO, \"Symmetric hash has already \"\n+\t\t\t\t\t\t\t\"been enabled\");\n+\t\t\treturn;\n+\t\t}\n+\t\treg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;\n+\t} else {\n+\t\tif (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {\n+\t\t\tPMD_DRV_LOG(INFO, \"Symmetric hash has already \"\n+\t\t\t\t\t\t\t\"been disabled\");\n+\t\t\treturn;\n+\t\t}\n+\t\treg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;\n+\t}\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);\n+\tI40E_WRITE_FLUSH(hw);\n+}\n+\n+/*\n+ * Get global configurations of hash function type and symmetric hash enable\n+ * per flow type (pctype). Note that global configuration means it affects all\n+ * the ports on the same NIC.\n+ */\n+static int\n+i40e_get_hash_filter_global_config(struct i40e_hw *hw,\n+\t\t\t\t struct rte_eth_hash_global_conf *g_cfg)\n+{\n+\tuint32_t reg, mask = I40E_FLOW_TYPES;\n+\tuint32_t i;\n+\tenum i40e_filter_pctype pctype;\n+\n+\tmemset(g_cfg, 0, sizeof(*g_cfg));\n+\treg = I40E_READ_REG(hw, I40E_GLQF_CTL);\n+\tif (reg & I40E_GLQF_CTL_HTOEP_MASK)\n+\t\tg_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;\n+\telse\n+\t\tg_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;\n+\tPMD_DRV_LOG(DEBUG, \"Hash function is %s\",\n+\t\t(reg & I40E_GLQF_CTL_HTOEP_MASK) ? \"Toeplitz\" : \"Simple XOR\");\n+\n+\tfor (i = 0; mask && i < RTE_ETH_FLOW_TYPE_MAX; i++) {\n+\t\tif (!(mask & (1UL << i)))\n+\t\t\tcontinue;\n+\t\tmask &= ~(1UL << i);\n+\t\t/* Bit set indicats the coresponding flow type is supported */\n+\t\tg_cfg->valid_bit_mask[0] |= (1UL << i);\n+\t\tpctype = i40e_flowtype_to_pctype((enum rte_eth_flow_type)i);\n+\t\treg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));\n+\t\tif (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)\n+\t\t\tg_cfg->sym_hash_enable_mask[0] |= (1UL << i);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)\n+{\n+\tuint32_t i;\n+\tuint32_t mask0, i40e_mask = I40E_FLOW_TYPES;\n+\n+\tif (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&\n+\t\tg_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&\n+\t\tg_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {\n+\t\tPMD_DRV_LOG(ERR, \"Unsupported hash function type %d\",\n+\t\t\t\t\t\tg_cfg->hash_func);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * As i40e supports less than 32 flow types, only first 32 bits need to\n+\t * be checked.\n+\t */\n+\tmask0 = g_cfg->valid_bit_mask[0];\n+\tfor (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {\n+\t\tif (i == 0) {\n+\t\t\t/* Check if any unsupported flow type configured */\n+\t\t\tif ((mask0 | i40e_mask) ^ i40e_mask)\n+\t\t\t\tgoto mask_err;\n+\t\t} else {\n+\t\t\tif (g_cfg->valid_bit_mask[i])\n+\t\t\t\tgoto mask_err;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+\n+mask_err:\n+\tPMD_DRV_LOG(ERR, \"i40e unsupported flow type bit(s) configured\");\n+\n+\treturn -EINVAL;\n+}\n+\n+/*\n+ * Set global configurations of hash function type and symmetric hash enable\n+ * per flow type (pctype). Note any modifying global configuration will affect\n+ * all the ports on the same NIC.\n+ */\n+static int\n+i40e_set_hash_filter_global_config(struct i40e_hw *hw,\n+\t\t\t\t struct rte_eth_hash_global_conf *g_cfg)\n+{\n+\tint ret;\n+\tuint32_t i, reg;\n+\tuint32_t mask0 = g_cfg->valid_bit_mask[0];\n+\tenum i40e_filter_pctype pctype;\n+\n+\t/* Check the input parameters */\n+\tret = i40e_hash_global_config_check(g_cfg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tfor (i = 0; mask0 && i < UINT32_BIT; i++) {\n+\t\tif (!(mask0 & (1UL << i)))\n+\t\t\tcontinue;\n+\t\tmask0 &= ~(1UL << i);\n+\t\tpctype = i40e_flowtype_to_pctype((enum rte_eth_flow_type)i);\n+\t\treg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?\n+\t\t\t\tI40E_GLQF_HSYM_SYMH_ENA_MASK : 0;\n+\t\tI40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);\n+\t}\n+\n+\treg = I40E_READ_REG(hw, I40E_GLQF_CTL);\n+\tif (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {\n+\t\t/* Toeplitz */\n+\t\tif (reg & I40E_GLQF_CTL_HTOEP_MASK) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Hash function already set to \"\n+\t\t\t\t\t\t\t\t\"Toeplitz\");\n+\t\t\tgoto out;\n+\t\t}\n+\t\treg |= I40E_GLQF_CTL_HTOEP_MASK;\n+\t} else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {\n+\t\t/* Simple XOR */\n+\t\tif (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Hash function already set to \"\n+\t\t\t\t\t\t\t\"Simple XOR\");\n+\t\t\tgoto out;\n+\t\t}\n+\t\treg &= ~I40E_GLQF_CTL_HTOEP_MASK;\n+\t} else\n+\t\t/* Use the default, and keep it as it is */\n+\t\tgoto out;\n+\n+\tI40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);\n+\n+out:\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)\n+{\n+\tint ret = 0;\n+\n+\tif (!hw || !info) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tswitch (info->info_type) {\n+\tcase RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:\n+\t\ti40e_get_symmetric_hash_enable_per_port(hw,\n+\t\t\t\t\t&(info->info.enable));\n+\t\tbreak;\n+\tcase RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:\n+\t\tret = i40e_get_hash_filter_global_config(hw,\n+\t\t\t\t&(info->info.global_conf));\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Hash filter info type (%d) not supported\",\n+\t\t\t\t\t\t\tinfo->info_type);\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)\n+{\n+\tint ret = 0;\n+\n+\tif (!hw || !info) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tswitch (info->info_type) {\n+\tcase RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:\n+\t\ti40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);\n+\t\tbreak;\n+\tcase RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:\n+\t\tret = i40e_set_hash_filter_global_config(hw,\n+\t\t\t\t&(info->info.global_conf));\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Hash filter info type (%d) not supported\",\n+\t\t\t\t\t\t\tinfo->info_type);\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+/* Operations for hash function */\n+static int\n+i40e_hash_filter_ctrl(struct rte_eth_dev *dev,\n+\t\t enum rte_filter_op filter_op,\n+\t\t void *arg)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tint ret = 0;\n+\n+\tswitch (filter_op) {\n+\tcase RTE_ETH_FILTER_NOP:\n+\t\tbreak;\n+\tcase RTE_ETH_FILTER_GET:\n+\t\tret = i40e_hash_filter_get(hw,\n+\t\t\t(struct rte_eth_hash_filter_info *)arg);\n+\t\tbreak;\n+\tcase RTE_ETH_FILTER_SET:\n+\t\tret = i40e_hash_filter_set(hw,\n+\t\t\t(struct rte_eth_hash_filter_info *)arg);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(WARNING, \"Filter operation (%d) not supported\",\n+\t\t\t\t\t\t\t\tfilter_op);\n+\t\tret = -ENOTSUP;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n /*\n * Configure ethertype filter, which can director packet by filtering\n * with mac address and ether_type or only ether_type\n@@ -5238,6 +5508,9 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n \t\treturn -EINVAL;\n \n \tswitch (filter_type) {\n+\tcase RTE_ETH_FILTER_HASH:\n+\t\tret = i40e_hash_filter_ctrl(dev, filter_op, arg);\n+\t\tbreak;\n \tcase RTE_ETH_FILTER_MACVLAN:\n \t\tret = i40e_mac_filter_handle(dev, filter_op, arg);\n \t\tbreak;\n@@ -5260,10 +5533,26 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n \treturn ret;\n }\n \n+/*\n+ * As some registers wouldn't be reset unless a global hardware reset,\n+ * hardware initialization is needed to put those registers into an\n+ * expected initial state.\n+ */\n+static void\n+i40e_hw_init(struct i40e_hw *hw)\n+{\n+\t/* clear the PF Queue Filter control register */\n+\tI40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);\n+\n+\t/* Disable symmetric hash per port */\n+\ti40e_set_symmetric_hash_enable_per_port(hw, 0);\n+}\n+\n enum i40e_filter_pctype\n i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)\n {\n-\tstatic const enum i40e_filter_pctype pctype_table[] = {\n+\tstatic const enum i40e_filter_pctype\n+\t\tpctype_table[RTE_ETH_FLOW_TYPE_MAX] = {\n \t\t[RTE_ETH_FLOW_TYPE_UDPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_UDP,\n \t\t[RTE_ETH_FLOW_TYPE_TCPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_TCP,\n \t\t[RTE_ETH_FLOW_TYPE_SCTPV4] = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,\n@@ -5286,7 +5575,8 @@ i40e_flowtype_to_pctype(enum rte_eth_flow_type flow_type)\n enum rte_eth_flow_type\n i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)\n {\n-\tstatic const enum rte_eth_flow_type flowtype_table[] = {\n+\tstatic const enum rte_eth_flow_type\n+\t\tflowtype_table[RTE_ETH_FLOW_TYPE_MAX] = {\n \t\t[I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = RTE_ETH_FLOW_TYPE_UDPV4,\n \t\t[I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = RTE_ETH_FLOW_TYPE_TCPV4,\n \t\t[I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = RTE_ETH_FLOW_TYPE_SCTPV4,\n", "prefixes": [ "dpdk-dev", "v9", "4/5" ] }