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GET /api/patches/21698/?format=api
{ "id": 21698, "url": "https://patches.dpdk.org/api/patches/21698/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20170310231334.2457-2-yskoh@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20170310231334.2457-2-yskoh@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20170310231334.2457-2-yskoh@mellanox.com", "date": "2017-03-10T23:13:33", "name": "[dpdk-dev,v2,1/2] net/mlx5: add enhanced multi-packet send for ConnectX-5", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5e13cce8d4a51a8cece44d0b31f6b369823c7619", "submitter": { "id": 636, "url": "https://patches.dpdk.org/api/people/636/?format=api", "name": "Yongseok Koh", "email": "yskoh@mellanox.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20170310231334.2457-2-yskoh@mellanox.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/21698/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/21698/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 033D4692F;\n\tSat, 11 Mar 2017 00:14:22 +0100 (CET)", "from EUR02-HE1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr10081.outbound.protection.outlook.com [40.107.1.81])\n\tby dpdk.org (Postfix) with ESMTP id 7DE6958FA\n\tfor <dev@dpdk.org>; Sat, 11 Mar 2017 00:13:56 +0100 (CET)", "from mellanox.com (12.250.235.110) by\n\tHE1PR0501MB2460.eurprd05.prod.outlook.com (10.168.126.16) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.947.12; Fri, 10 Mar 2017 23:13:53 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com;\n\ts=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=ASjuhcxpmB6QSrPnhf+lO/2YtdQMdrR+vuCEZb45xCo=;\n\tb=K6T4nENXOfBXXbb92o/7/ypmF3n5ajxAaDKXadjJVX94ujfpsSC1taWdW3ozRwO9xfP0UpYnT5VvLZU6cM9WQQLd/iZfW9DK5X75VAlYaMFPB7t/LU05bx3PnrhfHoI+iH3IvPemqPXk1ZWH0ySUWIOGnKiFKUDd/yCYAgGgQFw=", "Authentication-Results": "intel.com; dkim=none (message not signed)\n\theader.d=none; intel.com;\n\tdmarc=none action=none header.from=mellanox.com; ", "From": "Yongseok Koh <yskoh@mellanox.com>", "To": "<ferruh.yigit@intel.com>", "CC": "<dev@dpdk.org>, <adrien.mazarguil@6wind.com>,\n\t<nelio.laranjeiro@6wind.com>, Yongseok Koh <yskoh@mellanox.com>", "Date": "Fri, 10 Mar 2017 15:13:33 -0800", "Message-ID": "<20170310231334.2457-2-yskoh@mellanox.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170310231334.2457-1-yskoh@mellanox.com>", "References": "<20170310231334.2457-1-yskoh@mellanox.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[12.250.235.110]", "X-ClientProxiedBy": "MWHPR1201CA0011.namprd12.prod.outlook.com (10.174.253.21)\n\tTo HE1PR0501MB2460.eurprd05.prod.outlook.com\n\t(10.168.126.16)", "X-MS-Office365-Filtering-Correlation-Id": "0b1c18f0-fb28-45a3-4b72-08d4680b1f9d", "X-MS-Office365-Filtering-HT": "Tenant", "X-Microsoft-Antispam": "UriScan:; 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PCL:0;\n\tRULEID:(6040375)(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001)(6055026)(6041248)(20161123555025)(20161123560025)(20161123564025)(20161123558025)(20161123562025)(6072148);\n\tSRVR:HE1PR0501MB2460; BCL:0; PCL:0; RULEID:; SRVR:HE1PR0501MB2460; ", "X-Forefront-PRVS": "02426D11FE", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(4630300001)(6009001)(39450400003)(39840400002)(39860400002)(39850400002)(39410400002)(42186005)(76176999)(7736002)(305945005)(110136004)(66066001)(38730400002)(53936002)(50466002)(50226002)(48376002)(50986999)(81166006)(47776003)(8676002)(33646002)(2906002)(1076002)(5003940100001)(189998001)(25786008)(54906002)(33026002)(2351001)(36756003)(86362001)(6116002)(3846002)(55016002)(575784001)(5660300001)(6666003)(6916009)(2950100002)(4326008);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR0501MB2460; H:mellanox.com; FPR:;\n\tSPF:None; MLV:sfv; LANG:en; ", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "Mellanox.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "10 Mar 2017 23:13:53.6041\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "HE1PR0501MB2460", "Subject": "[dpdk-dev] [PATCH v2 1/2] net/mlx5: add enhanced multi-packet send\n\tfor ConnectX-5", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "ConnectX-5 supports enhanced version of multi-packet send (MPS). An MPS Tx\ndescriptor can carry multiple packets either by including pointers of\npackets or by inlining packets. Inlining packet data can be helpful to\nbetter utilize PCIe bandwidth. In addition, Enhanced MPS supports hybrid\nmode - mixing inlined packets and pointers in a descriptor. This feature is\nenabled by default if supported by HW.\n\nSigned-off-by: Yongseok Koh <yskoh@mellanox.com>\n---\n drivers/net/mlx5/mlx5.c | 37 +++-\n drivers/net/mlx5/mlx5.h | 4 +-\n drivers/net/mlx5/mlx5_defs.h | 7 +\n drivers/net/mlx5/mlx5_ethdev.c | 6 +-\n drivers/net/mlx5/mlx5_prm.h | 20 ++\n drivers/net/mlx5/mlx5_rxtx.c | 410 +++++++++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_rxtx.h | 7 +-\n drivers/net/mlx5/mlx5_txq.c | 28 ++-\n 8 files changed, 506 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 6f42948ab..5293f053e 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -84,6 +84,12 @@\n /* Device parameter to enable multi-packet send WQEs. */\n #define MLX5_TXQ_MPW_EN \"txq_mpw_en\"\n \n+/* Device parameter to include 2 dsegs in the title WQEBB. */\n+#define MLX5_TXQ_MPW_HDR_DSEG_EN \"txq_mpw_hdr_dseg_en\"\n+\n+/* Device parameter to limit the size of inlining packet. */\n+#define MLX5_TXQ_MAX_INLINE_LEN \"txq_max_inline_len\"\n+\n /* Device parameter to enable hardware TSO offload. */\n #define MLX5_TSO \"tso\"\n \n@@ -292,7 +298,11 @@ mlx5_args_check(const char *key, const char *val, void *opaque)\n \t} else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {\n \t\tpriv->txqs_inline = tmp;\n \t} else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {\n-\t\tpriv->mps &= !!tmp; /* Enable MPW only if HW supports */\n+\t\tpriv->mps = !!tmp ? priv->mps : MLX5_MPW_DISABLED;\n+\t} else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {\n+\t\tpriv->mpw_hdr_dseg = !!tmp;\n+\t} else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {\n+\t\tpriv->txq_max_inline_len = tmp;\n \t} else if (strcmp(MLX5_TSO, key) == 0) {\n \t\tpriv->tso = !!tmp;\n \t} else {\n@@ -321,6 +331,8 @@ mlx5_args(struct priv *priv, struct rte_devargs *devargs)\n \t\tMLX5_TXQ_INLINE,\n \t\tMLX5_TXQS_MIN_INLINE,\n \t\tMLX5_TXQ_MPW_EN,\n+\t\tMLX5_TXQ_MPW_HDR_DSEG_EN,\n+\t\tMLX5_TXQ_MAX_INLINE_LEN,\n \t\tMLX5_TSO,\n \t\tNULL,\n \t};\n@@ -432,24 +444,27 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\tswitch (pci_dev->id.device_id) {\n \t\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4:\n \t\t\ttunnel_en = 1;\n-\t\t\tmps = 0;\n+\t\t\tmps = MLX5_MPW_DISABLED;\n \t\t\tbreak;\n \t\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:\n+\t\t\tmps = MLX5_MPW;\n+\t\t\tbreak;\n \t\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX5:\n \t\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:\n \t\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:\n \t\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:\n-\t\t\tmps = 1;\n \t\t\ttunnel_en = 1;\n+\t\t\tmps = MLX5_MPW_ENHANCED;\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tmps = 0;\n+\t\t\tmps = MLX5_MPW_DISABLED;\n \t\t}\n \t\tINFO(\"PCI information matches, using device \\\"%s\\\"\"\n-\t\t \" (SR-IOV: %s, MPS: %s)\",\n+\t\t \" (SR-IOV: %s, %sMPS: %s)\",\n \t\t list[i]->name,\n \t\t sriov ? \"true\" : \"false\",\n-\t\t mps ? \"true\" : \"false\");\n+\t\t mps == MLX5_MPW_ENHANCED ? \"Enhanced \" : \"\",\n+\t\t mps != MLX5_MPW_DISABLED ? \"true\" : \"false\");\n \t\tattr_ctx = ibv_open_device(list[i]);\n \t\terr = errno;\n \t\tbreak;\n@@ -544,6 +559,13 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\tpriv->pd = pd;\n \t\tpriv->mtu = ETHER_MTU;\n \t\tpriv->mps = mps; /* Enable MPW by default if supported. */\n+\t\t/* Set default values for Enhanced MPW, a.k.a MPWv2. */\n+\t\tif (mps == MLX5_MPW_ENHANCED) {\n+\t\t\tpriv->mpw_hdr_dseg = 0;\n+\t\t\tpriv->txqs_inline = MLX5_EMPW_MIN_TXQS;\n+\t\t\tpriv->txq_max_inline_len = MLX5_EMPW_MAX_INLINE_LEN;\n+\t\t\tpriv->txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;\n+\t\t}\n \t\tpriv->cqe_comp = 1; /* Enable compression by default. */\n \t\tpriv->tunnel_en = tunnel_en;\n \t\terr = mlx5_args(priv, pci_dev->device.devargs);\n@@ -611,6 +633,9 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\t\t \"with TSO. MPS disabled\");\n \t\t\tpriv->mps = 0;\n \t\t}\n+\t\tINFO(\"%sMPS is %s\",\n+\t\t priv->mps == MLX5_MPW_ENHANCED ? \"Enhanced \" : \"\",\n+\t\t priv->mps != MLX5_MPW_DISABLED ? \"enabled\" : \"disabled\");\n \t\t/* Allocate and register default RSS hash keys. */\n \t\tpriv->rss_conf = rte_calloc(__func__, hash_rxq_init_n,\n \t\t\t\t\t sizeof((*priv->rss_conf)[0]), 0);\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 870e01ff5..0a11dc795 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -123,7 +123,8 @@ struct priv {\n \tunsigned int hw_fcs_strip:1; /* FCS stripping is supported. */\n \tunsigned int hw_padding:1; /* End alignment padding is supported. */\n \tunsigned int sriov:1; /* This is a VF or PF with VF devices. */\n-\tunsigned int mps:1; /* Whether multi-packet send is supported. */\n+\tunsigned int mps:2; /* Multi-packet send mode (0: disabled). */\n+\tunsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */\n \tunsigned int cqe_comp:1; /* Whether CQE compression is enabled. */\n \tunsigned int pending_alarm:1; /* An alarm is pending. */\n \tunsigned int tso:1; /* Whether TSO is supported. */\n@@ -132,6 +133,7 @@ struct priv {\n \tunsigned int max_tso_payload_sz; /* Maximum TCP payload for TSO. */\n \tunsigned int txq_inline; /* Maximum packet size for inlining. */\n \tunsigned int txqs_inline; /* Queue number threshold for inlining. */\n+\tunsigned int txq_max_inline_len; /* Max packet length for inlining. */\n \t/* RX/TX queues. */\n \tunsigned int rxqs_n; /* RX queues array size. */\n \tunsigned int txqs_n; /* TX queues array size. */\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex eecb908ec..201bb3362 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -55,6 +55,13 @@\n #define MLX5_TX_COMP_THRESH 32\n \n /*\n+ * Request TX completion every time the total number of WQEBBs used for inlining\n+ * packets exceeds the size of WQ divided by this divisor. Better to be power of\n+ * two for performance.\n+ */\n+#define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)\n+\n+/*\n * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP\n * from which buffers are to be transmitted will have to be mapped by this\n * driver to their own Memory Region (MR). This is a slow operation.\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex 5deb6e841..dd5fe5c1f 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -1590,7 +1590,11 @@ priv_select_tx_function(struct priv *priv)\n {\n \tpriv->dev->tx_pkt_burst = mlx5_tx_burst;\n \t/* Select appropriate TX function. */\n-\tif (priv->mps && priv->txq_inline) {\n+\tif (priv->mps == MLX5_MPW_ENHANCED) {\n+\t\tpriv->dev->tx_pkt_burst =\n+\t\t\tmlx5_tx_burst_empw;\n+\t\tDEBUG(\"selected Enhanced MPW TX function\");\n+\t} else if (priv->mps && priv->txq_inline) {\n \t\tpriv->dev->tx_pkt_burst = mlx5_tx_burst_mpw_inline;\n \t\tDEBUG(\"selected MPW inline TX function\");\n \t} else if (priv->mps) {\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex 0a77f5be8..155bdbad4 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -73,6 +73,9 @@\n /* WQE size */\n #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)\n \n+/* Max size of a WQE session. */\n+#define MLX5_WQE_SIZE_MAX 960U\n+\n /* Compute the number of DS. */\n #define MLX5_WQE_DS(n) \\\n \t(((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)\n@@ -80,10 +83,19 @@\n /* Room for inline data in multi-packet WQE. */\n #define MLX5_MWQE64_INL_DATA 28\n \n+/* Default minimum number of Tx queues for inlining packets. */\n+#define MLX5_EMPW_MIN_TXQS 8\n+\n+/* Default max packet length to be inlined. */\n+#define MLX5_EMPW_MAX_INLINE_LEN (4U * MLX5_WQE_SIZE)\n+\n #ifndef HAVE_VERBS_MLX5_OPCODE_TSO\n #define MLX5_OPCODE_TSO MLX5_OPCODE_LSO_MPW /* Compat with OFED 3.3. */\n #endif\n \n+#define MLX5_OPC_MOD_ENHANCED_MPSW 0\n+#define MLX5_OPCODE_ENHANCED_MPSW 0x29\n+\n /* CQE value to inform that VLAN is stripped. */\n #define MLX5_CQE_VLAN_STRIPPED (1u << 0)\n \n@@ -176,10 +188,18 @@ struct mlx5_wqe64 {\n \tuint8_t raw[32];\n } __rte_aligned(MLX5_WQE_SIZE);\n \n+/* MPW mode. */\n+enum mlx5_mpw_mode {\n+\tMLX5_MPW_DISABLED,\n+\tMLX5_MPW,\n+\tMLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */\n+};\n+\n /* MPW session status. */\n enum mlx5_mpw_state {\n \tMLX5_MPW_STATE_OPENED,\n \tMLX5_MPW_INL_STATE_OPENED,\n+\tMLX5_MPW_ENHANCED_STATE_OPENED,\n \tMLX5_MPW_STATE_CLOSED,\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 2d33f2d8f..b27b97f19 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -195,6 +195,62 @@ tx_mlx5_wqe(struct txq *txq, uint16_t ci)\n }\n \n /**\n+ * Return the size of tailroom of WQ.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ * @param addr\n+ * Pointer to tail of WQ.\n+ *\n+ * @return\n+ * Size of tailroom.\n+ */\n+static inline size_t\n+tx_mlx5_wqe_tailroom(struct txq *txq, void *addr)\n+{\n+\tsize_t tailroom;\n+\ttailroom = (uintptr_t)(txq->wqes) +\n+\t\t\t\t(1 << txq->wqe_n) * MLX5_WQE_SIZE -\n+\t\t\t\t(uintptr_t)addr;\n+\treturn tailroom;\n+}\n+\n+/**\n+ * Copy data to tailroom of circular queue.\n+ *\n+ * @param dst\n+ * Pointer to destination.\n+ * @param src\n+ * Pointer to source.\n+ * @param n\n+ * Number of bytes to copy.\n+ * @param base\n+ * Pointer to head of queue.\n+ * @param tailroom\n+ * Size of tailroom from dst.\n+ *\n+ * @return\n+ * Pointer after copied data.\n+ */\n+static inline void *\n+memcpy_to_tailroom(void *dst, const void *src, size_t n,\n+\t\tvoid *base, size_t tailroom)\n+{\n+\tvoid *ret;\n+\n+\tif (n > tailroom) {\n+\t\trte_memcpy(dst, src, tailroom);\n+\t\trte_memcpy(base, (void *)((uintptr_t)src + tailroom),\n+\t\t\t\tn - tailroom);\n+\t\tret = (uint8_t *)base + n - tailroom;\n+\t} else {\n+\t\trte_memcpy(dst, src, n);\n+\t\tret = (n == tailroom) ? base : (uint8_t *)dst + n;\n+\t}\n+\treturn ret;\n+}\n+\n+/**\n * Manage TX completions.\n *\n * When sending a burst, mlx5_tx_burst() posts several WRs.\n@@ -1267,6 +1323,360 @@ mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,\n }\n \n /**\n+ * Open an Enhanced MPW session.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ * @param mpw\n+ * Pointer to MPW session structure.\n+ * @param length\n+ * Packet length.\n+ */\n+static inline void\n+mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)\n+{\n+\tuint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);\n+\n+\tmpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;\n+\tmpw->pkts_n = 0;\n+\tmpw->total_len = sizeof(struct mlx5_wqe);\n+\tmpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);\n+\tmpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |\n+\t\t\t\t (txq->wqe_ci << 8) |\n+\t\t\t\t MLX5_OPCODE_ENHANCED_MPSW);\n+\tmpw->wqe->ctrl[2] = 0;\n+\tmpw->wqe->ctrl[3] = 0;\n+\tmemset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);\n+\tif (unlikely(padding)) {\n+\t\tuintptr_t addr = (uintptr_t)(mpw->wqe + 1);\n+\n+\t\t/* Pad the first 2 DWORDs with zero-length inline header. */\n+\t\t*(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);\n+\t\t*(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE)\n+\t\t\t= htonl(MLX5_INLINE_SEG);\n+\t\tmpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;\n+\t\t/* Start from the next WQEBB. */\n+\t\tmpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));\n+\t} else {\n+\t\tmpw->data.raw = (volatile void *)(mpw->wqe + 1);\n+\t}\n+}\n+\n+/**\n+ * Close an Enhanced MPW session.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ * @param mpw\n+ * Pointer to MPW session structure.\n+ *\n+ * @return\n+ * Number of consumed WQEs.\n+ */\n+static inline uint16_t\n+mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)\n+{\n+\tuint16_t ret;\n+\n+\t/* Store size in multiple of 16 bytes. Control and Ethernet segments\n+\t * count as 2.\n+\t */\n+\tmpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));\n+\tmpw->state = MLX5_MPW_STATE_CLOSED;\n+\tret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;\n+\ttxq->wqe_ci += ret;\n+\treturn ret;\n+}\n+\n+/**\n+ * DPDK callback for TX with Enhanced MPW support.\n+ *\n+ * @param dpdk_txq\n+ * Generic pointer to TX queue structure.\n+ * @param[in] pkts\n+ * Packets to transmit.\n+ * @param pkts_n\n+ * Number of packets in array.\n+ *\n+ * @return\n+ * Number of packets successfully transmitted (<= pkts_n).\n+ */\n+uint16_t\n+mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n+{\n+\tstruct txq *txq = (struct txq *)dpdk_txq;\n+\tuint16_t elts_head = txq->elts_head;\n+\tconst unsigned int elts_n = 1 << txq->elts_n;\n+\tunsigned int i = 0;\n+\tunsigned int j = 0;\n+\tunsigned int max_elts;\n+\tuint16_t max_wqe;\n+\tunsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;\n+\tunsigned int mpw_room = 0;\n+\tunsigned int inl_pad = 0;\n+\tuint32_t inl_hdr;\n+\tstruct mlx5_mpw mpw = {\n+\t\t.state = MLX5_MPW_STATE_CLOSED,\n+\t};\n+\n+\tif (unlikely(!pkts_n))\n+\t\treturn 0;\n+\t/* Start processing. */\n+\ttxq_complete(txq);\n+\tmax_elts = (elts_n - (elts_head - txq->elts_tail));\n+\tif (max_elts > elts_n)\n+\t\tmax_elts -= elts_n;\n+\t/* A CQE slot must always be available. */\n+\tassert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));\n+\tmax_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);\n+\tif (unlikely(!max_wqe))\n+\t\treturn 0;\n+\tdo {\n+\t\tstruct rte_mbuf *buf = *(pkts++);\n+\t\tunsigned int elts_head_next;\n+\t\tuintptr_t addr;\n+\t\tunsigned int n;\n+\t\tunsigned int do_inline = 0; /* Whether inline is possible. */\n+\t\tuint32_t length;\n+\t\tunsigned int segs_n = buf->nb_segs;\n+\t\tuint32_t cs_flags = 0;\n+\n+\t\t/*\n+\t\t * Make sure there is enough room to store this packet and\n+\t\t * that one ring entry remains unused.\n+\t\t */\n+\t\tassert(segs_n);\n+\t\tif (max_elts - j < segs_n + 1)\n+\t\t\tbreak;\n+\t\t/* Do not bother with large packets MPW cannot handle. */\n+\t\tif (segs_n > MLX5_MPW_DSEG_MAX)\n+\t\t\tbreak;\n+\t\t/* Should we enable HW CKSUM offload. */\n+\t\tif (buf->ol_flags &\n+\t\t (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))\n+\t\t\tcs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;\n+\t\t/* Retrieve packet information. */\n+\t\tlength = PKT_LEN(buf);\n+\t\t/* Start new session if:\n+\t\t * - multi-segment packet\n+\t\t * - no space left even for a dseg\n+\t\t * - next packet can be inlined with a new WQE\n+\t\t * - cs_flag differs\n+\t\t * It can't be MLX5_MPW_STATE_OPENED as always have a single\n+\t\t * segmented packet.\n+\t\t */\n+\t\tif (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {\n+\t\t\tif ((segs_n != 1) ||\n+\t\t\t (inl_pad + sizeof(struct mlx5_wqe_data_seg) >\n+\t\t\t\tmpw_room) ||\n+\t\t\t (length <= txq->max_inline_len &&\n+\t\t\t inl_pad + sizeof(inl_hdr) + length >\n+\t\t\t\tmpw_room) ||\n+\t\t\t (mpw.wqe->eseg.cs_flags != cs_flags))\n+\t\t\t\tmax_wqe -= mlx5_empw_close(txq, &mpw);\n+\t\t}\n+\t\tif (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {\n+\t\t\tif (unlikely(segs_n != 1)) {\n+\t\t\t\t/* Fall back to legacy MPW.\n+\t\t\t\t * A MPW session consumes 2 WQEs at most to\n+\t\t\t\t * include MLX5_MPW_DSEG_MAX pointers.\n+\t\t\t\t */\n+\t\t\t\tif (unlikely(max_wqe < 2))\n+\t\t\t\t\tbreak;\n+\t\t\t\tmlx5_mpw_new(txq, &mpw, length);\n+\t\t\t} else {\n+\t\t\t\t/* In Enhanced MPW, inline as much as the budget\n+\t\t\t\t * is allowed. The remaining space is to be\n+\t\t\t\t * filled with dsegs. If the title WQEBB isn't\n+\t\t\t\t * padded, it will have 2 dsegs there.\n+\t\t\t\t */\n+\t\t\t\tmpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,\n+\t\t\t\t\t (max_inline ? max_inline :\n+\t\t\t\t\t pkts_n * MLX5_WQE_DWORD_SIZE) +\n+\t\t\t\t\t MLX5_WQE_SIZE);\n+\t\t\t\tif (unlikely((max_wqe * MLX5_WQE_SIZE) <\n+\t\t\t\t\t\tmpw_room))\n+\t\t\t\t\tbreak;\n+\t\t\t\t/* Don't pad the title WQEBB to not waste WQ. */\n+\t\t\t\tmlx5_empw_new(txq, &mpw, 0);\n+\t\t\t\tmpw_room -= mpw.total_len;\n+\t\t\t\tinl_pad = 0;\n+\t\t\t\tdo_inline =\n+\t\t\t\t\tlength <= txq->max_inline_len &&\n+\t\t\t\t\t(sizeof(inl_hdr) + length) <=\n+\t\t\t\t\t\tmpw_room &&\n+\t\t\t\t\t!txq->mpw_hdr_dseg;\n+\t\t\t}\n+\t\t\tmpw.wqe->eseg.cs_flags = cs_flags;\n+\t\t} else {\n+\t\t\t/* Evaluate whether the next packet can be inlined.\n+\t\t\t * Inlininig is possible when:\n+\t\t\t * - length is less than configured value\n+\t\t\t * - length fits for remaining space\n+\t\t\t * - not required to fill the title WQEBB with dsegs\n+\t\t\t */\n+\t\t\tdo_inline =\n+\t\t\t\tlength <= txq->max_inline_len &&\n+\t\t\t\t(inl_pad + sizeof(inl_hdr) + length) <=\n+\t\t\t\t\tmpw_room &&\n+\t\t\t\t(!txq->mpw_hdr_dseg ||\n+\t\t\t\t mpw.total_len >= MLX5_WQE_SIZE);\n+\t\t}\n+\t\t/* Multi-segment packets must be alone in their MPW. */\n+\t\tassert((segs_n == 1) || (mpw.pkts_n == 0));\n+\t\tif (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {\n+#if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)\n+\t\t\tlength = 0;\n+#endif\n+\t\t\tdo {\n+\t\t\t\tvolatile struct mlx5_wqe_data_seg *dseg;\n+\n+\t\t\t\telts_head_next =\n+\t\t\t\t\t(elts_head + 1) & (elts_n - 1);\n+\t\t\t\tassert(buf);\n+\t\t\t\t(*txq->elts)[elts_head] = buf;\n+\t\t\t\tdseg = mpw.data.dseg[mpw.pkts_n];\n+\t\t\t\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n+\t\t\t\t*dseg = (struct mlx5_wqe_data_seg){\n+\t\t\t\t\t.byte_count = htonl(DATA_LEN(buf)),\n+\t\t\t\t\t.lkey = txq_mp2mr(txq, txq_mb2mp(buf)),\n+\t\t\t\t\t.addr = htonll(addr),\n+\t\t\t\t};\n+\t\t\t\telts_head = elts_head_next;\n+#if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)\n+\t\t\t\tlength += DATA_LEN(buf);\n+#endif\n+\t\t\t\tbuf = buf->next;\n+\t\t\t\t++j;\n+\t\t\t\t++mpw.pkts_n;\n+\t\t\t} while (--segs_n);\n+\t\t\t/* A multi-segmented packet takes one MPW session.\n+\t\t\t * TODO: Pack more multi-segmented packets if possible.\n+\t\t\t */\n+\t\t\tmlx5_mpw_close(txq, &mpw);\n+\t\t\tif (mpw.pkts_n < 3)\n+\t\t\t\tmax_wqe--;\n+\t\t\telse\n+\t\t\t\tmax_wqe -= 2;\n+\t\t} else if (do_inline) {\n+\t\t\t/* Inline packet into WQE. */\n+\t\t\tunsigned int max;\n+\n+\t\t\tassert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);\n+\t\t\tassert(length == DATA_LEN(buf));\n+\t\t\tinl_hdr = htonl(length | MLX5_INLINE_SEG);\n+\t\t\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n+\t\t\tmpw.data.raw = (volatile void *)\n+\t\t\t\t((uintptr_t)mpw.data.raw + inl_pad);\n+\t\t\tmax = tx_mlx5_wqe_tailroom(txq,\n+\t\t\t\t\t(void *)(uintptr_t)mpw.data.raw);\n+\t\t\t/* Copy inline header. */\n+\t\t\tmpw.data.raw = (volatile void *)\n+\t\t\t\tmemcpy_to_tailroom(\n+\t\t\t\t\t (void *)(uintptr_t)mpw.data.raw,\n+\t\t\t\t\t &inl_hdr,\n+\t\t\t\t\t sizeof(inl_hdr),\n+\t\t\t\t\t (void *)(uintptr_t)txq->wqes,\n+\t\t\t\t\t max);\n+\t\t\tmax = tx_mlx5_wqe_tailroom(txq,\n+\t\t\t\t\t(void *)(uintptr_t)mpw.data.raw);\n+\t\t\t/* Copy packet data. */\n+\t\t\tmpw.data.raw = (volatile void *)\n+\t\t\t\tmemcpy_to_tailroom(\n+\t\t\t\t\t (void *)(uintptr_t)mpw.data.raw,\n+\t\t\t\t\t (void *)addr,\n+\t\t\t\t\t length,\n+\t\t\t\t\t (void *)(uintptr_t)txq->wqes,\n+\t\t\t\t\t max);\n+\t\t\t++mpw.pkts_n;\n+\t\t\tmpw.total_len += (inl_pad + sizeof(inl_hdr) + length);\n+\t\t\t/* No need to get completion as the entire packet is\n+\t\t\t * copied to WQ. Free the buf right away.\n+\t\t\t */\n+\t\t\telts_head_next = elts_head;\n+\t\t\trte_pktmbuf_free_seg(buf);\n+\t\t\tmpw_room -= (inl_pad + sizeof(inl_hdr) + length);\n+\t\t\t/* Add pad in the next packet if any. */\n+\t\t\tinl_pad = (((uintptr_t)mpw.data.raw +\n+\t\t\t\t\t(MLX5_WQE_DWORD_SIZE - 1)) &\n+\t\t\t\t\t~(MLX5_WQE_DWORD_SIZE - 1)) -\n+\t\t\t\t (uintptr_t)mpw.data.raw;\n+\t\t} else {\n+\t\t\t/* No inline. Load a dseg of packet pointer. */\n+\t\t\tvolatile rte_v128u32_t *dseg;\n+\n+\t\t\tassert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);\n+\t\t\tassert((inl_pad + sizeof(*dseg)) <= mpw_room);\n+\t\t\tassert(length == DATA_LEN(buf));\n+\t\t\tif (!tx_mlx5_wqe_tailroom(txq,\n+\t\t\t\t\t(void *)((uintptr_t)mpw.data.raw\n+\t\t\t\t\t\t+ inl_pad)))\n+\t\t\t\tdseg = (volatile void *)txq->wqes;\n+\t\t\telse\n+\t\t\t\tdseg = (volatile void *)\n+\t\t\t\t\t((uintptr_t)mpw.data.raw +\n+\t\t\t\t\t inl_pad);\n+\t\t\telts_head_next = (elts_head + 1) & (elts_n - 1);\n+\t\t\t(*txq->elts)[elts_head] = buf;\n+\t\t\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n+\t\t\tfor (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)\n+\t\t\t\trte_prefetch2((void *)(addr +\n+\t\t\t\t\t\tn * RTE_CACHE_LINE_SIZE));\n+\t\t\taddr = htonll(addr);\n+\t\t\t*dseg = (rte_v128u32_t) {\n+\t\t\t\thtonl(length),\n+\t\t\t\ttxq_mp2mr(txq, txq_mb2mp(buf)),\n+\t\t\t\taddr,\n+\t\t\t\taddr >> 32,\n+\t\t\t};\n+\t\t\tmpw.data.raw = (volatile void *)(dseg + 1);\n+\t\t\tmpw.total_len += (inl_pad + sizeof(*dseg));\n+\t\t\t++j;\n+\t\t\t++mpw.pkts_n;\n+\t\t\tmpw_room -= (inl_pad + sizeof(*dseg));\n+\t\t\tinl_pad = 0;\n+\t\t}\n+\t\telts_head = elts_head_next;\n+#ifdef MLX5_PMD_SOFT_COUNTERS\n+\t\t/* Increment sent bytes counter. */\n+\t\ttxq->stats.obytes += length;\n+#endif\n+\t\t++i;\n+\t} while (i < pkts_n);\n+\t/* Take a shortcut if nothing must be sent. */\n+\tif (unlikely(i == 0))\n+\t\treturn 0;\n+\t/* Check whether completion threshold has been reached. */\n+\tif (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||\n+\t\t\t(uint16_t)(txq->wqe_ci - txq->mpw_comp) >=\n+\t\t\t (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {\n+\t\tvolatile struct mlx5_wqe *wqe = mpw.wqe;\n+\n+\t\t/* Request completion on last WQE. */\n+\t\twqe->ctrl[2] = htonl(8);\n+\t\t/* Save elts_head in unused \"immediate\" field of WQE. */\n+\t\twqe->ctrl[3] = elts_head;\n+\t\ttxq->elts_comp = 0;\n+\t\ttxq->mpw_comp = txq->wqe_ci;\n+\t\ttxq->cq_pi++;\n+\t} else {\n+\t\ttxq->elts_comp += j;\n+\t}\n+#ifdef MLX5_PMD_SOFT_COUNTERS\n+\t/* Increment sent packets counter. */\n+\ttxq->stats.opackets += i;\n+#endif\n+\tif (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)\n+\t\tmlx5_empw_close(txq, &mpw);\n+\telse if (mpw.state == MLX5_MPW_STATE_OPENED)\n+\t\tmlx5_mpw_close(txq, &mpw);\n+\t/* Ring QP doorbell. */\n+\tmlx5_tx_dbrec(txq, mpw.wqe);\n+\ttxq->elts_head = elts_head;\n+\treturn i;\n+}\n+\n+/**\n * Translate RX completion flags to packet type.\n *\n * @param[in] cqe\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 9669564fd..25e51b59e 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -247,17 +247,21 @@ struct txq {\n \tuint16_t elts_head; /* Current index in (*elts)[]. */\n \tuint16_t elts_tail; /* First element awaiting completion. */\n \tuint16_t elts_comp; /* Counter since last completion request. */\n+\tuint16_t mpw_comp; /* WQ index since last completion request. */\n \tuint16_t cq_ci; /* Consumer index for completion queue. */\n+\tuint16_t cq_pi; /* Producer index for completion queue. */\n \tuint16_t wqe_ci; /* Consumer index for work queue. */\n \tuint16_t wqe_pi; /* Producer index for work queue. */\n \tuint16_t elts_n:4; /* (*elts)[] length (in log2). */\n \tuint16_t cqe_n:4; /* Number of CQ elements (in log2). */\n \tuint16_t wqe_n:4; /* Number of of WQ elements (in log2). */\n-\tuint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */\n \tuint16_t inline_en:1; /* When set inline is enabled. */\n \tuint16_t tso_en:1; /* When set hardware TSO is enabled. */\n \tuint16_t tunnel_en:1;\n \t/* When set TX offload for tunneled packets are supported. */\n+\tuint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */\n+\tuint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */\n+\tuint16_t max_inline_len; /* Max packet length to inilne. */\n \tuint32_t qp_num_8s; /* QP number shifted by 8. */\n \tvolatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */\n \tvolatile void *wqes; /* Work queue (use volatile to write into). */\n@@ -324,6 +328,7 @@ uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);\n uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);\n uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);\n uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);\n+uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);\n uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);\n uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);\n uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 9d0c00f6d..e774954ca 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -266,6 +266,7 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,\n \t\tstruct ibv_exp_cq_attr cq_attr;\n \t} attr;\n \tenum ibv_exp_query_intf_status status;\n+\tunsigned int cqe_n;\n \tint ret = 0;\n \n \tif (mlx5_getenv_int(\"MLX5_ENABLE_CQE_COMPRESSION\")) {\n@@ -276,6 +277,8 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,\n \t(void)conf; /* Thresholds configuration (ignored). */\n \tassert(desc > MLX5_TX_COMP_THRESH);\n \ttmpl.txq.elts_n = log2above(desc);\n+\tif (priv->mps == MLX5_MPW_ENHANCED)\n+\t\ttmpl.txq.mpw_hdr_dseg = priv->mpw_hdr_dseg;\n \t/* MRs will be registered in mp2mr[] later. */\n \tattr.rd = (struct ibv_exp_res_domain_init_attr){\n \t\t.comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |\n@@ -294,9 +297,12 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,\n \t\t.comp_mask = IBV_EXP_CQ_INIT_ATTR_RES_DOMAIN,\n \t\t.res_domain = tmpl.rd,\n \t};\n+\tcqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?\n+\t\t((desc / MLX5_TX_COMP_THRESH) - 1) : 1;\n+\tif (priv->mps == MLX5_MPW_ENHANCED)\n+\t\tcqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;\n \ttmpl.cq = ibv_exp_create_cq(priv->ctx,\n-\t\t\t\t (((desc / MLX5_TX_COMP_THRESH) - 1) ?\n-\t\t\t\t ((desc / MLX5_TX_COMP_THRESH) - 1) : 1),\n+\t\t\t\t cqe_n,\n \t\t\t\t NULL, NULL, 0, &attr.cq);\n \tif (tmpl.cq == NULL) {\n \t\tret = ENOMEM;\n@@ -340,9 +346,23 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,\n \t\ttmpl.txq.max_inline =\n \t\t\t((priv->txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /\n \t\t\t RTE_CACHE_LINE_SIZE);\n-\t\tattr.init.cap.max_inline_data =\n-\t\t\ttmpl.txq.max_inline * RTE_CACHE_LINE_SIZE;\n \t\ttmpl.txq.inline_en = 1;\n+\t\t/* TSO and MPS can't be enabled concurrently. */\n+\t\tassert(!priv->tso || !priv->mps);\n+\t\tif (priv->mps == MLX5_MPW_ENHANCED) {\n+\t\t\ttmpl.txq.max_inline_len = priv->txq_max_inline_len;\n+\t\t\t/* To minimize the size of data set, avoid requesting\n+\t\t\t * too large WQ.\n+\t\t\t */\n+\t\t\tattr.init.cap.max_inline_data =\n+\t\t\t\t((RTE_MIN(priv->txq_inline,\n+\t\t\t\t\t priv->txq_max_inline_len) +\n+\t\t\t\t (RTE_CACHE_LINE_SIZE - 1)) /\n+\t\t\t\t RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;\n+\t\t} else {\n+\t\t\tattr.init.cap.max_inline_data =\n+\t\t\t\ttmpl.txq.max_inline * RTE_CACHE_LINE_SIZE;\n+\t\t}\n \t}\n \tif (priv->tso) {\n \t\tuint16_t max_tso_inline = ((MLX5_MAX_TSO_HEADER +\n", "prefixes": [ "dpdk-dev", "v2", "1/2" ] }