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GET /api/patches/21246/?format=api
{ "id": 21246, "url": "https://patches.dpdk.org/api/patches/21246/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1488533497-27682-2-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1488533497-27682-2-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1488533497-27682-2-git-send-email-beilei.xing@intel.com", "date": "2017-03-03T09:31:34", "name": "[dpdk-dev,1/4] net/i40e: support replace filter type", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f2bcc867ec81098a44c79baf38f7d19b239b0d84", "submitter": { "id": 410, "url": "https://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1488533497-27682-2-git-send-email-beilei.xing@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/21246/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/21246/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 6650B69C3;\n\tFri, 3 Mar 2017 10:33:02 +0100 (CET)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id 4D1C02C31\n\tfor <dev@dpdk.org>; Fri, 3 Mar 2017 10:32:49 +0100 (CET)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t03 Mar 2017 01:32:48 -0800", "from unknown (HELO dpdk9.sh.intel.com) ([10.239.129.31])\n\tby fmsmga006.fm.intel.com with ESMTP; 03 Mar 2017 01:32:46 -0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.35,236,1484035200\"; d=\"scan'208\";a=\"72335746\"", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "jingjing.wu@intel.com", "Cc": "helin.zhang@intel.com, dev@dpdk.org,\n\tBernard Iremonger <bernard.iremonger@intel.com>,\n\tStroe Laura <laura.stroe@intel.com>", "Date": "Fri, 3 Mar 2017 17:31:34 +0800", "Message-Id": "<1488533497-27682-2-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1488533497-27682-1-git-send-email-beilei.xing@intel.com>", "References": "<1488533497-27682-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH 1/4] net/i40e: support replace filter type", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add new admin queue function and extended fields\nin DCR 288:\n - Add admin queue function for Replace filter\n command (Opcode: 0x025F)\n - Add General fields for Add/Remove Cloud filters\n command\n\nThis patch will be removed to base driver in future.\n\nSigned-off-by: Bernard Iremonger <bernard.iremonger@intel.com>\nSigned-off-by: Stroe Laura <laura.stroe@intel.com>\nSigned-off-by: Jingjing Wu <jingjing.wu@intel.com>\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.h | 106 ++++++++++++++++++++++++++++\n drivers/net/i40e/i40e_flow.c | 152 +++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 258 insertions(+)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex f545850..3a49865 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -729,6 +729,100 @@ struct i40e_valid_pattern {\n \tparse_filter_t parse_filter;\n };\n \n+/* Support replace filter */\n+\n+/* i40e_aqc_add_remove_cloud_filters_element_big_data is used when\n+ * I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set. refer to\n+ * DCR288\n+ */\n+struct i40e_aqc_add_remove_cloud_filters_element_big_data {\n+\tstruct i40e_aqc_add_remove_cloud_filters_element_data element;\n+\tuint16_t general_fields[32];\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0\t0\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1\t1\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2\t2\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0\t3\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1\t4\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2\t5\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0\t6\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1\t7\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2\t8\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0\t9\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1\t10\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2\t11\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0\t12\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1\t13\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2\t14\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0\t15\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1\t16\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2\t17\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3\t18\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4\t19\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5\t20\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6\t21\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7\t22\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0\t23\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1\t24\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2\t25\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3\t26\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4\t27\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5\t28\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6\t29\n+#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7\t30\n+};\n+\n+/* Replace filter Command 0x025F\n+ * uses the i40e_aqc_replace_cloud_filters,\n+ * and the generic indirect completion structure\n+ */\n+struct i40e_filter_data {\n+\tuint8_t filter_type;\n+\tuint8_t input[3];\n+};\n+\n+struct i40e_aqc_replace_cloud_filters_cmd {\n+\tuint8_t valid_flags;\n+#define I40E_AQC_REPLACE_L1_FILTER\t0x0\n+#define I40E_AQC_REPLACE_CLOUD_FILTER\t0x1\n+#define I40E_AQC_GET_CLOUD_FILTERS\t0x2\n+#define I40E_AQC_MIRROR_CLOUD_FILTER\t0x4\n+#define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER\t0x8\n+\tuint8_t old_filter_type;\n+\tuint8_t new_filter_type;\n+\tuint8_t tr_bit;\n+\tuint8_t valid_bit_mask;\n+#define I40E_AQC_REPLACE_CLOUD_CMD_ENABLE_INPUT\t0x80\n+\tuint8_t reserved[4];\n+\tuint32_t addr_high;\n+\tuint32_t addr_low;\n+};\n+\n+struct i40e_aqc_replace_cloud_filters_cmd_buf {\n+\tuint8_t data[32];\n+\t/* Filter type INPUT codes*/\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX\t3\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED\t(1 << 7UL)\n+\n+\t/* Field Vector offsets */\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA\t0\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH\t6\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG\t7\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN\t8\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN\t9\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN\t10\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY\t11\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC\t12\n+\t/* big FLU */\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA\t14\n+\t/* big FLU */\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA\t15\n+\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN\t37\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0\t44\n+#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1\t45\n+\tstruct i40e_filter_data filters[8];\n+};\n+\n int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);\n int i40e_vsi_release(struct i40e_vsi *vsi);\n struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,\n@@ -806,6 +900,18 @@ int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,\n \t\t\t uint8_t add);\n int i40e_fdir_flush(struct rte_eth_dev *dev);\n \n+enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,\n+\t uint16_t seid,\n+\t struct i40e_aqc_add_remove_cloud_filters_element_big_data *filters,\n+\t uint8_t filter_count);\n+enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(\n+\tstruct i40e_hw *hw, uint16_t seid,\n+\tstruct i40e_aqc_add_remove_cloud_filters_element_big_data *filters,\n+\tuint8_t filter_count);\n+enum i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,\n+\t\t struct i40e_aqc_replace_cloud_filters_cmd *filters,\n+\t\t struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf);\n+\n #define I40E_DEV_TO_PCI(eth_dev) \\\n \tRTE_DEV_TO_PCI((eth_dev)->device)\n \ndiff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c\nindex f163ce5..3c49228 100644\n--- a/drivers/net/i40e/i40e_flow.c\n+++ b/drivers/net/i40e/i40e_flow.c\n@@ -1874,3 +1874,155 @@ i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)\n \n \treturn ret;\n }\n+\n+#define i40e_aqc_opc_replace_cloud_filters 0x025F\n+#define I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1\n+/**\n+ * i40e_aq_add_cloud_filters_big_buffer\n+ * @hw: pointer to the hardware structure\n+ * @seid: VSI seid to add cloud filters from\n+ * @filters: Buffer which contains the filters in big buffer to be added\n+ * @filter_count: number of filters contained in the buffer\n+ *\n+ * Set the cloud filters for a given VSI. The contents of the\n+ * i40e_aqc_add_remove_cloud_filters_element_big_data are filled\n+ * in by the caller of the function.\n+ *\n+ **/\n+enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(\n+\tstruct i40e_hw *hw, uint16_t seid,\n+\tstruct i40e_aqc_add_remove_cloud_filters_element_big_data *filters,\n+\tuint8_t filter_count)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_add_remove_cloud_filters *cmd =\n+\t\t(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;\n+\tenum i40e_status_code status;\n+\tuint16_t buff_len;\n+\tint i;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t i40e_aqc_opc_add_cloud_filters);\n+\n+\tbuff_len = filter_count * sizeof(*filters);\n+\tdesc.datalen = CPU_TO_LE16(buff_len);\n+\tdesc.flags |= CPU_TO_LE16(\n+\t\t(uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n+\tcmd->num_filters = filter_count;\n+\tcmd->seid = CPU_TO_LE16(seid);\n+\tcmd->reserved2[0] = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;\n+\n+\t/* adjust Geneve VNI for HW issue */\n+\tfor (i = 0; i < filter_count; i++) {\n+\t\tuint16_t tnl_type;\n+\t\tuint32_t ti;\n+\n+\t\ttnl_type = (LE16_TO_CPU(filters[i].element.flags) &\n+\t\t\t I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>\n+\t\t\tI40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;\n+\t\tif (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {\n+\t\t\tti = LE32_TO_CPU(filters[i].element.tenant_id);\n+\t\t\tfilters[i].element.tenant_id = CPU_TO_LE32(ti << 8);\n+\t\t}\n+\t}\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_aq_remove_cloud_filters_big_buffer\n+ * @hw: pointer to the hardware structure\n+ * @seid: VSI seid to remove cloud filters from\n+ * @filters: Buffer which contains the filters in big buffer to be removed\n+ * @filter_count: number of filters contained in the buffer\n+ *\n+ * Remove the cloud filters for a given VSI. The contents of the\n+ * i40e_aqc_add_remove_cloud_filters_element_big_data are filled\n+ * in by the caller of the function.\n+ *\n+ **/\n+enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(\n+\tstruct i40e_hw *hw, uint16_t seid,\n+\tstruct i40e_aqc_add_remove_cloud_filters_element_big_data *filters,\n+\tuint8_t filter_count)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_add_remove_cloud_filters *cmd =\n+\t\t(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;\n+\tenum i40e_status_code status;\n+\tuint16_t buff_len;\n+\tint i;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t i40e_aqc_opc_remove_cloud_filters);\n+\n+\tbuff_len = filter_count * sizeof(*filters);\n+\tdesc.datalen = CPU_TO_LE16(buff_len);\n+\tdesc.flags |= CPU_TO_LE16(\n+\t\t(uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n+\tcmd->num_filters = filter_count;\n+\tcmd->seid = CPU_TO_LE16(seid);\n+\tcmd->reserved2[0] = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;\n+\n+\t/* adjust Geneve VNI for HW issue */\n+\tfor (i = 0; i < filter_count; i++) {\n+\t\tuint16_t tnl_type;\n+\t\tuint32_t ti;\n+\n+\t\ttnl_type = (LE16_TO_CPU(filters[i].element.flags) &\n+\t\t\t I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>\n+\t\t\tI40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;\n+\t\tif (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {\n+\t\t\tti = LE32_TO_CPU(filters[i].element.tenant_id);\n+\t\t\tfilters[i].element.tenant_id = CPU_TO_LE32(ti << 8);\n+\t\t}\n+\t}\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_aq_replace_cloud_filters - Replace cloud filter command\n+ * @hw: pointer to the hw struct\n+ * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct\n+ * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct\n+ **/\n+enum\n+i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,\n+\t struct i40e_aqc_replace_cloud_filters_cmd *filters,\n+\t struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_replace_cloud_filters_cmd *cmd =\n+\t\t(struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;\n+\tenum i40e_status_code status = I40E_SUCCESS;\n+\tint i = 0;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t i40e_aqc_opc_replace_cloud_filters);\n+\n+\tdesc.datalen = CPU_TO_LE16(32);\n+\tdesc.flags |= CPU_TO_LE16(\n+\t\t(uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n+\tcmd->old_filter_type = filters->old_filter_type;\n+\tcmd->new_filter_type = filters->new_filter_type;\n+\tcmd->valid_flags = filters->valid_flags;\n+\tcmd->tr_bit = filters->tr_bit;\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, cmd_buf,\n+\t sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);\n+\n+\t/* for get cloud filters command */\n+\tfor (i = 0; i < 32; i += 4) {\n+\t\tcmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];\n+\t\tcmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];\n+\t\tcmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];\n+\t\tcmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];\n+\t}\n+\n+\treturn status;\n+}\n", "prefixes": [ "dpdk-dev", "1/4" ] }