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GET /api/patches/21179/?format=api
{ "id": 21179, "url": "https://patches.dpdk.org/api/patches/21179/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/BD6A1439499EDC42898C5257367F506233D9194F@SHSMSX101.ccr.corp.intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<BD6A1439499EDC42898C5257367F506233D9194F@SHSMSX101.ccr.corp.intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/BD6A1439499EDC42898C5257367F506233D9194F@SHSMSX101.ccr.corp.intel.com", "date": "2017-03-03T06:23:30", "name": "[dpdk-dev,1/2] crypto/qat: add ZUC EEA3 cipher capability", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "4b48ecb6c5b1297bb28dc7faa5f7ccf930e9e4a5", "submitter": { "id": 631, "url": "https://patches.dpdk.org/api/people/631/?format=api", "name": "yang yang", "email": "gangx.yang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/BD6A1439499EDC42898C5257367F506233D9194F@SHSMSX101.ccr.corp.intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/21179/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/21179/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id D91782A5E;\n\tFri, 3 Mar 2017 07:23:46 +0100 (CET)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id AF7A43DC\n\tfor <dev@dpdk.org>; Fri, 3 Mar 2017 07:23:36 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t02 Mar 2017 22:23:35 -0800", "from fmsmsx105.amr.corp.intel.com ([10.18.124.203])\n\tby orsmga002.jf.intel.com with ESMTP; 02 Mar 2017 22:23:35 -0800", "from shsmsx102.ccr.corp.intel.com (10.239.4.154) by\n\tFMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP\n\tServer (TLS) id 14.3.248.2; Thu, 2 Mar 2017 22:23:34 -0800", "from shsmsx101.ccr.corp.intel.com ([169.254.1.177]) by\n\tshsmsx102.ccr.corp.intel.com ([169.254.2.88]) with mapi id\n\t14.03.0248.002; Fri, 3 Mar 2017 14:23:30 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.35,235,1484035200\"; d=\"scan'208\";a=\"55351052\"", "From": "\"Yang, GangX\" <gangx.yang@intel.com>", "To": "\"dev@dpdk.org\" <dev@dpdk.org>", "CC": "\"Trahe, Fiona\" <fiona.trahe@intel.com>, \"De Lara Guarch, Pablo\"\n\t<pablo.de.lara.guarch@intel.com>, \"Griffin,\n\tJohn\" <john.griffin@intel.com>, \n\t\"Jain, Deepak K\" <deepak.k.jain@intel.com>, \"Kusztal, ArkadiuszX\"\n\t<arkadiuszx.kusztal@intel.com>, \"Yang, GangX\" <gangx.yang@intel.com>", "Thread-Topic": "[dpdk-dev] [PATCH 1/2] crypto/qat: add ZUC EEA3 cipher\n\tcapability", "Thread-Index": "AQHSkmFoDaPlm6CqZ0CNAvoqnD3LmqGCpdQQ", "Date": "Fri, 3 Mar 2017 06:23:30 +0000", "Message-ID": "<BD6A1439499EDC42898C5257367F506233D9194F@SHSMSX101.ccr.corp.intel.com>", "References": "<1488354962-12144-1-git-send-email-arkadiuszx.kusztal@intel.com>\n\t<1488354962-12144-2-git-send-email-arkadiuszx.kusztal@intel.com>", "In-Reply-To": "<1488354962-12144-2-git-send-email-arkadiuszx.kusztal@intel.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-originating-ip": "[10.239.127.40]", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "Subject": "Re: [dpdk-dev] [PATCH 1/2] crypto/qat: add ZUC EEA3 cipher\n\tcapability", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Tested-by: Yang Gang < gangx.yang@intel.com >\n- Check patch: success\n- Apply patch: success\n- compilation: success\n OS: fedora23\n GCC: gcc_x86-64, 5.3.1\n Commit: dpdk-next-crypto(081fefb01748e7063b1b9692af89d8115ec64632)\n x86_64-native-linuxapp-gcc: compile pass\n- dts validation:\n-- Test Commit: e5041333988936fdb09d578ec4fb7cb0ce796ecb\n-- OS/Kernel: Fedora23/4.2.3-300.fc23.x86_64\n-- GCC: gcc version 5.3.1\n-- CPU: Intel(R) Xeon(R) CPU E5-2680 v2 @ 1.80GHz\n-- NIC: Intel Corporation Ethernet Controller X710 for 10GbE SFP+ [8086:1572]\n-- total 2,failed 1 (case1: contain cryptodev_qat_autotest and all of others cryptodev cases on unit test .\n\t\t case 2: all of the related cases about HW zuc cipher only , cipher_hash and hash only on l2fwd-crypto test)\n-- failed message: case 1 pass . case 2 failed . QAT zuc failed when do cipher hash and hash only test . cipher_only is normal . \n\tMessage : \n\tAlgorithm zuc-eia3 not supported by cryptodev 0 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 1 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 2 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 3 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 4 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 5 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 6 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 7 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 8 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 9 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 10 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 11 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 12 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 13 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 14 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 15 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 16 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 17 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 18 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 19 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 20 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 21 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 22 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 23 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 24 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 25 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 26 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 27 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 28 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 29 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 30 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 31 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 32 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 33 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 34 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 35 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 36 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 37 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 38 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 39 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 40 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 41 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 42 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 43 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 44 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 45 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 46 or device not of preferred type (ANY)\n\tAlgorithm zuc-eia3 not supported by cryptodev 47 or device not of preferred type (ANY)\n\tEAL: Error - exiting with code: 1\n\t\t Cause: Number of capable crypto devices (0) has to be more or equal to number of ports (1)\n \n\n-----Original Message-----\nFrom: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Arek Kusztal\nSent: Wednesday, March 01, 2017 3:56 PM\nTo: dev@dpdk.org\nCc: Trahe, Fiona <fiona.trahe@intel.com>; De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>; Griffin, John <john.griffin@intel.com>; Jain, Deepak K <deepak.k.jain@intel.com>; Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>\nSubject: [dpdk-dev] [PATCH 1/2] crypto/qat: add ZUC EEA3 cipher capability\n\nThis commit adds ZUC EEA3 cipher capability to Intel(R) QuickAssist Technology driver\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\n---\n doc/guides/cryptodevs/qat.rst | 2 +\n drivers/crypto/qat/qat_adf/qat_algs.h | 11 ++-\n drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 97 ++++++++++++++++++++----\n drivers/crypto/qat/qat_crypto.c | 34 ++++++++-\n 4 files changed, 125 insertions(+), 19 deletions(-)\n\n--\n2.7.4", "diff": "diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 9ecd19b..79b9c9d 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -55,6 +55,7 @@ Cipher algorithms:\n * ``RTE_CRYPTO_CIPHER_NULL``\n * ``RTE_CRYPTO_CIPHER_KASUMI_F8``\n * ``RTE_CRYPTO_CIPHER_DES_CBC``\n+* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``\n \n Hash algorithms:\n \n@@ -79,6 +80,7 @@ Limitations\n * SNOW 3G (UEA2) and KASUMI (F8) supported only if cipher length, cipher offset fields are byte-aligned.\n * SNOW 3G (UIA2) and KASUMI (F9) supported only if hash length, hash offset fields are byte-aligned.\n * No BSD support as BSD QAT kernel driver not available.\n+* ZUC EEA3 is not supported by dh895xcc devices\n \n \n Installation\ndiff --git a/drivers/crypto/qat/qat_adf/qat_algs.h b/drivers/crypto/qat/qat_adf/qat_algs.h\nindex b9e3fd6..37f64d4 100644\n--- a/drivers/crypto/qat/qat_adf/qat_algs.h\n+++ b/drivers/crypto/qat/qat_adf/qat_algs.h\n@@ -80,6 +80,14 @@ struct qat_alg_buf {\n \tuint64_t addr;\n } __rte_packed;\n \n+enum qat_crypto_proto_flag {\n+\tQAT_CRYPTO_PROTO_FLAG_NONE = 0,\n+\tQAT_CRYPTO_PROTO_FLAG_CCM = 1,\n+\tQAT_CRYPTO_PROTO_FLAG_GCM = 2,\n+\tQAT_CRYPTO_PROTO_FLAG_SNOW3G = 3,\n+\tQAT_CRYPTO_PROTO_FLAG_ZUC = 4\n+};\n+\n /*\n * Maximum number of SGL entries\n */\n@@ -143,7 +151,7 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,\n \t\t\t\t\t\tunsigned int operation);\n \n void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header,\n-\t\t\t\t\t\tuint16_t proto);\n+\t\t\t\t\t\tenum qat_crypto_proto_flag proto_flags);\n \n void qat_alg_ablkcipher_init_enc(struct qat_alg_ablkcipher_cd *cd,\n \t\t\t\t\tint alg, const uint8_t *key,\n@@ -158,4 +166,5 @@ int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg); int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg); int qat_alg_validate_3des_key(int key_len, enum icp_qat_hw_cipher_algo *alg); int qat_alg_validate_des_key(int key_len, enum icp_qat_hw_cipher_algo *alg);\n+int qat_alg_validate_zuc_key(int key_len, enum icp_qat_hw_cipher_algo \n+*alg);\n #endif\ndiff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\nindex fbeef0a..3831d19 100644\n--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\n+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\n@@ -422,7 +422,7 @@ static int qat_alg_do_precomputes(enum icp_qat_hw_auth_algo hash_alg, }\n \n void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header,\n-\t\tuint16_t proto)\n+\t\tenum qat_crypto_proto_flag proto_flags)\n {\n \tPMD_INIT_FUNC_TRACE();\n \theader->hdr_flags =\n@@ -435,14 +435,60 @@ void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header,\n \t\t\t\t ICP_QAT_FW_LA_PARTIAL_NONE);\n \tICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(header->serv_specif_flags,\n \t\t\t\t\t ICP_QAT_FW_CIPH_IV_16BYTE_DATA);\n-\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n-\t\t\t\tproto);\n+\n+\tswitch (proto_flags)\t\t{\n+\tcase QAT_CRYPTO_PROTO_FLAG_NONE:\n+\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_NO_PROTO);\n+\t\tbreak;\n+\tcase QAT_CRYPTO_PROTO_FLAG_CCM:\n+\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_CCM_PROTO);\n+\t\tbreak;\n+\tcase QAT_CRYPTO_PROTO_FLAG_GCM:\n+\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_GCM_PROTO);\n+\t\tbreak;\n+\tcase QAT_CRYPTO_PROTO_FLAG_SNOW3G:\n+\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_SNOW_3G_PROTO);\n+\t\tbreak;\n+\tcase QAT_CRYPTO_PROTO_FLAG_ZUC:\n+\t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(header->serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_ZUC_3G_PROTO);\n+\t\tbreak;\n+\t}\n+\n \tICP_QAT_FW_LA_UPDATE_STATE_SET(header->serv_specif_flags,\n \t\t\t\t\t ICP_QAT_FW_LA_NO_UPDATE_STATE);\n \tICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(header->serv_specif_flags,\n \t\t\t\t\tICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);\n }\n \n+/*\n+ *\tSnow3G and ZUC should never use this function\n+ *\tand set its protocol flag in both cipher and auth part of content\n+ *\tdescriptor building function\n+ */\n+static enum qat_crypto_proto_flag\n+qat_get_crypto_proto_flag(uint16_t flags) {\n+\tint proto = ICP_QAT_FW_LA_PROTO_GET(flags);\n+\tenum qat_crypto_proto_flag qat_proto_flag =\n+\t\t\tQAT_CRYPTO_PROTO_FLAG_NONE;\n+\n+\tswitch (proto) {\n+\tcase ICP_QAT_FW_LA_GCM_PROTO:\n+\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;\n+\t\tbreak;\n+\tcase ICP_QAT_FW_LA_CCM_PROTO:\n+\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_CCM;\n+\t\tbreak;\n+\t}\n+\n+\treturn qat_proto_flag;\n+}\n+\n int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,\n \t\t\t\t\t\tuint8_t *cipherkey,\n \t\t\t\t\t\tuint32_t cipherkeylen)\n@@ -455,8 +501,9 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,\n \tstruct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;\n \tstruct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;\n \tenum icp_qat_hw_cipher_convert key_convert;\n+\tenum qat_crypto_proto_flag qat_proto_flag =\n+\t\tQAT_CRYPTO_PROTO_FLAG_NONE;\n \tuint32_t total_key_size;\n-\tuint16_t proto = ICP_QAT_FW_LA_NO_PROTO;\t/* no CCM/GCM/SNOW 3G */\n \tuint16_t cipher_offset, cd_size;\n \tuint32_t wordIndex = 0;\n \tuint32_t *temp_key = NULL;\n@@ -496,7 +543,8 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,\n \t\t */\n \t\tcdesc->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n \t\tkey_convert = ICP_QAT_HW_CIPHER_NO_CONVERT;\n-\t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2)\n+\t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2\n+\t\t|| cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)\n \t\tkey_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;\n \telse if (cdesc->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT)\n \t\tkey_convert = ICP_QAT_HW_CIPHER_NO_CONVERT; @@ -508,7 +556,8 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,\n \t\t\tICP_QAT_HW_SNOW_3G_UEA2_IV_SZ;\n \t\tcipher_cd_ctrl->cipher_state_sz =\n \t\t\tICP_QAT_HW_SNOW_3G_UEA2_IV_SZ >> 3;\n-\t\tproto = ICP_QAT_FW_LA_SNOW_3G_PROTO;\n+\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;\n+\n \t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {\n \t\ttotal_key_size = ICP_QAT_HW_KASUMI_F8_KEY_SZ;\n \t\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_KASUMI_BLK_SZ >> 3; @@ -517,25 +566,30 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,\n \t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES) {\n \t\ttotal_key_size = ICP_QAT_HW_3DES_KEY_SZ;\n \t\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_3DES_BLK_SZ >> 3;\n-\t\tproto = ICP_QAT_FW_LA_PROTO_GET(header->serv_specif_flags);\n+\t\tqat_proto_flag = \n+qat_get_crypto_proto_flag(header->serv_specif_flags);\n \t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_DES) {\n \t\ttotal_key_size = ICP_QAT_HW_DES_KEY_SZ;\n \t\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_DES_BLK_SZ >> 3;\n-\t\tproto = ICP_QAT_FW_LA_PROTO_GET(header->serv_specif_flags);\n+\t\tqat_proto_flag = qat_get_crypto_proto_flag(header->serv_specif_flags);\n+\t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n+\t\ttotal_key_size = ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ +\n+\t\t\tICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;\n+\t\tcipher_cd_ctrl->cipher_state_sz =\n+\t\t\tICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;\n+\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n \t} else {\n \t\ttotal_key_size = cipherkeylen;\n \t\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;\n-\t\tproto = ICP_QAT_FW_LA_PROTO_GET(header->serv_specif_flags);\n+\t\tqat_proto_flag = \n+qat_get_crypto_proto_flag(header->serv_specif_flags);\n \t}\n \tcipher_cd_ctrl->cipher_key_sz = total_key_size >> 3;\n \tcipher_offset = cdesc->cd_cur_ptr-((uint8_t *)&cdesc->cd);\n \tcipher_cd_ctrl->cipher_cfg_offset = cipher_offset >> 3;\n \n \theader->service_cmd_id = cdesc->qat_cmd;\n-\tqat_alg_init_common_hdr(header, proto);\n+\tqat_alg_init_common_hdr(header, qat_proto_flag);\n \n \tcipher = (struct icp_qat_hw_cipher_algo_blk *)cdesc->cd_cur_ptr;\n-\n \tcipher->cipher_config.val =\n \t ICP_QAT_HW_CIPHER_CONFIG_BUILD(cdesc->qat_mode,\n \t\t\t\t\tcdesc->qat_cipher_alg, key_convert, @@ -596,12 +650,13 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,\n \t\t(struct icp_qat_fw_la_auth_req_params *)\n \t\t((char *)&req_tmpl->serv_specif_rqpars +\n \t\tsizeof(struct icp_qat_fw_la_cipher_req_params));\n-\tuint16_t proto = ICP_QAT_FW_LA_NO_PROTO;\t/* no CCM/GCM/SNOW 3G */\n \tuint16_t state1_size = 0, state2_size = 0;\n \tuint16_t hash_offset, cd_size;\n \tuint32_t *aad_len = NULL;\n \tuint32_t wordIndex = 0;\n \tuint32_t *pTempKey;\n+\tenum qat_crypto_proto_flag qat_proto_flag =\n+\t\tQAT_CRYPTO_PROTO_FLAG_NONE;\n \n \tPMD_INIT_FUNC_TRACE();\n \n@@ -714,7 +769,7 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\n \tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_64:\n-\t\tproto = ICP_QAT_FW_LA_GCM_PROTO;\n+\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;\n \t\tstate1_size = ICP_QAT_HW_GALOIS_128_STATE1_SZ;\n \t\tif (qat_alg_do_precomputes(cdesc->qat_hash_alg,\n \t\t\tauthkey, authkeylen, cdesc->cd_cur_ptr + state1_size, @@ -736,7 +791,7 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,\n \t\t*aad_len = rte_bswap32(add_auth_data_length);\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:\n-\t\tproto = ICP_QAT_FW_LA_SNOW_3G_PROTO;\n+\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;\n \t\tstate1_size = qat_hash_get_state1_size(\n \t\t\t\tICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2);\n \t\tstate2_size = ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ;\n@@ -794,7 +849,7 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,\n \t}\n \n \t/* Request template setup */\n-\tqat_alg_init_common_hdr(header, proto);\n+\tqat_alg_init_common_hdr(header, qat_proto_flag);\n \theader->service_cmd_id = cdesc->qat_cmd;\n \n \t/* Auth CD config setup */\n@@ -886,3 +941,15 @@ int qat_alg_validate_3des_key(int key_len, enum icp_qat_hw_cipher_algo *alg)\n \t}\n \treturn 0;\n }\n+\n+int qat_alg_validate_zuc_key(int key_len, enum icp_qat_hw_cipher_algo \n+*alg) {\n+\tswitch (key_len) {\n+\tcase ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ:\n+\t\t*alg = ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c index 43e1d00..fff51c8 100644\n--- a/drivers/crypto/qat/qat_crypto.c\n+++ b/drivers/crypto/qat/qat_crypto.c\n@@ -516,6 +516,26 @@ static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {\n \t\t\t}, }\n \t\t}, }\n \t},\n+\t\t{\t/* ZUC (EEA3) */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n \n@@ -674,13 +694,20 @@ qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,\n \t\t}\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n \t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_ZUC_EEA3:\n+\t\tif (qat_alg_validate_zuc_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid ZUC cipher key size\");\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n+\t\tbreak;\n \tcase RTE_CRYPTO_CIPHER_3DES_ECB:\n \tcase RTE_CRYPTO_CIPHER_AES_ECB:\n \tcase RTE_CRYPTO_CIPHER_AES_CCM:\n \tcase RTE_CRYPTO_CIPHER_AES_F8:\n \tcase RTE_CRYPTO_CIPHER_AES_XTS:\n \tcase RTE_CRYPTO_CIPHER_ARC4:\n-\tcase RTE_CRYPTO_CIPHER_ZUC_EEA3:\n \t\tPMD_DRV_LOG(ERR, \"Crypto QAT PMD: Unsupported Cipher alg %u\",\n \t\t\t\tcipher_xform->algo);\n \t\tgoto error_out;\n@@ -1085,14 +1112,15 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,\n \n \t\tif (ctx->qat_cipher_alg ==\n \t\t\t\t\t ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n-\t\t\tctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {\n+\t\t\tctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI\t||\n+\t\t\tctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n \n \t\t\tif (unlikely(\n \t\t\t\t(cipher_param->cipher_length % BYTE_LENGTH != 0)\n \t\t\t\t || (cipher_param->cipher_offset\n \t\t\t\t\t\t\t% BYTE_LENGTH != 0))) {\n \t\t\t\tPMD_DRV_LOG(ERR,\n-\t\t \"SNOW3G/KASUMI in QAT PMD only supports byte aligned values\");\n+\t\t \"SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values\");\n \t\t\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n \t\t\t\treturn -EINVAL;\n \t\t\t}\n", "prefixes": [ "dpdk-dev", "1/2" ] }