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{
    "id": 21158,
    "url": "https://patches.dpdk.org/api/patches/21158/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20170303031727.461-4-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20170303031727.461-4-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20170303031727.461-4-qi.z.zhang@intel.com",
    "date": "2017-03-03T03:17:13",
    "name": "[dpdk-dev,03/17] net/fm10k/base: expose macros needed by DPDK",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "56d8c1c423d43b295a86732f897f4614affec945",
    "submitter": {
        "id": 504,
        "url": "https://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20170303031727.461-4-qi.z.zhang@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/21158/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/21158/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 4FABAD4E0;\n\tFri,  3 Mar 2017 03:27:07 +0100 (CET)",
            "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby dpdk.org (Postfix) with ESMTP id 0F9BC37AA\n\tfor <dev@dpdk.org>; Fri,  3 Mar 2017 03:26:39 +0100 (CET)",
            "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby orsmga104.jf.intel.com with ESMTP; 02 Mar 2017 18:26:39 -0800",
            "from unknown (HELO localhost.localdomain.sh.intel.com)\n\t([10.239.129.167])\n\tby orsmga005.jf.intel.com with ESMTP; 02 Mar 2017 18:26:38 -0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.35,234,1484035200\"; d=\"scan'208\";a=\"71069207\"",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "jing.d.chen@intel.com",
        "Cc": "helin.zhang@intel.com,\n\tdev@dpdk.org,\n\tQi Zhang <qi.z.zhang@intel.com>",
        "Date": "Thu,  2 Mar 2017 22:17:13 -0500",
        "Message-Id": "<20170303031727.461-4-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.9.3",
        "In-Reply-To": "<20170303031727.461-1-qi.z.zhang@intel.com>",
        "References": "<20170303031727.461-1-qi.z.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 03/17] net/fm10k/base: expose macros needed by\n\tDPDK",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Some defines were previously wrapped to strip them from opensource driver\nbuilds, but these are required by DPDK.  Change the wrapping of these so \nthat the DPDK gets them as long as DPDK_SUPPORT is correctly added as a \nstrip flag, while we can remove the reduandant ones in fm10k_osdep.h.\n\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/fm10k/base/fm10k_osdep.h | 17 ------------\n drivers/net/fm10k/base/fm10k_type.h  | 50 ++++++++++++++++++++++++++++++++++++\n 2 files changed, 50 insertions(+), 17 deletions(-)",
    "diff": "diff --git a/drivers/net/fm10k/base/fm10k_osdep.h b/drivers/net/fm10k/base/fm10k_osdep.h\nindex f07b678..199ebd8 100644\n--- a/drivers/net/fm10k/base/fm10k_osdep.h\n+++ b/drivers/net/fm10k/base/fm10k_osdep.h\n@@ -163,23 +163,6 @@ typedef int        bool;\n #define FM10K_RXD_PKTTYPE_MASK\t\t0x03F0\n #define FM10K_RXD_PKTTYPE_SHIFT\t\t4\n \n-enum fm10k_rdesc_pkt_type {\n-\t/* L3 type */\n-\tFM10K_PKTTYPE_OTHER\t= 0x00,\n-\tFM10K_PKTTYPE_IPV4\t= 0x01,\n-\tFM10K_PKTTYPE_IPV4_EX\t= 0x02,\n-\tFM10K_PKTTYPE_IPV6\t= 0x03,\n-\tFM10K_PKTTYPE_IPV6_EX\t= 0x04,\n-\n-\t/* L4 type */\n-\tFM10K_PKTTYPE_TCP\t= 0x08,\n-\tFM10K_PKTTYPE_UDP\t= 0x10,\n-\tFM10K_PKTTYPE_GRE\t= 0x18,\n-\tFM10K_PKTTYPE_VXLAN\t= 0x20,\n-\tFM10K_PKTTYPE_NVGRE\t= 0x28,\n-\tFM10K_PKTTYPE_GENEVE\t= 0x30\n-};\n-\n #define FM10K_RXD_STATUS_IPCS\t\t0x0008 /* Indicates IPv4 csum */\n #define FM10K_RXD_STATUS_HBO\t\t0x0400 /* header buffer overrun */\n \ndiff --git a/drivers/net/fm10k/base/fm10k_type.h b/drivers/net/fm10k/base/fm10k_type.h\nindex fe3e498..8ddfd49 100644\n--- a/drivers/net/fm10k/base/fm10k_type.h\n+++ b/drivers/net/fm10k/base/fm10k_type.h\n@@ -40,6 +40,9 @@ struct fm10k_hw;\n #include \"fm10k_osdep.h\"\n #include \"fm10k_mbx.h\"\n \n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+#define FM10K_INTEL_VENDOR_ID\t\t0x8086\n+#endif\n #define FM10K_DEV_ID_PF\t\t\t0x15A4\n #define FM10K_DEV_ID_VF\t\t\t0x15A5\n #ifdef BOULDER_RAPIDS_HW\n@@ -125,11 +128,19 @@ struct fm10k_hw;\n \n /* Interrupt control registers */\n #define FM10K_EICR\t\t0x0006\n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+#define FM10K_EICR_PCA_FAULT\t\t\t0x00000001\n+#define FM10K_EICR_THI_FAULT\t\t\t0x00000004\n+#define FM10K_EICR_FUM_FAULT\t\t\t0x00000020\n+#endif\n #define FM10K_EICR_FAULT_MASK\t\t\t0x0000003F\n #define FM10K_EICR_MAILBOX\t\t\t0x00000040\n #define FM10K_EICR_SWITCHREADY\t\t\t0x00000080\n #define FM10K_EICR_SWITCHNOTREADY\t\t0x00000100\n #define FM10K_EICR_SWITCHINTERRUPT\t\t0x00000200\n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+#define FM10K_EICR_SRAMERROR\t\t\t0x00000400\n+#endif\n #define FM10K_EICR_VFLR\t\t\t\t0x00000800\n #define FM10K_EICR_MAXHOLDTIME\t\t\t0x00001000\n #define FM10K_EIMR\t\t0x0007\n@@ -211,6 +222,9 @@ struct fm10k_hw;\n #define FM10K_DMA_CTRL_RX_ENABLE\t\t0x00000010\n #define FM10K_DMA_CTRL_RX_ACTIVE\t\t0x00000080\n #define FM10K_DMA_CTRL_RX_DESC_SIZE\t\t0x00000100\n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+#define FM10K_DMA_CTRL_MINMSS_SHIFT\t\t9\n+#endif\n #define FM10K_DMA_CTRL_MINMSS_64\t\t0x00008000\n #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3\t0x04800000\n #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2\t0x04000000\n@@ -283,6 +297,9 @@ struct fm10k_hw;\n #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY\t0x00000001\n #define FM10K_RXDCTL_DROP_ON_EMPTY\t\t0x00000200\n #define FM10K_RXINT(_n)\t\t((0x40 * (_n)) + 0x4008)\n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+#define FM10K_RXINT_TIMER_SHIFT\t\t\t8\n+#endif\n #define FM10K_SRRCTL(_n)\t((0x40 * (_n)) + 0x4009)\n #define FM10K_SRRCTL_BSIZEPKT_SHIFT\t\t8 /* shift _right_ */\n #define FM10K_SRRCTL_LOOPBACK_SUPPRESS\t\t0x40000000\n@@ -336,6 +353,9 @@ struct fm10k_hw;\n #define FM10K_TXQCTL_VID_MASK\t\t\t0x0FFF0000\n #define FM10K_TXQCTL_UNLIMITED_BW\t\t0x10000000\n #define FM10K_TXINT(_n)\t\t((0x40 * (_n)) + 0x8008)\n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+#define FM10K_TXINT_TIMER_SHIFT\t\t\t8\n+#endif\n \n /* Tx Statistics */\n #define FM10K_QPTC(_n)\t\t((0x40 * (_n)) + 0x8009)\n@@ -374,6 +394,9 @@ struct fm10k_hw;\n /* Switch manager interrupt registers */\n #define FM10K_IP\t\t0x13000\n #define FM10K_IP_NOTINRESET\t\t\t0x00000100\n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+#define FM10K_SRAM_IP\t\t0x13003\n+#endif\n \n /* VLAN registers */\n #define FM10K_VLAN_TABLE(_n, _m)\t((0x80 * (_n)) + (_m) + 0x14000)\n@@ -815,6 +838,30 @@ enum fm10k_rdesc_rss_type {\n \t/* Reserved 0x9 - 0xF */\n };\n \n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+#define FM10K_RXD_PKTTYPE_MASK\t\t0x03F0\n+#endif\n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+#define FM10K_RXD_PKTTYPE_SHIFT\t\t4\n+#endif\n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+enum fm10k_rdesc_pkt_type {\n+\t/* L3 type */\n+\tFM10K_PKTTYPE_OTHER\t= 0x00,\n+\tFM10K_PKTTYPE_IPV4\t= 0x01,\n+\tFM10K_PKTTYPE_IPV4_EX\t= 0x02,\n+\tFM10K_PKTTYPE_IPV6\t= 0x03,\n+\tFM10K_PKTTYPE_IPV6_EX\t= 0x04,\n+\n+\t/* L4 type */\n+\tFM10K_PKTTYPE_TCP\t= 0x08,\n+\tFM10K_PKTTYPE_UDP\t= 0x10,\n+\tFM10K_PKTTYPE_GRE\t= 0x18,\n+\tFM10K_PKTTYPE_VXLAN\t= 0x20,\n+\tFM10K_PKTTYPE_NVGRE\t= 0x28,\n+\tFM10K_PKTTYPE_GENEVE\t= 0x30\n+};\n+#endif\n \n #define FM10K_RXD_HDR_INFO_XC_MASK\t0x0006\n enum fm10k_rxdesc_xc {\n@@ -826,6 +873,9 @@ enum fm10k_rxdesc_xc {\n \n #define FM10K_RXD_STATUS_DD\t\t0x0001 /* Descriptor done */\n #define FM10K_RXD_STATUS_EOP\t\t0x0002 /* End of packet */\n+#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT)\n+#define FM10K_RXD_STATUS_IPCS\t\t0x0008 /* Indicates IPv4 csum */\n+#endif\n #define FM10K_RXD_STATUS_L4CS\t\t0x0010 /* Indicates an L4 csum */\n #define FM10K_RXD_STATUS_L4CS2\t\t0x0040 /* Inner header L4 csum */\n #define FM10K_RXD_STATUS_L4E2\t\t0x0800 /* Inner header L4 csum err */\n",
    "prefixes": [
        "dpdk-dev",
        "03/17"
    ]
}