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GET /api/patches/17249/?format=api
{ "id": 17249, "url": "https://patches.dpdk.org/api/patches/17249/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/d4553cbb56244ca8b2251bf869515e2078e0f08d.1479995764.git.nelio.laranjeiro@6wind.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<d4553cbb56244ca8b2251bf869515e2078e0f08d.1479995764.git.nelio.laranjeiro@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/d4553cbb56244ca8b2251bf869515e2078e0f08d.1479995764.git.nelio.laranjeiro@6wind.com", "date": "2016-11-24T16:03:31", "name": "[dpdk-dev,2/7] net/mlx5: use work queue buffer as a raw buffer", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7cfd4371ce472d9d3ab3ffd30a3c3a4e05450e62", "submitter": { "id": 243, "url": "https://patches.dpdk.org/api/people/243/?format=api", "name": "Nélio Laranjeiro", "email": "nelio.laranjeiro@6wind.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/d4553cbb56244ca8b2251bf869515e2078e0f08d.1479995764.git.nelio.laranjeiro@6wind.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/17249/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/17249/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 327A9567A;\n\tThu, 24 Nov 2016 17:04:15 +0100 (CET)", "from mail-wm0-f53.google.com (mail-wm0-f53.google.com\n\t[74.125.82.53]) by dpdk.org (Postfix) with ESMTP id 8C43E2BEF\n\tfor <dev@dpdk.org>; Thu, 24 Nov 2016 17:04:02 +0100 (CET)", "by mail-wm0-f53.google.com with SMTP id t79so66078002wmt.0\n\tfor <dev@dpdk.org>; Thu, 24 Nov 2016 08:04:02 -0800 (PST)", "from ping.vm.6wind.com (guy78-3-82-239-227-177.fbx.proxad.net.\n\t[82.239.227.177]) by smtp.gmail.com with ESMTPSA id\n\tvr9sm42495142wjc.35.2016.11.24.08.04.00\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tThu, 24 Nov 2016 08:04:01 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=6wind-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:in-reply-to:references;\n\tbh=ia4umRQTxh4DCTLBU89AdGqvbzCpTk6vAglhyIY2T+o=;\n\tb=rcS8gA/kscwgFRkIoy36VNfrcos+2eXdegZ2fadYDGa5yFvfokCb+n1Sf/iYFATmYP\n\tDhhfVavFZhLjnWBha6hZECS0F0cCB+IMUCLx/XZQs26gSutPdk03YCsg8lALwHUHoPQw\n\tyN/BIu6WoSL5anywkpK6d5jJTNMSYlwENItvxIRprplLC6MrqCYrci1c6X0UO0zrj+RJ\n\tarxY3zdNUxGyTIvYSusgZ3Jjyd61BcTJzjgte+FzaDORHZh5mT6vEURXQP9x3FdlXexm\n\t5svX3iH95/MPJoznrawdpzKASNjz0avLw9BaJwk0UU6/GIFMyzgGZKvuMW6wNtaGNFGy\n\tEAFg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:in-reply-to:references;\n\tbh=ia4umRQTxh4DCTLBU89AdGqvbzCpTk6vAglhyIY2T+o=;\n\tb=VbRGVTZwEW4wLeVEtoLdj5trjjw6px8QJFRO6gC3uTjtH5wUY5QjE600foA8ETzomV\n\tZmJsxTGH1USrCK2KPxHmBYJAy18KsH2H5U0rs2Ybt8z4gl58mhB6PrKY3JC7vUu4hJ8J\n\tHmA5IrRTYZqKrvmTC1XujH/ezL2sfC2OO3i1U28dxUJIb0qthO8lRpuCXvS8BMLRhpK/\n\tTYV9hCvLIeOOaKQuwBXrVk//JYrUs/rb/wLDWxkRKkLP9XyMiS0J+vjzEgs94WVUANHj\n\tI8+YIcGfpBFD5IFQ7hzs9IQNDTALhu9q+WQYkepVWz2AFTU9S84O7H8pKof7OlpmeU5O\n\tevCw==", "X-Gm-Message-State": "AKaTC02A3ML02fZYPiK4L5DrQ272+p5I8QPmqgVcDhQAiuqVMVwUZggSU0Gj/yPXU9dWXdfP", "X-Received": "by 10.28.199.71 with SMTP id x68mr2923872wmf.34.1480003441834;\n\tThu, 24 Nov 2016 08:04:01 -0800 (PST)", "From": "Nelio Laranjeiro <nelio.laranjeiro@6wind.com>", "To": "dev@dpdk.org", "Cc": "Thomas Monjalon <thomas.monjalon@6wind.com>,\n\tAdrien Mazarguil <adrien.mazarguil@6wind.com>", "Date": "Thu, 24 Nov 2016 17:03:31 +0100", "Message-Id": "<d4553cbb56244ca8b2251bf869515e2078e0f08d.1479995764.git.nelio.laranjeiro@6wind.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": [ "<cover.1479995764.git.nelio.laranjeiro@6wind.com>", "<cover.1479995764.git.nelio.laranjeiro@6wind.com>" ], "References": [ "<cover.1479995764.git.nelio.laranjeiro@6wind.com>", "<cover.1479995764.git.nelio.laranjeiro@6wind.com>" ], "Subject": "[dpdk-dev] [PATCH 2/7] net/mlx5: use work queue buffer as a raw\n\tbuffer", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Define a single work queue element type that encompasses them all. It\nincludes control, Ethernet segment and raw data all grouped in a single\nplace.\n\nSigned-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>\nAcked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>\n---\n drivers/net/mlx5/mlx5_prm.h | 13 ++++--\n drivers/net/mlx5/mlx5_rxtx.c | 103 ++++++++++++++++++++++---------------------\n drivers/net/mlx5/mlx5_rxtx.h | 2 +-\n drivers/net/mlx5/mlx5_txq.c | 8 ++--\n 4 files changed, 68 insertions(+), 58 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex 7f31a2f..3dd4cbe 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -114,12 +114,19 @@ struct mlx5_wqe_eth_seg_small {\n \tuint32_t rsvd2;\n \tuint16_t inline_hdr_sz;\n \tuint8_t inline_hdr[2];\n-};\n+} __rte_aligned(MLX5_WQE_DWORD_SIZE);\n \n struct mlx5_wqe_inl_small {\n \tuint32_t byte_cnt;\n \tuint8_t raw;\n-};\n+} __rte_aligned(MLX5_WQE_DWORD_SIZE);\n+\n+struct mlx5_wqe_ctrl {\n+\tuint32_t ctrl0;\n+\tuint32_t ctrl1;\n+\tuint32_t ctrl2;\n+\tuint32_t ctrl3;\n+} __rte_aligned(MLX5_WQE_DWORD_SIZE);\n \n /* Small common part of the WQE. */\n struct mlx5_wqe {\n@@ -131,7 +138,7 @@ struct mlx5_wqe {\n struct mlx5_wqe64 {\n \tstruct mlx5_wqe hdr;\n \tuint8_t raw[32];\n-} __rte_aligned(64);\n+} __rte_aligned(MLX5_WQE_SIZE);\n \n /* MPW session status. */\n enum mlx5_mpw_state {\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 5dacd93..ada8e74 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -154,6 +154,24 @@ check_cqe(volatile struct mlx5_cqe *cqe,\n \treturn 0;\n }\n \n+/**\n+ * Return the address of the WQE.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ * @param wqe_ci\n+ * WQE consumer index.\n+ *\n+ * @return\n+ * WQE address.\n+ */\n+static inline uintptr_t *\n+tx_mlx5_wqe(struct txq *txq, uint16_t ci)\n+{\n+\tci &= ((1 << txq->wqe_n) - 1);\n+\treturn (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);\n+}\n+\n static inline void\n txq_complete(struct txq *txq) __attribute__((always_inline));\n \n@@ -175,7 +193,7 @@ txq_complete(struct txq *txq)\n \tuint16_t elts_tail;\n \tuint16_t cq_ci = txq->cq_ci;\n \tvolatile struct mlx5_cqe *cqe = NULL;\n-\tvolatile struct mlx5_wqe *wqe;\n+\tvolatile struct mlx5_wqe_ctrl *ctrl;\n \n \tdo {\n \t\tvolatile struct mlx5_cqe *tmp;\n@@ -201,9 +219,9 @@ txq_complete(struct txq *txq)\n \t} while (1);\n \tif (unlikely(cqe == NULL))\n \t\treturn;\n-\twqe = &(*txq->wqes)[ntohs(cqe->wqe_counter) &\n-\t\t\t ((1 << txq->wqe_n) - 1)].hdr;\n-\telts_tail = wqe->ctrl[3];\n+\tctrl = (volatile struct mlx5_wqe_ctrl *)\n+\t\ttx_mlx5_wqe(txq, ntohs(cqe->wqe_counter));\n+\telts_tail = ctrl->ctrl3;\n \tassert(elts_tail < (1 << txq->wqe_n));\n \t/* Free buffers. */\n \twhile (elts_free != elts_tail) {\n@@ -331,23 +349,6 @@ tx_prefetch_cqe(struct txq *txq, uint16_t ci)\n }\n \n /**\n- * Prefetch a WQE.\n- *\n- * @param txq\n- * Pointer to TX queue structure.\n- * @param wqe_ci\n- * WQE consumer index.\n- */\n-static inline void\n-tx_prefetch_wqe(struct txq *txq, uint16_t ci)\n-{\n-\tvolatile struct mlx5_wqe64 *wqe;\n-\n-\twqe = &(*txq->wqes)[ci & ((1 << txq->wqe_n) - 1)];\n-\trte_prefetch0(wqe);\n-}\n-\n-/**\n * DPDK callback for TX.\n *\n * @param dpdk_txq\n@@ -411,9 +412,9 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t--segs_n;\n \t\tif (!segs_n)\n \t\t\t--pkts_n;\n-\t\twqe = &(*txq->wqes)[txq->wqe_ci &\n-\t\t\t\t ((1 << txq->wqe_n) - 1)].hdr;\n-\t\ttx_prefetch_wqe(txq, txq->wqe_ci + 1);\n+\t\twqe = (volatile struct mlx5_wqe *)\n+\t\t\ttx_mlx5_wqe(txq, txq->wqe_ci);\n+\t\trte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));\n \t\tif (pkts_n > 1)\n \t\t\trte_prefetch0(*pkts);\n \t\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n@@ -464,8 +465,9 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t}\n \t\t/* Inline if enough room. */\n \t\tif (txq->max_inline != 0) {\n-\t\t\tuintptr_t end =\n-\t\t\t\t(uintptr_t)&(*txq->wqes)[1 << txq->wqe_n];\n+\t\t\tuintptr_t end = (uintptr_t)\n+\t\t\t\t(((uintptr_t)txq->wqes) +\n+\t\t\t\t (1 << txq->wqe_n) * MLX5_WQE_SIZE);\n \t\t\tuint16_t max_inline =\n \t\t\t\ttxq->max_inline * RTE_CACHE_LINE_SIZE;\n \t\t\tuint16_t room;\n@@ -496,12 +498,13 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\t */\n \t\t\tds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);\n \t\t\tif (length > 0) {\n-\t\t\t\tdseg = (struct mlx5_wqe_data_seg *)\n+\t\t\t\tdseg = (volatile struct mlx5_wqe_data_seg *)\n \t\t\t\t\t((uintptr_t)wqe +\n \t\t\t\t\t (ds * MLX5_WQE_DWORD_SIZE));\n \t\t\t\tif ((uintptr_t)dseg >= end)\n-\t\t\t\t\tdseg = (struct mlx5_wqe_data_seg *)\n-\t\t\t\t\t\t((uintptr_t)&(*txq->wqes)[0]);\n+\t\t\t\t\tdseg = (volatile struct\n+\t\t\t\t\t\tmlx5_wqe_data_seg *)\n+\t\t\t\t\t txq->wqes;\n \t\t\t\tgoto use_dseg;\n \t\t\t} else if (!segs_n) {\n \t\t\t\tgoto next_pkt;\n@@ -514,12 +517,12 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\t * Ethernet Header as been stored.\n \t\t\t */\n \t\t\twqe->eseg.inline_hdr_sz = htons(MLX5_WQE_DWORD_SIZE);\n-\t\t\tdseg = (struct mlx5_wqe_data_seg *)\n+\t\t\tdseg = (volatile struct mlx5_wqe_data_seg *)\n \t\t\t\t((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));\n \t\t\tds = 3;\n use_dseg:\n \t\t\t/* Add the remaining packet as a simple ds. */\n-\t\t\t*dseg = (struct mlx5_wqe_data_seg) {\n+\t\t\t*dseg = (volatile struct mlx5_wqe_data_seg) {\n \t\t\t\t.addr = htonll(addr),\n \t\t\t\t.byte_count = htonl(length),\n \t\t\t\t.lkey = txq_mp2mr(txq, txq_mb2mp(buf)),\n@@ -542,9 +545,9 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\tunsigned int n = (txq->wqe_ci + ((ds + 3) / 4)) &\n \t\t\t\t((1 << txq->wqe_n) - 1);\n \n-\t\t\tdseg = (struct mlx5_wqe_data_seg *)\n-\t\t\t\t((uintptr_t)&(*txq->wqes)[n]);\n-\t\t\ttx_prefetch_wqe(txq, n + 1);\n+\t\t\tdseg = (volatile struct mlx5_wqe_data_seg *)\n+\t\t\t tx_mlx5_wqe(txq, n);\n+\t\t\trte_prefetch0(tx_mlx5_wqe(txq, n + 1));\n \t\t} else {\n \t\t\t++dseg;\n \t\t}\n@@ -556,7 +559,7 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\ttotal_length += length;\n #endif\n \t\t/* Store segment information. */\n-\t\t*dseg = (struct mlx5_wqe_data_seg) {\n+\t\t*dseg = (volatile struct mlx5_wqe_data_seg) {\n \t\t\t.addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t)),\n \t\t\t.byte_count = htonl(length),\n \t\t\t.lkey = txq_mp2mr(txq, txq_mb2mp(buf)),\n@@ -629,13 +632,13 @@ mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)\n \tuint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);\n \tvolatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =\n \t\t(volatile struct mlx5_wqe_data_seg (*)[])\n-\t\t(uintptr_t)&(*txq->wqes)[(idx + 1) & ((1 << txq->wqe_n) - 1)];\n+\t\ttx_mlx5_wqe(txq, idx + 1);\n \n \tmpw->state = MLX5_MPW_STATE_OPENED;\n \tmpw->pkts_n = 0;\n \tmpw->len = length;\n \tmpw->total_len = 0;\n-\tmpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;\n+\tmpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);\n \tmpw->wqe->eseg.mss = htons(length);\n \tmpw->wqe->eseg.inline_hdr_sz = 0;\n \tmpw->wqe->eseg.rsvd0 = 0;\n@@ -677,8 +680,8 @@ mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)\n \t\t++txq->wqe_ci;\n \telse\n \t\ttxq->wqe_ci += 2;\n-\ttx_prefetch_wqe(txq, txq->wqe_ci);\n-\ttx_prefetch_wqe(txq, txq->wqe_ci + 1);\n+\trte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));\n+\trte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));\n }\n \n /**\n@@ -712,8 +715,8 @@ mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\treturn 0;\n \t/* Prefetch first packet cacheline. */\n \ttx_prefetch_cqe(txq, txq->cq_ci);\n-\ttx_prefetch_wqe(txq, txq->wqe_ci);\n-\ttx_prefetch_wqe(txq, txq->wqe_ci + 1);\n+\trte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));\n+\trte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));\n \t/* Start processing. */\n \ttxq_complete(txq);\n \tmax = (elts_n - (elts_head - txq->elts_tail));\n@@ -841,7 +844,7 @@ mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)\n \tmpw->pkts_n = 0;\n \tmpw->len = length;\n \tmpw->total_len = 0;\n-\tmpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;\n+\tmpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);\n \tmpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |\n \t\t\t\t (txq->wqe_ci << 8) |\n \t\t\t\t MLX5_OPCODE_TSO);\n@@ -917,8 +920,8 @@ mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,\n \t\treturn 0;\n \t/* Prefetch first packet cacheline. */\n \ttx_prefetch_cqe(txq, txq->cq_ci);\n-\ttx_prefetch_wqe(txq, txq->wqe_ci);\n-\ttx_prefetch_wqe(txq, txq->wqe_ci + 1);\n+\trte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));\n+\trte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));\n \t/* Start processing. */\n \ttxq_complete(txq);\n \tmax = (elts_n - (elts_head - txq->elts_tail));\n@@ -1019,14 +1022,15 @@ mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,\n \t\t\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n \t\t\t(*txq->elts)[elts_head] = buf;\n \t\t\t/* Maximum number of bytes before wrapping. */\n-\t\t\tmax = ((uintptr_t)&(*txq->wqes)[1 << txq->wqe_n] -\n+\t\t\tmax = ((((uintptr_t)(txq->wqes)) +\n+\t\t\t\t(1 << txq->wqe_n) *\n+\t\t\t\tMLX5_WQE_SIZE) -\n \t\t\t (uintptr_t)mpw.data.raw);\n \t\t\tif (length > max) {\n \t\t\t\trte_memcpy((void *)(uintptr_t)mpw.data.raw,\n \t\t\t\t\t (void *)addr,\n \t\t\t\t\t max);\n-\t\t\t\tmpw.data.raw =\n-\t\t\t\t\t(volatile void *)&(*txq->wqes)[0];\n+\t\t\t\tmpw.data.raw = (volatile void *)txq->wqes;\n \t\t\t\trte_memcpy((void *)(uintptr_t)mpw.data.raw,\n \t\t\t\t\t (void *)(addr + max),\n \t\t\t\t\t length - max);\n@@ -1038,9 +1042,8 @@ mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,\n \t\t\t\tmpw.data.raw += length;\n \t\t\t}\n \t\t\tif ((uintptr_t)mpw.data.raw ==\n-\t\t\t (uintptr_t)&(*txq->wqes)[1 << txq->wqe_n])\n-\t\t\t\tmpw.data.raw =\n-\t\t\t\t\t(volatile void *)&(*txq->wqes)[0];\n+\t\t\t (uintptr_t)tx_mlx5_wqe(txq, 1 << txq->wqe_n))\n+\t\t\t\tmpw.data.raw = (volatile void *)txq->wqes;\n \t\t\t++mpw.pkts_n;\n \t\t\t++j;\n \t\t\tif (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 8f2cddb..b9b90a7 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -259,7 +259,7 @@ struct txq {\n \tuint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */\n \tuint32_t qp_num_8s; /* QP number shifted by 8. */\n \tvolatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */\n-\tvolatile struct mlx5_wqe64 (*wqes)[]; /* Work queue. */\n+\tvolatile void *wqes; /* Work queue (use volatile to write into). */\n \tvolatile uint32_t *qp_db; /* Work queue doorbell. */\n \tvolatile uint32_t *cq_db; /* Completion queue doorbell. */\n \tvolatile void *bf_reg; /* Blueflame register. */\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 053665d..f4c6682 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -82,7 +82,9 @@ txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n)\n \tfor (i = 0; (i != elts_n); ++i)\n \t\t(*txq_ctrl->txq.elts)[i] = NULL;\n \tfor (i = 0; (i != (1u << txq_ctrl->txq.wqe_n)); ++i) {\n-\t\tvolatile struct mlx5_wqe64 *wqe = &(*txq_ctrl->txq.wqes)[i];\n+\t\tvolatile struct mlx5_wqe64 *wqe =\n+\t\t\t(volatile struct mlx5_wqe64 *)\n+\t\t\ttxq_ctrl->txq.wqes + i;\n \n \t\tmemset((void *)(uintptr_t)wqe, 0x0, sizeof(*wqe));\n \t}\n@@ -214,9 +216,7 @@ txq_setup(struct txq_ctrl *tmpl, struct txq_ctrl *txq_ctrl)\n \t}\n \ttmpl->txq.cqe_n = log2above(ibcq->cqe);\n \ttmpl->txq.qp_num_8s = qp->ctrl_seg.qp_num << 8;\n-\ttmpl->txq.wqes =\n-\t\t(volatile struct mlx5_wqe64 (*)[])\n-\t\t(uintptr_t)qp->gen_data.sqstart;\n+\ttmpl->txq.wqes = qp->gen_data.sqstart;\n \ttmpl->txq.wqe_n = log2above(qp->sq.wqe_cnt);\n \ttmpl->txq.qp_db = &qp->gen_data.db[MLX5_SND_DBR];\n \ttmpl->txq.bf_reg = qp->gen_data.bf->reg;\n", "prefixes": [ "dpdk-dev", "2/7" ] }