Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 17219,
    "url": "https://patches.dpdk.org/api/patches/17219/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1479921780-9813-12-git-send-email-wenzhuo.lu@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1479921780-9813-12-git-send-email-wenzhuo.lu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1479921780-9813-12-git-send-email-wenzhuo.lu@intel.com",
    "date": "2016-11-23T17:22:55",
    "name": "[dpdk-dev,11/16] e1000/base: enable new i219 devices",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "f5e35e2e0e646af66c74b66d77d564b8cb6059a8",
    "submitter": {
        "id": 258,
        "url": "https://patches.dpdk.org/api/people/258/?format=api",
        "name": "Wenzhuo Lu",
        "email": "wenzhuo.lu@intel.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1479921780-9813-12-git-send-email-wenzhuo.lu@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/17219/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/17219/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id DBD6D5936;\n\tThu, 24 Nov 2016 02:33:23 +0100 (CET)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby dpdk.org (Postfix) with ESMTP id 91C6829D6\n\tfor <dev@dpdk.org>; Thu, 24 Nov 2016 02:32:16 +0100 (CET)",
            "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby orsmga105.jf.intel.com with ESMTP; 23 Nov 2016 17:32:16 -0800",
            "from dpdk26.sh.intel.com ([10.239.128.228])\n\tby fmsmga006.fm.intel.com with ESMTP; 23 Nov 2016 17:32:15 -0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.31,689,1473145200\"; d=\"scan'208\";a=\"35041927\"",
        "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "Date": "Wed, 23 Nov 2016 12:22:55 -0500",
        "Message-Id": "<1479921780-9813-12-git-send-email-wenzhuo.lu@intel.com>",
        "X-Mailer": "git-send-email 1.9.3",
        "In-Reply-To": "<1479921780-9813-1-git-send-email-wenzhuo.lu@intel.com>",
        "References": "<1479921780-9813-1-git-send-email-wenzhuo.lu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 11/16] e1000/base: enable new i219 devices",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Enable the support of new i219 devices.\nAlso define some registers for future usage.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/e1000/base/e1000_api.c     |  12 +\n drivers/net/e1000/base/e1000_defines.h |   7 +\n drivers/net/e1000/base/e1000_hw.h      |  15 +-\n drivers/net/e1000/base/e1000_ich8lan.c | 790 ++++++++++++++++++++++++++++++---\n drivers/net/e1000/base/e1000_ich8lan.h |  12 +\n drivers/net/e1000/base/e1000_regs.h    |   7 +\n 6 files changed, 792 insertions(+), 51 deletions(-)",
    "diff": "diff --git a/drivers/net/e1000/base/e1000_api.c b/drivers/net/e1000/base/e1000_api.c\nindex bbfcae8..2abe8db 100644\n--- a/drivers/net/e1000/base/e1000_api.c\n+++ b/drivers/net/e1000/base/e1000_api.c\n@@ -298,6 +298,17 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)\n \tcase E1000_DEV_ID_PCH_I218_V3:\n \t\tmac->type = e1000_pch_lpt;\n \t\tbreak;\n+\tcase E1000_DEV_ID_PCH_SPT_I219_LM:\n+\tcase E1000_DEV_ID_PCH_SPT_I219_V:\n+\tcase E1000_DEV_ID_PCH_SPT_I219_LM2:\n+\tcase E1000_DEV_ID_PCH_SPT_I219_V2:\n+\tcase E1000_DEV_ID_PCH_LBG_I219_LM3:\n+\tcase E1000_DEV_ID_PCH_SPT_I219_LM4:\n+\tcase E1000_DEV_ID_PCH_SPT_I219_V4:\n+\tcase E1000_DEV_ID_PCH_SPT_I219_LM5:\n+\tcase E1000_DEV_ID_PCH_SPT_I219_V5:\n+\t\tmac->type = e1000_pch_spt;\n+\t\tbreak;\n \tcase E1000_DEV_ID_82575EB_COPPER:\n \tcase E1000_DEV_ID_82575EB_FIBER_SERDES:\n \tcase E1000_DEV_ID_82575GB_QUAD_COPPER:\n@@ -448,6 +459,7 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)\n \tcase e1000_pchlan:\n \tcase e1000_pch2lan:\n \tcase e1000_pch_lpt:\n+\tcase e1000_pch_spt:\n \t\te1000_init_function_pointers_ich8lan(hw);\n \t\tbreak;\n \tcase e1000_82575:\ndiff --git a/drivers/net/e1000/base/e1000_defines.h b/drivers/net/e1000/base/e1000_defines.h\nindex 7d70ba6..dbc2bbb 100644\n--- a/drivers/net/e1000/base/e1000_defines.h\n+++ b/drivers/net/e1000/base/e1000_defines.h\n@@ -198,6 +198,7 @@ POSSIBILITY OF SUCH DAMAGE.\n #define E1000_RCTL_DTYP_PS\t0x00000400 /* Packet Split descriptor */\n #define E1000_RCTL_RDMTS_HALF\t0x00000000 /* Rx desc min thresh size */\n #define E1000_RCTL_RDMTS_HEX\t0x00010000\n+#define E1000_RCTL_RDMTS1_HEX\tE1000_RCTL_RDMTS_HEX\n #define E1000_RCTL_MO_SHIFT\t12 /* multicast offset shift */\n #define E1000_RCTL_MO_3\t\t0x00003000 /* multicast offset 15:4 */\n #define E1000_RCTL_BAM\t\t0x00008000 /* broadcast enable */\n@@ -753,6 +754,12 @@ POSSIBILITY OF SUCH DAMAGE.\n #define E1000_TSYNCTXCTL_VALID\t\t0x00000001 /* Tx timestamp valid */\n #define E1000_TSYNCTXCTL_ENABLED\t0x00000010 /* enable Tx timestamping */\n \n+/* HH Time Sync */\n+#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK\t0x0000F000 /* max delay */\n+#define E1000_TSYNCTXCTL_SYNC_COMP_ERR\t\t0x20000000 /* sync err */\n+#define E1000_TSYNCTXCTL_SYNC_COMP\t\t0x40000000 /* sync complete */\n+#define E1000_TSYNCTXCTL_START_SYNC\t\t0x80000000 /* initiate sync */\n+\n #define E1000_TSYNCRXCTL_VALID\t\t0x00000001 /* Rx timestamp valid */\n #define E1000_TSYNCRXCTL_TYPE_MASK\t0x0000000E /* Rx type mask */\n #define E1000_TSYNCRXCTL_TYPE_L2_V2\t0x00\ndiff --git a/drivers/net/e1000/base/e1000_hw.h b/drivers/net/e1000/base/e1000_hw.h\nindex e4e4f76..14e2e87 100644\n--- a/drivers/net/e1000/base/e1000_hw.h\n+++ b/drivers/net/e1000/base/e1000_hw.h\n@@ -136,6 +136,15 @@ struct e1000_hw;\n #define E1000_DEV_ID_PCH_I218_V2\t\t0x15A1\n #define E1000_DEV_ID_PCH_I218_LM3\t\t0x15A2 /* Wildcat Point PCH */\n #define E1000_DEV_ID_PCH_I218_V3\t\t0x15A3 /* Wildcat Point PCH */\n+#define E1000_DEV_ID_PCH_SPT_I219_LM\t\t0x156F /* Sunrise Point PCH */\n+#define E1000_DEV_ID_PCH_SPT_I219_V\t\t0x1570 /* Sunrise Point PCH */\n+#define E1000_DEV_ID_PCH_SPT_I219_LM2\t\t0x15B7 /* Sunrise Point-H PCH */\n+#define E1000_DEV_ID_PCH_SPT_I219_V2\t\t0x15B8 /* Sunrise Point-H PCH */\n+#define E1000_DEV_ID_PCH_LBG_I219_LM3\t\t0x15B9 /* LEWISBURG PCH */\n+#define E1000_DEV_ID_PCH_SPT_I219_LM4\t\t0x15D7\n+#define E1000_DEV_ID_PCH_SPT_I219_V4\t\t0x15D8\n+#define E1000_DEV_ID_PCH_SPT_I219_LM5\t\t0x15E3\n+#define E1000_DEV_ID_PCH_SPT_I219_V5\t\t0x15D6\n #define E1000_DEV_ID_82576\t\t\t0x10C9\n #define E1000_DEV_ID_82576_FIBER\t\t0x10E6\n #define E1000_DEV_ID_82576_SERDES\t\t0x10E7\n@@ -221,6 +230,7 @@ enum e1000_mac_type {\n \te1000_pchlan,\n \te1000_pch2lan,\n \te1000_pch_lpt,\n+\te1000_pch_spt,\n \te1000_82575,\n \te1000_82576,\n \te1000_82580,\n@@ -954,7 +964,10 @@ struct e1000_dev_spec_ich8lan {\n \tu16 eee_lp_ability;\n #ifdef ULP_SUPPORT\n \tenum e1000_ulp_state ulp_state;\n-#endif /* NAHUM6LP_HW && ULP_SUPPORT */\n+\tbool ulp_capability_disabled;\n+\tbool during_suspend_flow;\n+\tbool during_dpg_exit;\n+#endif /* ULP_SUPPORT */\n \tu16 lat_enc;\n \tu16 max_ltr_enc;\n \tbool smbus_disable;\ndiff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c\nindex 0837a40..7ab0f7c 100644\n--- a/drivers/net/e1000/base/e1000_ich8lan.c\n+++ b/drivers/net/e1000/base/e1000_ich8lan.c\n@@ -94,10 +94,13 @@ STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,\n \t\t\t\t\t    bool active);\n STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,\n \t\t\t\t   u16 words, u16 *data);\n+STATIC s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,\n+\t\t\t       u16 *data);\n STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,\n \t\t\t\t    u16 words, u16 *data);\n STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);\n STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);\n+STATIC s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);\n STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,\n \t\t\t\t\t    u16 *data);\n STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);\n@@ -125,6 +128,14 @@ STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,\n \t\t\t\t\t  u32 offset, u8 *data);\n STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n \t\t\t\t\t  u8 size, u16 *data);\n+STATIC s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,\n+\t\t\t\t\t    u32 *data);\n+STATIC s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,\n+\t\t\t\t\t   u32 offset, u32 *data);\n+STATIC s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,\n+\t\t\t\t\t     u32 offset, u32 data);\n+STATIC s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,\n+\t\t\t\t\t\t  u32 offset, u32 dword);\n STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,\n \t\t\t\t\t  u32 offset, u16 *data);\n STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,\n@@ -233,7 +244,7 @@ STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)\n \tif (ret_val)\n \t\treturn false;\n out:\n-\tif (hw->mac.type == e1000_pch_lpt) {\n+\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\t/* Only unforce SMBus if ME is not active */\n \t\tif (!(E1000_READ_REG(hw, E1000_FWSM) &\n \t\t    E1000_ICH_FWSM_FW_VALID)) {\n@@ -334,6 +345,7 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)\n \t */\n \tswitch (hw->mac.type) {\n \tcase e1000_pch_lpt:\n+\tcase e1000_pch_spt:\n \t\tif (e1000_phy_is_accessible_pchlan(hw))\n \t\t\tbreak;\n \n@@ -481,6 +493,7 @@ STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)\n \t\t\t/* fall-through */\n \t\tcase e1000_pch2lan:\n \t\tcase e1000_pch_lpt:\n+\t\tcase e1000_pch_spt:\n \t\t\t/* In case the PHY needs to be in mdio slow mode,\n \t\t\t * set slow mode and try to get the PHY id again.\n \t\t\t */\n@@ -623,36 +636,57 @@ STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)\n \tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n \tu32 gfpreg, sector_base_addr, sector_end_addr;\n \tu16 i;\n+\tu32 nvm_size;\n \n \tDEBUGFUNC(\"e1000_init_nvm_params_ich8lan\");\n \n-\t/* Can't read flash registers if the register set isn't mapped. */\n \tnvm->type = e1000_nvm_flash_sw;\n-\tif (!hw->flash_address) {\n-\t\tDEBUGOUT(\"ERROR: Flash registers not mapped\\n\");\n-\t\treturn -E1000_ERR_CONFIG;\n-\t}\n \n-\tgfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);\n+\tif (hw->mac.type >= e1000_pch_spt) {\n+\t\t/* in SPT, gfpreg doesn't exist. NVM size is taken from the\n+\t\t * STRAP register. This is because in SPT the GbE Flash region\n+\t\t * is no longer accessed through the flash registers. Instead,\n+\t\t * the mechanism has changed, and the Flash region access\n+\t\t * registers are now implemented in GbE memory space.\n+\t\t */\n+\t\tnvm->flash_base_addr = 0;\n+\t\tnvm_size =\n+\t\t    (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)\n+\t\t    * NVM_SIZE_MULTIPLIER;\n+\t\tnvm->flash_bank_size = nvm_size / 2;\n+\t\t/* Adjust to word count */\n+\t\tnvm->flash_bank_size /= sizeof(u16);\n+\t\t/* Set the base address for flash register access */\n+\t\thw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;\n+\t} else {\n+\t\t/* Can't read flash registers if register set isn't mapped. */\n+\t\tif (!hw->flash_address) {\n+\t\t\tDEBUGOUT(\"ERROR: Flash registers not mapped\\n\");\n+\t\t\treturn -E1000_ERR_CONFIG;\n+\t\t}\n \n-\t/* sector_X_addr is a \"sector\"-aligned address (4096 bytes)\n-\t * Add 1 to sector_end_addr since this sector is included in\n-\t * the overall size.\n-\t */\n-\tsector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;\n-\tsector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;\n+\t\tgfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);\n+\n+\t\t/* sector_X_addr is a \"sector\"-aligned address (4096 bytes)\n+\t\t * Add 1 to sector_end_addr since this sector is included in\n+\t\t * the overall size.\n+\t\t */\n+\t\tsector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;\n+\t\tsector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;\n \n-\t/* flash_base_addr is byte-aligned */\n-\tnvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;\n+\t\t/* flash_base_addr is byte-aligned */\n+\t\tnvm->flash_base_addr = sector_base_addr\n+\t\t\t\t       << FLASH_SECTOR_ADDR_SHIFT;\n \n-\t/* find total size of the NVM, then cut in half since the total\n-\t * size represents two separate NVM banks.\n-\t */\n-\tnvm->flash_bank_size = ((sector_end_addr - sector_base_addr)\n-\t\t\t\t<< FLASH_SECTOR_ADDR_SHIFT);\n-\tnvm->flash_bank_size /= 2;\n-\t/* Adjust to word count */\n-\tnvm->flash_bank_size /= sizeof(u16);\n+\t\t/* find total size of the NVM, then cut in half since the total\n+\t\t * size represents two separate NVM banks.\n+\t\t */\n+\t\tnvm->flash_bank_size = ((sector_end_addr - sector_base_addr)\n+\t\t\t\t\t<< FLASH_SECTOR_ADDR_SHIFT);\n+\t\tnvm->flash_bank_size /= 2;\n+\t\t/* Adjust to word count */\n+\t\tnvm->flash_bank_size /= sizeof(u16);\n+\t}\n \n \tnvm->word_size = E1000_SHADOW_RAM_WORDS;\n \n@@ -668,8 +702,13 @@ STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)\n \t/* Function Pointers */\n \tnvm->ops.acquire\t= e1000_acquire_nvm_ich8lan;\n \tnvm->ops.release\t= e1000_release_nvm_ich8lan;\n-\tnvm->ops.read\t\t= e1000_read_nvm_ich8lan;\n-\tnvm->ops.update\t\t= e1000_update_nvm_checksum_ich8lan;\n+\tif (hw->mac.type >= e1000_pch_spt) {\n+\t\tnvm->ops.read\t= e1000_read_nvm_spt;\n+\t\tnvm->ops.update\t= e1000_update_nvm_checksum_spt;\n+\t} else {\n+\t\tnvm->ops.read\t= e1000_read_nvm_ich8lan;\n+\t\tnvm->ops.update\t= e1000_update_nvm_checksum_ich8lan;\n+\t}\n \tnvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;\n \tnvm->ops.validate\t= e1000_validate_nvm_checksum_ich8lan;\n \tnvm->ops.write\t\t= e1000_write_nvm_ich8lan;\n@@ -758,6 +797,7 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)\n \t\tmac->ops.rar_set = e1000_rar_set_pch2lan;\n \t\t/* fall-through */\n \tcase e1000_pch_lpt:\n+\tcase e1000_pch_spt:\n #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT\n \t\t/* multicast address update for pch2 */\n \t\tmac->ops.update_mc_addr_list =\n@@ -768,7 +808,13 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)\n #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)\n \t\t/* save PCH revision_id */\n \t\te1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);\n-\t\thw->revision_id = (u8)(pci_cfg &= 0x000F);\n+\t\t/* SPT uses full byte for revision ID,\n+\t\t * as opposed to previous generations\n+\t\t */\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n+\t\t\thw->revision_id = (u8)(pci_cfg &= 0x00FF);\n+\t\telse\n+\t\t\thw->revision_id = (u8)(pci_cfg &= 0x000F);\n #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */\n \t\t/* check management mode */\n \t\tmac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;\n@@ -786,7 +832,7 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)\n \t\tbreak;\n \t}\n \n-\tif (mac->type == e1000_pch_lpt) {\n+\tif (mac->type >= e1000_pch_lpt) {\n \t\tmac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;\n \t\tmac->ops.rar_set = e1000_rar_set_pch_lpt;\n \t\tmac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;\n@@ -1015,8 +1061,9 @@ release:\n \t\t/* clear FEXTNVM6 bit 8 on link down or 10/100 */\n \t\tfextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;\n \n-\t\tif (!link || ((status & E1000_STATUS_SPEED_100) &&\n-\t\t\t      (status & E1000_STATUS_FD)))\n+\t\tif ((hw->phy.revision > 5) || !link ||\n+\t\t    ((status & E1000_STATUS_SPEED_100) &&\n+\t\t     (status & E1000_STATUS_FD)))\n \t\t\tgoto update_fextnvm6;\n \n \t\tret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);\n@@ -1490,8 +1537,7 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t * aggressive resulting in many collisions. To avoid this, increase\n \t * the IPG and reduce Rx latency in the PHY.\n \t */\n-\tif (((hw->mac.type == e1000_pch2lan) ||\n-\t     (hw->mac.type == e1000_pch_lpt)) && link) {\n+\tif ((hw->mac.type >= e1000_pch2lan) && link) {\n \t\tu16 speed, duplex;\n \n \t\te1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);\n@@ -1502,6 +1548,10 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t\t\ttipg_reg |= 0xFF;\n \t\t\t/* Reduce Rx latency in analog PHY */\n \t\t\temi_val = 0;\n+\t\t} else if (hw->mac.type >= e1000_pch_spt &&\n+\t\t\t   duplex == FULL_DUPLEX && speed != SPEED_1000) {\n+\t\t\ttipg_reg |= 0xC;\n+\t\t\temi_val = 1;\n \t\t} else {\n \t\t\t/* Roll back the default values */\n \t\t\ttipg_reg |= 0x08;\n@@ -1539,6 +1589,49 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \n \t\tif (ret_val)\n \t\t\treturn ret_val;\n+\n+\t\tif (hw->mac.type >= e1000_pch_spt) {\n+\t\t\tu16 data;\n+\t\t\tu16 ptr_gap;\n+\n+\t\t\tif (speed == SPEED_1000) {\n+\t\t\t\tret_val = hw->phy.ops.acquire(hw);\n+\t\t\t\tif (ret_val)\n+\t\t\t\t\treturn ret_val;\n+\n+\t\t\t\tret_val = hw->phy.ops.read_reg_locked(hw,\n+\t\t\t\t\t\t\t      PHY_REG(776, 20),\n+\t\t\t\t\t\t\t      &data);\n+\t\t\t\tif (ret_val) {\n+\t\t\t\t\thw->phy.ops.release(hw);\n+\t\t\t\t\treturn ret_val;\n+\t\t\t\t}\n+\n+\t\t\t\tptr_gap = (data & (0x3FF << 2)) >> 2;\n+\t\t\t\tif (ptr_gap < 0x18) {\n+\t\t\t\t\tdata &= ~(0x3FF << 2);\n+\t\t\t\t\tdata |= (0x18 << 2);\n+\t\t\t\t\tret_val =\n+\t\t\t\t\t\thw->phy.ops.write_reg_locked(hw,\n+\t\t\t\t\t\t\tPHY_REG(776, 20), data);\n+\t\t\t\t}\n+\t\t\t\thw->phy.ops.release(hw);\n+\t\t\t\tif (ret_val)\n+\t\t\t\t\treturn ret_val;\n+\t\t\t} else {\n+\t\t\t\tret_val = hw->phy.ops.acquire(hw);\n+\t\t\t\tif (ret_val)\n+\t\t\t\t\treturn ret_val;\n+\n+\t\t\t\tret_val = hw->phy.ops.write_reg_locked(hw,\n+\t\t\t\t\t\t\t     PHY_REG(776, 20),\n+\t\t\t\t\t\t\t     0xC023);\n+\t\t\t\thw->phy.ops.release(hw);\n+\t\t\t\tif (ret_val)\n+\t\t\t\t\treturn ret_val;\n+\n+\t\t\t}\n+\t\t}\n \t}\n \n \t/* I217 Packet Loss issue:\n@@ -1546,7 +1639,7 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \t * on power up.\n \t * Set the Beacon Duration for I217 to 8 usec\n \t */\n-\tif (hw->mac.type == e1000_pch_lpt) {\n+\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\tu32 mac_reg;\n \n \t\tmac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);\n@@ -1568,10 +1661,26 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \thw->dev_spec.ich8lan.eee_lp_ability = 0;\n \n \t/* Configure K0s minimum time */\n-\tif (hw->mac.type == e1000_pch_lpt) {\n+\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\te1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);\n \t}\n \n+\tif (hw->mac.type >= e1000_pch_lpt) {\n+\t\tu32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);\n+\n+\t\tif (hw->mac.type == e1000_pch_spt) {\n+\t\t\t/* FEXTNVM6 K1-off workaround - for SPT only */\n+\t\t\tu32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);\n+\n+\t\t\tif (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)\n+\t\t\t\tfextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;\n+\t\t\telse\n+\t\t\t\tfextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;\n+\t\t}\n+\n+\t\tE1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);\n+\t}\n+\n \tif (!link)\n \t\treturn E1000_SUCCESS; /* No link detected */\n \n@@ -1665,6 +1774,7 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)\n \tcase e1000_pchlan:\n \tcase e1000_pch2lan:\n \tcase e1000_pch_lpt:\n+\tcase e1000_pch_spt:\n \t\thw->phy.ops.init_params = e1000_init_phy_params_pchlan;\n \t\tbreak;\n \tdefault:\n@@ -2130,6 +2240,7 @@ STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)\n \tcase e1000_pchlan:\n \tcase e1000_pch2lan:\n \tcase e1000_pch_lpt:\n+\tcase e1000_pch_spt:\n \t\tsw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;\n \t\tbreak;\n \tdefault:\n@@ -3253,6 +3364,40 @@ STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)\n \tDEBUGFUNC(\"e1000_valid_nvm_bank_detect_ich8lan\");\n \n \tswitch (hw->mac.type) {\n+\tcase e1000_pch_spt:\n+\t\tbank1_offset = nvm->flash_bank_size;\n+\t\tact_offset = E1000_ICH_NVM_SIG_WORD;\n+\n+\t\t/* set bank to 0 in case flash read fails */\n+\t\t*bank = 0;\n+\n+\t\t/* Check bank 0 */\n+\t\tret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,\n+\t\t\t\t\t\t\t &nvm_dword);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\tsig_byte = (u8)((nvm_dword & 0xFF00) >> 8);\n+\t\tif ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==\n+\t\t    E1000_ICH_NVM_SIG_VALUE) {\n+\t\t\t*bank = 0;\n+\t\t\treturn E1000_SUCCESS;\n+\t\t}\n+\n+\t\t/* Check bank 1 */\n+\t\tret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +\n+\t\t\t\t\t\t\t bank1_offset,\n+\t\t\t\t\t\t\t &nvm_dword);\n+\t\tif (ret_val)\n+\t\t\treturn ret_val;\n+\t\tsig_byte = (u8)((nvm_dword & 0xFF00) >> 8);\n+\t\tif ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==\n+\t\t    E1000_ICH_NVM_SIG_VALUE) {\n+\t\t\t*bank = 1;\n+\t\t\treturn E1000_SUCCESS;\n+\t\t}\n+\n+\t\tDEBUGOUT(\"ERROR: No valid NVM bank present\\n\");\n+\t\treturn -E1000_ERR_NVM;\n \tcase e1000_ich8lan:\n \tcase e1000_ich9lan:\n \t\teecd = E1000_READ_REG(hw, E1000_EECD);\n@@ -3300,6 +3445,99 @@ STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)\n }\n \n /**\n+ *  e1000_read_nvm_spt - NVM access for SPT\n+ *  @hw: pointer to the HW structure\n+ *  @offset: The offset (in bytes) of the word(s) to read.\n+ *  @words: Size of data to read in words.\n+ *  @data: pointer to the word(s) to read at offset.\n+ *\n+ *  Reads a word(s) from the NVM\n+ **/\n+STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,\n+\t\t\t      u16 *data)\n+{\n+\tstruct e1000_nvm_info *nvm = &hw->nvm;\n+\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n+\tu32 act_offset;\n+\ts32 ret_val = E1000_SUCCESS;\n+\tu32 bank = 0;\n+\tu32 dword = 0;\n+\tu16 offset_to_read;\n+\tu16 i;\n+\n+\tDEBUGFUNC(\"e1000_read_nvm_spt\");\n+\n+\tif ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||\n+\t    (words == 0)) {\n+\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n+\t\tret_val = -E1000_ERR_NVM;\n+\t\tgoto out;\n+\t}\n+\n+\tnvm->ops.acquire(hw);\n+\n+\tret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);\n+\tif (ret_val != E1000_SUCCESS) {\n+\t\tDEBUGOUT(\"Could not detect valid bank, assuming bank 0\\n\");\n+\t\tbank = 0;\n+\t}\n+\n+\tact_offset = (bank) ? nvm->flash_bank_size : 0;\n+\tact_offset += offset;\n+\n+\tret_val = E1000_SUCCESS;\n+\n+\tfor (i = 0; i < words; i += 2) {\n+\t\tif (words - i == 1) {\n+\t\t\tif (dev_spec->shadow_ram[offset+i].modified) {\n+\t\t\t\tdata[i] = dev_spec->shadow_ram[offset+i].value;\n+\t\t\t} else {\n+\t\t\t\toffset_to_read = act_offset + i -\n+\t\t\t\t\t\t ((act_offset + i) % 2);\n+\t\t\t\tret_val =\n+\t\t\t\t   e1000_read_flash_dword_ich8lan(hw,\n+\t\t\t\t\t\t\t\t offset_to_read,\n+\t\t\t\t\t\t\t\t &dword);\n+\t\t\t\tif (ret_val)\n+\t\t\t\t\tbreak;\n+\t\t\t\tif ((act_offset + i) % 2 == 0)\n+\t\t\t\t\tdata[i] = (u16)(dword & 0xFFFF);\n+\t\t\t\telse\n+\t\t\t\t\tdata[i] = (u16)((dword >> 16) & 0xFFFF);\n+\t\t\t}\n+\t\t} else {\n+\t\t\toffset_to_read = act_offset + i;\n+\t\t\tif (!(dev_spec->shadow_ram[offset+i].modified) ||\n+\t\t\t    !(dev_spec->shadow_ram[offset+i+1].modified)) {\n+\t\t\t\tret_val =\n+\t\t\t\t   e1000_read_flash_dword_ich8lan(hw,\n+\t\t\t\t\t\t\t\t offset_to_read,\n+\t\t\t\t\t\t\t\t &dword);\n+\t\t\t\tif (ret_val)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (dev_spec->shadow_ram[offset+i].modified)\n+\t\t\t\tdata[i] = dev_spec->shadow_ram[offset+i].value;\n+\t\t\telse\n+\t\t\t\tdata[i] = (u16) (dword & 0xFFFF);\n+\t\t\tif (dev_spec->shadow_ram[offset+i].modified)\n+\t\t\t\tdata[i+1] =\n+\t\t\t\t   dev_spec->shadow_ram[offset+i+1].value;\n+\t\t\telse\n+\t\t\t\tdata[i+1] = (u16) (dword >> 16 & 0xFFFF);\n+\t\t}\n+\t}\n+\n+\tnvm->ops.release(hw);\n+\n+out:\n+\tif (ret_val)\n+\t\tDEBUGOUT1(\"NVM read error: %d\\n\", ret_val);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM\n  *  @hw: pointer to the HW structure\n  *  @offset: The offset (in bytes) of the word(s) to read.\n@@ -3386,7 +3624,11 @@ STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)\n \t/* Clear FCERR and DAEL in hw status by writing 1 */\n \thsfsts.hsf_status.flcerr = 1;\n \thsfsts.hsf_status.dael = 1;\n-\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);\n+\tif (hw->mac.type >= e1000_pch_spt)\n+\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,\n+\t\t\t\t      hsfsts.regval & 0xFFFF);\n+\telse\n+\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);\n \n \t/* Either we should have a hardware SPI cycle in progress\n \t * bit to check against, in order to start a new cycle or\n@@ -3402,7 +3644,12 @@ STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)\n \t\t * Begin by setting Flash Cycle Done.\n \t\t */\n \t\thsfsts.hsf_status.flcdone = 1;\n-\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n+\t\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,\n+\t\t\t\t\t      hsfsts.regval & 0xFFFF);\n+\t\telse\n+\t\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,\n+\t\t\t\t\t\thsfsts.regval);\n \t\tret_val = E1000_SUCCESS;\n \t} else {\n \t\ts32 i;\n@@ -3424,8 +3671,12 @@ STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)\n \t\t\t * now set the Flash Cycle Done.\n \t\t\t */\n \t\t\thsfsts.hsf_status.flcdone = 1;\n-\t\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,\n-\t\t\t\t\t\thsfsts.regval);\n+\t\t\tif (hw->mac.type >= e1000_pch_spt)\n+\t\t\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,\n+\t\t\t\t\t\t      hsfsts.regval & 0xFFFF);\n+\t\t\telse\n+\t\t\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,\n+\t\t\t\t\t\t\thsfsts.regval);\n \t\t} else {\n \t\t\tDEBUGOUT(\"Flash controller busy, cannot get access\\n\");\n \t\t}\n@@ -3450,10 +3701,17 @@ STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)\n \tDEBUGFUNC(\"e1000_flash_cycle_ich8lan\");\n \n \t/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */\n-\thsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);\n+\tif (hw->mac.type >= e1000_pch_spt)\n+\t\thsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;\n+\telse\n+\t\thsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);\n \thsflctl.hsf_ctrl.flcgo = 1;\n \n-\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);\n+\tif (hw->mac.type >= e1000_pch_spt)\n+\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,\n+\t\t\t\t      hsflctl.regval << 16);\n+\telse\n+\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);\n \n \t/* wait till FDONE bit is set to 1 */\n \tdo {\n@@ -3470,6 +3728,29 @@ STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)\n }\n \n /**\n+ *  e1000_read_flash_dword_ich8lan - Read dword from flash\n+ *  @hw: pointer to the HW structure\n+ *  @offset: offset to data location\n+ *  @data: pointer to the location for storing the data\n+ *\n+ *  Reads the flash dword at offset into data.  Offset is converted\n+ *  to bytes before read.\n+ **/\n+STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,\n+\t\t\t\t\t  u32 *data)\n+{\n+\tDEBUGFUNC(\"e1000_read_flash_dword_ich8lan\");\n+\n+\tif (!data)\n+\t\treturn -E1000_ERR_NVM;\n+\n+\t/* Must convert word offset into bytes. */\n+\toffset <<= 1;\n+\n+\treturn e1000_read_flash_data32_ich8lan(hw, offset, data);\n+}\n+\n+/**\n  *  e1000_read_flash_word_ich8lan - Read word from flash\n  *  @hw: pointer to the HW structure\n  *  @offset: offset to data location\n@@ -3506,7 +3787,13 @@ STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,\n \ts32 ret_val;\n \tu16 word = 0;\n \n-\tret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);\n+\t/* In SPT, only 32 bits access is supported,\n+\t * so this function should not be called.\n+\t */\n+\tif (hw->mac.type >= e1000_pch_spt)\n+\t\treturn -E1000_ERR_NVM;\n+\telse\n+\t\tret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);\n \n \tif (ret_val)\n \t\treturn ret_val;\n@@ -3592,6 +3879,83 @@ STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n \treturn ret_val;\n }\n \n+/**\n+ *  e1000_read_flash_data32_ich8lan - Read dword from NVM\n+ *  @hw: pointer to the HW structure\n+ *  @offset: The offset (in bytes) of the dword to read.\n+ *  @data: Pointer to the dword to store the value read.\n+ *\n+ *  Reads a byte or word from the NVM using the flash access registers.\n+ **/\n+STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,\n+\t\t\t\t\t   u32 *data)\n+{\n+\tunion ich8_hws_flash_status hsfsts;\n+\tunion ich8_hws_flash_ctrl hsflctl;\n+\tu32 flash_linear_addr;\n+\ts32 ret_val = -E1000_ERR_NVM;\n+\tu8 count = 0;\n+\n+\tDEBUGFUNC(\"e1000_read_flash_data_ich8lan\");\n+\n+\t\tif (offset > ICH_FLASH_LINEAR_ADDR_MASK ||\n+\t\t    hw->mac.type < e1000_pch_spt)\n+\t\t\treturn -E1000_ERR_NVM;\n+\tflash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +\n+\t\t\t     hw->nvm.flash_base_addr);\n+\n+\tdo {\n+\t\tusec_delay(1);\n+\t\t/* Steps */\n+\t\tret_val = e1000_flash_cycle_init_ich8lan(hw);\n+\t\tif (ret_val != E1000_SUCCESS)\n+\t\t\tbreak;\n+\t\t/* In SPT, This register is in Lan memory space, not flash.\n+\t\t * Therefore, only 32 bit access is supported\n+\t\t */\n+\t\thsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;\n+\n+\t\t/* 0b/1b corresponds to 1 or 2 byte size, respectively. */\n+\t\thsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;\n+\t\thsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;\n+\t\t/* In SPT, This register is in Lan memory space, not flash.\n+\t\t * Therefore, only 32 bit access is supported\n+\t\t */\n+\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,\n+\t\t\t\t      (u32)hsflctl.regval << 16);\n+\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);\n+\n+\t\tret_val = e1000_flash_cycle_ich8lan(hw,\n+\t\t\t\t\t\tICH_FLASH_READ_COMMAND_TIMEOUT);\n+\n+\t\t/* Check if FCERR is set to 1, if set to 1, clear it\n+\t\t * and try the whole sequence a few more times, else\n+\t\t * read in (shift in) the Flash Data0, the order is\n+\t\t * least significant byte first msb to lsb\n+\t\t */\n+\t\tif (ret_val == E1000_SUCCESS) {\n+\t\t\t*data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);\n+\t\t\tbreak;\n+\t\t} else {\n+\t\t\t/* If we've gotten here, then things are probably\n+\t\t\t * completely hosed, but if the error condition is\n+\t\t\t * detected, it won't hurt to give it another try...\n+\t\t\t * ICH_FLASH_CYCLE_REPEAT_COUNT times.\n+\t\t\t */\n+\t\t\thsfsts.regval = E1000_READ_FLASH_REG16(hw,\n+\t\t\t\t\t\t\t      ICH_FLASH_HSFSTS);\n+\t\t\tif (hsfsts.hsf_status.flcerr) {\n+\t\t\t\t/* Repeat for some time before giving up. */\n+\t\t\t\tcontinue;\n+\t\t\t} else if (!hsfsts.hsf_status.flcdone) {\n+\t\t\t\tDEBUGOUT(\"Timeout error - flash cycle did not complete.\\n\");\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);\n+\n+\treturn ret_val;\n+}\n \n /**\n  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM\n@@ -3630,6 +3994,175 @@ STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,\n }\n \n /**\n+ *  e1000_update_nvm_checksum_spt - Update the checksum for NVM\n+ *  @hw: pointer to the HW structure\n+ *\n+ *  The NVM checksum is updated by calling the generic update_nvm_checksum,\n+ *  which writes the checksum to the shadow ram.  The changes in the shadow\n+ *  ram are then committed to the EEPROM by processing each bank at a time\n+ *  checking for the modified bit and writing only the pending changes.\n+ *  After a successful commit, the shadow ram is cleared and is ready for\n+ *  future writes.\n+ **/\n+STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)\n+{\n+\tstruct e1000_nvm_info *nvm = &hw->nvm;\n+\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n+\tu32 i, act_offset, new_bank_offset, old_bank_offset, bank;\n+\ts32 ret_val;\n+\tu32 dword = 0;\n+\n+\tDEBUGFUNC(\"e1000_update_nvm_checksum_spt\");\n+\n+\tret_val = e1000_update_nvm_checksum_generic(hw);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tif (nvm->type != e1000_nvm_flash_sw)\n+\t\tgoto out;\n+\n+\tnvm->ops.acquire(hw);\n+\n+\t/* We're writing to the opposite bank so if we're on bank 1,\n+\t * write to bank 0 etc.  We also need to erase the segment that\n+\t * is going to be written\n+\t */\n+\tret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);\n+\tif (ret_val != E1000_SUCCESS) {\n+\t\tDEBUGOUT(\"Could not detect valid bank, assuming bank 0\\n\");\n+\t\tbank = 0;\n+\t}\n+\n+\tif (bank == 0) {\n+\t\tnew_bank_offset = nvm->flash_bank_size;\n+\t\told_bank_offset = 0;\n+\t\tret_val = e1000_erase_flash_bank_ich8lan(hw, 1);\n+\t\tif (ret_val)\n+\t\t\tgoto release;\n+\t} else {\n+\t\told_bank_offset = nvm->flash_bank_size;\n+\t\tnew_bank_offset = 0;\n+\t\tret_val = e1000_erase_flash_bank_ich8lan(hw, 0);\n+\t\tif (ret_val)\n+\t\t\tgoto release;\n+\t}\n+\tfor (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {\n+\t\t/* Determine whether to write the value stored\n+\t\t * in the other NVM bank or a modified value stored\n+\t\t * in the shadow RAM\n+\t\t */\n+\t\tret_val = e1000_read_flash_dword_ich8lan(hw,\n+\t\t\t\t\t\t\t i + old_bank_offset,\n+\t\t\t\t\t\t\t &dword);\n+\n+\t\tif (dev_spec->shadow_ram[i].modified) {\n+\t\t\tdword &= 0xffff0000;\n+\t\t\tdword |= (dev_spec->shadow_ram[i].value & 0xffff);\n+\t\t}\n+\t\tif (dev_spec->shadow_ram[i + 1].modified) {\n+\t\t\tdword &= 0x0000ffff;\n+\t\t\tdword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)\n+\t\t\t\t  << 16);\n+\t\t}\n+\t\tif (ret_val)\n+\t\t\tbreak;\n+\n+\t\t/* If the word is 0x13, then make sure the signature bits\n+\t\t * (15:14) are 11b until the commit has completed.\n+\t\t * This will allow us to write 10b which indicates the\n+\t\t * signature is valid.  We want to do this after the write\n+\t\t * has completed so that we don't mark the segment valid\n+\t\t * while the write is still in progress\n+\t\t */\n+\t\tif (i == E1000_ICH_NVM_SIG_WORD - 1)\n+\t\t\tdword |= E1000_ICH_NVM_SIG_MASK << 16;\n+\n+\t\t/* Convert offset to bytes. */\n+\t\tact_offset = (i + new_bank_offset) << 1;\n+\n+\t\tusec_delay(100);\n+\n+\t\t/* Write the data to the new bank. Offset in words*/\n+\t\tact_offset = i + new_bank_offset;\n+\t\tret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,\n+\t\t\t\t\t\t\t\tdword);\n+\t\tif (ret_val)\n+\t\t\tbreak;\n+\t }\n+\n+\t/* Don't bother writing the segment valid bits if sector\n+\t * programming failed.\n+\t */\n+\tif (ret_val) {\n+\t\tDEBUGOUT(\"Flash commit failed.\\n\");\n+\t\tgoto release;\n+\t}\n+\n+\t/* Finally validate the new segment by setting bit 15:14\n+\t * to 10b in word 0x13 , this can be done without an\n+\t * erase as well since these bits are 11 to start with\n+\t * and we need to change bit 14 to 0b\n+\t */\n+\tact_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;\n+\n+\t/*offset in words but we read dword*/\n+\t--act_offset;\n+\tret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);\n+\n+\tif (ret_val)\n+\t\tgoto release;\n+\n+\tdword &= 0xBFFFFFFF;\n+\tret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);\n+\n+\tif (ret_val)\n+\t\tgoto release;\n+\n+\t/* And invalidate the previously valid segment by setting\n+\t * its signature word (0x13) high_byte to 0b. This can be\n+\t * done without an erase because flash erase sets all bits\n+\t * to 1's. We can write 1's to 0's without an erase\n+\t */\n+\tact_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;\n+\n+\t/* offset in words but we read dword*/\n+\tact_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;\n+\tret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);\n+\n+\tif (ret_val)\n+\t\tgoto release;\n+\n+\tdword &= 0x00FFFFFF;\n+\tret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);\n+\n+\tif (ret_val)\n+\t\tgoto release;\n+\n+\t/* Great!  Everything worked, we can now clear the cached entries. */\n+\tfor (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {\n+\t\tdev_spec->shadow_ram[i].modified = false;\n+\t\tdev_spec->shadow_ram[i].value = 0xFFFF;\n+\t}\n+\n+release:\n+\tnvm->ops.release(hw);\n+\n+\t/* Reload the EEPROM, or else modifications will not appear\n+\t * until after the next adapter reset.\n+\t */\n+\tif (!ret_val) {\n+\t\tnvm->ops.reload(hw);\n+\t\tmsec_delay(10);\n+\t}\n+\n+out:\n+\tif (ret_val)\n+\t\tDEBUGOUT1(\"NVM update error: %d\\n\", ret_val);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM\n  *  @hw: pointer to the HW structure\n  *\n@@ -3806,6 +4339,7 @@ STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)\n \t */\n \tswitch (hw->mac.type) {\n \tcase e1000_pch_lpt:\n+\tcase e1000_pch_spt:\n \t\tword = NVM_COMPAT;\n \t\tvalid_csum_mask = NVM_COMPAT_VALID_CSUM;\n \t\tbreak;\n@@ -3853,8 +4387,13 @@ STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n \n \tDEBUGFUNC(\"e1000_write_ich8_data\");\n \n-\tif (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)\n-\t\treturn -E1000_ERR_NVM;\n+\tif (hw->mac.type >= e1000_pch_spt) {\n+\t\tif (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)\n+\t\t\treturn -E1000_ERR_NVM;\n+\t} else {\n+\t\tif (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)\n+\t\t\treturn -E1000_ERR_NVM;\n+\t}\n \n \tflash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +\n \t\t\t     hw->nvm.flash_base_addr);\n@@ -3865,12 +4404,29 @@ STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n \t\tret_val = e1000_flash_cycle_init_ich8lan(hw);\n \t\tif (ret_val != E1000_SUCCESS)\n \t\t\tbreak;\n-\t\thsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);\n+\t\t/* In SPT, This register is in Lan memory space, not\n+\t\t * flash.  Therefore, only 32 bit access is supported\n+\t\t */\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n+\t\t\thsflctl.regval =\n+\t\t\t    E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;\n+\t\telse\n+\t\t\thsflctl.regval =\n+\t\t\t    E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);\n \n \t\t/* 0b/1b corresponds to 1 or 2 byte size, respectively. */\n \t\thsflctl.hsf_ctrl.fldbcount = size - 1;\n \t\thsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;\n-\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);\n+\t\t/* In SPT, This register is in Lan memory space,\n+\t\t * not flash.  Therefore, only 32 bit access is\n+\t\t * supported\n+\t\t */\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n+\t\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,\n+\t\t\t\t\t      hsflctl.regval << 16);\n+\t\telse\n+\t\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,\n+\t\t\t\t\t\thsflctl.regval);\n \n \t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);\n \n@@ -3908,6 +4464,94 @@ STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n \treturn ret_val;\n }\n \n+/**\n+*  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM\n+*  @hw: pointer to the HW structure\n+*  @offset: The offset (in bytes) of the dwords to read.\n+*  @data: The 4 bytes to write to the NVM.\n+*\n+*  Writes one/two/four bytes to the NVM using the flash access registers.\n+**/\n+STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,\n+\t\t\t\t\t    u32 data)\n+{\n+\tunion ich8_hws_flash_status hsfsts;\n+\tunion ich8_hws_flash_ctrl hsflctl;\n+\tu32 flash_linear_addr;\n+\ts32 ret_val;\n+\tu8 count = 0;\n+\n+\tDEBUGFUNC(\"e1000_write_flash_data32_ich8lan\");\n+\n+\tif (hw->mac.type >= e1000_pch_spt) {\n+\t\tif (offset > ICH_FLASH_LINEAR_ADDR_MASK)\n+\t\t\treturn -E1000_ERR_NVM;\n+\t}\n+\tflash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +\n+\t\t\t     hw->nvm.flash_base_addr);\n+\tdo {\n+\t\tusec_delay(1);\n+\t\t/* Steps */\n+\t\tret_val = e1000_flash_cycle_init_ich8lan(hw);\n+\t\tif (ret_val != E1000_SUCCESS)\n+\t\t\tbreak;\n+\n+\t\t/* In SPT, This register is in Lan memory space, not\n+\t\t * flash.  Therefore, only 32 bit access is supported\n+\t\t */\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n+\t\t\thsflctl.regval = E1000_READ_FLASH_REG(hw,\n+\t\t\t\t\t\t\t      ICH_FLASH_HSFSTS)\n+\t\t\t\t\t >> 16;\n+\t\telse\n+\t\t\thsflctl.regval = E1000_READ_FLASH_REG16(hw,\n+\t\t\t\t\t\t\t      ICH_FLASH_HSFCTL);\n+\n+\t\thsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;\n+\t\thsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;\n+\n+\t\t/* In SPT, This register is in Lan memory space,\n+\t\t * not flash.  Therefore, only 32 bit access is\n+\t\t * supported\n+\t\t */\n+\t\tif (hw->mac.type >= e1000_pch_spt)\n+\t\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,\n+\t\t\t\t\t      hsflctl.regval << 16);\n+\t\telse\n+\t\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,\n+\t\t\t\t\t\thsflctl.regval);\n+\n+\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);\n+\n+\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);\n+\n+\t\t/* check if FCERR is set to 1 , if set to 1, clear it\n+\t\t * and try the whole sequence a few more times else done\n+\t\t */\n+\t\tret_val = e1000_flash_cycle_ich8lan(hw,\n+\t\t\t\t\t       ICH_FLASH_WRITE_COMMAND_TIMEOUT);\n+\n+\t\tif (ret_val == E1000_SUCCESS)\n+\t\t\tbreak;\n+\n+\t\t/* If we're here, then things are most likely\n+\t\t * completely hosed, but if the error condition\n+\t\t * is detected, it won't hurt to give it another\n+\t\t * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.\n+\t\t */\n+\t\thsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);\n+\n+\t\tif (hsfsts.hsf_status.flcerr)\n+\t\t\t/* Repeat for some time before giving up. */\n+\t\t\tcontinue;\n+\t\tif (!hsfsts.hsf_status.flcdone) {\n+\t\t\tDEBUGOUT(\"Timeout error - flash cycle did not complete.\\n\");\n+\t\t\tbreak;\n+\t\t}\n+\t} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);\n+\n+\treturn ret_val;\n+}\n \n /**\n  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM\n@@ -3927,7 +4571,42 @@ STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,\n \treturn e1000_write_flash_data_ich8lan(hw, offset, 1, word);\n }\n \n+/**\n+*  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM\n+*  @hw: pointer to the HW structure\n+*  @offset: The offset of the word to write.\n+*  @dword: The dword to write to the NVM.\n+*\n+*  Writes a single dword to the NVM using the flash access registers.\n+*  Goes through a retry algorithm before giving up.\n+**/\n+STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,\n+\t\t\t\t\t\t u32 offset, u32 dword)\n+{\n+\ts32 ret_val;\n+\tu16 program_retries;\n+\n+\tDEBUGFUNC(\"e1000_retry_write_flash_dword_ich8lan\");\n+\n+\t/* Must convert word offset into bytes. */\n+\toffset <<= 1;\n \n+\tret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);\n+\n+\tif (!ret_val)\n+\t\treturn ret_val;\n+\tfor (program_retries = 0; program_retries < 100; program_retries++) {\n+\t\tDEBUGOUT2(\"Retrying Byte %8.8X at offset %u\\n\", dword, offset);\n+\t\tusec_delay(100);\n+\t\tret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);\n+\t\tif (ret_val == E1000_SUCCESS)\n+\t\t\tbreak;\n+\t}\n+\tif (program_retries == 100)\n+\t\treturn -E1000_ERR_NVM;\n+\n+\treturn E1000_SUCCESS;\n+}\n \n /**\n  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM\n@@ -4037,12 +4716,22 @@ STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)\n \t\t\t/* Write a value 11 (block Erase) in Flash\n \t\t\t * Cycle field in hw flash control\n \t\t\t */\n-\t\t\thsflctl.regval =\n-\t\t\t    E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);\n+\t\t\tif (hw->mac.type >= e1000_pch_spt)\n+\t\t\t\thsflctl.regval =\n+\t\t\t\t    E1000_READ_FLASH_REG(hw,\n+\t\t\t\t\t\t\t ICH_FLASH_HSFSTS)>>16;\n+\t\t\telse\n+\t\t\t\thsflctl.regval =\n+\t\t\t\t    E1000_READ_FLASH_REG16(hw,\n+\t\t\t\t\t\t\t   ICH_FLASH_HSFCTL);\n \n \t\t\thsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;\n-\t\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,\n-\t\t\t\t\t\thsflctl.regval);\n+\t\t\tif (hw->mac.type >= e1000_pch_spt)\n+\t\t\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,\n+\t\t\t\t\t\t      hsflctl.regval << 16);\n+\t\t\telse\n+\t\t\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,\n+\t\t\t\t\t\t\thsflctl.regval);\n \n \t\t\t/* Write the last 24 bits of an index within the\n \t\t\t * block into Flash Linear address field in Flash\n@@ -4475,7 +5164,7 @@ STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)\n \tE1000_WRITE_REG(hw, E1000_RFCTL, reg);\n \n \t/* Enable ECC on Lynxpoint */\n-\tif (hw->mac.type == e1000_pch_lpt) {\n+\tif (hw->mac.type >= e1000_pch_lpt) {\n \t\treg = E1000_READ_REG(hw, E1000_PBECCSTS);\n \t\treg |= E1000_PBECCSTS_ECC_ENABLE;\n \t\tE1000_WRITE_REG(hw, E1000_PBECCSTS, reg);\n@@ -4907,7 +5596,8 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)\n \t\tif ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||\n \t\t    (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||\n \t\t    (device_id == E1000_DEV_ID_PCH_I218_LM3) ||\n-\t\t    (device_id == E1000_DEV_ID_PCH_I218_V3)) {\n+\t\t    (device_id == E1000_DEV_ID_PCH_I218_V3) ||\n+\t\t    (hw->mac.type >= e1000_pch_spt)) {\n \t\t\tu32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);\n \n \t\t\tE1000_WRITE_REG(hw, E1000_FEXTNVM6,\ndiff --git a/drivers/net/e1000/base/e1000_ich8lan.h b/drivers/net/e1000/base/e1000_ich8lan.h\nindex 352b959..50e0e79 100644\n--- a/drivers/net/e1000/base/e1000_ich8lan.h\n+++ b/drivers/net/e1000/base/e1000_ich8lan.h\n@@ -121,6 +121,18 @@ POSSIBILITY OF SUCH DAMAGE.\n #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)\n #define E1000_FEXTNVM7_DISABLE_SMB_PERST\t0x00000020\n #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */\n+#define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS\t0x00000800\n+#define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS\t0x00001000\n+#define E1000_FEXTNVM11_DISABLE_PB_READ\t\t0x00000200\n+#define E1000_FEXTNVM11_DISABLE_MULR_FIX\t0x00002000\n+\n+/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */\n+#define E1000_RXDCTL_THRESH_UNIT_DESC\t0x01000000\n+\n+#define NVM_SIZE_MULTIPLIER 4096  /*multiplier for NVMS field*/\n+#define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/\n+#define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */\n+#define E1000_TARC0_CB_MULTIQ_3_REQ\t(1 << 28 | 1 << 29)\n #define PCIE_ICH8_SNOOP_ALL\tPCIE_NO_SNOOP_ALL\n \n #define E1000_ICH_RAR_ENTRIES\t7\ndiff --git a/drivers/net/e1000/base/e1000_regs.h b/drivers/net/e1000/base/e1000_regs.h\nindex 84531a9..364a726 100644\n--- a/drivers/net/e1000/base/e1000_regs.h\n+++ b/drivers/net/e1000/base/e1000_regs.h\n@@ -66,6 +66,8 @@ POSSIBILITY OF SUCH DAMAGE.\n #define E1000_FEXTNVM4\t0x00024  /* Future Extended NVM 4 - RW */\n #define E1000_FEXTNVM6\t0x00010  /* Future Extended NVM 6 - RW */\n #define E1000_FEXTNVM7\t0x000E4  /* Future Extended NVM 7 - RW */\n+#define E1000_FEXTNVM9\t0x5BB4  /* Future Extended NVM 9 - RW */\n+#define E1000_FEXTNVM11\t0x5BBC  /* Future Extended NVM 11 - RW */\n #define E1000_PCIEANACFG\t0x00F18 /* PCIE Analog Config */\n #define E1000_FCT\t0x00030  /* Flow Control Type - RW */\n #define E1000_CONNSW\t0x00034  /* Copper/Fiber switch control - RW */\n@@ -109,6 +111,7 @@ POSSIBILITY OF SUCH DAMAGE.\n #define E1000_PBA\t0x01000  /* Packet Buffer Allocation - RW */\n #define E1000_PBS\t0x01008  /* Packet Buffer Size */\n #define E1000_PBECCSTS\t0x0100C  /* Packet Buffer ECC Status - RW */\n+#define E1000_IOSFPC\t0x00F28  /* TX corrupted data  */\n #define E1000_EEMNGCTL\t0x01010  /* MNG EEprom Control */\n #define E1000_EEMNGCTL_I210\t0x01010  /* i210 MNG EEprom Mode Control */\n #define E1000_EEARBC\t0x01024  /* EEPROM Auto Read Bus Control */\n@@ -591,6 +594,10 @@ POSSIBILITY OF SUCH DAMAGE.\n #define E1000_TIMADJL\t0x0B60C /* Time sync time adjustment offset Low - RW */\n #define E1000_TIMADJH\t0x0B610 /* Time sync time adjustment offset High - RW */\n #define E1000_TSAUXC\t0x0B640 /* Timesync Auxiliary Control register */\n+#define\tE1000_SYSSTMPL\t0x0B648 /* HH Timesync system stamp low register */\n+#define\tE1000_SYSSTMPH\t0x0B64C /* HH Timesync system stamp hi register */\n+#define\tE1000_PLTSTMPL\t0x0B640 /* HH Timesync platform stamp low register */\n+#define\tE1000_PLTSTMPH\t0x0B644 /* HH Timesync platform stamp hi register */\n #define E1000_SYSTIMR\t0x0B6F8 /* System time register Residue */\n #define E1000_TSICR\t0x0B66C /* Interrupt Cause Register */\n #define E1000_TSIM\t0x0B674 /* Interrupt Mask Register */\n",
    "prefixes": [
        "dpdk-dev",
        "11/16"
    ]
}