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{
    "id": 17159,
    "url": "https://patches.dpdk.org/api/patches/17159/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1479740470-6723-31-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1479740470-6723-31-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1479740470-6723-31-git-send-email-arybchenko@solarflare.com",
    "date": "2016-11-21T15:00:44",
    "name": "[dpdk-dev,30/56] net/sfc: include libefx in build",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "09c47a2c8c9e8b8500f38e8448893be9eb5a9d5b",
    "submitter": {
        "id": 607,
        "url": "https://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1479740470-6723-31-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/17159/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/17159/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 30819D6B6;\n\tMon, 21 Nov 2016 16:03:57 +0100 (CET)",
            "from nbfkord-smmo02.seg.att.com (nbfkord-smmo02.seg.att.com\n\t[209.65.160.78]) by dpdk.org (Postfix) with ESMTP id 490345583\n\tfor <dev@dpdk.org>; Mon, 21 Nov 2016 16:01:57 +0100 (CET)",
            "from unknown [12.187.104.26] (EHLO nbfkord-smmo02.seg.att.com)\n\tby nbfkord-smmo02.seg.att.com(mxl_mta-7.2.4-7) with ESMTP id\n\t56c03385.2b92c94a1940.1541333.00-2474.3424384.nbfkord-smmo02.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tMon, 21 Nov 2016 15:01:57 +0000 (UTC)",
            "from unknown [12.187.104.26]\n\tby nbfkord-smmo02.seg.att.com(mxl_mta-7.2.4-7) with SMTP id\n\t75c03385.0.1541303.00-2362.3424256.nbfkord-smmo02.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tMon, 21 Nov 2016 15:01:46 +0000 (UTC)",
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            "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1Ku2007188; Mon, 21 Nov 2016 15:01:20 GMT",
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        ],
        "X-MXL-Hash": [
            "58330c6500e2a81f-c08fc823366bd4797f2e1fe29a0fed04a702d8ad",
            "58330c5a56132418-d3cca79c411c04a972d9b509fc64b711b8b4c31d"
        ],
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<dev@dpdk.org>",
        "CC": "Artem Andreev <Artem.Andreev@oktetlabs.ru>",
        "Date": "Mon, 21 Nov 2016 15:00:44 +0000",
        "Message-ID": "<1479740470-6723-31-git-send-email-arybchenko@solarflare.com>",
        "X-Mailer": "git-send-email 1.8.2.3",
        "In-Reply-To": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>",
        "References": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-AnalysisOut": [
            "[v=2.1 cv=UI/baXry c=1 sm=1 tr=0 a=8BlWFWvVlq5taO8ncb8nKg==]",
            "[:17 a=L24OOQBejmoA:10 a=pK7X0mNQAAAA:8 a=zRKbQ67AAAAA:8 a=]",
            "[FbPFeROUtwPyUZECJiUA:9 a=5HA-qpC1VU4iIGLgRoNS:22 a=PA03WX8]",
            "[tBzeizutn5_OT:22]"
        ],
        "X-Spam": "[F=0.4931296366; CM=0.500; S=0.493(2015072901)]",
        "X-MAIL-FROM": "<arybchenko@solarflare.com>",
        "X-SOURCE-IP": "[12.187.104.26]",
        "Subject": "[dpdk-dev] [PATCH 30/56] net/sfc: include libefx in build",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
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        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
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        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Artem Andreev <Artem.Andreev@oktetlabs.ru>\n\nImplement efsys.h for the PMD.\n\nReviewed-by: Andy Moreton <amoreton@solarflare.com>\nSigned-off-by: Artem Andreev <Artem.Andreev@oktetlabs.ru>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/efx/Makefile |  54 +++\n drivers/net/sfc/efx/efsys.h  | 767 +++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 821 insertions(+)\n create mode 100644 drivers/net/sfc/efx/efsys.h",
    "diff": "diff --git a/drivers/net/sfc/efx/Makefile b/drivers/net/sfc/efx/Makefile\nindex 71f07ca..de95ea8 100644\n--- a/drivers/net/sfc/efx/Makefile\n+++ b/drivers/net/sfc/efx/Makefile\n@@ -33,6 +33,8 @@ include $(RTE_SDK)/mk/rte.vars.mk\n #\n LIB = librte_pmd_sfc_efx.a\n \n+CFLAGS += -I$(SRCDIR)/base/\n+CFLAGS += -I$(SRCDIR)\n CFLAGS += -O3\n \n # Enable basic warnings but disable some which are accepted\n@@ -60,6 +62,17 @@ CFLAGS += -Wstrict-prototypes\n CFLAGS += -Wundef\n CFLAGS += -Wwrite-strings\n \n+# Extra CFLAGS for base driver files\n+CFLAGS_BASE_DRIVER += -Wno-unused-variable\n+CFLAGS_BASE_DRIVER += -Wno-unused-but-set-variable\n+\n+#\n+# List of base driver object files for which\n+# special CFLAGS above should be applied\n+#\n+BASE_DRIVER_OBJS=$(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c)))\n+$(foreach obj, $(BASE_DRIVER_OBJS), $(eval CFLAGS+=$(CFLAGS_BASE_DRIVER)))\n+\n EXPORT_MAP := rte_pmd_sfc_efx_version.map\n \n LIBABIVER := 1\n@@ -70,6 +83,47 @@ LIBABIVER := 1\n SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += sfc_ethdev.c\n SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += sfc_kvargs.c\n \n+VPATH += $(SRCDIR)/base\n+\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_bootcfg.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_crc32.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_ev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_filter.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_hash.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_intr.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_lic.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_mac.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_mcdi.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_mon.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_nic.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_nvram.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_phy.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_port.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_rx.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_sram.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_tx.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += efx_vpd.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += mcdi_mon.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += siena_mac.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += siena_mcdi.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += siena_nic.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += siena_nvram.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += siena_phy.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += siena_sram.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += siena_vpd.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_ev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_filter.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_intr.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_mac.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_mcdi.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_nic.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_nvram.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_phy.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_rx.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_tx.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += ef10_vpd.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += hunt_nic.c\n+SRCS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += medford_nic.c\n \n # this lib depends upon:\n DEPDIRS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += lib/librte_eal\ndiff --git a/drivers/net/sfc/efx/efsys.h b/drivers/net/sfc/efx/efsys.h\nnew file mode 100644\nindex 0000000..2eef996\n--- /dev/null\n+++ b/drivers/net/sfc/efx/efsys.h\n@@ -0,0 +1,767 @@\n+/*-\n+ * Copyright (c) 2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * This software was jointly developed between OKTET Labs (under contract\n+ * for Solarflare) and Solarflare Communications, Inc.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _SFC_COMMON_EFSYS_H\n+#define\t_SFC_COMMON_EFSYS_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_spinlock.h>\n+#include <rte_byteorder.h>\n+#include <rte_debug.h>\n+#include <rte_memzone.h>\n+#include <rte_memory.h>\n+#include <rte_memcpy.h>\n+#include <rte_cycles.h>\n+#include <rte_prefetch.h>\n+#include <rte_common.h>\n+#include <rte_malloc.h>\n+#include <rte_log.h>\n+\n+#include \"sfc_debug.h\"\n+\n+\n+#define\tEFSYS_HAS_UINT64 1\n+#define\tEFSYS_USE_UINT64 1\n+#define\tEFSYS_HAS_SSE2_M128 1\n+\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+#define\tEFSYS_IS_BIG_ENDIAN 1\n+#define\tEFSYS_IS_LITTLE_ENDIAN 0\n+#elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+#define\tEFSYS_IS_BIG_ENDIAN 0\n+#define\tEFSYS_IS_LITTLE_ENDIAN 1\n+#else\n+#error \"Cannot determine system endianness\"\n+#endif\n+#include \"efx_types.h\"\n+\n+\n+#ifndef _NOTE\n+#define\t_NOTE(s)\n+#endif\n+\n+typedef uint8_t boolean_t;\n+\n+#ifndef B_FALSE\n+#define\tB_FALSE\t0\n+#endif\n+#ifndef B_TRUE\n+#define\tB_TRUE\t1\n+#endif\n+\n+/*\n+ * RTE_MAX() and RTE_MIN() cannot be used since braced-group within\n+ * expression allowed only inside a function, but MAX() is used as\n+ * a number of elements in array.\n+ */\n+#ifndef MAX\n+#define\tMAX(v1, v2)\t((v1) > (v2) ? (v1) : (v2))\n+#endif\n+#ifndef MIN\n+#define\tMIN(v1, v2)\t((v1) < (v2) ? (v1) : (v2))\n+#endif\n+\n+/* There are macros for alignment in DPDK, but we need to make a proper\n+ * correspondence here, if we want to re-use them at all\n+ */\n+#ifndef IS_P2ALIGNED\n+#define\tIS_P2ALIGNED(v, a)\t((((uintptr_t)(v)) & ((uintptr_t)(a) - 1)) == 0)\n+#endif\n+\n+#ifndef P2ROUNDUP\n+#define\tP2ROUNDUP(x, align)\t(-(-(x) & -(align)))\n+#endif\n+\n+#ifndef P2ALIGN\n+#define\tP2ALIGN(_x, _a)\t\t((_x) & -(_a))\n+#endif\n+\n+#ifndef IS2P\n+#define\tISP2(x)\t\t\trte_is_power_of_2(x)\n+#endif\n+\n+#define\tENOTACTIVE\tENOTCONN\n+\n+static inline void\n+prefetch_read_many(const volatile void *addr)\n+{\n+\trte_prefetch0(addr);\n+}\n+\n+static inline void\n+prefetch_read_once(const volatile void *addr)\n+{\n+\trte_prefetch_non_temporal(addr);\n+}\n+\n+/* Modifiers used for Windows builds */\n+#define\t__in\n+#define\t__in_opt\n+#define\t__in_ecount(_n)\n+#define\t__in_ecount_opt(_n)\n+#define\t__in_bcount(_n)\n+#define\t__in_bcount_opt(_n)\n+\n+#define\t__out\n+#define\t__out_opt\n+#define\t__out_ecount(_n)\n+#define\t__out_ecount_opt(_n)\n+#define\t__out_bcount(_n)\n+#define\t__out_bcount_opt(_n)\n+\n+#define\t__deref_out\n+\n+#define\t__inout\n+#define\t__inout_opt\n+#define\t__inout_ecount(_n)\n+#define\t__inout_ecount_opt(_n)\n+#define\t__inout_bcount(_n)\n+#define\t__inout_bcount_opt(_n)\n+#define\t__inout_bcount_full_opt(_n)\n+\n+#define\t__deref_out_bcount_opt(n)\n+\n+#define\t__checkReturn\n+#define\t__success(_x)\n+\n+#define\t__drv_when(_p, _c)\n+\n+/* Code inclusion options */\n+\n+\n+#define\tEFSYS_OPT_NAMES 0\n+\n+#define\tEFSYS_OPT_SIENA 0\n+#define\tEFSYS_OPT_HUNTINGTON 1\n+#define\tEFSYS_OPT_MEDFORD 1\n+#ifdef RTE_LIBRTE_SFC_EFX_DEBUG\n+#define\tEFSYS_OPT_CHECK_REG 1\n+#else\n+#define\tEFSYS_OPT_CHECK_REG 0\n+#endif\n+\n+#define\tEFSYS_OPT_MCDI 1\n+#define\tEFSYS_OPT_MCDI_LOGGING 0\n+#define\tEFSYS_OPT_MCDI_PROXY_AUTH 0\n+\n+#define\tEFSYS_OPT_MAC_STATS 0\n+\n+#define\tEFSYS_OPT_LOOPBACK 0\n+\n+#define\tEFSYS_OPT_MON_MCDI 0\n+#define\tEFSYS_OPT_MON_STATS 0\n+\n+#define\tEFSYS_OPT_PHY_STATS 0\n+#define\tEFSYS_OPT_BIST 0\n+#define\tEFSYS_OPT_PHY_LED_CONTROL 0\n+#define\tEFSYS_OPT_PHY_FLAGS 0\n+\n+#define\tEFSYS_OPT_VPD 0\n+#define\tEFSYS_OPT_NVRAM 0\n+#define\tEFSYS_OPT_BOOTCFG 0\n+\n+#define\tEFSYS_OPT_DIAG 0\n+#define\tEFSYS_OPT_RX_SCALE 0\n+#define\tEFSYS_OPT_QSTATS 0\n+#define\tEFSYS_OPT_FILTER 1\n+#define\tEFSYS_OPT_RX_SCATTER 0\n+\n+#define\tEFSYS_OPT_EV_PREFETCH 0\n+\n+#define\tEFSYS_OPT_DECODE_INTR_FATAL 0\n+\n+#define\tEFSYS_OPT_LICENSING 0\n+\n+#define\tEFSYS_OPT_ALLOW_UNCONFIGURED_NIC 0\n+\n+#define\tEFSYS_OPT_RX_PACKED_STREAM 0\n+\n+/* ID */\n+\n+typedef struct __efsys_identifier_s efsys_identifier_t;\n+\n+\n+#define\tEFSYS_PROBE(_name)\t\t\t\t\t\t\\\n+\tdo { } while (0)\n+\n+#define\tEFSYS_PROBE1(_name, _type1, _arg1)\t\t\t\t\\\n+\tdo { } while (0)\n+\n+#define\tEFSYS_PROBE2(_name, _type1, _arg1, _type2, _arg2)\t\t\\\n+\tdo { } while (0)\n+\n+#define\tEFSYS_PROBE3(_name, _type1, _arg1, _type2, _arg2,\t\t\\\n+\t\t     _type3, _arg3)\t\t\t\t\t\\\n+\tdo { } while (0)\n+\n+#define\tEFSYS_PROBE4(_name, _type1, _arg1, _type2, _arg2,\t\t\\\n+\t\t     _type3, _arg3, _type4, _arg4)\t\t\t\\\n+\tdo { } while (0)\n+\n+#define\tEFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2,\t\t\\\n+\t\t     _type3, _arg3, _type4, _arg4, _type5, _arg5)\t\\\n+\tdo { } while (0)\n+\n+#define\tEFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2,\t\t\\\n+\t\t     _type3, _arg3, _type4, _arg4, _type5, _arg5,\t\\\n+\t\t     _type6, _arg6)\t\t\t\t\t\\\n+\tdo { } while (0)\n+\n+#define\tEFSYS_PROBE7(_name, _type1, _arg1, _type2, _arg2,\t\t\\\n+\t\t     _type3, _arg3, _type4, _arg4, _type5, _arg5,\t\\\n+\t\t     _type6, _arg6, _type7, _arg7)\t\t\t\\\n+\tdo { } while (0)\n+\n+\n+/* DMA */\n+\n+typedef phys_addr_t efsys_dma_addr_t;\n+\n+typedef struct efsys_mem_s {\n+\tconst struct rte_memzone\t*esm_mz;\n+\t/*\n+\t * Ideally it should have volatile qualifier to denote that\n+\t * the memory may be updated by someone else. However, it adds\n+\t * qualifier discard warnings when the pointer or its derivative\n+\t * is passed to memset() or rte_mov16().\n+\t * So, skip the qualifier here, but make sure that it is added\n+\t * below in access macros.\n+\t */\n+\tvoid\t\t\t\t*esm_base;\n+\tefsys_dma_addr_t\t\tesm_addr;\n+} efsys_mem_t;\n+\n+\n+#define\tEFSYS_MEM_ZERO(_esmp, _size)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(void)memset((void *)(_esmp)->esm_base, 0, (_size));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_MEM_READD(_esmp, _offset, _edp)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t  *_base = (_esmp)->esm_base;\t\t\\\n+\t\tvolatile uint32_t *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_dword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile uint32_t *)(_base + (_offset));\t\\\n+\t\t(_edp)->ed_u32[0] = _addr[0];\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE2(mem_readl, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_edp)->ed_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_MEM_READQ(_esmp, _offset, _eqp)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t  *_base = (_esmp)->esm_base;\t\t\\\n+\t\tvolatile uint64_t *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_qword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile uint64_t *)(_base + (_offset));\t\\\n+\t\t(_eqp)->eq_u64[0] = _addr[0];\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE3(mem_readq, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_eqp)->eq_u32[1],\t\\\n+\t\t\t\t\t uint32_t, (_eqp)->eq_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_MEM_READO(_esmp, _offset, _eop)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t *_base = (_esmp)->esm_base;\t\t\\\n+\t\tvolatile __m128i *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_oword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile __m128i *)(_base + (_offset));\t\\\n+\t\t(_eop)->eo_u128[0] = _addr[0];\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE5(mem_reado, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[3],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[2],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[1],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+\n+#define\tEFSYS_MEM_WRITED(_esmp, _offset, _edp)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t  *_base = (_esmp)->esm_base;\t\t\\\n+\t\tvolatile uint32_t *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_dword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE2(mem_writed, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_edp)->ed_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile uint32_t *)(_base + (_offset));\t\\\n+\t\t_addr[0] = (_edp)->ed_u32[0];\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_MEM_WRITEQ(_esmp, _offset, _eqp)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t  *_base = (_esmp)->esm_base;\t\t\\\n+\t\tvolatile uint64_t *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_qword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE3(mem_writeq, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_eqp)->eq_u32[1],\t\\\n+\t\t\t\t\t uint32_t, (_eqp)->eq_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile uint64_t *)(_base + (_offset));\t\\\n+\t\t_addr[0] = (_eqp)->eq_u64[0];\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_MEM_WRITEO(_esmp, _offset, _eop)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t *_base = (_esmp)->esm_base;\t\t\\\n+\t\tvolatile __m128i *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_oword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE5(mem_writeo, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[3],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[2],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[1],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile __m128i *)(_base + (_offset));\t\\\n+\t\t_addr[0] = (_eop)->eo_u128[0];\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+\n+#define\tEFSYS_MEM_ADDR(_esmp)\t\t\t\t\t\t\\\n+\t((_esmp)->esm_addr)\n+\n+#define\tEFSYS_MEM_IS_NULL(_esmp)\t\t\t\t\t\\\n+\t((_esmp)->esm_base == NULL)\n+\n+#define\tEFSYS_MEM_PREFETCH(_esmp, _offset)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t *_base = (_esmp)->esm_base;\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trte_prefetch0(_base + (_offset));\t\t\t\\\n+\t} while (0)\n+\n+\n+/* BAR */\n+\n+typedef struct efsys_bar_s {\n+\trte_spinlock_t\t\tesb_lock;\n+\tint\t\t\tesb_rid;\n+\tstruct rte_pci_device\t*esb_dev;\n+\t/*\n+\t * Ideally it should have volatile qualifier to denote that\n+\t * the memory may be updated by someone else. However, it adds\n+\t * qualifier discard warnings when the pointer or its derivative\n+\t * is passed to memset() or rte_mov16().\n+\t * So, skip the qualifier here, but make sure that it is added\n+\t * below in access macros.\n+\t */\n+\tvoid\t\t\t*esb_base;\n+} efsys_bar_t;\n+\n+#define\tSFC_BAR_LOCK_INIT(_esbp, _ifname)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\trte_spinlock_init(&(_esbp)->esb_lock);\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+#define\tSFC_BAR_LOCK_DESTROY(_esbp)\t((void)0)\n+#define\tSFC_BAR_LOCK(_esbp)\t\trte_spinlock_lock(&(_esbp)->esb_lock)\n+#define\tSFC_BAR_UNLOCK(_esbp)\t\trte_spinlock_unlock(&(_esbp)->esb_lock)\n+\n+#define\tEFSYS_BAR_READD(_esbp, _offset, _edp, _lock)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t  *_base = (_esbp)->esb_base;\t\t\\\n+\t\tvolatile uint32_t *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_dword_t)));\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tif (_lock)\t\t\t\t\t\t\\\n+\t\t\tSFC_BAR_LOCK(_esbp);\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile uint32_t *)(_base + (_offset));\t\\\n+\t\trte_rmb();\t\t\t\t\t\t\\\n+\t\t(_edp)->ed_u32[0] = _addr[0];\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE2(bar_readd, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_edp)->ed_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tif (_lock)\t\t\t\t\t\t\\\n+\t\t\tSFC_BAR_UNLOCK(_esbp);\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_BAR_READQ(_esbp, _offset, _eqp)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t  *_base = (_esbp)->esb_base;\t\t\\\n+\t\tvolatile uint64_t *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_qword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tSFC_BAR_LOCK(_esbp);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile uint64_t *)(_base + (_offset));\t\\\n+\t\trte_rmb();\t\t\t\t\t\t\\\n+\t\t(_eqp)->eq_u64[0] = _addr[0];\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE3(bar_readq, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_eqp)->eq_u32[1],\t\\\n+\t\t\t\t\t uint32_t, (_eqp)->eq_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tSFC_BAR_UNLOCK(_esbp);\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_BAR_READO(_esbp, _offset, _eop, _lock)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t *_base = (_esbp)->esb_base;\t\t\\\n+\t\tvolatile __m128i *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_oword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tif (_lock)\t\t\t\t\t\t\\\n+\t\t\tSFC_BAR_LOCK(_esbp);\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile __m128i *)(_base + (_offset));\t\\\n+\t\trte_rmb();\t\t\t\t\t\t\\\n+\t\t(_eop)->eo_u128[0] = _addr[0];\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE5(bar_reado, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[3],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[2],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[1],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tif (_lock)\t\t\t\t\t\t\\\n+\t\t\tSFC_BAR_UNLOCK(_esbp);\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+\n+#define\tEFSYS_BAR_WRITED(_esbp, _offset, _edp, _lock)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t  *_base = (_esbp)->esb_base;\t\t\\\n+\t\tvolatile uint32_t *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_dword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tif (_lock)\t\t\t\t\t\t\\\n+\t\t\tSFC_BAR_LOCK(_esbp);\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE2(bar_writed, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_edp)->ed_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile uint32_t *)(_base + (_offset));\t\\\n+\t\t_addr[0] = (_edp)->ed_u32[0];\t\t\t\t\\\n+\t\trte_wmb();\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tif (_lock)\t\t\t\t\t\t\\\n+\t\t\tSFC_BAR_UNLOCK(_esbp);\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_BAR_WRITEQ(_esbp, _offset, _eqp)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t  *_base = (_esbp)->esb_base;\t\t\\\n+\t\tvolatile uint64_t *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_qword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tSFC_BAR_LOCK(_esbp);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE3(bar_writeq, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_eqp)->eq_u32[1],\t\\\n+\t\t\t\t\t uint32_t, (_eqp)->eq_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile uint64_t *)(_base + (_offset));\t\\\n+\t\t_addr[0] = (_eqp)->eq_u64[0];\t\t\t\t\\\n+\t\trte_wmb();\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tSFC_BAR_UNLOCK(_esbp);\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/*\n+ * Guarantees 64bit aligned 64bit writes to write combined BAR mapping\n+ * (required by PIO hardware).\n+ *\n+ * Neither VFIO, nor UIO, nor NIC UIO (on FreeBSD) support\n+ * write-combined memory mapped to user-land, so just abort if used.\n+ */\n+#define\tEFSYS_BAR_WC_WRITEQ(_esbp, _offset, _eqp)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\trte_panic(\"Write-combined BAR access not supported\");\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_BAR_WRITEO(_esbp, _offset, _eop, _lock)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tvolatile uint8_t *_base = (_esbp)->esb_base;\t\t\\\n+\t\tvolatile __m128i *_addr;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tSFC_ASSERT(IS_P2ALIGNED(_offset, sizeof(efx_oword_t)));\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tif (_lock)\t\t\t\t\t\t\\\n+\t\t\tSFC_BAR_LOCK(_esbp);\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE5(bar_writeo, unsigned int, (_offset),\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[3],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[2],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[1],\t\\\n+\t\t\t\t\t uint32_t, (_eop)->eo_u32[0]);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_addr = (volatile __m128i *)(_base + (_offset));\t\\\n+\t\t_addr[0] = (_eop)->eo_u128[0];\t\t\t\t\\\n+\t\trte_wmb();\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t\tif (_lock)\t\t\t\t\t\t\\\n+\t\t\tSFC_BAR_UNLOCK(_esbp);\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/* Use the standard octo-word write for doorbell writes */\n+#define\tEFSYS_BAR_DOORBELL_WRITEO(_esbp, _offset, _eop)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_BAR_WRITEO((_esbp), (_offset), (_eop), B_FALSE);\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/* SPIN */\n+\n+#define\tEFSYS_SPIN(_us)\t\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\trte_delay_us(_us);\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_SLEEP EFSYS_SPIN\n+\n+/* BARRIERS */\n+\n+#define\tEFSYS_MEM_READ_BARRIER()\trte_rmb()\n+#define\tEFSYS_PIO_WRITE_BARRIER()\trte_wmb()\n+\n+/* DMA SYNC */\n+\n+/*\n+ * DPDK does not provide any DMA syncing API, and no PMD drivers\n+ * have any traces of explicit DMA syncing.\n+ * DMA mapping is assumed to be coherent.\n+ */\n+\n+#define\tEFSYS_DMA_SYNC_FOR_KERNEL(_esmp, _offset, _size)\t((void)0)\n+#define\tEFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size)\t((void)0)\n+\n+/* TIMESTAMP */\n+\n+typedef uint64_t efsys_timestamp_t;\n+\n+#define\tEFSYS_TIMESTAMP(_usp)\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t*(_usp) = rte_get_timer_cycles() * 1000000 /\t\t\\\n+\t\t\trte_get_timer_hz();\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/* KMEM */\n+\n+#define\tEFSYS_KMEM_ALLOC(_esip, _size, _p)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_esip) = (_esip);\t\t\t\t\t\\\n+\t\t(_p) = rte_zmalloc(\"sfc\", (_size), 0);\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_KMEM_FREE(_esip, _size, _p)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(void)(_esip);\t\t\t\t\t\t\\\n+\t\t(void)(_size);\t\t\t\t\t\t\\\n+\t\trte_free((_p));\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/* LOCK */\n+\n+typedef rte_spinlock_t efsys_lock_t;\n+\n+#define\tSFC_EFSYS_LOCK_INIT(_eslp, _ifname, _label)\t\\\n+\trte_spinlock_init((_eslp))\n+#define\tSFC_EFSYS_LOCK_DESTROY(_eslp) ((void)0)\n+#define\tSFC_EFSYS_LOCK(_eslp)\t\t\t\t\\\n+\trte_spinlock_lock((_eslp))\n+#define\tSFC_EFSYS_UNLOCK(_eslp)\t\t\t\t\\\n+\trte_spinlock_unlock((_eslp))\n+#define\tSFC_EFSYS_LOCK_ASSERT_OWNED(_eslp)\t\t\\\n+\tSFC_ASSERT(rte_spinlock_is_locked((_eslp)))\n+\n+typedef int efsys_lock_state_t;\n+\n+#define\tEFSYS_LOCK_MAGIC\t0x000010c4\n+\n+#define\tEFSYS_LOCK(_lockp, _state)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\\\n+\t\tSFC_EFSYS_LOCK(_lockp);\t\t\t\t\\\n+\t\t(_state) = EFSYS_LOCK_MAGIC;\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_UNLOCK(_lockp, _state)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\\\n+\t\tSFC_ASSERT((_state) == EFSYS_LOCK_MAGIC);\t\\\n+\t\tSFC_EFSYS_UNLOCK(_lockp);\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/* STAT */\n+\n+typedef uint64_t\tefsys_stat_t;\n+\n+#define\tEFSYS_STAT_INCR(_knp, _delta)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\\\n+\t\t*(_knp) += (_delta);\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_STAT_DECR(_knp, _delta)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\\\n+\t\t*(_knp) -= (_delta);\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_STAT_SET(_knp, _val)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\\\n+\t\t*(_knp) = (_val);\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_STAT_SET_QWORD(_knp, _valp)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\\\n+\t\t*(_knp) = rte_le_to_cpu_64((_valp)->eq_u64[0]);\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_STAT_SET_DWORD(_knp, _valp)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\\\n+\t\t*(_knp) = rte_le_to_cpu_32((_valp)->ed_u32[0]);\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_STAT_INCR_QWORD(_knp, _valp)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t*(_knp) += rte_le_to_cpu_64((_valp)->eq_u64[0]);\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFSYS_STAT_SUBR_QWORD(_knp, _valp)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t*(_knp) -= rte_le_to_cpu_64((_valp)->eq_u64[0]);\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/* ERR */\n+\n+#if EFSYS_OPT_DECODE_INTR_FATAL\n+#define\tEFSYS_ERR(_esip, _code, _dword0, _dword1)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(void)(_esip);\t\t\t\t\t\t\\\n+\t\tRTE_LOG(ERR, PMD, \"FATAL ERROR #%u (0x%08x%08x)\\n\",\t\\\n+\t\t\t(_code), (_dword0), (_dword1));\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION);\t\t\t\t\\\n+\t} while (B_FALSE)\n+#endif\n+\n+/* ASSERT */\n+\n+/* RTE_VERIFY from DPDK treats expressions with % operator incorrectly,\n+ * so we re-implement it here\n+ */\n+#ifdef RTE_LIBRTE_SFC_EFX_DEBUG\n+#define\tEFSYS_ASSERT(_exp)\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tif (unlikely(!(_exp)))\t\t\t\t\t\\\n+\t\t\trte_panic(\"line %d\\tassert \\\"%s\\\" failed\\n\",\t\\\n+\t\t\t\t  __LINE__, (#_exp));\t\t\t\\\n+\t} while (0)\n+#else\n+#define\tEFSYS_ASSERT(_exp)\t\t(void)(_exp)\n+#endif\n+\n+#define\tEFSYS_ASSERT3(_x, _op, _y, _t)\tEFSYS_ASSERT((_t)(_x) _op (_t)(_y))\n+\n+#define\tEFSYS_ASSERT3U(_x, _op, _y)\tEFSYS_ASSERT3(_x, _op, _y, uint64_t)\n+#define\tEFSYS_ASSERT3S(_x, _op, _y)\tEFSYS_ASSERT3(_x, _op, _y, int64_t)\n+#define\tEFSYS_ASSERT3P(_x, _op, _y)\tEFSYS_ASSERT3(_x, _op, _y, uintptr_t)\n+\n+/* ROTATE */\n+\n+#define\tEFSYS_HAS_ROTL_DWORD\t0\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif  /* _SFC_COMMON_EFSYS_H */\n",
    "prefixes": [
        "dpdk-dev",
        "30/56"
    ]
}