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{
    "id": 17132,
    "url": "https://patches.dpdk.org/api/patches/17132/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1479740470-6723-3-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1479740470-6723-3-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1479740470-6723-3-git-send-email-arybchenko@solarflare.com",
    "date": "2016-11-21T15:00:16",
    "name": "[dpdk-dev,02/56] net/sfc: import libefx base",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "56a5403eeef830414f280168945480d884facccd",
    "submitter": {
        "id": 607,
        "url": "https://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1479740470-6723-3-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/17132/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/17132/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 528DAD574;\n\tMon, 21 Nov 2016 16:03:20 +0100 (CET)",
            "from nbfkord-smmo02.seg.att.com (nbfkord-smmo02.seg.att.com\n\t[209.65.160.78]) by dpdk.org (Postfix) with ESMTP id CBBFF377A\n\tfor <dev@dpdk.org>; Mon, 21 Nov 2016 16:01:35 +0100 (CET)",
            "from unknown [12.187.104.26]\n\tby nbfkord-smmo02.seg.att.com(mxl_mta-7.2.4-7) with SMTP id\n\tf4c03385.0.1541303.00-2367.3424218.nbfkord-smmo02.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tMon, 21 Nov 2016 15:01:35 +0000 (UTC)",
            "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 21 Nov 2016 07:01:21 -0800",
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            "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1JV7007100 for <dev@dpdk.org>; Mon, 21 Nov 2016 15:01:19 GMT",
            "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1J2r006765 for <dev@dpdk.org>; Mon, 21 Nov 2016 15:01:19 GMT"
        ],
        "X-MXL-Hash": "58330c4f6e7a6939-43282143cd1dbe856e43aa69c295860b49b442a5",
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<dev@dpdk.org>",
        "Date": "Mon, 21 Nov 2016 15:00:16 +0000",
        "Message-ID": "<1479740470-6723-3-git-send-email-arybchenko@solarflare.com>",
        "X-Mailer": "git-send-email 1.8.2.3",
        "In-Reply-To": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>",
        "References": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-AnalysisOut": [
            "[v=2.1 cv=UI/baXry c=1 sm=1 tr=0 a=8BlWFWvVlq5taO8ncb8nKg==]",
            "[:17 a=L24OOQBejmoA:10 a=zRKbQ67AAAAA:8 a=hOkPH7apAAAA:8 a=]",
            "[S37PJWLLiXWq2LdgOOgA:9 a=1rQW9vNupjhtIAhB:21 a=RPqFqMusizl]",
            "[7Jh03:21 a=Uhk-FQUjAG77lyWx:21 a=PA03WX8tBzeizutn5_OT:22 a]",
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        ],
        "X-Spam": "[F=0.4997159789; CM=0.500; S=0.499(2015072901)]",
        "X-MAIL-FROM": "<arybchenko@solarflare.com>",
        "X-SOURCE-IP": "[12.187.104.26]",
        "Subject": "[dpdk-dev] [PATCH 02/56] net/sfc: import libefx base",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "libefx is a platform-independent library to implement drivers\nfor Solarflare network adapters. It provides unified adapter\nfamily independent interface (if possible).\n\nDriver must provide efsys.h header which defines options\n(EFSYS_OPT_*) to be used and macros/functions to allocate\nmemory, read/write DMA-mapped memory, read/write PCI BAR\nspace, locks, barriers etc.\n\nefx.h and efx_types.h provide external interfaces intended\nto be used by drivers. Other header files are internal.\n\nFrom Solarflare Communications Inc.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/efx/base/README        |   36 +\n drivers/net/sfc/efx/base/efx.h         | 1067 +++++++++++++++++++++\n drivers/net/sfc/efx/base/efx_check.h   |  171 ++++\n drivers/net/sfc/efx/base/efx_crc32.c   |  122 +++\n drivers/net/sfc/efx/base/efx_ev.c      |  432 +++++++++\n drivers/net/sfc/efx/base/efx_hash.c    |  328 +++++++\n drivers/net/sfc/efx/base/efx_impl.h    |  658 +++++++++++++\n drivers/net/sfc/efx/base/efx_intr.c    |  201 ++++\n drivers/net/sfc/efx/base/efx_mac.c     |  489 ++++++++++\n drivers/net/sfc/efx/base/efx_mon.c     |  118 +++\n drivers/net/sfc/efx/base/efx_nic.c     |  549 +++++++++++\n drivers/net/sfc/efx/base/efx_phy.c     |  248 +++++\n drivers/net/sfc/efx/base/efx_phy_ids.h |   51 +\n drivers/net/sfc/efx/base/efx_port.c    |  151 +++\n drivers/net/sfc/efx/base/efx_rx.c      |  242 +++++\n drivers/net/sfc/efx/base/efx_sram.c    |  168 ++++\n drivers/net/sfc/efx/base/efx_tx.c      |  463 +++++++++\n drivers/net/sfc/efx/base/efx_types.h   | 1647 ++++++++++++++++++++++++++++++++\n 18 files changed, 7141 insertions(+)\n create mode 100644 drivers/net/sfc/efx/base/README\n create mode 100644 drivers/net/sfc/efx/base/efx.h\n create mode 100644 drivers/net/sfc/efx/base/efx_check.h\n create mode 100644 drivers/net/sfc/efx/base/efx_crc32.c\n create mode 100644 drivers/net/sfc/efx/base/efx_ev.c\n create mode 100644 drivers/net/sfc/efx/base/efx_hash.c\n create mode 100644 drivers/net/sfc/efx/base/efx_impl.h\n create mode 100644 drivers/net/sfc/efx/base/efx_intr.c\n create mode 100644 drivers/net/sfc/efx/base/efx_mac.c\n create mode 100644 drivers/net/sfc/efx/base/efx_mon.c\n create mode 100644 drivers/net/sfc/efx/base/efx_nic.c\n create mode 100644 drivers/net/sfc/efx/base/efx_phy.c\n create mode 100644 drivers/net/sfc/efx/base/efx_phy_ids.h\n create mode 100644 drivers/net/sfc/efx/base/efx_port.c\n create mode 100644 drivers/net/sfc/efx/base/efx_rx.c\n create mode 100644 drivers/net/sfc/efx/base/efx_sram.c\n create mode 100644 drivers/net/sfc/efx/base/efx_tx.c\n create mode 100644 drivers/net/sfc/efx/base/efx_types.h",
    "diff": "diff --git a/drivers/net/sfc/efx/base/README b/drivers/net/sfc/efx/base/README\nnew file mode 100644\nindex 0000000..9019e8b\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/README\n@@ -0,0 +1,36 @@\n+\n+   Copyright (c) 2006-2016 Solarflare Communications Inc.\n+   All rights reserved.\n+\n+   Redistribution and use in source and binary forms, with or without\n+   modification, are permitted provided that the following conditions are met:\n+\n+   1. Redistributions of source code must retain the above copyright notice,\n+      this list of conditions and the following disclaimer.\n+   2. Redistributions in binary form must reproduce the above copyright notice,\n+      this list of conditions and the following disclaimer in the documentation\n+      and/or other materials provided with the distribution.\n+\n+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+   THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+   PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+   EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+   PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+   OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+   WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+   OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+   EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+Solarflare libefx driver library\n+================================\n+\n+This directory contains source code of Solarflare Communications libefx\n+driver library of version v4.10.0.1012.\n+\n+Updating\n+========\n+\n+The source code in this directory should not be modified.\n+Please contact the driver maintainers to request changes.\ndiff --git a/drivers/net/sfc/efx/base/efx.h b/drivers/net/sfc/efx/base/efx.h\nnew file mode 100644\nindex 0000000..79c6fdc\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx.h\n@@ -0,0 +1,1067 @@\n+/*\n+ * Copyright (c) 2006-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#ifndef\t_SYS_EFX_H\n+#define\t_SYS_EFX_H\n+\n+#include \"efsys.h\"\n+#include \"efx_check.h\"\n+#include \"efx_phy_ids.h\"\n+\n+#ifdef\t__cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define\tEFX_STATIC_ASSERT(_cond)\t\t\\\n+\t((void)sizeof(char[(_cond) ? 1 : -1]))\n+\n+#define\tEFX_ARRAY_SIZE(_array)\t\t\t\\\n+\t(sizeof(_array) / sizeof((_array)[0]))\n+\n+#define\tEFX_FIELD_OFFSET(_type, _field)\t\t\\\n+\t((size_t) &(((_type *)0)->_field))\n+\n+/* Return codes */\n+\n+typedef __success(return == 0) int efx_rc_t;\n+\n+\n+/* Chip families */\n+\n+typedef enum efx_family_e {\n+\tEFX_FAMILY_INVALID,\n+\tEFX_FAMILY_FALCON,\t/* Obsolete and not supported */\n+\tEFX_FAMILY_SIENA,\n+\tEFX_FAMILY_HUNTINGTON,\n+\tEFX_FAMILY_MEDFORD,\n+\tEFX_FAMILY_NTYPES\n+} efx_family_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_family(\n+\t__in\t\tuint16_t venid,\n+\t__in\t\tuint16_t devid,\n+\t__out\t\tefx_family_t *efp);\n+\n+\n+#define\tEFX_PCI_VENID_SFC\t\t\t0x1924\n+\n+#define\tEFX_PCI_DEVID_FALCON\t\t\t0x0710\t/* SFC4000 */\n+\n+#define\tEFX_PCI_DEVID_BETHPAGE\t\t\t0x0803\t/* SFC9020 */\n+#define\tEFX_PCI_DEVID_SIENA\t\t\t0x0813\t/* SFL9021 */\n+#define\tEFX_PCI_DEVID_SIENA_F1_UNINIT\t\t0x0810\n+\n+#define\tEFX_PCI_DEVID_HUNTINGTON_PF_UNINIT\t0x0901\n+#define\tEFX_PCI_DEVID_FARMINGDALE\t\t0x0903\t/* SFC9120 PF */\n+#define\tEFX_PCI_DEVID_GREENPORT\t\t\t0x0923\t/* SFC9140 PF */\n+\n+#define\tEFX_PCI_DEVID_FARMINGDALE_VF\t\t0x1903\t/* SFC9120 VF */\n+#define\tEFX_PCI_DEVID_GREENPORT_VF\t\t0x1923\t/* SFC9140 VF */\n+\n+#define\tEFX_PCI_DEVID_MEDFORD_PF_UNINIT\t\t0x0913\n+#define\tEFX_PCI_DEVID_MEDFORD\t\t\t0x0A03\t/* SFC9240 PF */\n+#define\tEFX_PCI_DEVID_MEDFORD_VF\t\t0x1A03\t/* SFC9240 VF */\n+\n+#define\tEFX_MEM_BAR\t2\n+\n+/* Error codes */\n+\n+enum {\n+\tEFX_ERR_INVALID,\n+\tEFX_ERR_SRAM_OOB,\n+\tEFX_ERR_BUFID_DC_OOB,\n+\tEFX_ERR_MEM_PERR,\n+\tEFX_ERR_RBUF_OWN,\n+\tEFX_ERR_TBUF_OWN,\n+\tEFX_ERR_RDESQ_OWN,\n+\tEFX_ERR_TDESQ_OWN,\n+\tEFX_ERR_EVQ_OWN,\n+\tEFX_ERR_EVFF_OFLO,\n+\tEFX_ERR_ILL_ADDR,\n+\tEFX_ERR_SRAM_PERR,\n+\tEFX_ERR_NCODES\n+};\n+\n+/* Calculate the IEEE 802.3 CRC32 of a MAC addr */\n+extern\t__checkReturn\t\tuint32_t\n+efx_crc32_calculate(\n+\t__in\t\t\tuint32_t crc_init,\n+\t__in_ecount(length)\tuint8_t const *input,\n+\t__in\t\t\tint length);\n+\n+\n+/* Type prototypes */\n+\n+typedef struct efx_rxq_s\tefx_rxq_t;\n+\n+/* NIC */\n+\n+typedef struct efx_nic_s\tefx_nic_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_create(\n+\t__in\t\tefx_family_t family,\n+\t__in\t\tefsys_identifier_t *esip,\n+\t__in\t\tefsys_bar_t *esbp,\n+\t__in\t\tefsys_lock_t *eslp,\n+\t__deref_out\tefx_nic_t **enpp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_probe(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_init(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_reset(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t\tvoid\n+efx_nic_fini(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t\tvoid\n+efx_nic_unprobe(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t\tvoid\n+efx_nic_destroy(\n+\t__in\tefx_nic_t *enp);\n+\n+#define\tEFX_PCIE_LINK_SPEED_GEN1\t\t1\n+#define\tEFX_PCIE_LINK_SPEED_GEN2\t\t2\n+#define\tEFX_PCIE_LINK_SPEED_GEN3\t\t3\n+\n+typedef enum efx_pcie_link_performance_e {\n+\tEFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,\n+\tEFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,\n+\tEFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,\n+\tEFX_PCIE_LINK_PERFORMANCE_OPTIMAL\n+} efx_pcie_link_performance_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_calculate_pcie_link_bandwidth(\n+\t__in\t\tuint32_t pcie_link_width,\n+\t__in\t\tuint32_t pcie_link_gen,\n+\t__out\t\tuint32_t *bandwidth_mbpsp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_check_pcie_link_speed(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tuint32_t pcie_link_width,\n+\t__in\t\tuint32_t pcie_link_gen,\n+\t__out\t\tefx_pcie_link_performance_t *resultp);\n+\n+/* INTR */\n+\n+#define\tEFX_NINTR_SIENA 1024\n+\n+typedef enum efx_intr_type_e {\n+\tEFX_INTR_INVALID = 0,\n+\tEFX_INTR_LINE,\n+\tEFX_INTR_MESSAGE,\n+\tEFX_INTR_NTYPES\n+} efx_intr_type_t;\n+\n+#define\tEFX_INTR_SIZE\t(sizeof (efx_oword_t))\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_intr_init(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_intr_type_t type,\n+\t__in\t\tefsys_mem_t *esmp);\n+\n+extern\t\t\tvoid\n+efx_intr_enable(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t\t\tvoid\n+efx_intr_disable(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t\t\tvoid\n+efx_intr_disable_unlocked(\n+\t__in\t\tefx_nic_t *enp);\n+\n+#define\tEFX_INTR_NEVQS\t32\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_intr_trigger(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int level);\n+\n+extern\t\t\tvoid\n+efx_intr_status_line(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tboolean_t *fatalp,\n+\t__out\t\tuint32_t *maskp);\n+\n+extern\t\t\tvoid\n+efx_intr_status_message(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int message,\n+\t__out\t\tboolean_t *fatalp);\n+\n+extern\t\t\tvoid\n+efx_intr_fatal(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t\t\tvoid\n+efx_intr_fini(\n+\t__in\t\tefx_nic_t *enp);\n+\n+/* MAC */\n+\n+typedef enum efx_link_mode_e {\n+\tEFX_LINK_UNKNOWN = 0,\n+\tEFX_LINK_DOWN,\n+\tEFX_LINK_10HDX,\n+\tEFX_LINK_10FDX,\n+\tEFX_LINK_100HDX,\n+\tEFX_LINK_100FDX,\n+\tEFX_LINK_1000HDX,\n+\tEFX_LINK_1000FDX,\n+\tEFX_LINK_10000FDX,\n+\tEFX_LINK_40000FDX,\n+\tEFX_LINK_NMODES\n+} efx_link_mode_t;\n+\n+#define\tEFX_MAC_ADDR_LEN 6\n+\n+#define\tEFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)\n+\n+#define\tEFX_MAC_MULTICAST_LIST_MAX\t256\n+\n+#define\tEFX_MAC_SDU_MAX\t9202\n+\n+#define\tEFX_MAC_PDU_ADJUSTMENT\t\t\t\t\t\\\n+\t(/* EtherII */ 14\t\t\t\t\t\\\n+\t    + /* VLAN */ 4\t\t\t\t\t\\\n+\t    + /* CRC */ 4\t\t\t\t\t\\\n+\t    + /* bug16011 */ 16)\t\t\t\t\\\n+\n+#define\tEFX_MAC_PDU(_sdu)\t\t\t\t\t\\\n+\tP2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)\n+\n+/*\n+ * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give\n+ * the SDU rounded up slightly.\n+ */\n+#define\tEFX_MAC_SDU_FROM_PDU(_pdu)\t((_pdu) - EFX_MAC_PDU_ADJUSTMENT)\n+\n+#define\tEFX_MAC_PDU_MIN\t60\n+#define\tEFX_MAC_PDU_MAX\tEFX_MAC_PDU(EFX_MAC_SDU_MAX)\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_mac_pdu_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tsize_t *pdu);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_mac_pdu_set(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tsize_t pdu);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_mac_addr_set(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tuint8_t *addr);\n+\n+extern\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_filter_set(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tboolean_t all_unicst,\n+\t__in\t\t\t\tboolean_t mulcst,\n+\t__in\t\t\t\tboolean_t all_mulcst,\n+\t__in\t\t\t\tboolean_t brdcst);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_mac_multicast_list_set(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in_ecount(6*count)\t\tuint8_t const *addrs,\n+\t__in\t\t\t\tint count);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_mac_filter_default_rxq_set(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_rxq_t *erp,\n+\t__in\t\tboolean_t using_rss);\n+\n+extern\t\t\tvoid\n+efx_mac_filter_default_rxq_clear(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_mac_drain(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tboolean_t enabled);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_mac_up(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tboolean_t *mac_upp);\n+\n+#define\tEFX_FCNTL_RESPOND\t0x00000001\n+#define\tEFX_FCNTL_GENERATE\t0x00000002\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_mac_fcntl_set(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int fcntl,\n+\t__in\t\tboolean_t autoneg);\n+\n+extern\t\t\tvoid\n+efx_mac_fcntl_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tunsigned int *fcntl_wantedp,\n+\t__out\t\tunsigned int *fcntl_linkp);\n+\n+\n+/* MON */\n+\n+typedef enum efx_mon_type_e {\n+\tEFX_MON_INVALID = 0,\n+\tEFX_MON_SFC90X0,\n+\tEFX_MON_SFC91X0,\n+\tEFX_MON_SFC92X0,\n+\tEFX_MON_NTYPES\n+} efx_mon_type_t;\n+\n+#if EFSYS_OPT_NAMES\n+\n+extern\t\tconst char *\n+efx_mon_name(\n+\t__in\tefx_nic_t *enp);\n+\n+#endif\t/* EFSYS_OPT_NAMES */\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_mon_init(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t\tvoid\n+efx_mon_fini(\n+\t__in\tefx_nic_t *enp);\n+\n+/* PHY */\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_phy_verify(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_port_init(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_port_poll(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out_opt\tefx_link_mode_t\t*link_modep);\n+\n+extern\t\tvoid\n+efx_port_fini(\n+\t__in\tefx_nic_t *enp);\n+\n+typedef enum efx_phy_cap_type_e {\n+\tEFX_PHY_CAP_INVALID = 0,\n+\tEFX_PHY_CAP_10HDX,\n+\tEFX_PHY_CAP_10FDX,\n+\tEFX_PHY_CAP_100HDX,\n+\tEFX_PHY_CAP_100FDX,\n+\tEFX_PHY_CAP_1000HDX,\n+\tEFX_PHY_CAP_1000FDX,\n+\tEFX_PHY_CAP_10000FDX,\n+\tEFX_PHY_CAP_PAUSE,\n+\tEFX_PHY_CAP_ASYM,\n+\tEFX_PHY_CAP_AN,\n+\tEFX_PHY_CAP_40000FDX,\n+\tEFX_PHY_CAP_NTYPES\n+} efx_phy_cap_type_t;\n+\n+\n+#define\tEFX_PHY_CAP_CURRENT\t0x00000000\n+#define\tEFX_PHY_CAP_DEFAULT\t0x00000001\n+#define\tEFX_PHY_CAP_PERM\t0x00000002\n+\n+extern\t\tvoid\n+efx_phy_adv_cap_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tuint32_t flag,\n+\t__out\t\tuint32_t *maskp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_phy_adv_cap_set(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tuint32_t mask);\n+\n+extern\t\t\tvoid\n+efx_phy_lp_cap_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tuint32_t *maskp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_phy_oui_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tuint32_t *ouip);\n+\n+typedef enum efx_phy_media_type_e {\n+\tEFX_PHY_MEDIA_INVALID = 0,\n+\tEFX_PHY_MEDIA_XAUI,\n+\tEFX_PHY_MEDIA_CX4,\n+\tEFX_PHY_MEDIA_KX4,\n+\tEFX_PHY_MEDIA_XFP,\n+\tEFX_PHY_MEDIA_SFP_PLUS,\n+\tEFX_PHY_MEDIA_BASE_T,\n+\tEFX_PHY_MEDIA_QSFP_PLUS,\n+\tEFX_PHY_MEDIA_NTYPES\n+} efx_phy_media_type_t;\n+\n+/* Get the type of medium currently used.  If the board has ports for\n+ * modules, a module is present, and we recognise the media type of\n+ * the module, then this will be the media type of the module.\n+ * Otherwise it will be the media type of the port.\n+ */\n+extern\t\t\tvoid\n+efx_phy_media_type_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tefx_phy_media_type_t *typep);\n+\n+extern\t\t\t\t\tefx_rc_t\n+efx_phy_module_get_info(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tuint8_t dev_addr,\n+\t__in\t\t\t\tuint8_t offset,\n+\t__in\t\t\t\tuint8_t len,\n+\t__out_bcount(len)\t\tuint8_t *data);\n+\n+\n+#define\tEFX_FEATURE_IPV6\t\t0x00000001\n+#define\tEFX_FEATURE_LFSR_HASH_INSERT\t0x00000002\n+#define\tEFX_FEATURE_LINK_EVENTS\t\t0x00000004\n+#define\tEFX_FEATURE_PERIODIC_MAC_STATS\t0x00000008\n+#define\tEFX_FEATURE_MCDI\t\t0x00000020\n+#define\tEFX_FEATURE_LOOKAHEAD_SPLIT\t0x00000040\n+#define\tEFX_FEATURE_MAC_HEADER_FILTERS\t0x00000080\n+#define\tEFX_FEATURE_TURBO\t\t0x00000100\n+#define\tEFX_FEATURE_MCDI_DMA\t\t0x00000200\n+#define\tEFX_FEATURE_TX_SRC_FILTERS\t0x00000400\n+#define\tEFX_FEATURE_PIO_BUFFERS\t\t0x00000800\n+#define\tEFX_FEATURE_FW_ASSISTED_TSO\t0x00001000\n+#define\tEFX_FEATURE_FW_ASSISTED_TSO_V2\t0x00002000\n+#define\tEFX_FEATURE_PACKED_STREAM\t0x00004000\n+\n+typedef struct efx_nic_cfg_s {\n+\tuint32_t\t\tenc_board_type;\n+\tuint32_t\t\tenc_phy_type;\n+#if EFSYS_OPT_NAMES\n+\tchar\t\t\tenc_phy_name[21];\n+#endif\n+\tchar\t\t\tenc_phy_revision[21];\n+\tefx_mon_type_t\t\tenc_mon_type;\n+\tunsigned int\t\tenc_features;\n+\tuint8_t\t\t\tenc_mac_addr[6];\n+\tuint8_t\t\t\tenc_port;\t/* PHY port number */\n+\tuint32_t\t\tenc_intr_vec_base;\n+\tuint32_t\t\tenc_intr_limit;\n+\tuint32_t\t\tenc_evq_limit;\n+\tuint32_t\t\tenc_txq_limit;\n+\tuint32_t\t\tenc_rxq_limit;\n+\tuint32_t\t\tenc_txq_max_ndescs;\n+\tuint32_t\t\tenc_buftbl_limit;\n+\tuint32_t\t\tenc_piobuf_limit;\n+\tuint32_t\t\tenc_piobuf_size;\n+\tuint32_t\t\tenc_piobuf_min_alloc_size;\n+\tuint32_t\t\tenc_evq_timer_quantum_ns;\n+\tuint32_t\t\tenc_evq_timer_max_us;\n+\tuint32_t\t\tenc_clk_mult;\n+\tuint32_t\t\tenc_rx_prefix_size;\n+\tuint32_t\t\tenc_rx_buf_align_start;\n+\tuint32_t\t\tenc_rx_buf_align_end;\n+\tboolean_t\t\tenc_bug26807_workaround;\n+\tboolean_t\t\tenc_bug35388_workaround;\n+\tboolean_t\t\tenc_bug41750_workaround;\n+\tboolean_t\t\tenc_bug61265_workaround;\n+\tboolean_t\t\tenc_rx_batching_enabled;\n+\t/* Maximum number of descriptors completed in an rx event. */\n+\tuint32_t\t\tenc_rx_batch_max;\n+\t/* Number of rx descriptors the hardware requires for a push. */\n+\tuint32_t\t\tenc_rx_push_align;\n+\t/*\n+\t * Maximum number of bytes into the packet the TCP header can start for\n+\t * the hardware to apply TSO packet edits.\n+\t */\n+\tuint32_t\t\tenc_tx_tso_tcp_header_offset_limit;\n+\tboolean_t\t\tenc_fw_assisted_tso_enabled;\n+\tboolean_t\t\tenc_fw_assisted_tso_v2_enabled;\n+\t/* Number of TSO contexts on the NIC (FATSOv2) */\n+\tuint32_t\t\tenc_fw_assisted_tso_v2_n_contexts;\n+\tboolean_t\t\tenc_hw_tx_insert_vlan_enabled;\n+\t/* Number of PFs on the NIC */\n+\tuint32_t\t\tenc_hw_pf_count;\n+\t/* Datapath firmware vadapter/vport/vswitch support */\n+\tboolean_t\t\tenc_datapath_cap_evb;\n+\tboolean_t\t\tenc_rx_disable_scatter_supported;\n+\tboolean_t\t\tenc_allow_set_mac_with_installed_filters;\n+\tboolean_t\t\tenc_enhanced_set_mac_supported;\n+\tboolean_t\t\tenc_init_evq_v2_supported;\n+\tboolean_t\t\tenc_rx_packed_stream_supported;\n+\tboolean_t\t\tenc_rx_var_packed_stream_supported;\n+\tboolean_t\t\tenc_pm_and_rxdp_counters;\n+\tboolean_t\t\tenc_mac_stats_40g_tx_size_bins;\n+\t/* External port identifier */\n+\tuint8_t\t\t\tenc_external_port;\n+\tuint32_t\t\tenc_mcdi_max_payload_length;\n+\t/* VPD may be per-PF or global */\n+\tboolean_t\t\tenc_vpd_is_global;\n+\t/* Minimum unidirectional bandwidth in Mb/s to max out all ports */\n+\tuint32_t\t\tenc_required_pcie_bandwidth_mbps;\n+\tuint32_t\t\tenc_max_pcie_link_gen;\n+\t/* Firmware verifies integrity of NVRAM updates */\n+\tuint32_t\t\tenc_fw_verified_nvram_update_required;\n+} efx_nic_cfg_t;\n+\n+#define\tEFX_PCI_FUNCTION_IS_PF(_encp)\t((_encp)->enc_vf == 0xffff)\n+#define\tEFX_PCI_FUNCTION_IS_VF(_encp)\t((_encp)->enc_vf != 0xffff)\n+\n+#define\tEFX_PCI_FUNCTION(_encp)\t\\\n+\t(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)\n+\n+#define\tEFX_PCI_VF_PARENT(_encp)\t((_encp)->enc_pf)\n+\n+extern\t\t\tconst efx_nic_cfg_t *\n+efx_nic_cfg_get(\n+\t__in\t\tefx_nic_t *enp);\n+\n+/* Driver resource limits (minimum required/maximum usable). */\n+typedef struct efx_drv_limits_s {\n+\tuint32_t\tedl_min_evq_count;\n+\tuint32_t\tedl_max_evq_count;\n+\n+\tuint32_t\tedl_min_rxq_count;\n+\tuint32_t\tedl_max_rxq_count;\n+\n+\tuint32_t\tedl_min_txq_count;\n+\tuint32_t\tedl_max_txq_count;\n+\n+\t/* PIO blocks (sub-allocated from piobuf) */\n+\tuint32_t\tedl_min_pio_alloc_size;\n+\tuint32_t\tedl_max_pio_alloc_count;\n+} efx_drv_limits_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_set_drv_limits(\n+\t__inout\t\tefx_nic_t *enp,\n+\t__in\t\tefx_drv_limits_t *edlp);\n+\n+typedef enum efx_nic_region_e {\n+\tEFX_REGION_VI,\t\t\t/* Memory BAR UC mapping */\n+\tEFX_REGION_PIO_WRITE_VI,\t/* Memory BAR WC mapping */\n+} efx_nic_region_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_get_bar_region(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_nic_region_t region,\n+\t__out\t\tuint32_t *offsetp,\n+\t__out\t\tsize_t *sizep);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_get_vi_pool(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tuint32_t *evq_countp,\n+\t__out\t\tuint32_t *rxq_countp,\n+\t__out\t\tuint32_t *txq_countp);\n+\n+\n+/* NVRAM */\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_sram_buf_tbl_set(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tsize_t n);\n+\n+extern\t\tvoid\n+efx_sram_buf_tbl_clear(\n+\t__in\tefx_nic_t *enp,\n+\t__in\tuint32_t id,\n+\t__in\tsize_t n);\n+\n+#define\tEFX_BUF_TBL_SIZE\t0x20000\n+\n+#define\tEFX_BUF_SIZE\t\t4096\n+\n+/* EV */\n+\n+typedef struct efx_evq_s\tefx_evq_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_ev_init(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t\tvoid\n+efx_ev_fini(\n+\t__in\t\tefx_nic_t *enp);\n+\n+#define\tEFX_EVQ_MAXNEVS\t\t32768\n+#define\tEFX_EVQ_MINNEVS\t\t512\n+\n+#define\tEFX_EVQ_SIZE(_nevs)\t((_nevs) * sizeof (efx_qword_t))\n+#define\tEFX_EVQ_NBUFS(_nevs)\t(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)\n+\n+#define\tEFX_EVQ_FLAGS_TYPE_MASK\t\t(0x3)\n+#define\tEFX_EVQ_FLAGS_TYPE_AUTO\t\t(0x0)\n+#define\tEFX_EVQ_FLAGS_TYPE_THROUGHPUT\t(0x1)\n+#define\tEFX_EVQ_FLAGS_TYPE_LOW_LATENCY\t(0x2)\n+\n+#define\tEFX_EVQ_FLAGS_NOTIFY_MASK\t(0xC)\n+#define\tEFX_EVQ_FLAGS_NOTIFY_INTERRUPT\t(0x0)\t/* Interrupting (default) */\n+#define\tEFX_EVQ_FLAGS_NOTIFY_DISABLED\t(0x4)\t/* Non-interrupting */\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_ev_qcreate(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int index,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tsize_t n,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tuint32_t us,\n+\t__in\t\tuint32_t flags,\n+\t__deref_out\tefx_evq_t **eepp);\n+\n+extern\t\tvoid\n+efx_ev_qpost(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tuint16_t data);\n+\n+typedef __checkReturn\tboolean_t\n+(*efx_initialized_ev_t)(\n+\t__in_opt\tvoid *arg);\n+\n+#define\tEFX_PKT_UNICAST\t\t0x0004\n+#define\tEFX_PKT_START\t\t0x0008\n+\n+#define\tEFX_PKT_VLAN_TAGGED\t0x0010\n+#define\tEFX_CKSUM_TCPUDP\t0x0020\n+#define\tEFX_CKSUM_IPV4\t\t0x0040\n+#define\tEFX_PKT_CONT\t\t0x0080\n+\n+#define\tEFX_CHECK_VLAN\t\t0x0100\n+#define\tEFX_PKT_TCP\t\t0x0200\n+#define\tEFX_PKT_UDP\t\t0x0400\n+#define\tEFX_PKT_IPV4\t\t0x0800\n+\n+#define\tEFX_PKT_IPV6\t\t0x1000\n+#define\tEFX_PKT_PREFIX_LEN\t0x2000\n+#define\tEFX_ADDR_MISMATCH\t0x4000\n+#define\tEFX_DISCARD\t\t0x8000\n+\n+/*\n+ * The following flags are used only for packed stream\n+ * mode. The values for the flags are reused to fit into 16 bit,\n+ * since EFX_PKT_START and EFX_PKT_CONT are never used in\n+ * packed stream mode\n+ */\n+#define\tEFX_PKT_PACKED_STREAM_NEW_BUFFER\tEFX_PKT_START\n+#define\tEFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE\tEFX_PKT_CONT\n+\n+\n+#define\tEFX_EV_RX_NLABELS\t32\n+#define\tEFX_EV_TX_NLABELS\t32\n+\n+typedef\t__checkReturn\tboolean_t\n+(*efx_rx_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint32_t label,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tuint32_t size,\n+\t__in\t\tuint16_t flags);\n+\n+typedef\t__checkReturn\tboolean_t\n+(*efx_tx_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint32_t label,\n+\t__in\t\tuint32_t id);\n+\n+#define\tEFX_EXCEPTION_RX_RECOVERY\t0x00000001\n+#define\tEFX_EXCEPTION_RX_DSC_ERROR\t0x00000002\n+#define\tEFX_EXCEPTION_TX_DSC_ERROR\t0x00000003\n+#define\tEFX_EXCEPTION_UNKNOWN_SENSOREVT\t0x00000004\n+#define\tEFX_EXCEPTION_FWALERT_SRAM\t0x00000005\n+#define\tEFX_EXCEPTION_UNKNOWN_FWALERT\t0x00000006\n+#define\tEFX_EXCEPTION_RX_ERROR\t\t0x00000007\n+#define\tEFX_EXCEPTION_TX_ERROR\t\t0x00000008\n+#define\tEFX_EXCEPTION_EV_ERROR\t\t0x00000009\n+\n+typedef\t__checkReturn\tboolean_t\n+(*efx_exception_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint32_t label,\n+\t__in\t\tuint32_t data);\n+\n+typedef\t__checkReturn\tboolean_t\n+(*efx_rxq_flush_done_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint32_t rxq_index);\n+\n+typedef\t__checkReturn\tboolean_t\n+(*efx_rxq_flush_failed_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint32_t rxq_index);\n+\n+typedef\t__checkReturn\tboolean_t\n+(*efx_txq_flush_done_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint32_t txq_index);\n+\n+typedef\t__checkReturn\tboolean_t\n+(*efx_software_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint16_t magic);\n+\n+typedef\t__checkReturn\tboolean_t\n+(*efx_sram_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint32_t code);\n+\n+#define\tEFX_SRAM_CLEAR\t\t0\n+#define\tEFX_SRAM_UPDATE\t\t1\n+#define\tEFX_SRAM_ILLEGAL_CLEAR\t2\n+\n+typedef\t__checkReturn\tboolean_t\n+(*efx_wake_up_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint32_t label);\n+\n+typedef\t__checkReturn\tboolean_t\n+(*efx_timer_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint32_t label);\n+\n+typedef __checkReturn\tboolean_t\n+(*efx_link_change_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tefx_link_mode_t\tlink_mode);\n+\n+typedef struct efx_ev_callbacks_s {\n+\tefx_initialized_ev_t\t\teec_initialized;\n+\tefx_rx_ev_t\t\t\teec_rx;\n+\tefx_tx_ev_t\t\t\teec_tx;\n+\tefx_exception_ev_t\t\teec_exception;\n+\tefx_rxq_flush_done_ev_t\t\teec_rxq_flush_done;\n+\tefx_rxq_flush_failed_ev_t\teec_rxq_flush_failed;\n+\tefx_txq_flush_done_ev_t\t\teec_txq_flush_done;\n+\tefx_software_ev_t\t\teec_software;\n+\tefx_sram_ev_t\t\t\teec_sram;\n+\tefx_wake_up_ev_t\t\teec_wake_up;\n+\tefx_timer_ev_t\t\t\teec_timer;\n+\tefx_link_change_ev_t\t\teec_link_change;\n+} efx_ev_callbacks_t;\n+\n+extern\t__checkReturn\tboolean_t\n+efx_ev_qpending(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tunsigned int count);\n+\n+extern\t\t\tvoid\n+efx_ev_qpoll(\n+\t__in\t\tefx_evq_t *eep,\n+\t__inout\t\tunsigned int *countp,\n+\t__in\t\tconst efx_ev_callbacks_t *eecp,\n+\t__in_opt\tvoid *arg);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_ev_usecs_to_ticks(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int usecs,\n+\t__out\t\tunsigned int *ticksp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_ev_qmoderate(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tunsigned int us);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_ev_qprime(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tunsigned int count);\n+\n+extern\t\tvoid\n+efx_ev_qdestroy(\n+\t__in\tefx_evq_t *eep);\n+\n+/* RX */\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_rx_init(\n+\t__inout\t\tefx_nic_t *enp);\n+\n+extern\t\tvoid\n+efx_rx_fini(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_psuedo_hdr_pkt_length_get(\n+\t__in\t\tefx_rxq_t *erp,\n+\t__in\t\tuint8_t *buffer,\n+\t__out\t\tuint16_t *pkt_lengthp);\n+\n+#define\tEFX_RXQ_MAXNDESCS\t\t4096\n+#define\tEFX_RXQ_MINNDESCS\t\t512\n+\n+#define\tEFX_RXQ_SIZE(_ndescs)\t\t((_ndescs) * sizeof (efx_qword_t))\n+#define\tEFX_RXQ_NBUFS(_ndescs)\t\t(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)\n+#define\tEFX_RXQ_LIMIT(_ndescs)\t\t((_ndescs) - 16)\n+#define\tEFX_RXQ_DC_NDESCS(_dcsize)\t(8 << _dcsize)\n+\n+typedef enum efx_rxq_type_e {\n+\tEFX_RXQ_TYPE_DEFAULT,\n+\tEFX_RXQ_TYPE_SCATTER,\n+\tEFX_RXQ_TYPE_PACKED_STREAM_1M,\n+\tEFX_RXQ_TYPE_PACKED_STREAM_512K,\n+\tEFX_RXQ_TYPE_PACKED_STREAM_256K,\n+\tEFX_RXQ_TYPE_PACKED_STREAM_128K,\n+\tEFX_RXQ_TYPE_PACKED_STREAM_64K,\n+\tEFX_RXQ_NTYPES\n+} efx_rxq_type_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_rx_qcreate(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int index,\n+\t__in\t\tunsigned int label,\n+\t__in\t\tefx_rxq_type_t type,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tsize_t n,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tefx_evq_t *eep,\n+\t__deref_out\tefx_rxq_t **erpp);\n+\n+typedef struct efx_buffer_s {\n+\tefsys_dma_addr_t\teb_addr;\n+\tsize_t\t\t\teb_size;\n+\tboolean_t\t\teb_eop;\n+} efx_buffer_t;\n+\n+typedef struct efx_desc_s {\n+\tefx_qword_t ed_eq;\n+} efx_desc_t;\n+\n+extern\t\t\tvoid\n+efx_rx_qpost(\n+\t__in\t\tefx_rxq_t *erp,\n+\t__in_ecount(n)\tefsys_dma_addr_t *addrp,\n+\t__in\t\tsize_t size,\n+\t__in\t\tunsigned int n,\n+\t__in\t\tunsigned int completed,\n+\t__in\t\tunsigned int added);\n+\n+extern\t\tvoid\n+efx_rx_qpush(\n+\t__in\tefx_rxq_t *erp,\n+\t__in\tunsigned int added,\n+\t__inout\tunsigned int *pushedp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_rx_qflush(\n+\t__in\tefx_rxq_t *erp);\n+\n+extern\t\tvoid\n+efx_rx_qenable(\n+\t__in\tefx_rxq_t *erp);\n+\n+extern\t\tvoid\n+efx_rx_qdestroy(\n+\t__in\tefx_rxq_t *erp);\n+\n+/* TX */\n+\n+typedef struct efx_txq_s\tefx_txq_t;\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_tx_init(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t\tvoid\n+efx_tx_fini(\n+\t__in\tefx_nic_t *enp);\n+\n+#define\tEFX_TXQ_MINNDESCS\t\t512\n+\n+#define\tEFX_TXQ_SIZE(_ndescs)\t\t((_ndescs) * sizeof (efx_qword_t))\n+#define\tEFX_TXQ_NBUFS(_ndescs)\t\t(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)\n+#define\tEFX_TXQ_LIMIT(_ndescs)\t\t((_ndescs) - 16)\n+#define\tEFX_TXQ_DC_NDESCS(_dcsize)\t(8 << _dcsize)\n+\n+#define\tEFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */\n+\n+#define\tEFX_TXQ_CKSUM_IPV4\t0x0001\n+#define\tEFX_TXQ_CKSUM_TCPUDP\t0x0002\n+#define\tEFX_TXQ_FATSOV2\t\t0x0004\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_tx_qcreate(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int index,\n+\t__in\t\tunsigned int label,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tsize_t n,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tuint16_t flags,\n+\t__in\t\tefx_evq_t *eep,\n+\t__deref_out\tefx_txq_t **etpp,\n+\t__out\t\tunsigned int *addedp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_tx_qpost(\n+\t__in\t\tefx_txq_t *etp,\n+\t__in_ecount(n)\tefx_buffer_t *eb,\n+\t__in\t\tunsigned int n,\n+\t__in\t\tunsigned int completed,\n+\t__inout\t\tunsigned int *addedp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_tx_qpace(\n+\t__in\t\tefx_txq_t *etp,\n+\t__in\t\tunsigned int ns);\n+\n+extern\t\t\tvoid\n+efx_tx_qpush(\n+\t__in\t\tefx_txq_t *etp,\n+\t__in\t\tunsigned int added,\n+\t__in\t\tunsigned int pushed);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_tx_qflush(\n+\t__in\t\tefx_txq_t *etp);\n+\n+extern\t\t\tvoid\n+efx_tx_qenable(\n+\t__in\t\tefx_txq_t *etp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_tx_qpio_enable(\n+\t__in\t\tefx_txq_t *etp);\n+\n+extern\t\t\tvoid\n+efx_tx_qpio_disable(\n+\t__in\t\tefx_txq_t *etp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_tx_qpio_write(\n+\t__in\t\t\tefx_txq_t *etp,\n+\t__in_ecount(buf_length)\tuint8_t *buffer,\n+\t__in\t\t\tsize_t buf_length,\n+\t__in\t\t\tsize_t pio_buf_offset);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_tx_qpio_post(\n+\t__in\t\t\tefx_txq_t *etp,\n+\t__in\t\t\tsize_t pkt_length,\n+\t__in\t\t\tunsigned int completed,\n+\t__inout\t\t\tunsigned int *addedp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_tx_qdesc_post(\n+\t__in\t\tefx_txq_t *etp,\n+\t__in_ecount(n)\tefx_desc_t *ed,\n+\t__in\t\tunsigned int n,\n+\t__in\t\tunsigned int completed,\n+\t__inout\t\tunsigned int *addedp);\n+\n+extern\tvoid\n+efx_tx_qdesc_dma_create(\n+\t__in\tefx_txq_t *etp,\n+\t__in\tefsys_dma_addr_t addr,\n+\t__in\tsize_t size,\n+\t__in\tboolean_t eop,\n+\t__out\tefx_desc_t *edp);\n+\n+extern\tvoid\n+efx_tx_qdesc_tso_create(\n+\t__in\tefx_txq_t *etp,\n+\t__in\tuint16_t ipv4_id,\n+\t__in\tuint32_t tcp_seq,\n+\t__in\tuint8_t  tcp_flags,\n+\t__out\tefx_desc_t *edp);\n+\n+/* Number of FATSOv2 option descriptors */\n+#define\tEFX_TX_FATSOV2_OPT_NDESCS\t\t2\n+\n+/* Maximum number of DMA segments per TSO packet (not superframe) */\n+#define\tEFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX\t24\n+\n+extern\tvoid\n+efx_tx_qdesc_tso2_create(\n+\t__in\t\t\tefx_txq_t *etp,\n+\t__in\t\t\tuint16_t ipv4_id,\n+\t__in\t\t\tuint32_t tcp_seq,\n+\t__in\t\t\tuint16_t tcp_mss,\n+\t__out_ecount(count)\tefx_desc_t *edp,\n+\t__in\t\t\tint count);\n+\n+extern\tvoid\n+efx_tx_qdesc_vlantci_create(\n+\t__in\tefx_txq_t *etp,\n+\t__in\tuint16_t tci,\n+\t__out\tefx_desc_t *edp);\n+\n+extern\t\tvoid\n+efx_tx_qdestroy(\n+\t__in\tefx_txq_t *etp);\n+\n+\n+/* FILTER */\n+\n+/* HASH */\n+\n+extern\t__checkReturn\t\tuint32_t\n+efx_hash_dwords(\n+\t__in_ecount(count)\tuint32_t const *input,\n+\t__in\t\t\tsize_t count,\n+\t__in\t\t\tuint32_t init);\n+\n+extern\t__checkReturn\t\tuint32_t\n+efx_hash_bytes(\n+\t__in_ecount(length)\tuint8_t const *input,\n+\t__in\t\t\tsize_t length,\n+\t__in\t\t\tuint32_t init);\n+\n+\n+\n+#ifdef\t__cplusplus\n+}\n+#endif\n+\n+#endif\t/* _SYS_EFX_H */\ndiff --git a/drivers/net/sfc/efx/base/efx_check.h b/drivers/net/sfc/efx/base/efx_check.h\nnew file mode 100644\nindex 0000000..78cfd8e\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_check.h\n@@ -0,0 +1,171 @@\n+/*\n+ * Copyright (c) 2012-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#ifndef _SYS_EFX_CHECK_H\n+#define\t_SYS_EFX_CHECK_H\n+\n+#include \"efsys.h\"\n+\n+/*\n+ * Check that the efsys.h header in client code has a valid combination of\n+ * EFSYS_OPT_xxx options.\n+ *\n+ * NOTE: Keep checks for obsolete options here to ensure that they are removed\n+ * from client code (and do not reappear in merges from other branches).\n+ */\n+\n+#ifdef EFSYS_OPT_FALCON\n+# error \"FALCON is obsolete and is not supported.\"\n+#endif\n+\n+#if EFSYS_OPT_CHECK_REG\n+/* Verify chip implements accessed registers */\n+#  error \"CHECK_REG requires SIENA or HUNTINGTON or MEDFORD\"\n+#endif /* EFSYS_OPT_CHECK_REG */\n+\n+#if EFSYS_OPT_DECODE_INTR_FATAL\n+/* Decode fatal errors */\n+#  error \"INTR_FATAL requires SIENA\"\n+#endif /* EFSYS_OPT_DECODE_INTR_FATAL */\n+\n+#ifdef EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE\n+# error \"FALCON_NIC_CFG_OVERRIDE is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_MAC_FALCON_GMAC\n+# error \"MAC_FALCON_GMAC is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_MAC_FALCON_XMAC\n+# error \"MAC_FALCON_XMAC is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_MON_LM87\n+# error \"MON_LM87 is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_MON_MAX6647\n+# error \"MON_MAX6647 is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_MON_NULL\n+# error \"MON_NULL is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_MON_SIENA\n+#  error \"MON_SIENA is obsolete (replaced by MON_MCDI).\"\n+#endif\n+\n+#ifdef EFSYS_OPT_MON_HUNTINGTON\n+#  error \"MON_HUNTINGTON is obsolete (replaced by MON_MCDI).\"\n+#endif\n+\n+#if EFSYS_OPT_NAMES\n+/* Support printable names for statistics */\n+# if !(EFSYS_OPT_LOOPBACK || EFSYS_OPT_MAC_STATS || EFSYS_OPT_MCDI || \\\n+\tEFSYS_MON_STATS || EFSYS_OPT_PHY_STATS || EFSYS_OPT_QSTATS)\n+#  error \"NAMES requires LOOPBACK or xxxSTATS or MCDI\"\n+# endif\n+#endif /* EFSYS_OPT_NAMES */\n+\n+#ifdef EFSYS_OPT_NVRAM_FALCON_BOOTROM\n+# error \"NVRAM_FALCON_BOOTROM is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_NVRAM_SFT9001\n+# error \"NVRAM_SFT9001 is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_NVRAM_SFX7101\n+# error \"NVRAM_SFX7101 is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_PCIE_TUNE\n+# error \"PCIE_TUNE is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_PHY_BIST\n+# error \"PHY_BIST is obsolete (replaced by BIST).\"\n+#endif\n+\n+#ifdef EFSYS_OPT_PHY_NULL\n+# error \"PHY_NULL is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_PHY_PM8358\n+# error \"PHY_PM8358 is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_PHY_PROPS\n+# error \"PHY_PROPS is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_PHY_QT2022C2\n+# error \"PHY_QT2022C2 is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_PHY_QT2025C\n+# error \"PHY_QT2025C is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_PHY_SFT9001\n+# error \"PHY_SFT9001 is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_PHY_SFX7101\n+# error \"PHY_SFX7101 is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_PHY_TXC43128\n+# error \"PHY_TXC43128 is obsolete and is not supported.\"\n+#endif\n+\n+#ifdef EFSYS_OPT_RX_HDR_SPLIT\n+# error \"RX_HDR_SPLIT is obsolete and is not supported\"\n+#endif\n+\n+#ifdef EFSYS_OPT_STAT_NAME\n+# error \"STAT_NAME is obsolete (replaced by NAMES).\"\n+#endif\n+\n+#ifdef EFSYS_OPT_WOL\n+# error \"WOL is obsolete and is not supported\"\n+#endif /* EFSYS_OPT_WOL */\n+\n+#ifdef EFSYS_OPT_MCAST_FILTER_LIST\n+#  error \"MCAST_FILTER_LIST is obsolete and is not supported\"\n+#endif\n+\n+#if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC\n+/* Support adapters with missing static config (for factory use only) */\n+#  error \"ALLOW_UNCONFIGURED_NIC requires MEDFORD\"\n+#endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */\n+\n+#endif /* _SYS_EFX_CHECK_H */\ndiff --git a/drivers/net/sfc/efx/base/efx_crc32.c b/drivers/net/sfc/efx/base/efx_crc32.c\nnew file mode 100644\nindex 0000000..27e2708\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_crc32.c\n@@ -0,0 +1,122 @@\n+/*\n+ * Copyright (c) 2013-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+/*\n+ * Precomputed table for computing IEEE 802.3 CRC32\n+ * with polynomial 0x04c11db7 (bit-reversed 0xedb88320)\n+ */\n+\n+static const uint32_t efx_crc32_table[256] = {\n+    0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,\n+    0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,\n+    0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,\n+    0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,\n+    0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,\n+    0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,\n+    0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,\n+    0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,\n+    0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,\n+    0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,\n+    0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,\n+    0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,\n+    0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,\n+    0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,\n+    0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,\n+    0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,\n+    0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,\n+    0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,\n+    0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,\n+    0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,\n+    0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,\n+    0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,\n+    0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,\n+    0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,\n+    0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,\n+    0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,\n+    0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,\n+    0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,\n+    0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,\n+    0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,\n+    0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,\n+    0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,\n+    0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,\n+    0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,\n+    0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,\n+    0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,\n+    0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,\n+    0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,\n+    0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,\n+    0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,\n+    0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,\n+    0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,\n+    0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,\n+    0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,\n+    0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,\n+    0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,\n+    0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,\n+    0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,\n+    0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,\n+    0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,\n+    0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,\n+    0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,\n+    0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,\n+    0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,\n+    0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,\n+    0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,\n+    0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,\n+    0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,\n+    0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,\n+    0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,\n+    0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,\n+    0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,\n+    0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,\n+    0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d\n+};\n+\n+/* Calculate the IEEE 802.3 CRC32 of a MAC addr */\n+\t__checkReturn\t\tuint32_t\n+efx_crc32_calculate(\n+\t__in\t\t\tuint32_t crc_init,\n+\t__in_ecount(length)\tuint8_t const *input,\n+\t__in\t\t\tint length)\n+{\n+\tint index;\n+\tuint32_t crc = crc_init;\n+\n+\tfor (index = 0; index < length; index++) {\n+\t\tuint32_t data = *(input++);\n+\t\tcrc = (crc >> 8) ^ efx_crc32_table[(crc ^ data) & 0xff];\n+\t}\n+\n+\treturn (crc);\n+}\ndiff --git a/drivers/net/sfc/efx/base/efx_ev.c b/drivers/net/sfc/efx/base/efx_ev.c\nnew file mode 100644\nindex 0000000..2bd365f\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_ev.c\n@@ -0,0 +1,432 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+#define\tEFX_EV_QSTAT_INCR(_eep, _stat)\n+\n+#define\tEFX_EV_PRESENT(_qword)\t\t\t\t\t\t\\\n+\t(EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&\t\\\n+\tEFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)\n+\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_ev_init(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_ev_ops_t *eevop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);\n+\n+\tif (enp->en_mod_flags & EFX_MOD_EV) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tswitch (enp->en_family) {\n+\n+\tdefault:\n+\t\tEFSYS_ASSERT(0);\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\n+\tEFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);\n+\n+\tif ((rc = eevop->eevo_init(enp)) != 0)\n+\t\tgoto fail2;\n+\n+\tenp->en_eevop = eevop;\n+\tenp->en_mod_flags |= EFX_MOD_EV;\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\tenp->en_eevop = NULL;\n+\tenp->en_mod_flags &= ~EFX_MOD_EV;\n+\treturn (rc);\n+}\n+\n+\t\tvoid\n+efx_ev_fini(\n+\t__in\tefx_nic_t *enp)\n+{\n+\tconst efx_ev_ops_t *eevop = enp->en_eevop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));\n+\tEFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);\n+\n+\teevop->eevo_fini(enp);\n+\n+\tenp->en_eevop = NULL;\n+\tenp->en_mod_flags &= ~EFX_MOD_EV;\n+}\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_ev_qcreate(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int index,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tsize_t n,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tuint32_t us,\n+\t__in\t\tuint32_t flags,\n+\t__deref_out\tefx_evq_t **eepp)\n+{\n+\tconst efx_ev_ops_t *eevop = enp->en_eevop;\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tefx_evq_t *eep;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);\n+\n+\tEFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);\n+\n+\tswitch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {\n+\tcase EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:\n+\t\tbreak;\n+\tcase EFX_EVQ_FLAGS_NOTIFY_DISABLED:\n+\t\tif (us != 0) {\n+\t\t\trc = EINVAL;\n+\t\t\tgoto fail1;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\trc = EINVAL;\n+\t\tgoto fail2;\n+\t}\n+\n+\t/* Allocate an EVQ object */\n+\tEFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);\n+\tif (eep == NULL) {\n+\t\trc = ENOMEM;\n+\t\tgoto fail3;\n+\t}\n+\n+\teep->ee_magic = EFX_EVQ_MAGIC;\n+\teep->ee_enp = enp;\n+\teep->ee_index = index;\n+\teep->ee_mask = n - 1;\n+\teep->ee_flags = flags;\n+\teep->ee_esmp = esmp;\n+\n+\t/*\n+\t * Set outputs before the queue is created because interrupts may be\n+\t * raised for events immediately after the queue is created, before the\n+\t * function call below returns. See bug58606.\n+\t *\n+\t * The eepp pointer passed in by the client must therefore point to data\n+\t * shared with the client's event processing context.\n+\t */\n+\tenp->en_ev_qcount++;\n+\t*eepp = eep;\n+\n+\tif ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,\n+\t    eep)) != 0)\n+\t\tgoto fail4;\n+\n+\treturn (0);\n+\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+\n+\t*eepp = NULL;\n+\tenp->en_ev_qcount--;\n+\tEFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t\tvoid\n+efx_ev_qdestroy(\n+\t__in\tefx_evq_t *eep)\n+{\n+\tefx_nic_t *enp = eep->ee_enp;\n+\tconst efx_ev_ops_t *eevop = enp->en_eevop;\n+\n+\tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n+\n+\tEFSYS_ASSERT(enp->en_ev_qcount != 0);\n+\t--enp->en_ev_qcount;\n+\n+\teevop->eevo_qdestroy(eep);\n+\n+\t/* Free the EVQ object */\n+\tEFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_ev_qprime(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tunsigned int count)\n+{\n+\tefx_nic_t *enp = eep->ee_enp;\n+\tconst efx_ev_ops_t *eevop = enp->en_eevop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n+\n+\tif (!(enp->en_mod_flags & EFX_MOD_INTR)) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif ((rc = eevop->eevo_qprime(eep, count)) != 0)\n+\t\tgoto fail2;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tboolean_t\n+efx_ev_qpending(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tunsigned int count)\n+{\n+\tsize_t offset;\n+\tefx_qword_t qword;\n+\n+\tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n+\n+\toffset = (count & eep->ee_mask) * sizeof (efx_qword_t);\n+\tEFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);\n+\n+\treturn (EFX_EV_PRESENT(qword));\n+}\n+\n+#define\tEFX_EV_BATCH\t8\n+\n+\t\t\tvoid\n+efx_ev_qpoll(\n+\t__in\t\tefx_evq_t *eep,\n+\t__inout\t\tunsigned int *countp,\n+\t__in\t\tconst efx_ev_callbacks_t *eecp,\n+\t__in_opt\tvoid *arg)\n+{\n+\tefx_qword_t ev[EFX_EV_BATCH];\n+\tunsigned int batch;\n+\tunsigned int total;\n+\tunsigned int count;\n+\tunsigned int index;\n+\tsize_t offset;\n+\n+\t/* Ensure events codes match for EF10 (Huntington/Medford) and Siena */\n+\tEFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);\n+\tEFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);\n+\n+\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);\n+\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);\n+\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);\n+\tEFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==\n+\t    FSE_AZ_EV_CODE_DRV_GEN_EV);\n+\n+\tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n+\tEFSYS_ASSERT(countp != NULL);\n+\tEFSYS_ASSERT(eecp != NULL);\n+\n+\tcount = *countp;\n+\tdo {\n+\t\t/* Read up until the end of the batch period */\n+\t\tbatch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));\n+\t\toffset = (count & eep->ee_mask) * sizeof (efx_qword_t);\n+\t\tfor (total = 0; total < batch; ++total) {\n+\t\t\tEFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));\n+\n+\t\t\tif (!EFX_EV_PRESENT(ev[total]))\n+\t\t\t\tbreak;\n+\n+\t\t\tEFSYS_PROBE3(event, unsigned int, eep->ee_index,\n+\t\t\t    uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),\n+\t\t\t    uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));\n+\n+\t\t\toffset += sizeof (efx_qword_t);\n+\t\t}\n+\n+\t\t/* Process the batch of events */\n+\t\tfor (index = 0; index < total; ++index) {\n+\t\t\tboolean_t should_abort;\n+\t\t\tuint32_t code;\n+\n+\t\t\tEFX_EV_QSTAT_INCR(eep, EV_ALL);\n+\n+\t\t\tcode = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);\n+\t\t\tswitch (code) {\n+\t\t\tcase FSE_AZ_EV_CODE_RX_EV:\n+\t\t\t\tshould_abort = eep->ee_rx(eep,\n+\t\t\t\t    &(ev[index]), eecp, arg);\n+\t\t\t\tbreak;\n+\t\t\tcase FSE_AZ_EV_CODE_TX_EV:\n+\t\t\t\tshould_abort = eep->ee_tx(eep,\n+\t\t\t\t    &(ev[index]), eecp, arg);\n+\t\t\t\tbreak;\n+\t\t\tcase FSE_AZ_EV_CODE_DRIVER_EV:\n+\t\t\t\tshould_abort = eep->ee_driver(eep,\n+\t\t\t\t    &(ev[index]), eecp, arg);\n+\t\t\t\tbreak;\n+\t\t\tcase FSE_AZ_EV_CODE_DRV_GEN_EV:\n+\t\t\t\tshould_abort = eep->ee_drv_gen(eep,\n+\t\t\t\t    &(ev[index]), eecp, arg);\n+\t\t\t\tbreak;\n+\t\t\tcase FSE_AZ_EV_CODE_GLOBAL_EV:\n+\t\t\t\tif (eep->ee_global) {\n+\t\t\t\t\tshould_abort = eep->ee_global(eep,\n+\t\t\t\t\t    &(ev[index]), eecp, arg);\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\t/* else fallthrough */\n+\t\t\tdefault:\n+\t\t\t\tEFSYS_PROBE3(bad_event,\n+\t\t\t\t    unsigned int, eep->ee_index,\n+\t\t\t\t    uint32_t,\n+\t\t\t\t    EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),\n+\t\t\t\t    uint32_t,\n+\t\t\t\t    EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));\n+\n+\t\t\t\tEFSYS_ASSERT(eecp->eec_exception != NULL);\n+\t\t\t\t(void) eecp->eec_exception(arg,\n+\t\t\t\t\tEFX_EXCEPTION_EV_ERROR, code);\n+\t\t\t\tshould_abort = B_TRUE;\n+\t\t\t}\n+\t\t\tif (should_abort) {\n+\t\t\t\t/* Ignore subsequent events */\n+\t\t\t\ttotal = index + 1;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/*\n+\t\t * Now that the hardware has most likely moved onto dma'ing\n+\t\t * into the next cache line, clear the processed events. Take\n+\t\t * care to only clear out events that we've processed\n+\t\t */\n+\t\tEFX_SET_QWORD(ev[0]);\n+\t\toffset = (count & eep->ee_mask) * sizeof (efx_qword_t);\n+\t\tfor (index = 0; index < total; ++index) {\n+\t\t\tEFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));\n+\t\t\toffset += sizeof (efx_qword_t);\n+\t\t}\n+\n+\t\tcount += total;\n+\n+\t} while (total == batch);\n+\n+\t*countp = count;\n+}\n+\n+\t\t\tvoid\n+efx_ev_qpost(\n+\t__in\tefx_evq_t *eep,\n+\t__in\tuint16_t data)\n+{\n+\tefx_nic_t *enp = eep->ee_enp;\n+\tconst efx_ev_ops_t *eevop = enp->en_eevop;\n+\n+\tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n+\n+\tEFSYS_ASSERT(eevop != NULL &&\n+\t    eevop->eevo_qpost != NULL);\n+\n+\teevop->eevo_qpost(eep, data);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_ev_usecs_to_ticks(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int us,\n+\t__out\t\tunsigned int *ticksp)\n+{\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tunsigned int ticks;\n+\n+\t/* Convert microseconds to a timer tick count */\n+\tif (us == 0)\n+\t\tticks = 0;\n+\telse if (us * 1000 < encp->enc_evq_timer_quantum_ns)\n+\t\tticks = 1;\t/* Never round down to zero */\n+\telse\n+\t\tticks = us * 1000 / encp->enc_evq_timer_quantum_ns;\n+\n+\t*ticksp = ticks;\n+\treturn (0);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_ev_qmoderate(\n+\t__in\t\tefx_evq_t *eep,\n+\t__in\t\tunsigned int us)\n+{\n+\tefx_nic_t *enp = eep->ee_enp;\n+\tconst efx_ev_ops_t *eevop = enp->en_eevop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);\n+\n+\tif ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==\n+\t    EFX_EVQ_FLAGS_NOTIFY_DISABLED) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif ((rc = eevop->eevo_qmoderate(eep, us)) != 0)\n+\t\tgoto fail2;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\ndiff --git a/drivers/net/sfc/efx/base/efx_hash.c b/drivers/net/sfc/efx/base/efx_hash.c\nnew file mode 100644\nindex 0000000..3cc0d20\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_hash.c\n@@ -0,0 +1,328 @@\n+/*\n+ * Copyright 2006 Bob Jenkins\n+ *\n+ * Derived from public domain source, see\n+ *     <http://burtleburtle.net/bob/c/lookup3.c>:\n+ *\n+ * \"lookup3.c, by Bob Jenkins, May 2006, Public Domain.\n+ *\n+ *  These are functions for producing 32-bit hashes for hash table lookup...\n+ *  ...You can use this free for any purpose.  It's in the public domain.\n+ *  It has no warranty.\"\n+ *\n+ * Copyright (c) 2014-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+/* Hash initial value */\n+#define\tEFX_HASH_INITIAL_VALUE\t0xdeadbeef\n+\n+/*\n+ * Rotate a 32-bit value left\n+ *\n+ * Allow platform to provide an intrinsic or optimised routine and\n+ * fall-back to a simple shift based implementation.\n+ */\n+#if EFSYS_HAS_ROTL_DWORD\n+\n+#define\tEFX_HASH_ROTATE(_value, _shift)\t\t\t\t\t\\\n+\tEFSYS_ROTL_DWORD(_value, _shift)\n+\n+#else\n+\n+#define\tEFX_HASH_ROTATE(_value, _shift)\t\t\t\t\t\\\n+\t(((_value) << (_shift)) | ((_value) >> (32 - (_shift))))\n+\n+#endif\n+\n+/* Mix three 32-bit values reversibly */\n+#define\tEFX_HASH_MIX(_a, _b, _c)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_a -= _c;\t\t\t\t\t\t\\\n+\t\t_a ^= EFX_HASH_ROTATE(_c, 4);\t\t\t\t\\\n+\t\t_c += _b;\t\t\t\t\t\t\\\n+\t\t_b -= _a;\t\t\t\t\t\t\\\n+\t\t_b ^= EFX_HASH_ROTATE(_a, 6);\t\t\t\t\\\n+\t\t_a += _c;\t\t\t\t\t\t\\\n+\t\t_c -= _b;\t\t\t\t\t\t\\\n+\t\t_c ^= EFX_HASH_ROTATE(_b, 8);\t\t\t\t\\\n+\t\t_b += _a;\t\t\t\t\t\t\\\n+\t\t_a -= _c;\t\t\t\t\t\t\\\n+\t\t_a ^= EFX_HASH_ROTATE(_c, 16);\t\t\t\t\\\n+\t\t_c += _b;\t\t\t\t\t\t\\\n+\t\t_b -= _a;\t\t\t\t\t\t\\\n+\t\t_b ^= EFX_HASH_ROTATE(_a, 19);\t\t\t\t\\\n+\t\t_a += _c;\t\t\t\t\t\t\\\n+\t\t_c -= _b;\t\t\t\t\t\t\\\n+\t\t_c ^= EFX_HASH_ROTATE(_b, 4);\t\t\t\t\\\n+\t\t_b += _a;\t\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/* Final mixing of three 32-bit values into one (_c) */\n+#define\tEFX_HASH_FINALISE(_a, _b, _c)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_c ^= _b;\t\t\t\t\t\t\\\n+\t\t_c -= EFX_HASH_ROTATE(_b, 14);\t\t\t\t\\\n+\t\t_a ^= _c;\t\t\t\t\t\t\\\n+\t\t_a -= EFX_HASH_ROTATE(_c, 11);\t\t\t\t\\\n+\t\t_b ^= _a;\t\t\t\t\t\t\\\n+\t\t_b -= EFX_HASH_ROTATE(_a, 25);\t\t\t\t\\\n+\t\t_c ^= _b;\t\t\t\t\t\t\\\n+\t\t_c -= EFX_HASH_ROTATE(_b, 16);\t\t\t\t\\\n+\t\t_a ^= _c;\t\t\t\t\t\t\\\n+\t\t_a -= EFX_HASH_ROTATE(_c, 4);\t\t\t\t\\\n+\t\t_b ^= _a;\t\t\t\t\t\t\\\n+\t\t_b -= EFX_HASH_ROTATE(_a, 14);\t\t\t\t\\\n+\t\t_c ^= _b;\t\t\t\t\t\t\\\n+\t\t_c -= EFX_HASH_ROTATE(_b, 24);\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+\n+/* Produce a 32-bit hash from 32-bit aligned input */\n+\t__checkReturn\t\tuint32_t\n+efx_hash_dwords(\n+\t__in_ecount(count)\tuint32_t const *input,\n+\t__in\t\t\tsize_t count,\n+\t__in\t\t\tuint32_t init)\n+{\n+\tuint32_t a;\n+\tuint32_t b;\n+\tuint32_t c;\n+\n+\t/* Set up the initial internal state */\n+\ta = b = c = EFX_HASH_INITIAL_VALUE +\n+\t\t(((uint32_t)count) * sizeof (uint32_t)) + init;\n+\n+\t/* Handle all but the last three dwords of the input */\n+\twhile (count > 3) {\n+\t\ta += input[0];\n+\t\tb += input[1];\n+\t\tc += input[2];\n+\t\tEFX_HASH_MIX(a, b, c);\n+\n+\t\tcount -= 3;\n+\t\tinput += 3;\n+\t}\n+\n+\t/* Handle the left-overs */\n+\tswitch (count) {\n+\tcase 3:\n+\t\tc += input[2];\n+\t\t/* Fall-through */\n+\tcase 2:\n+\t\tb += input[1];\n+\t\t/* Fall-through */\n+\tcase 1:\n+\t\ta += input[0];\n+\t\tEFX_HASH_FINALISE(a, b, c);\n+\t\tbreak;\n+\n+\tcase 0:\n+\t\t/* Should only get here if count parameter was zero */\n+\t\tbreak;\n+\t}\n+\n+\treturn (c);\n+}\n+\n+#if EFSYS_IS_BIG_ENDIAN\n+\n+/* Produce a 32-bit hash from arbitrarily aligned input */\n+\t__checkReturn\t\tuint32_t\n+efx_hash_bytes(\n+\t__in_ecount(length)\tuint8_t const *input,\n+\t__in\t\t\tsize_t length,\n+\t__in\t\t\tuint32_t init)\n+{\n+\tuint32_t a;\n+\tuint32_t b;\n+\tuint32_t c;\n+\n+\t/* Set up the initial internal state */\n+\ta = b = c = EFX_HASH_INITIAL_VALUE + (uint32_t)length + init;\n+\n+\t/* Handle all but the last twelve bytes of the input */\n+\twhile (length > 12) {\n+\t\ta += ((uint32_t)input[0]) << 24;\n+\t\ta += ((uint32_t)input[1]) << 16;\n+\t\ta += ((uint32_t)input[2]) << 8;\n+\t\ta += ((uint32_t)input[3]);\n+\t\tb += ((uint32_t)input[4]) << 24;\n+\t\tb += ((uint32_t)input[5]) << 16;\n+\t\tb += ((uint32_t)input[6]) << 8;\n+\t\tb += ((uint32_t)input[7]);\n+\t\tc += ((uint32_t)input[8]) << 24;\n+\t\tc += ((uint32_t)input[9]) << 16;\n+\t\tc += ((uint32_t)input[10]) << 8;\n+\t\tc += ((uint32_t)input[11]);\n+\t\tEFX_HASH_MIX(a, b, c);\n+\t\tlength -= 12;\n+\t\tinput += 12;\n+\t}\n+\n+\t/* Handle the left-overs */\n+\tswitch (length) {\n+\tcase 12:\n+\t\tc += ((uint32_t)input[11]);\n+\t\t/* Fall-through */\n+\tcase 11:\n+\t\tc += ((uint32_t)input[10]) << 8;\n+\t\t/* Fall-through */\n+\tcase 10:\n+\t\tc += ((uint32_t)input[9]) << 16;\n+\t\t/* Fall-through */\n+\tcase 9:\n+\t\tc += ((uint32_t)input[8]) << 24;\n+\t\t/* Fall-through */\n+\tcase 8:\n+\t\tb += ((uint32_t)input[7]);\n+\t\t/* Fall-through */\n+\tcase 7:\n+\t\tb += ((uint32_t)input[6]) << 8;\n+\t\t/* Fall-through */\n+\tcase 6:\n+\t\tb += ((uint32_t)input[5]) << 16;\n+\t\t/* Fall-through */\n+\tcase 5:\n+\t\tb += ((uint32_t)input[4]) << 24;\n+\t\t/* Fall-through */\n+\tcase 4:\n+\t\ta += ((uint32_t)input[3]);\n+\t\t/* Fall-through */\n+\tcase 3:\n+\t\ta += ((uint32_t)input[2]) << 8;\n+\t\t/* Fall-through */\n+\tcase 2:\n+\t\ta += ((uint32_t)input[1]) << 16;\n+\t\t/* Fall-through */\n+\tcase 1:\n+\t\ta += ((uint32_t)input[0]) << 24;\n+\t\tEFX_HASH_FINALISE(a, b, c);\n+\t\tbreak;\n+\n+\tcase 0:\n+\t\t/* Should only get here if length parameter was zero */\n+\t\tbreak;\n+\t}\n+\n+\treturn (c);\n+}\n+\n+#elif EFSYS_IS_LITTLE_ENDIAN\n+\n+/* Produce a 32-bit hash from arbitrarily aligned input */\n+\t__checkReturn\t\tuint32_t\n+efx_hash_bytes(\n+\t__in_ecount(length)\tuint8_t const *input,\n+\t__in\t\t\tsize_t length,\n+\t__in\t\t\tuint32_t init)\n+{\n+\tuint32_t a;\n+\tuint32_t b;\n+\tuint32_t c;\n+\n+\t/* Set up the initial internal state */\n+\ta = b = c = EFX_HASH_INITIAL_VALUE + (uint32_t)length + init;\n+\n+\t/* Handle all but the last twelve bytes of the input */\n+\twhile (length > 12) {\n+\t\ta += ((uint32_t)input[0]);\n+\t\ta += ((uint32_t)input[1]) << 8;\n+\t\ta += ((uint32_t)input[2]) << 16;\n+\t\ta += ((uint32_t)input[3]) << 24;\n+\t\tb += ((uint32_t)input[4]);\n+\t\tb += ((uint32_t)input[5]) << 8;\n+\t\tb += ((uint32_t)input[6]) << 16;\n+\t\tb += ((uint32_t)input[7]) << 24;\n+\t\tc += ((uint32_t)input[8]);\n+\t\tc += ((uint32_t)input[9]) << 8;\n+\t\tc += ((uint32_t)input[10]) << 16;\n+\t\tc += ((uint32_t)input[11]) << 24;\n+\t\tEFX_HASH_MIX(a, b, c);\n+\t\tlength -= 12;\n+\t\tinput += 12;\n+\t}\n+\n+\t/* Handle the left-overs */\n+\tswitch (length) {\n+\tcase 12:\n+\t\tc += ((uint32_t)input[11]) << 24;\n+\t\t/* Fall-through */\n+\tcase 11:\n+\t\tc += ((uint32_t)input[10]) << 16;\n+\t\t/* Fall-through */\n+\tcase 10:\n+\t\tc += ((uint32_t)input[9]) << 8;\n+\t\t/* Fall-through */\n+\tcase 9:\n+\t\tc += ((uint32_t)input[8]);\n+\t\t/* Fall-through */\n+\tcase 8:\n+\t\tb += ((uint32_t)input[7]) << 24;\n+\t\t/* Fall-through */\n+\tcase 7:\n+\t\tb += ((uint32_t)input[6]) << 16;\n+\t\t/* Fall-through */\n+\tcase 6:\n+\t\tb += ((uint32_t)input[5]) << 8;\n+\t\t/* Fall-through */\n+\tcase 5:\n+\t\tb += ((uint32_t)input[4]);\n+\t\t/* Fall-through */\n+\tcase 4:\n+\t\ta += ((uint32_t)input[3]) << 24;\n+\t\t/* Fall-through */\n+\tcase 3:\n+\t\ta += ((uint32_t)input[2]) << 16;\n+\t\t/* Fall-through */\n+\tcase 2:\n+\t\ta += ((uint32_t)input[1]) << 8;\n+\t\t/* Fall-through */\n+\tcase 1:\n+\t\ta += ((uint32_t)input[0]);\n+\t\tEFX_HASH_FINALISE(a, b, c);\n+\t\tbreak;\n+\n+\tcase 0:\n+\t\t/* Should only get here if length parameter was zero */\n+\t\tbreak;\n+\t}\n+\n+\treturn (c);\n+}\n+\n+#else\n+\n+#error \"Neither of EFSYS_IS_{BIG,LITTLE}_ENDIAN is set\"\n+\n+#endif\ndiff --git a/drivers/net/sfc/efx/base/efx_impl.h b/drivers/net/sfc/efx/base/efx_impl.h\nnew file mode 100644\nindex 0000000..15bca37\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_impl.h\n@@ -0,0 +1,658 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#ifndef\t_SYS_EFX_IMPL_H\n+#define\t_SYS_EFX_IMPL_H\n+\n+#include \"efx.h\"\n+#include \"efx_regs.h\"\n+#include \"efx_regs_ef10.h\"\n+\n+/* FIXME: Add definition for driver generated software events */\n+#ifndef\tESE_DZ_EV_CODE_DRV_GEN_EV\n+#define\tESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV\n+#endif\n+\n+\n+#ifdef\t__cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define\tEFX_MOD_MCDI\t\t0x00000001\n+#define\tEFX_MOD_PROBE\t\t0x00000002\n+#define\tEFX_MOD_NVRAM\t\t0x00000004\n+#define\tEFX_MOD_VPD\t\t0x00000008\n+#define\tEFX_MOD_NIC\t\t0x00000010\n+#define\tEFX_MOD_INTR\t\t0x00000020\n+#define\tEFX_MOD_EV\t\t0x00000040\n+#define\tEFX_MOD_RX\t\t0x00000080\n+#define\tEFX_MOD_TX\t\t0x00000100\n+#define\tEFX_MOD_PORT\t\t0x00000200\n+#define\tEFX_MOD_MON\t\t0x00000400\n+#define\tEFX_MOD_FILTER\t\t0x00001000\n+#define\tEFX_MOD_LIC\t\t0x00002000\n+\n+#define\tEFX_RESET_PHY\t\t0x00000001\n+#define\tEFX_RESET_RXQ_ERR\t0x00000002\n+#define\tEFX_RESET_TXQ_ERR\t0x00000004\n+\n+typedef enum efx_mac_type_e {\n+\tEFX_MAC_INVALID = 0,\n+\tEFX_MAC_SIENA,\n+\tEFX_MAC_HUNTINGTON,\n+\tEFX_MAC_MEDFORD,\n+\tEFX_MAC_NTYPES\n+} efx_mac_type_t;\n+\n+typedef struct efx_ev_ops_s {\n+\tefx_rc_t\t(*eevo_init)(efx_nic_t *);\n+\tvoid\t\t(*eevo_fini)(efx_nic_t *);\n+\tefx_rc_t\t(*eevo_qcreate)(efx_nic_t *, unsigned int,\n+\t\t\t\t\t  efsys_mem_t *, size_t, uint32_t,\n+\t\t\t\t\t  uint32_t, uint32_t, efx_evq_t *);\n+\tvoid\t\t(*eevo_qdestroy)(efx_evq_t *);\n+\tefx_rc_t\t(*eevo_qprime)(efx_evq_t *, unsigned int);\n+\tvoid\t\t(*eevo_qpost)(efx_evq_t *, uint16_t);\n+\tefx_rc_t\t(*eevo_qmoderate)(efx_evq_t *, unsigned int);\n+} efx_ev_ops_t;\n+\n+typedef struct efx_tx_ops_s {\n+\tefx_rc_t\t(*etxo_init)(efx_nic_t *);\n+\tvoid\t\t(*etxo_fini)(efx_nic_t *);\n+\tefx_rc_t\t(*etxo_qcreate)(efx_nic_t *,\n+\t\t\t\t\tunsigned int, unsigned int,\n+\t\t\t\t\tefsys_mem_t *, size_t,\n+\t\t\t\t\tuint32_t, uint16_t,\n+\t\t\t\t\tefx_evq_t *, efx_txq_t *,\n+\t\t\t\t\tunsigned int *);\n+\tvoid\t\t(*etxo_qdestroy)(efx_txq_t *);\n+\tefx_rc_t\t(*etxo_qpost)(efx_txq_t *, efx_buffer_t *,\n+\t\t\t\t      unsigned int, unsigned int,\n+\t\t\t\t      unsigned int *);\n+\tvoid\t\t(*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);\n+\tefx_rc_t\t(*etxo_qpace)(efx_txq_t *, unsigned int);\n+\tefx_rc_t\t(*etxo_qflush)(efx_txq_t *);\n+\tvoid\t\t(*etxo_qenable)(efx_txq_t *);\n+\tefx_rc_t\t(*etxo_qpio_enable)(efx_txq_t *);\n+\tvoid\t\t(*etxo_qpio_disable)(efx_txq_t *);\n+\tefx_rc_t\t(*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,\n+\t\t\t\t\t   size_t);\n+\tefx_rc_t\t(*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,\n+\t\t\t\t\t   unsigned int *);\n+\tefx_rc_t\t(*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,\n+\t\t\t\t      unsigned int, unsigned int,\n+\t\t\t\t      unsigned int *);\n+\tvoid\t\t(*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,\n+\t\t\t\t\t\tsize_t, boolean_t,\n+\t\t\t\t\t\tefx_desc_t *);\n+\tvoid\t\t(*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,\n+\t\t\t\t\t\tuint32_t, uint8_t,\n+\t\t\t\t\t\tefx_desc_t *);\n+\tvoid\t\t(*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,\n+\t\t\t\t\t\tuint32_t, uint16_t,\n+\t\t\t\t\t\tefx_desc_t *, int);\n+\tvoid\t\t(*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,\n+\t\t\t\t\t\tefx_desc_t *);\n+} efx_tx_ops_t;\n+\n+typedef struct efx_rx_ops_s {\n+\tefx_rc_t\t(*erxo_init)(efx_nic_t *);\n+\tvoid\t\t(*erxo_fini)(efx_nic_t *);\n+\tefx_rc_t\t(*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,\n+\t\t\t\t\t      uint16_t *);\n+\tvoid\t\t(*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,\n+\t\t\t\t      unsigned int, unsigned int,\n+\t\t\t\t      unsigned int);\n+\tvoid\t\t(*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);\n+\tefx_rc_t\t(*erxo_qflush)(efx_rxq_t *);\n+\tvoid\t\t(*erxo_qenable)(efx_rxq_t *);\n+\tefx_rc_t\t(*erxo_qcreate)(efx_nic_t *enp, unsigned int,\n+\t\t\t\t\tunsigned int, efx_rxq_type_t,\n+\t\t\t\t\tefsys_mem_t *, size_t, uint32_t,\n+\t\t\t\t\tefx_evq_t *, efx_rxq_t *);\n+\tvoid\t\t(*erxo_qdestroy)(efx_rxq_t *);\n+} efx_rx_ops_t;\n+\n+typedef struct efx_mac_ops_s {\n+\tefx_rc_t\t(*emo_poll)(efx_nic_t *, efx_link_mode_t *);\n+\tefx_rc_t\t(*emo_up)(efx_nic_t *, boolean_t *);\n+\tefx_rc_t\t(*emo_addr_set)(efx_nic_t *);\n+\tefx_rc_t\t(*emo_pdu_set)(efx_nic_t *);\n+\tefx_rc_t\t(*emo_pdu_get)(efx_nic_t *, size_t *);\n+\tefx_rc_t\t(*emo_reconfigure)(efx_nic_t *);\n+\tefx_rc_t\t(*emo_multicast_list_set)(efx_nic_t *);\n+\tefx_rc_t\t(*emo_filter_default_rxq_set)(efx_nic_t *,\n+\t\t\t\t\t\t      efx_rxq_t *, boolean_t);\n+\tvoid\t\t(*emo_filter_default_rxq_clear)(efx_nic_t *);\n+} efx_mac_ops_t;\n+\n+typedef struct efx_phy_ops_s {\n+\tefx_rc_t\t(*epo_power)(efx_nic_t *, boolean_t); /* optional */\n+\tefx_rc_t\t(*epo_reset)(efx_nic_t *);\n+\tefx_rc_t\t(*epo_reconfigure)(efx_nic_t *);\n+\tefx_rc_t\t(*epo_verify)(efx_nic_t *);\n+\tefx_rc_t\t(*epo_oui_get)(efx_nic_t *, uint32_t *);\n+} efx_phy_ops_t;\n+\n+\n+typedef struct efx_port_s {\n+\tefx_mac_type_t\t\tep_mac_type;\n+\tuint32_t\t\tep_phy_type;\n+\tuint8_t\t\t\tep_port;\n+\tuint32_t\t\tep_mac_pdu;\n+\tuint8_t\t\t\tep_mac_addr[6];\n+\tefx_link_mode_t\t\tep_link_mode;\n+\tboolean_t\t\tep_all_unicst;\n+\tboolean_t\t\tep_mulcst;\n+\tboolean_t\t\tep_all_mulcst;\n+\tboolean_t\t\tep_brdcst;\n+\tunsigned int\t\tep_fcntl;\n+\tboolean_t\t\tep_fcntl_autoneg;\n+\tefx_oword_t\t\tep_multicst_hash[2];\n+\tuint8_t\t\t\tep_mulcst_addr_list[EFX_MAC_ADDR_LEN *\n+\t\t\t\t\t\t    EFX_MAC_MULTICAST_LIST_MAX];\n+\tuint32_t\t\tep_mulcst_addr_count;\n+\tefx_phy_media_type_t\tep_fixed_port_type;\n+\tefx_phy_media_type_t\tep_module_type;\n+\tuint32_t\t\tep_adv_cap_mask;\n+\tuint32_t\t\tep_lp_cap_mask;\n+\tuint32_t\t\tep_default_adv_cap_mask;\n+\tuint32_t\t\tep_phy_cap_mask;\n+\tboolean_t\t\tep_mac_drain;\n+\tboolean_t\t\tep_mac_stats_pending;\n+\tconst efx_mac_ops_t\t*ep_emop;\n+\tconst efx_phy_ops_t\t*ep_epop;\n+} efx_port_t;\n+\n+typedef struct efx_mon_ops_s {\n+} efx_mon_ops_t;\n+\n+typedef struct efx_mon_s {\n+\tefx_mon_type_t\t\tem_type;\n+\tconst efx_mon_ops_t\t*em_emop;\n+} efx_mon_t;\n+\n+typedef struct efx_intr_ops_s {\n+\tefx_rc_t\t(*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);\n+\tvoid\t\t(*eio_enable)(efx_nic_t *);\n+\tvoid\t\t(*eio_disable)(efx_nic_t *);\n+\tvoid\t\t(*eio_disable_unlocked)(efx_nic_t *);\n+\tefx_rc_t\t(*eio_trigger)(efx_nic_t *, unsigned int);\n+\tvoid\t\t(*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);\n+\tvoid\t\t(*eio_status_message)(efx_nic_t *, unsigned int,\n+\t\t\t\t boolean_t *);\n+\tvoid\t\t(*eio_fatal)(efx_nic_t *);\n+\tvoid\t\t(*eio_fini)(efx_nic_t *);\n+} efx_intr_ops_t;\n+\n+typedef struct efx_intr_s {\n+\tconst efx_intr_ops_t\t*ei_eiop;\n+\tefsys_mem_t\t\t*ei_esmp;\n+\tefx_intr_type_t\t\tei_type;\n+\tunsigned int\t\tei_level;\n+} efx_intr_t;\n+\n+typedef struct efx_nic_ops_s {\n+\tefx_rc_t\t(*eno_probe)(efx_nic_t *);\n+\tefx_rc_t\t(*eno_board_cfg)(efx_nic_t *);\n+\tefx_rc_t\t(*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);\n+\tefx_rc_t\t(*eno_reset)(efx_nic_t *);\n+\tefx_rc_t\t(*eno_init)(efx_nic_t *);\n+\tefx_rc_t\t(*eno_get_vi_pool)(efx_nic_t *, uint32_t *);\n+\tefx_rc_t\t(*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,\n+\t\t\t\t\tuint32_t *, size_t *);\n+\tvoid\t\t(*eno_fini)(efx_nic_t *);\n+\tvoid\t\t(*eno_unprobe)(efx_nic_t *);\n+} efx_nic_ops_t;\n+\n+#ifndef EFX_TXQ_LIMIT_TARGET\n+#define\tEFX_TXQ_LIMIT_TARGET 259\n+#endif\n+#ifndef EFX_RXQ_LIMIT_TARGET\n+#define\tEFX_RXQ_LIMIT_TARGET 512\n+#endif\n+#ifndef EFX_TXQ_DC_SIZE\n+#define\tEFX_TXQ_DC_SIZE 1 /* 16 descriptors */\n+#endif\n+#ifndef EFX_RXQ_DC_SIZE\n+#define\tEFX_RXQ_DC_SIZE 3 /* 64 descriptors */\n+#endif\n+\n+typedef struct efx_drv_cfg_s {\n+\tuint32_t\t\tedc_min_vi_count;\n+\tuint32_t\t\tedc_max_vi_count;\n+\n+\tuint32_t\t\tedc_max_piobuf_count;\n+\tuint32_t\t\tedc_pio_alloc_size;\n+} efx_drv_cfg_t;\n+\n+struct efx_nic_s {\n+\tuint32_t\t\ten_magic;\n+\tefx_family_t\t\ten_family;\n+\tuint32_t\t\ten_features;\n+\tefsys_identifier_t\t*en_esip;\n+\tefsys_lock_t\t\t*en_eslp;\n+\tefsys_bar_t\t\t*en_esbp;\n+\tunsigned int\t\ten_mod_flags;\n+\tunsigned int\t\ten_reset_flags;\n+\tefx_nic_cfg_t\t\ten_nic_cfg;\n+\tefx_drv_cfg_t\t\ten_drv_cfg;\n+\tefx_port_t\t\ten_port;\n+\tefx_mon_t\t\ten_mon;\n+\tefx_intr_t\t\ten_intr;\n+\tuint32_t\t\ten_ev_qcount;\n+\tuint32_t\t\ten_rx_qcount;\n+\tuint32_t\t\ten_tx_qcount;\n+\tconst efx_nic_ops_t\t*en_enop;\n+\tconst efx_ev_ops_t\t*en_eevop;\n+\tconst efx_tx_ops_t\t*en_etxop;\n+\tconst efx_rx_ops_t\t*en_erxop;\n+\tuint32_t\t\ten_vport_id;\n+\tunion {\n+\t\tint\tenu_unused;\n+\t} en_u;\n+};\n+\n+\n+#define\tEFX_NIC_MAGIC\t0x02121996\n+\n+typedef\tboolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,\n+    const efx_ev_callbacks_t *, void *);\n+\n+typedef struct efx_evq_rxq_state_s {\n+\tunsigned int\t\t\teers_rx_read_ptr;\n+\tunsigned int\t\t\teers_rx_mask;\n+} efx_evq_rxq_state_t;\n+\n+struct efx_evq_s {\n+\tuint32_t\t\t\tee_magic;\n+\tefx_nic_t\t\t\t*ee_enp;\n+\tunsigned int\t\t\tee_index;\n+\tunsigned int\t\t\tee_mask;\n+\tefsys_mem_t\t\t\t*ee_esmp;\n+\n+\tefx_ev_handler_t\t\tee_rx;\n+\tefx_ev_handler_t\t\tee_tx;\n+\tefx_ev_handler_t\t\tee_driver;\n+\tefx_ev_handler_t\t\tee_global;\n+\tefx_ev_handler_t\t\tee_drv_gen;\n+\n+\tefx_evq_rxq_state_t\t\tee_rxq_state[EFX_EV_RX_NLABELS];\n+\n+\tuint32_t\t\t\tee_flags;\n+};\n+\n+#define\tEFX_EVQ_MAGIC\t0x08081997\n+\n+#define\tEFX_EVQ_SIENA_TIMER_QUANTUM_NS\t6144 /* 768 cycles */\n+\n+struct efx_rxq_s {\n+\tuint32_t\t\t\ter_magic;\n+\tefx_nic_t\t\t\t*er_enp;\n+\tefx_evq_t\t\t\t*er_eep;\n+\tunsigned int\t\t\ter_index;\n+\tunsigned int\t\t\ter_label;\n+\tunsigned int\t\t\ter_mask;\n+\tefsys_mem_t\t\t\t*er_esmp;\n+};\n+\n+#define\tEFX_RXQ_MAGIC\t0x15022005\n+\n+struct efx_txq_s {\n+\tuint32_t\t\t\tet_magic;\n+\tefx_nic_t\t\t\t*et_enp;\n+\tunsigned int\t\t\tet_index;\n+\tunsigned int\t\t\tet_mask;\n+\tefsys_mem_t\t\t\t*et_esmp;\n+};\n+\n+#define\tEFX_TXQ_MAGIC\t0x05092005\n+\n+#define\tEFX_MAC_ADDR_COPY(_dst, _src)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_dst)[0] = (_src)[0];\t\t\t\t\t\\\n+\t\t(_dst)[1] = (_src)[1];\t\t\t\t\t\\\n+\t\t(_dst)[2] = (_src)[2];\t\t\t\t\t\\\n+\t\t(_dst)[3] = (_src)[3];\t\t\t\t\t\\\n+\t\t(_dst)[4] = (_src)[4];\t\t\t\t\t\\\n+\t\t(_dst)[5] = (_src)[5];\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_MAC_BROADCAST_ADDR_SET(_dst)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tuint16_t *_d = (uint16_t *)(_dst);\t\t\t\\\n+\t\t_d[0] = 0xffff;\t\t\t\t\t\t\\\n+\t\t_d[1] = 0xffff;\t\t\t\t\t\t\\\n+\t\t_d[2] = 0xffff;\t\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#if EFSYS_OPT_CHECK_REG\n+#define\tEFX_CHECK_REG(_enp, _reg)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tconst char *name = #_reg;\t\t\t\t\\\n+\t\tchar min = name[4];\t\t\t\t\t\\\n+\t\tchar max = name[5];\t\t\t\t\t\\\n+\t\tchar rev;\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tswitch ((_enp)->en_family) {\t\t\t\t\\\n+\t\tcase EFX_FAMILY_SIENA:\t\t\t\t\t\\\n+\t\t\trev = 'C';\t\t\t\t\t\\\n+\t\t\tbreak;\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tcase EFX_FAMILY_HUNTINGTON:\t\t\t\t\\\n+\t\t\trev = 'D';\t\t\t\t\t\\\n+\t\t\tbreak;\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tcase EFX_FAMILY_MEDFORD:\t\t\t\t\\\n+\t\t\trev = 'E';\t\t\t\t\t\\\n+\t\t\tbreak;\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tdefault:\t\t\t\t\t\t\\\n+\t\t\trev = '?';\t\t\t\t\t\\\n+\t\t\tbreak;\t\t\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tEFSYS_ASSERT3S(rev, >=, min);\t\t\t\t\\\n+\t\tEFSYS_ASSERT3S(rev, <=, max);\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+#else\n+#define\tEFX_CHECK_REG(_enp, _reg) do {\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+#endif\n+\n+#define\tEFX_BAR_READD(_enp, _reg, _edp, _lock)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,\t\t\\\n+\t\t    (_edp), (_lock));\t\t\t\t\t\\\n+\t\tEFSYS_PROBE3(efx_bar_readd, const char *, #_reg,\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_edp)->ed_u32[0]);\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_WRITED(_enp, _reg, _edp, _lock)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_PROBE3(efx_bar_writed, const char *, #_reg,\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_edp)->ed_u32[0]);\t\t\t\\\n+\t\tEFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,\t\\\n+\t\t    (_edp), (_lock));\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_READQ(_enp, _reg, _eqp)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,\t\t\\\n+\t\t    (_eqp));\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE4(efx_bar_readq, const char *, #_reg,\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_eqp)->eq_u32[1],\t\t\t\\\n+\t\t    uint32_t, (_eqp)->eq_u32[0]);\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_WRITEQ(_enp, _reg, _eqp)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_eqp)->eq_u32[1],\t\t\t\\\n+\t\t    uint32_t, (_eqp)->eq_u32[0]);\t\t\t\\\n+\t\tEFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,\t\\\n+\t\t    (_eqp));\t\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_READO(_enp, _reg, _eop)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,\t\t\\\n+\t\t    (_eop), B_TRUE);\t\t\t\t\t\\\n+\t\tEFSYS_PROBE6(efx_bar_reado, const char *, #_reg,\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[3],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[2],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[1],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[0]);\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_WRITEO(_enp, _reg, _eop)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[3],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[2],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[1],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[0]);\t\t\t\\\n+\t\tEFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,\t\\\n+\t\t    (_eop), B_TRUE);\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_BAR_READD((_enp)->en_esbp,\t\t\t\\\n+\t\t    (_reg ## _OFST + ((_index) * _reg ## _STEP)),\t\\\n+\t\t    (_edp), (_lock));\t\t\t\t\t\\\n+\t\tEFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,\t\\\n+\t\t    uint32_t, (_index),\t\t\t\t\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_edp)->ed_u32[0]);\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,\t\\\n+\t\t    uint32_t, (_index),\t\t\t\t\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_edp)->ed_u32[0]);\t\t\t\\\n+\t\tEFSYS_BAR_WRITED((_enp)->en_esbp,\t\t\t\\\n+\t\t    (_reg ## _OFST + ((_index) * _reg ## _STEP)),\t\\\n+\t\t    (_edp), (_lock));\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,\t\\\n+\t\t    uint32_t, (_index),\t\t\t\t\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_edp)->ed_u32[0]);\t\t\t\\\n+\t\tEFSYS_BAR_WRITED((_enp)->en_esbp,\t\t\t\\\n+\t\t    (_reg ## _OFST +\t\t\t\t\t\\\n+\t\t    (2 * sizeof (efx_dword_t)) +\t\t\t\\\n+\t\t    ((_index) * _reg ## _STEP)),\t\t\t\\\n+\t\t    (_edp), (_lock));\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,\t\\\n+\t\t    uint32_t, (_index),\t\t\t\t\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_edp)->ed_u32[0]);\t\t\t\\\n+\t\tEFSYS_BAR_WRITED((_enp)->en_esbp,\t\t\t\\\n+\t\t    (_reg ## _OFST +\t\t\t\t\t\\\n+\t\t    (3 * sizeof (efx_dword_t)) +\t\t\t\\\n+\t\t    ((_index) * _reg ## _STEP)),\t\t\t\\\n+\t\t    (_edp), (_lock));\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_BAR_READQ((_enp)->en_esbp,\t\t\t\\\n+\t\t    (_reg ## _OFST + ((_index) * _reg ## _STEP)),\t\\\n+\t\t    (_eqp));\t\t\t\t\t\t\\\n+\t\tEFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,\t\\\n+\t\t    uint32_t, (_index),\t\t\t\t\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_eqp)->eq_u32[1],\t\t\t\\\n+\t\t    uint32_t, (_eqp)->eq_u32[0]);\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,\t\\\n+\t\t    uint32_t, (_index),\t\t\t\t\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_eqp)->eq_u32[1],\t\t\t\\\n+\t\t    uint32_t, (_eqp)->eq_u32[0]);\t\t\t\\\n+\t\tEFSYS_BAR_WRITEQ((_enp)->en_esbp,\t\t\t\\\n+\t\t    (_reg ## _OFST + ((_index) * _reg ## _STEP)),\t\\\n+\t\t    (_eqp));\t\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_BAR_READO((_enp)->en_esbp,\t\t\t\\\n+\t\t    (_reg ## _OFST + ((_index) * _reg ## _STEP)),\t\\\n+\t\t    (_eop), (_lock));\t\t\t\t\t\\\n+\t\tEFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,\t\\\n+\t\t    uint32_t, (_index),\t\t\t\t\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[3],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[2],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[1],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[0]);\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,\t\\\n+\t\t    uint32_t, (_index),\t\t\t\t\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[3],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[2],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[1],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[0]);\t\t\t\\\n+\t\tEFSYS_BAR_WRITEO((_enp)->en_esbp,\t\t\t\\\n+\t\t    (_reg ## _OFST + ((_index) * _reg ## _STEP)),\t\\\n+\t\t    (_eop), (_lock));\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/*\n+ * Allow drivers to perform optimised 128-bit doorbell writes.\n+ * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are\n+ * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid\n+ * the need for locking in the host, and are the only ones known to be safe to\n+ * use 128-bites write with.\n+ */\n+#define\tEFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tEFX_CHECK_REG((_enp), (_reg));\t\t\t\t\\\n+\t\tEFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,\t\t\\\n+\t\t    const char *,\t\t\t\t\t\\\n+\t\t    #_reg,\t\t\t\t\t\t\\\n+\t\t    uint32_t, (_index),\t\t\t\t\t\\\n+\t\t    uint32_t, _reg ## _OFST,\t\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[3],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[2],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[1],\t\t\t\\\n+\t\t    uint32_t, (_eop)->eo_u32[0]);\t\t\t\\\n+\t\tEFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,\t\t\\\n+\t\t    (_reg ## _OFST + ((_index) * _reg ## _STEP)),\t\\\n+\t\t    (_eop));\t\t\t\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int _new = (_wptr);\t\t\t\t\\\n+\t\tunsigned int _old = (_owptr);\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tif ((_new) >= (_old))\t\t\t\t\t\\\n+\t\t\tEFSYS_DMA_SYNC_FOR_DEVICE((_esmp),\t\t\\\n+\t\t\t    (_old) * sizeof (efx_desc_t),\t\t\\\n+\t\t\t    ((_new) - (_old)) * sizeof (efx_desc_t));\t\\\n+\t\telse\t\t\t\t\t\t\t\\\n+\t\t\t/*\t\t\t\t\t\t\\\n+\t\t\t * It is cheaper to sync entire map than sync\t\\\n+\t\t\t * two parts especially when offset/size are\t\\\n+\t\t\t * ignored and entire map is synced in any case.\\\n+\t\t\t */\t\t\t\t\t\t\\\n+\t\t\tEFSYS_DMA_SYNC_FOR_DEVICE((_esmp),\t\t\\\n+\t\t\t    0,\t\t\t\t\t\t\\\n+\t\t\t    (_entries) * sizeof (efx_desc_t));\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_nic_biu_test(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_mac_select(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\tvoid\n+efx_mac_multicast_hash_compute(\n+\t__in_ecount(6*count)\t\tuint8_t const *addrs,\n+\t__in\t\t\t\tint count,\n+\t__out\t\t\t\tefx_oword_t *hash_low,\n+\t__out\t\t\t\tefx_oword_t *hash_high);\n+\n+extern\t__checkReturn\tefx_rc_t\n+efx_phy_probe(\n+\t__in\t\tefx_nic_t *enp);\n+\n+extern\t\t\tvoid\n+efx_phy_unprobe(\n+\t__in\t\tefx_nic_t *enp);\n+\n+#ifdef\t__cplusplus\n+}\n+#endif\n+\n+#endif\t/* _SYS_EFX_IMPL_H */\ndiff --git a/drivers/net/sfc/efx/base/efx_intr.c b/drivers/net/sfc/efx/base/efx_intr.c\nnew file mode 100644\nindex 0000000..fb1812b\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_intr.c\n@@ -0,0 +1,201 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_intr_init(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_intr_type_t type,\n+\t__in\t\tefsys_mem_t *esmp)\n+{\n+\tefx_intr_t *eip = &(enp->en_intr);\n+\tconst efx_intr_ops_t *eiop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\n+\tif (enp->en_mod_flags & EFX_MOD_INTR) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\teip->ei_esmp = esmp;\n+\teip->ei_type = type;\n+\teip->ei_level = 0;\n+\n+\tenp->en_mod_flags |= EFX_MOD_INTR;\n+\n+\tswitch (enp->en_family) {\n+\n+\tdefault:\n+\t\tEFSYS_ASSERT(B_FALSE);\n+\t\trc = ENOTSUP;\n+\t\tgoto fail2;\n+\t}\n+\n+\tif ((rc = eiop->eio_init(enp, type, esmp)) != 0)\n+\t\tgoto fail3;\n+\n+\teip->ei_eiop = eiop;\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\tvoid\n+efx_intr_fini(\n+\t__in\tefx_nic_t *enp)\n+{\n+\tefx_intr_t *eip = &(enp->en_intr);\n+\tconst efx_intr_ops_t *eiop = eip->ei_eiop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);\n+\n+\teiop->eio_fini(enp);\n+\n+\tenp->en_mod_flags &= ~EFX_MOD_INTR;\n+}\n+\n+\t\t\tvoid\n+efx_intr_enable(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_intr_t *eip = &(enp->en_intr);\n+\tconst efx_intr_ops_t *eiop = eip->ei_eiop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);\n+\n+\teiop->eio_enable(enp);\n+}\n+\n+\t\t\tvoid\n+efx_intr_disable(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_intr_t *eip = &(enp->en_intr);\n+\tconst efx_intr_ops_t *eiop = eip->ei_eiop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);\n+\n+\teiop->eio_disable(enp);\n+}\n+\n+\t\t\tvoid\n+efx_intr_disable_unlocked(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_intr_t *eip = &(enp->en_intr);\n+\tconst efx_intr_ops_t *eiop = eip->ei_eiop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);\n+\n+\teiop->eio_disable_unlocked(enp);\n+}\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_intr_trigger(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int level)\n+{\n+\tefx_intr_t *eip = &(enp->en_intr);\n+\tconst efx_intr_ops_t *eiop = eip->ei_eiop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);\n+\n+\treturn (eiop->eio_trigger(enp, level));\n+}\n+\n+\t\t\tvoid\n+efx_intr_status_line(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tboolean_t *fatalp,\n+\t__out\t\tuint32_t *qmaskp)\n+{\n+\tefx_intr_t *eip = &(enp->en_intr);\n+\tconst efx_intr_ops_t *eiop = eip->ei_eiop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);\n+\n+\teiop->eio_status_line(enp, fatalp, qmaskp);\n+}\n+\n+\t\t\tvoid\n+efx_intr_status_message(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int message,\n+\t__out\t\tboolean_t *fatalp)\n+{\n+\tefx_intr_t *eip = &(enp->en_intr);\n+\tconst efx_intr_ops_t *eiop = eip->ei_eiop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);\n+\n+\teiop->eio_status_message(enp, message, fatalp);\n+}\n+\n+\t\tvoid\n+efx_intr_fatal(\n+\t__in\tefx_nic_t *enp)\n+{\n+\tefx_intr_t *eip = &(enp->en_intr);\n+\tconst efx_intr_ops_t *eiop = eip->ei_eiop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);\n+\n+\teiop->eio_fatal(enp);\n+}\n+\n+\n+/* ************************************************************************* */\n+/* ************************************************************************* */\n+/* ************************************************************************* */\n+\ndiff --git a/drivers/net/sfc/efx/base/efx_mac.c b/drivers/net/sfc/efx/base/efx_mac.c\nnew file mode 100644\nindex 0000000..169dcf1\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_mac.c\n@@ -0,0 +1,489 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_pdu_set(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tsize_t pdu)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tuint32_t old_pdu;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\tEFSYS_ASSERT(emop != NULL);\n+\n+\tif (pdu < EFX_MAC_PDU_MIN) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif (pdu > EFX_MAC_PDU_MAX) {\n+\t\trc = EINVAL;\n+\t\tgoto fail2;\n+\t}\n+\n+\told_pdu = epp->ep_mac_pdu;\n+\tepp->ep_mac_pdu = (uint32_t)pdu;\n+\tif ((rc = emop->emo_pdu_set(enp)) != 0)\n+\t\tgoto fail3;\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+\n+\tepp->ep_mac_pdu = old_pdu;\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_mac_pdu_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tsize_t *pdu)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tefx_rc_t rc;\n+\n+\tif ((rc = emop->emo_pdu_get(enp, pdu)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_addr_set(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tuint8_t *addr)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tuint8_t old_addr[6];\n+\tuint32_t oui;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tif (EFX_MAC_ADDR_IS_MULTICAST(addr)) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\toui = addr[0] << 16 | addr[1] << 8 | addr[2];\n+\tif (oui == 0x000000) {\n+\t\trc = EINVAL;\n+\t\tgoto fail2;\n+\t}\n+\n+\tEFX_MAC_ADDR_COPY(old_addr, epp->ep_mac_addr);\n+\tEFX_MAC_ADDR_COPY(epp->ep_mac_addr, addr);\n+\tif ((rc = emop->emo_addr_set(enp)) != 0)\n+\t\tgoto fail3;\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+\n+\tEFX_MAC_ADDR_COPY(epp->ep_mac_addr, old_addr);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_filter_set(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tboolean_t all_unicst,\n+\t__in\t\t\t\tboolean_t mulcst,\n+\t__in\t\t\t\tboolean_t all_mulcst,\n+\t__in\t\t\t\tboolean_t brdcst)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tboolean_t old_all_unicst;\n+\tboolean_t old_mulcst;\n+\tboolean_t old_all_mulcst;\n+\tboolean_t old_brdcst;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\told_all_unicst = epp->ep_all_unicst;\n+\told_mulcst = epp->ep_mulcst;\n+\told_all_mulcst = epp->ep_all_mulcst;\n+\told_brdcst = epp->ep_brdcst;\n+\n+\tepp->ep_all_unicst = all_unicst;\n+\tepp->ep_mulcst = mulcst;\n+\tepp->ep_all_mulcst = all_mulcst;\n+\tepp->ep_brdcst = brdcst;\n+\n+\tif ((rc = emop->emo_reconfigure(enp)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\tepp->ep_all_unicst = old_all_unicst;\n+\tepp->ep_mulcst = old_mulcst;\n+\tepp->ep_all_mulcst = old_all_mulcst;\n+\tepp->ep_brdcst = old_brdcst;\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_drain(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tboolean_t enabled)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\tEFSYS_ASSERT(emop != NULL);\n+\n+\tif (epp->ep_mac_drain == enabled)\n+\t\treturn (0);\n+\n+\tepp->ep_mac_drain = enabled;\n+\n+\tif ((rc = emop->emo_reconfigure(enp)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_mac_up(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tboolean_t *mac_upp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tif ((rc = emop->emo_up(enp, mac_upp)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_fcntl_set(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tunsigned int fcntl,\n+\t__in\t\t\t\tboolean_t autoneg)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tconst efx_phy_ops_t *epop = epp->ep_epop;\n+\tunsigned int old_fcntl;\n+\tboolean_t old_autoneg;\n+\tunsigned int old_adv_cap;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tif ((fcntl & ~(EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE)) != 0) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\t/*\n+\t * Ignore a request to set flow control auto-negotiation\n+\t * if the PHY doesn't support it.\n+\t */\n+\tif (~epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))\n+\t\tautoneg = B_FALSE;\n+\n+\told_fcntl = epp->ep_fcntl;\n+\told_autoneg = epp->ep_fcntl_autoneg;\n+\told_adv_cap = epp->ep_adv_cap_mask;\n+\n+\tepp->ep_fcntl = fcntl;\n+\tepp->ep_fcntl_autoneg = autoneg;\n+\n+\t/*\n+\t * Always encode the flow control settings in the advertised\n+\t * capabilities even if we are not trying to auto-negotiate\n+\t * them and reconfigure both the PHY and the MAC.\n+\t */\n+\tif (fcntl & EFX_FCNTL_RESPOND)\n+\t\tepp->ep_adv_cap_mask |=    (1 << EFX_PHY_CAP_PAUSE |\n+\t\t\t\t\t    1 << EFX_PHY_CAP_ASYM);\n+\telse\n+\t\tepp->ep_adv_cap_mask &=   ~(1 << EFX_PHY_CAP_PAUSE |\n+\t\t\t\t\t    1 << EFX_PHY_CAP_ASYM);\n+\n+\tif (fcntl & EFX_FCNTL_GENERATE)\n+\t\tepp->ep_adv_cap_mask ^= (1 << EFX_PHY_CAP_ASYM);\n+\n+\tif ((rc = epop->epo_reconfigure(enp)) != 0)\n+\t\tgoto fail2;\n+\n+\tif ((rc = emop->emo_reconfigure(enp)) != 0)\n+\t\tgoto fail3;\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\n+\tepp->ep_fcntl = old_fcntl;\n+\tepp->ep_fcntl_autoneg = old_autoneg;\n+\tepp->ep_adv_cap_mask = old_adv_cap;\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+efx_mac_fcntl_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tunsigned int *fcntl_wantedp,\n+\t__out\t\tunsigned int *fcntl_linkp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tunsigned int wanted = 0;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\t/*\n+\t * Decode the requested flow control settings from the PHY\n+\t * advertised capabilities.\n+\t */\n+\tif (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_PAUSE))\n+\t\twanted = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;\n+\tif (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_ASYM))\n+\t\twanted ^= EFX_FCNTL_GENERATE;\n+\n+\t*fcntl_linkp = epp->ep_fcntl;\n+\t*fcntl_wantedp = wanted;\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_mac_multicast_list_set(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in_ecount(6*count)\t\tuint8_t const *addrs,\n+\t__in\t\t\t\tint count)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tuint8_t\t*old_mulcst_addr_list = NULL;\n+\tuint32_t old_mulcst_addr_count;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tif (count > EFX_MAC_MULTICAST_LIST_MAX) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\told_mulcst_addr_count = epp->ep_mulcst_addr_count;\n+\tif (old_mulcst_addr_count > 0) {\n+\t\t/* Allocate memory to store old list (instead of using stack) */\n+\t\tEFSYS_KMEM_ALLOC(enp->en_esip,\n+\t\t\t\told_mulcst_addr_count * EFX_MAC_ADDR_LEN,\n+\t\t\t\told_mulcst_addr_list);\n+\t\tif (old_mulcst_addr_list == NULL) {\n+\t\t\trc = ENOMEM;\n+\t\t\tgoto fail2;\n+\t\t}\n+\n+\t\t/* Save the old list in case we need to rollback */\n+\t\tmemcpy(old_mulcst_addr_list, epp->ep_mulcst_addr_list,\n+\t\t\told_mulcst_addr_count * EFX_MAC_ADDR_LEN);\n+\t}\n+\n+\t/* Store the new list */\n+\tmemcpy(epp->ep_mulcst_addr_list, addrs,\n+\t\tcount * EFX_MAC_ADDR_LEN);\n+\tepp->ep_mulcst_addr_count = count;\n+\n+\tif ((rc = emop->emo_multicast_list_set(enp)) != 0)\n+\t\tgoto fail3;\n+\n+\tif (old_mulcst_addr_count > 0) {\n+\t\tEFSYS_KMEM_FREE(enp->en_esip,\n+\t\t\t\told_mulcst_addr_count * EFX_MAC_ADDR_LEN,\n+\t\t\t\told_mulcst_addr_list);\n+\t}\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+\n+\t/* Restore original list on failure */\n+\tepp->ep_mulcst_addr_count = old_mulcst_addr_count;\n+\tif (old_mulcst_addr_count > 0) {\n+\t\tmemcpy(epp->ep_mulcst_addr_list, old_mulcst_addr_list,\n+\t\t\told_mulcst_addr_count * EFX_MAC_ADDR_LEN);\n+\n+\t\tEFSYS_KMEM_FREE(enp->en_esip,\n+\t\t\t\told_mulcst_addr_count * EFX_MAC_ADDR_LEN,\n+\t\t\t\told_mulcst_addr_list);\n+\t}\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_mac_filter_default_rxq_set(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_rxq_t *erp,\n+\t__in\t\tboolean_t using_rss)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tif (emop->emo_filter_default_rxq_set != NULL) {\n+\t\trc = emop->emo_filter_default_rxq_set(enp, erp, using_rss);\n+\t\tif (rc != 0)\n+\t\t\tgoto fail1;\n+\t}\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+efx_mac_filter_default_rxq_clear(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tif (emop->emo_filter_default_rxq_clear != NULL)\n+\t\temop->emo_filter_default_rxq_clear(enp);\n+}\n+\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_select(\n+\t__in\t\t\t\tefx_nic_t *enp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tefx_mac_type_t type = EFX_MAC_INVALID;\n+\tconst efx_mac_ops_t *emop;\n+\tint rc = EINVAL;\n+\n+\tswitch (enp->en_family) {\n+\n+\tdefault:\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tEFSYS_ASSERT(type != EFX_MAC_INVALID);\n+\tEFSYS_ASSERT3U(type, <, EFX_MAC_NTYPES);\n+\tEFSYS_ASSERT(emop != NULL);\n+\n+\tepp->ep_emop = emop;\n+\tepp->ep_mac_type = type;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\ndiff --git a/drivers/net/sfc/efx/base/efx_mon.c b/drivers/net/sfc/efx/base/efx_mon.c\nnew file mode 100644\nindex 0000000..d3ed40d\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_mon.c\n@@ -0,0 +1,118 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+#if EFSYS_OPT_NAMES\n+\n+static const char * const __efx_mon_name[] = {\n+\t\"\",\n+\t\"sfx90x0\",\n+\t\"sfx91x0\",\n+\t\"sfx92x0\"\n+};\n+\n+\t\tconst char *\n+efx_mon_name(\n+\t__in\tefx_nic_t *enp)\n+{\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\n+\tEFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID);\n+\tEFSYS_ASSERT3U(encp->enc_mon_type, <, EFX_MON_NTYPES);\n+\treturn (__efx_mon_name[encp->enc_mon_type]);\n+}\n+\n+#endif\t/* EFSYS_OPT_NAMES */\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_mon_init(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tefx_mon_t *emp = &(enp->en_mon);\n+\tconst efx_mon_ops_t *emop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\n+\tif (enp->en_mod_flags & EFX_MOD_MON) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tenp->en_mod_flags |= EFX_MOD_MON;\n+\n+\temp->em_type = encp->enc_mon_type;\n+\n+\tEFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID);\n+\tswitch (emp->em_type) {\n+\tdefault:\n+\t\trc = ENOTSUP;\n+\t\tgoto fail2;\n+\t}\n+\n+\temp->em_emop = emop;\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\n+\temp->em_type = EFX_MON_INVALID;\n+\n+\tenp->en_mod_flags &= ~EFX_MOD_MON;\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\tvoid\n+efx_mon_fini(\n+\t__in\tefx_nic_t *enp)\n+{\n+\tefx_mon_t *emp = &(enp->en_mon);\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MON);\n+\n+\temp->em_emop = NULL;\n+\n+\temp->em_type = EFX_MON_INVALID;\n+\n+\tenp->en_mod_flags &= ~EFX_MOD_MON;\n+}\ndiff --git a/drivers/net/sfc/efx/base/efx_nic.c b/drivers/net/sfc/efx/base/efx_nic.c\nnew file mode 100644\nindex 0000000..b5548d7\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_nic.c\n@@ -0,0 +1,549 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+\t__checkReturn\tefx_rc_t\n+efx_family(\n+\t__in\t\tuint16_t venid,\n+\t__in\t\tuint16_t devid,\n+\t__out\t\tefx_family_t *efp)\n+{\n+\tif (venid == EFX_PCI_VENID_SFC) {\n+\t\tswitch (devid) {\n+\n+\t\tcase EFX_PCI_DEVID_FALCON:\t/* Obsolete, not supported */\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t*efp = EFX_FAMILY_INVALID;\n+\treturn (ENOTSUP);\n+}\n+\n+\n+#define\tEFX_BIU_MAGIC0\t0x01234567\n+#define\tEFX_BIU_MAGIC1\t0xfedcba98\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_biu_test(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_oword_t oword;\n+\tefx_rc_t rc;\n+\n+\t/*\n+\t * Write magic values to scratch registers 0 and 1, then\n+\t * verify that the values were written correctly.  Interleave\n+\t * the accesses to ensure that the BIU is not just reading\n+\t * back the cached value that was last written.\n+\t */\n+\tEFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);\n+\tEFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);\n+\n+\tEFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);\n+\tEFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);\n+\n+\tEFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);\n+\tif (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {\n+\t\trc = EIO;\n+\t\tgoto fail1;\n+\t}\n+\n+\tEFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);\n+\tif (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {\n+\t\trc = EIO;\n+\t\tgoto fail2;\n+\t}\n+\n+\t/*\n+\t * Perform the same test, with the values swapped.  This\n+\t * ensures that subsequent tests don't start with the correct\n+\t * values already written into the scratch registers.\n+\t */\n+\tEFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);\n+\tEFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);\n+\n+\tEFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);\n+\tEFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);\n+\n+\tEFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);\n+\tif (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {\n+\t\trc = EIO;\n+\t\tgoto fail3;\n+\t}\n+\n+\tEFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);\n+\tif (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {\n+\t\trc = EIO;\n+\t\tgoto fail4;\n+\t}\n+\n+\treturn (0);\n+\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_create(\n+\t__in\t\tefx_family_t family,\n+\t__in\t\tefsys_identifier_t *esip,\n+\t__in\t\tefsys_bar_t *esbp,\n+\t__in\t\tefsys_lock_t *eslp,\n+\t__deref_out\tefx_nic_t **enpp)\n+{\n+\tefx_nic_t *enp;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);\n+\tEFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);\n+\n+\t/* Allocate a NIC object */\n+\tEFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);\n+\n+\tif (enp == NULL) {\n+\t\trc = ENOMEM;\n+\t\tgoto fail1;\n+\t}\n+\n+\tenp->en_magic = EFX_NIC_MAGIC;\n+\n+\tswitch (family) {\n+\n+\tdefault:\n+\t\trc = ENOTSUP;\n+\t\tgoto fail2;\n+\t}\n+\n+\tenp->en_family = family;\n+\tenp->en_esip = esip;\n+\tenp->en_esbp = esbp;\n+\tenp->en_eslp = eslp;\n+\n+\t*enpp = enp;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\n+\tenp->en_magic = 0;\n+\n+\t/* Free the NIC object */\n+\tEFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_probe(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_nic_ops_t *enop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));\n+\n+\tenop = enp->en_enop;\n+\tif ((rc = enop->eno_probe(enp)) != 0)\n+\t\tgoto fail1;\n+\n+\tif ((rc = efx_phy_probe(enp)) != 0)\n+\t\tgoto fail2;\n+\n+\tenp->en_mod_flags |= EFX_MOD_PROBE;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\n+\tenop->eno_unprobe(enp);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_set_drv_limits(\n+\t__inout\t\tefx_nic_t *enp,\n+\t__in\t\tefx_drv_limits_t *edlp)\n+{\n+\tconst efx_nic_ops_t *enop = enp->en_enop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\n+\tif (enop->eno_set_drv_limits != NULL) {\n+\t\tif ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)\n+\t\t\tgoto fail1;\n+\t}\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_get_bar_region(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefx_nic_region_t region,\n+\t__out\t\tuint32_t *offsetp,\n+\t__out\t\tsize_t *sizep)\n+{\n+\tconst efx_nic_ops_t *enop = enp->en_enop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\n+\tif (enop->eno_get_bar_region == NULL) {\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\tif ((rc = (enop->eno_get_bar_region)(enp,\n+\t\t    region, offsetp, sizep)) != 0) {\n+\t\tgoto fail2;\n+\t}\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_get_vi_pool(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tuint32_t *evq_countp,\n+\t__out\t\tuint32_t *rxq_countp,\n+\t__out\t\tuint32_t *txq_countp)\n+{\n+\tconst efx_nic_ops_t *enop = enp->en_enop;\n+\tefx_nic_cfg_t *encp = &enp->en_nic_cfg;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\n+\tif (enop->eno_get_vi_pool != NULL) {\n+\t\tuint32_t vi_count = 0;\n+\n+\t\tif ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)\n+\t\t\tgoto fail1;\n+\n+\t\t*evq_countp = vi_count;\n+\t\t*rxq_countp = vi_count;\n+\t\t*txq_countp = vi_count;\n+\t} else {\n+\t\t/* Use NIC limits as default value */\n+\t\t*evq_countp = encp->enc_evq_limit;\n+\t\t*rxq_countp = encp->enc_rxq_limit;\n+\t\t*txq_countp = encp->enc_txq_limit;\n+\t}\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_init(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_nic_ops_t *enop = enp->en_enop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\n+\tif (enp->en_mod_flags & EFX_MOD_NIC) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif ((rc = enop->eno_init(enp)) != 0)\n+\t\tgoto fail2;\n+\n+\tenp->en_mod_flags |= EFX_MOD_NIC;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+efx_nic_fini(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_nic_ops_t *enop = enp->en_enop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);\n+\tEFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));\n+\n+\tenop->eno_fini(enp);\n+\n+\tenp->en_mod_flags &= ~EFX_MOD_NIC;\n+}\n+\n+\t\t\tvoid\n+efx_nic_unprobe(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_nic_ops_t *enop = enp->en_enop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));\n+\tEFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));\n+\n+\tefx_phy_unprobe(enp);\n+\n+\tenop->eno_unprobe(enp);\n+\n+\tenp->en_mod_flags &= ~EFX_MOD_PROBE;\n+}\n+\n+\t\t\tvoid\n+efx_nic_destroy(\n+\t__in\tefx_nic_t *enp)\n+{\n+\tefsys_identifier_t *esip = enp->en_esip;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);\n+\n+\tenp->en_family = 0;\n+\tenp->en_esip = NULL;\n+\tenp->en_esbp = NULL;\n+\tenp->en_eslp = NULL;\n+\n+\tenp->en_enop = NULL;\n+\n+\tenp->en_magic = 0;\n+\n+\t/* Free the NIC object */\n+\tEFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_reset(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_nic_ops_t *enop = enp->en_enop;\n+\tunsigned int mod_flags;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);\n+\t/*\n+\t * All modules except the MCDI, PROBE, NVRAM, VPD, MON\n+\t * (which we do not reset here) must have been shut down or never\n+\t * initialized.\n+\t *\n+\t * A rule of thumb here is: If the controller or MC reboots, is *any*\n+\t * state lost. If it's lost and needs reapplying, then the module\n+\t * *must* not be initialised during the reset.\n+\t */\n+\tmod_flags = enp->en_mod_flags;\n+\tmod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |\n+\t\t    EFX_MOD_VPD | EFX_MOD_MON);\n+\tEFSYS_ASSERT3U(mod_flags, ==, 0);\n+\tif (mod_flags != 0) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif ((rc = enop->eno_reset(enp)) != 0)\n+\t\tgoto fail2;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\t\tconst efx_nic_cfg_t *\n+efx_nic_cfg_get(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\n+\treturn (&(enp->en_nic_cfg));\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_calculate_pcie_link_bandwidth(\n+\t__in\t\tuint32_t pcie_link_width,\n+\t__in\t\tuint32_t pcie_link_gen,\n+\t__out\t\tuint32_t *bandwidth_mbpsp)\n+{\n+\tuint32_t lane_bandwidth;\n+\tuint32_t total_bandwidth;\n+\tefx_rc_t rc;\n+\n+\tif ((pcie_link_width == 0) || (pcie_link_width > 16) ||\n+\t    !ISP2(pcie_link_width)) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tswitch (pcie_link_gen) {\n+\tcase EFX_PCIE_LINK_SPEED_GEN1:\n+\t\t/* 2.5 Gb/s raw bandwidth with 8b/10b encoding */\n+\t\tlane_bandwidth = 2000;\n+\t\tbreak;\n+\tcase EFX_PCIE_LINK_SPEED_GEN2:\n+\t\t/* 5.0 Gb/s raw bandwidth with 8b/10b encoding */\n+\t\tlane_bandwidth = 4000;\n+\t\tbreak;\n+\tcase EFX_PCIE_LINK_SPEED_GEN3:\n+\t\t/* 8.0 Gb/s raw bandwidth with 128b/130b encoding */\n+\t\tlane_bandwidth = 7877;\n+\t\tbreak;\n+\tdefault:\n+\t\trc = EINVAL;\n+\t\tgoto fail2;\n+\t}\n+\n+\ttotal_bandwidth = lane_bandwidth * pcie_link_width;\n+\t*bandwidth_mbpsp = total_bandwidth;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_nic_check_pcie_link_speed(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tuint32_t pcie_link_width,\n+\t__in\t\tuint32_t pcie_link_gen,\n+\t__out\t\tefx_pcie_link_performance_t *resultp)\n+{\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tuint32_t bandwidth;\n+\tefx_pcie_link_performance_t result;\n+\tefx_rc_t rc;\n+\n+\tif ((encp->enc_required_pcie_bandwidth_mbps == 0) ||\n+\t    (pcie_link_width == 0) || (pcie_link_width == 32) ||\n+\t    (pcie_link_gen == 0)) {\n+\t\t/*\n+\t\t * No usable info on what is required and/or in use. In virtual\n+\t\t * machines, sometimes the PCIe link width is reported as 0 or\n+\t\t * 32, or the speed as 0.\n+\t\t */\n+\t\tresult = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;\n+\t\tgoto out;\n+\t}\n+\n+\t/* Calculate the available bandwidth in megabits per second */\n+\trc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,\n+\t\t\t\t\t    pcie_link_gen, &bandwidth);\n+\tif (rc != 0)\n+\t\tgoto fail1;\n+\n+\tif (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {\n+\t\tresult = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;\n+\t} else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {\n+\t\t/* The link provides enough bandwidth but not optimal latency */\n+\t\tresult = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;\n+\t} else {\n+\t\tresult = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;\n+\t}\n+\n+out:\n+\t*resultp = result;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\ndiff --git a/drivers/net/sfc/efx/base/efx_phy.c b/drivers/net/sfc/efx/base/efx_phy.c\nnew file mode 100644\nindex 0000000..7b9a330\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_phy.c\n@@ -0,0 +1,248 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_phy_probe(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tconst efx_phy_ops_t *epop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\n+\tepp->ep_port = encp->enc_port;\n+\tepp->ep_phy_type = encp->enc_phy_type;\n+\n+\t/* Hook in operations structure */\n+\tswitch (enp->en_family) {\n+\tdefault:\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\n+\tepp->ep_epop = epop;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\tepp->ep_port = 0;\n+\tepp->ep_phy_type = 0;\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_phy_verify(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_phy_ops_t *epop = epp->ep_epop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\treturn (epop->epo_verify(enp));\n+}\n+\n+\t\t\tvoid\n+efx_phy_adv_cap_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tuint32_t flag,\n+\t__out\t\tuint32_t *maskp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\n+\tswitch (flag) {\n+\tcase EFX_PHY_CAP_CURRENT:\n+\t\t*maskp = epp->ep_adv_cap_mask;\n+\t\tbreak;\n+\tcase EFX_PHY_CAP_DEFAULT:\n+\t\t*maskp = epp->ep_default_adv_cap_mask;\n+\t\tbreak;\n+\tcase EFX_PHY_CAP_PERM:\n+\t\t*maskp = epp->ep_phy_cap_mask;\n+\t\tbreak;\n+\tdefault:\n+\t\tEFSYS_ASSERT(B_FALSE);\n+\t\tbreak;\n+\t}\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_phy_adv_cap_set(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tuint32_t mask)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_phy_ops_t *epop = epp->ep_epop;\n+\tuint32_t old_mask;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tif ((mask & ~epp->ep_phy_cap_mask) != 0) {\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif (epp->ep_adv_cap_mask == mask)\n+\t\tgoto done;\n+\n+\told_mask = epp->ep_adv_cap_mask;\n+\tepp->ep_adv_cap_mask = mask;\n+\n+\tif ((rc = epop->epo_reconfigure(enp)) != 0)\n+\t\tgoto fail2;\n+\n+done:\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\n+\tepp->ep_adv_cap_mask = old_mask;\n+\t/* Reconfigure for robustness */\n+\tif (epop->epo_reconfigure(enp) != 0) {\n+\t\t/*\n+\t\t * We may have an inconsistent view of our advertised speed\n+\t\t * capabilities.\n+\t\t */\n+\t\tEFSYS_ASSERT(0);\n+\t}\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\tvoid\n+efx_phy_lp_cap_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tuint32_t *maskp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\t*maskp = epp->ep_lp_cap_mask;\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_phy_oui_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tuint32_t *ouip)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_phy_ops_t *epop = epp->ep_epop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\treturn (epop->epo_oui_get(enp, ouip));\n+}\n+\n+\t\t\tvoid\n+efx_phy_media_type_get(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out\t\tefx_phy_media_type_t *typep)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tif (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)\n+\t\t*typep = epp->ep_module_type;\n+\telse\n+\t\t*typep = epp->ep_fixed_port_type;\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_phy_module_get_info(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tuint8_t dev_addr,\n+\t__in\t\t\tuint8_t offset,\n+\t__in\t\t\tuint8_t len,\n+\t__out_bcount(len)\tuint8_t *data)\n+{\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT(data != NULL);\n+\n+\tif ((uint32_t)offset + len > 0xff) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,\n+\t    offset, len, data)) != 0)\n+\t\tgoto fail2;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\n+\t\t\tvoid\n+efx_phy_unprobe(\n+\t__in\tefx_nic_t *enp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\n+\tepp->ep_epop = NULL;\n+\n+\tepp->ep_adv_cap_mask = 0;\n+\n+\tepp->ep_port = 0;\n+\tepp->ep_phy_type = 0;\n+}\ndiff --git a/drivers/net/sfc/efx/base/efx_phy_ids.h b/drivers/net/sfc/efx/base/efx_phy_ids.h\nnew file mode 100644\nindex 0000000..9d9a0f9\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_phy_ids.h\n@@ -0,0 +1,51 @@\n+/*\n+ * Copyright (c) 2013-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#ifndef\t_SYS_EFX_PHY_IDS_H\n+#define\t_SYS_EFX_PHY_IDS_H\n+\n+#define\tEFX_PHY_NULL\t0\n+\n+typedef enum efx_phy_type_e {\t\t\t/* GENERATED BY scripts/genfwdef */\n+\tEFX_PHY_TXC43128 = 1,\n+\tEFX_PHY_SFX7101 = 3,\n+\tEFX_PHY_QT2022C2 = 4,\n+\tEFX_PHY_PM8358 = 6,\n+\tEFX_PHY_SFT9001A = 8,\n+\tEFX_PHY_QT2025C = 9,\n+\tEFX_PHY_SFT9001B = 10,\n+\tEFX_PHY_QLX111V = 12,\n+\tEFX_PHY_QT2025_KR = 17,\n+\tEFX_PHY_AEL3020 = 18,\n+\tEFX_PHY_XFI_FARMI = 19,\n+} efx_phy_type_t;\n+\n+\n+#endif\t/* _SYS_EFX_PHY_IDS_H */\ndiff --git a/drivers/net/sfc/efx/base/efx_port.c b/drivers/net/sfc/efx/base/efx_port.c\nnew file mode 100644\nindex 0000000..291a8e9\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_port.c\n@@ -0,0 +1,151 @@\n+/*\n+ * Copyright (c) 2009-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+\t__checkReturn\tefx_rc_t\n+efx_port_init(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_phy_ops_t *epop = epp->ep_epop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\n+\tif (enp->en_mod_flags & EFX_MOD_PORT) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tenp->en_mod_flags |= EFX_MOD_PORT;\n+\n+\tepp->ep_mac_type = EFX_MAC_INVALID;\n+\tepp->ep_link_mode = EFX_LINK_UNKNOWN;\n+\tepp->ep_mac_drain = B_TRUE;\n+\n+\t/* Configure the MAC */\n+\tif ((rc = efx_mac_select(enp)) != 0)\n+\t\tgoto fail1;\n+\n+\tepp->ep_emop->emo_reconfigure(enp);\n+\n+\t/* Pick up current phy capababilities */\n+\tefx_port_poll(enp, NULL);\n+\n+\t/*\n+\t * Turn on the PHY if available, otherwise reset it, and\n+\t * reconfigure it with the current configuration.\n+\t */\n+\tif (epop->epo_power != NULL) {\n+\t\tif ((rc = epop->epo_power(enp, B_TRUE)) != 0)\n+\t\t\tgoto fail2;\n+\t} else {\n+\t\tif ((rc = epop->epo_reset(enp)) != 0)\n+\t\t\tgoto fail2;\n+\t}\n+\n+\tEFSYS_ASSERT(enp->en_reset_flags & EFX_RESET_PHY);\n+\tenp->en_reset_flags &= ~EFX_RESET_PHY;\n+\n+\tif ((rc = epop->epo_reconfigure(enp)) != 0)\n+\t\tgoto fail3;\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\tenp->en_mod_flags &= ~EFX_MOD_PORT;\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_port_poll(\n+\t__in\t\tefx_nic_t *enp,\n+\t__out_opt\tefx_link_mode_t\t*link_modep)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tefx_link_mode_t ignore_link_mode;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tEFSYS_ASSERT(emop != NULL);\n+\tEFSYS_ASSERT(!epp->ep_mac_stats_pending);\n+\n+\tif (link_modep == NULL)\n+\t\tlink_modep = &ignore_link_mode;\n+\n+\tif ((rc = emop->emo_poll(enp, link_modep)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+efx_port_fini(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_phy_ops_t *epop = epp->ep_epop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tEFSYS_ASSERT(epp->ep_mac_drain);\n+\n+\tepp->ep_emop = NULL;\n+\tepp->ep_mac_type = EFX_MAC_INVALID;\n+\tepp->ep_mac_drain = B_FALSE;\n+\n+\t/* Turn off the PHY */\n+\tif (epop->epo_power != NULL)\n+\t\t(void) epop->epo_power(enp, B_FALSE);\n+\n+\tenp->en_mod_flags &= ~EFX_MOD_PORT;\n+}\ndiff --git a/drivers/net/sfc/efx/base/efx_rx.c b/drivers/net/sfc/efx/base/efx_rx.c\nnew file mode 100644\nindex 0000000..4129e09\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_rx.c\n@@ -0,0 +1,242 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_rx_init(\n+\t__inout\t\tefx_nic_t *enp)\n+{\n+\tconst efx_rx_ops_t *erxop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\n+\tif (!(enp->en_mod_flags & EFX_MOD_EV)) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif (enp->en_mod_flags & EFX_MOD_RX) {\n+\t\trc = EINVAL;\n+\t\tgoto fail2;\n+\t}\n+\n+\tswitch (enp->en_family) {\n+\n+\tdefault:\n+\t\tEFSYS_ASSERT(0);\n+\t\trc = ENOTSUP;\n+\t\tgoto fail3;\n+\t}\n+\n+\tif ((rc = erxop->erxo_init(enp)) != 0)\n+\t\tgoto fail4;\n+\n+\tenp->en_erxop = erxop;\n+\tenp->en_mod_flags |= EFX_MOD_RX;\n+\treturn (0);\n+\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\tenp->en_erxop = NULL;\n+\tenp->en_mod_flags &= ~EFX_MOD_RX;\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+efx_rx_fini(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_rx_ops_t *erxop = enp->en_erxop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);\n+\tEFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);\n+\n+\terxop->erxo_fini(enp);\n+\n+\tenp->en_erxop = NULL;\n+\tenp->en_mod_flags &= ~EFX_MOD_RX;\n+}\n+\n+\t\t\tvoid\n+efx_rx_qpost(\n+\t__in\t\tefx_rxq_t *erp,\n+\t__in_ecount(n)\tefsys_dma_addr_t *addrp,\n+\t__in\t\tsize_t size,\n+\t__in\t\tunsigned int n,\n+\t__in\t\tunsigned int completed,\n+\t__in\t\tunsigned int added)\n+{\n+\tefx_nic_t *enp = erp->er_enp;\n+\tconst efx_rx_ops_t *erxop = enp->en_erxop;\n+\n+\tEFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);\n+\n+\terxop->erxo_qpost(erp, addrp, size, n, completed, added);\n+}\n+\n+\t\t\tvoid\n+efx_rx_qpush(\n+\t__in\t\tefx_rxq_t *erp,\n+\t__in\t\tunsigned int added,\n+\t__inout\t\tunsigned int *pushedp)\n+{\n+\tefx_nic_t *enp = erp->er_enp;\n+\tconst efx_rx_ops_t *erxop = enp->en_erxop;\n+\n+\tEFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);\n+\n+\terxop->erxo_qpush(erp, added, pushedp);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_rx_qflush(\n+\t__in\t\tefx_rxq_t *erp)\n+{\n+\tefx_nic_t *enp = erp->er_enp;\n+\tconst efx_rx_ops_t *erxop = enp->en_erxop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);\n+\n+\tif ((rc = erxop->erxo_qflush(erp)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+efx_rx_qenable(\n+\t__in\t\tefx_rxq_t *erp)\n+{\n+\tefx_nic_t *enp = erp->er_enp;\n+\tconst efx_rx_ops_t *erxop = enp->en_erxop;\n+\n+\tEFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);\n+\n+\terxop->erxo_qenable(erp);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_rx_qcreate(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int index,\n+\t__in\t\tunsigned int label,\n+\t__in\t\tefx_rxq_type_t type,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tsize_t n,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tefx_evq_t *eep,\n+\t__deref_out\tefx_rxq_t **erpp)\n+{\n+\tconst efx_rx_ops_t *erxop = enp->en_erxop;\n+\tefx_rxq_t *erp;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);\n+\n+\t/* Allocate an RXQ object */\n+\tEFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);\n+\n+\tif (erp == NULL) {\n+\t\trc = ENOMEM;\n+\t\tgoto fail1;\n+\t}\n+\n+\terp->er_magic = EFX_RXQ_MAGIC;\n+\terp->er_enp = enp;\n+\terp->er_index = index;\n+\terp->er_mask = n - 1;\n+\terp->er_esmp = esmp;\n+\n+\tif ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,\n+\t    eep, erp)) != 0)\n+\t\tgoto fail2;\n+\n+\tenp->en_rx_qcount++;\n+\t*erpp = erp;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\n+\tEFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+efx_rx_qdestroy(\n+\t__in\t\tefx_rxq_t *erp)\n+{\n+\tefx_nic_t *enp = erp->er_enp;\n+\tconst efx_rx_ops_t *erxop = enp->en_erxop;\n+\n+\tEFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);\n+\n+\terxop->erxo_qdestroy(erp);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_psuedo_hdr_pkt_length_get(\n+\t__in\t\tefx_rxq_t *erp,\n+\t__in\t\tuint8_t *buffer,\n+\t__out\t\tuint16_t *lengthp)\n+{\n+\tefx_nic_t *enp = erp->er_enp;\n+\tconst efx_rx_ops_t *erxop = enp->en_erxop;\n+\n+\tEFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);\n+\n+\treturn (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));\n+}\n+\ndiff --git a/drivers/net/sfc/efx/base/efx_sram.c b/drivers/net/sfc/efx/base/efx_sram.c\nnew file mode 100644\nindex 0000000..0f16376\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_sram.c\n@@ -0,0 +1,168 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+\t__checkReturn\tefx_rc_t\n+efx_sram_buf_tbl_set(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tsize_t n)\n+{\n+\tefx_qword_t qword;\n+\tuint32_t start = id;\n+\tuint32_t stop = start + n;\n+\tefsys_dma_addr_t addr;\n+\tefx_oword_t oword;\n+\tunsigned int count;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\n+\tif (stop >= EFX_BUF_TBL_SIZE) {\n+\t\trc = EFBIG;\n+\t\tgoto fail1;\n+\t}\n+\n+\t/* Add the entries into the buffer table */\n+\taddr = EFSYS_MEM_ADDR(esmp);\n+\tfor (id = start; id != stop; id++) {\n+\t\tEFX_POPULATE_QWORD_5(qword,\n+\t\t    FRF_AZ_IP_DAT_BUF_SIZE, 0, FRF_AZ_BUF_ADR_REGION, 0,\n+\t\t    FRF_AZ_BUF_ADR_FBUF_DW0,\n+\t\t    (uint32_t)((addr >> 12) & 0xffffffff),\n+\t\t    FRF_AZ_BUF_ADR_FBUF_DW1,\n+\t\t    (uint32_t)((addr >> 12) >> 32),\n+\t\t    FRF_AZ_BUF_OWNER_ID_FBUF, 0);\n+\n+\t\tEFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_FULL_TBL,\n+\t\t\t\t    id, &qword);\n+\n+\t\taddr += EFX_BUF_SIZE;\n+\t}\n+\n+\tEFSYS_PROBE2(buf, uint32_t, start, uint32_t, stop - 1);\n+\n+\t/* Flush the write buffer */\n+\tEFX_POPULATE_OWORD_2(oword, FRF_AZ_BUF_UPD_CMD, 1,\n+\t    FRF_AZ_BUF_CLR_CMD, 0);\n+\tEFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword);\n+\n+\t/* Poll for the last entry being written to the buffer table */\n+\tEFSYS_ASSERT3U(id, ==, stop);\n+\taddr -= EFX_BUF_SIZE;\n+\n+\tcount = 0;\n+\tdo {\n+\t\tEFSYS_PROBE1(wait, unsigned int, count);\n+\n+\t\t/* Spin for 1 ms */\n+\t\tEFSYS_SPIN(1000);\n+\n+\t\tEFX_BAR_TBL_READQ(enp, FR_AZ_BUF_FULL_TBL,\n+\t\t\t\t    id - 1, &qword);\n+\n+\t\tif (EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW0) ==\n+\t\t    (uint32_t)((addr >> 12) & 0xffffffff) &&\n+\t\t    EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW1) ==\n+\t\t    (uint32_t)((addr >> 12) >> 32))\n+\t\t\tgoto verify;\n+\n+\t} while (++count < 100);\n+\n+\trc = ETIMEDOUT;\n+\tgoto fail2;\n+\n+verify:\n+\t/* Verify the rest of the entries in the buffer table */\n+\twhile (--id != start) {\n+\t\taddr -= EFX_BUF_SIZE;\n+\n+\t\t/* Read the buffer table entry */\n+\t\tEFX_BAR_TBL_READQ(enp, FR_AZ_BUF_FULL_TBL,\n+\t\t\t\t    id - 1, &qword);\n+\n+\t\tif (EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW0) !=\n+\t\t    (uint32_t)((addr >> 12) & 0xffffffff) ||\n+\t\t    EFX_QWORD_FIELD(qword, FRF_AZ_BUF_ADR_FBUF_DW1) !=\n+\t\t    (uint32_t)((addr >> 12) >> 32)) {\n+\t\t\trc = EFAULT;\n+\t\t\tgoto fail3;\n+\t\t}\n+\t}\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+\n+\tid = stop;\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\n+\tEFX_POPULATE_OWORD_4(oword, FRF_AZ_BUF_UPD_CMD, 0,\n+\t    FRF_AZ_BUF_CLR_CMD, 1, FRF_AZ_BUF_CLR_END_ID, id - 1,\n+\t    FRF_AZ_BUF_CLR_START_ID, start);\n+\tEFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\tvoid\n+efx_sram_buf_tbl_clear(\n+\t__in\tefx_nic_t *enp,\n+\t__in\tuint32_t id,\n+\t__in\tsize_t n)\n+{\n+\tefx_oword_t oword;\n+\tuint32_t start = id;\n+\tuint32_t stop = start + n;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\n+\tEFSYS_ASSERT3U(stop, <, EFX_BUF_TBL_SIZE);\n+\n+\tEFSYS_PROBE2(buf, uint32_t, start, uint32_t, stop - 1);\n+\n+\tEFX_POPULATE_OWORD_4(oword, FRF_AZ_BUF_UPD_CMD, 0,\n+\t    FRF_AZ_BUF_CLR_CMD, 1, FRF_AZ_BUF_CLR_END_ID, stop - 1,\n+\t    FRF_AZ_BUF_CLR_START_ID, start);\n+\tEFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword);\n+}\n+\n+\ndiff --git a/drivers/net/sfc/efx/base/efx_tx.c b/drivers/net/sfc/efx/base/efx_tx.c\nnew file mode 100644\nindex 0000000..4f0099f\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_tx.c\n@@ -0,0 +1,463 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#include \"efx.h\"\n+#include \"efx_impl.h\"\n+\n+#define\tEFX_TX_QSTAT_INCR(_etp, _stat)\n+\n+\n+\t__checkReturn\tefx_rc_t\n+efx_tx_init(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tconst efx_tx_ops_t *etxop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\n+\tif (!(enp->en_mod_flags & EFX_MOD_EV)) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif (enp->en_mod_flags & EFX_MOD_TX) {\n+\t\trc = EINVAL;\n+\t\tgoto fail2;\n+\t}\n+\n+\tswitch (enp->en_family) {\n+\n+\tdefault:\n+\t\tEFSYS_ASSERT(0);\n+\t\trc = ENOTSUP;\n+\t\tgoto fail3;\n+\t}\n+\n+\tEFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0);\n+\n+\tif ((rc = etxop->etxo_init(enp)) != 0)\n+\t\tgoto fail4;\n+\n+\tenp->en_etxop = etxop;\n+\tenp->en_mod_flags |= EFX_MOD_TX;\n+\treturn (0);\n+\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\tenp->en_etxop = NULL;\n+\tenp->en_mod_flags &= ~EFX_MOD_TX;\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+efx_tx_fini(\n+\t__in\tefx_nic_t *enp)\n+{\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX);\n+\tEFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0);\n+\n+\tetxop->etxo_fini(enp);\n+\n+\tenp->en_etxop = NULL;\n+\tenp->en_mod_flags &= ~EFX_MOD_TX;\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_tx_qcreate(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tunsigned int index,\n+\t__in\t\tunsigned int label,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tsize_t n,\n+\t__in\t\tuint32_t id,\n+\t__in\t\tuint16_t flags,\n+\t__in\t\tefx_evq_t *eep,\n+\t__deref_out\tefx_txq_t **etpp,\n+\t__out\t\tunsigned int *addedp)\n+{\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tefx_txq_t *etp;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX);\n+\n+\tEFSYS_ASSERT3U(enp->en_tx_qcount + 1, <, encp->enc_txq_limit);\n+\n+\t/* Allocate an TXQ object */\n+\tEFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_txq_t), etp);\n+\n+\tif (etp == NULL) {\n+\t\trc = ENOMEM;\n+\t\tgoto fail1;\n+\t}\n+\n+\tetp->et_magic = EFX_TXQ_MAGIC;\n+\tetp->et_enp = enp;\n+\tetp->et_index = index;\n+\tetp->et_mask = n - 1;\n+\tetp->et_esmp = esmp;\n+\n+\t/* Initial descriptor index may be modified by etxo_qcreate */\n+\t*addedp = 0;\n+\n+\tif ((rc = etxop->etxo_qcreate(enp, index, label, esmp,\n+\t    n, id, flags, eep, etp, addedp)) != 0)\n+\t\tgoto fail2;\n+\n+\tenp->en_tx_qcount++;\n+\t*etpp = etp;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+\tEFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t\tvoid\n+efx_tx_qdestroy(\n+\t__in\tefx_txq_t *etp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tEFSYS_ASSERT(enp->en_tx_qcount != 0);\n+\t--enp->en_tx_qcount;\n+\n+\tetxop->etxo_qdestroy(etp);\n+\n+\t/* Free the TXQ object */\n+\tEFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_tx_qpost(\n+\t__in\t\tefx_txq_t *etp,\n+\t__in_ecount(n)\tefx_buffer_t *eb,\n+\t__in\t\tunsigned int n,\n+\t__in\t\tunsigned int completed,\n+\t__inout\t\tunsigned int *addedp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tif ((rc = etxop->etxo_qpost(etp, eb,\n+\t    n, completed, addedp)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+efx_tx_qpush(\n+\t__in\tefx_txq_t *etp,\n+\t__in\tunsigned int added,\n+\t__in\tunsigned int pushed)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tetxop->etxo_qpush(etp, added, pushed);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_tx_qpace(\n+\t__in\t\tefx_txq_t *etp,\n+\t__in\t\tunsigned int ns)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tif ((rc = etxop->etxo_qpace(etp, ns)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_tx_qflush(\n+\t__in\tefx_txq_t *etp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tif ((rc = etxop->etxo_qflush(etp)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t\t\tvoid\n+efx_tx_qenable(\n+\t__in\tefx_txq_t *etp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tetxop->etxo_qenable(etp);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_tx_qpio_enable(\n+\t__in\tefx_txq_t *etp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tif (~enp->en_features & EFX_FEATURE_PIO_BUFFERS) {\n+\t\trc = ENOTSUP;\n+\t\tgoto fail1;\n+\t}\n+\tif (etxop->etxo_qpio_enable == NULL) {\n+\t\trc = ENOTSUP;\n+\t\tgoto fail2;\n+\t}\n+\tif ((rc = etxop->etxo_qpio_enable(etp)) != 0)\n+\t\tgoto fail3;\n+\n+\treturn (0);\n+\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t\tvoid\n+efx_tx_qpio_disable(\n+\t__in\tefx_txq_t *etp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tif (etxop->etxo_qpio_disable != NULL)\n+\t\tetxop->etxo_qpio_disable(etp);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_tx_qpio_write(\n+\t__in\t\t\tefx_txq_t *etp,\n+\t__in_ecount(buf_length)\tuint8_t *buffer,\n+\t__in\t\t\tsize_t buf_length,\n+\t__in\t\t\tsize_t pio_buf_offset)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tif (etxop->etxo_qpio_write != NULL) {\n+\t\tif ((rc = etxop->etxo_qpio_write(etp, buffer, buf_length,\n+\t\t\t\t\t\tpio_buf_offset)) != 0)\n+\t\t\tgoto fail1;\n+\t\treturn (0);\n+\t}\n+\n+\treturn (ENOTSUP);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_tx_qpio_post(\n+\t__in\t\t\tefx_txq_t *etp,\n+\t__in\t\t\tsize_t pkt_length,\n+\t__in\t\t\tunsigned int completed,\n+\t__inout\t\t\tunsigned int *addedp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tif (etxop->etxo_qpio_post != NULL) {\n+\t\tif ((rc = etxop->etxo_qpio_post(etp, pkt_length, completed,\n+\t\t\t\t\t\taddedp)) != 0)\n+\t\t\tgoto fail1;\n+\t\treturn (0);\n+\t}\n+\n+\treturn (ENOTSUP);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_tx_qdesc_post(\n+\t__in\t\tefx_txq_t *etp,\n+\t__in_ecount(n)\tefx_desc_t *ed,\n+\t__in\t\tunsigned int n,\n+\t__in\t\tunsigned int completed,\n+\t__inout\t\tunsigned int *addedp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\n+\tif ((rc = etxop->etxo_qdesc_post(etp, ed,\n+\t    n, completed, addedp)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\treturn (rc);\n+}\n+\n+\tvoid\n+efx_tx_qdesc_dma_create(\n+\t__in\tefx_txq_t *etp,\n+\t__in\tefsys_dma_addr_t addr,\n+\t__in\tsize_t size,\n+\t__in\tboolean_t eop,\n+\t__out\tefx_desc_t *edp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\tEFSYS_ASSERT(etxop->etxo_qdesc_dma_create != NULL);\n+\n+\tetxop->etxo_qdesc_dma_create(etp, addr, size, eop, edp);\n+}\n+\n+\tvoid\n+efx_tx_qdesc_tso_create(\n+\t__in\tefx_txq_t *etp,\n+\t__in\tuint16_t ipv4_id,\n+\t__in\tuint32_t tcp_seq,\n+\t__in\tuint8_t  tcp_flags,\n+\t__out\tefx_desc_t *edp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\tEFSYS_ASSERT(etxop->etxo_qdesc_tso_create != NULL);\n+\n+\tetxop->etxo_qdesc_tso_create(etp, ipv4_id, tcp_seq, tcp_flags, edp);\n+}\n+\n+\tvoid\n+efx_tx_qdesc_tso2_create(\n+\t__in\t\t\tefx_txq_t *etp,\n+\t__in\t\t\tuint16_t ipv4_id,\n+\t__in\t\t\tuint32_t tcp_seq,\n+\t__in\t\t\tuint16_t mss,\n+\t__out_ecount(count)\tefx_desc_t *edp,\n+\t__in\t\t\tint count)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\tEFSYS_ASSERT(etxop->etxo_qdesc_tso2_create != NULL);\n+\n+\tetxop->etxo_qdesc_tso2_create(etp, ipv4_id, tcp_seq, mss, edp, count);\n+}\n+\n+\tvoid\n+efx_tx_qdesc_vlantci_create(\n+\t__in\tefx_txq_t *etp,\n+\t__in\tuint16_t tci,\n+\t__out\tefx_desc_t *edp)\n+{\n+\tefx_nic_t *enp = etp->et_enp;\n+\tconst efx_tx_ops_t *etxop = enp->en_etxop;\n+\n+\tEFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);\n+\tEFSYS_ASSERT(etxop->etxo_qdesc_vlantci_create != NULL);\n+\n+\tetxop->etxo_qdesc_vlantci_create(etp, tci, edp);\n+}\n+\n+\ndiff --git a/drivers/net/sfc/efx/base/efx_types.h b/drivers/net/sfc/efx/base/efx_types.h\nnew file mode 100644\nindex 0000000..b8ee14a\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_types.h\n@@ -0,0 +1,1647 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ *\n+ * Ackowledgement to Fen Systems Ltd.\n+ */\n+\n+#ifndef\t_SYS_EFX_TYPES_H\n+#define\t_SYS_EFX_TYPES_H\n+\n+#include \"efsys.h\"\n+\n+#ifdef\t__cplusplus\n+extern \"C\" {\n+#endif\n+\n+/*\n+ * Bitfield access\n+ *\n+ * Solarflare NICs make extensive use of bitfields up to 128 bits\n+ * wide.  Since there is no native 128-bit datatype on most systems,\n+ * and since 64-bit datatypes are inefficient on 32-bit systems and\n+ * vice versa, we wrap accesses in a way that uses the most efficient\n+ * datatype.\n+ *\n+ * The NICs are PCI devices and therefore little-endian.  Since most\n+ * of the quantities that we deal with are DMAed to/from host memory,\n+ * we define\tour datatypes (efx_oword_t, efx_qword_t and efx_dword_t)\n+ * to be little-endian.\n+ *\n+ * In the less common case of using PIO for individual register\n+ * writes, we construct the little-endian datatype in host memory and\n+ * then use non-swapping register access primitives, rather than\n+ * constructing a native-endian datatype and relying on implicit\n+ * byte-swapping.  (We use a similar strategy for register reads.)\n+ */\n+\n+/*\n+ * NOTE: Field definitions here and elsewhere are done in terms of a lowest\n+ *       bit number (LBN) and a width.\n+ */\n+\n+#define\tEFX_DUMMY_FIELD_LBN 0\n+#define\tEFX_DUMMY_FIELD_WIDTH 0\n+\n+#define\tEFX_BYTE_0_LBN 0\n+#define\tEFX_BYTE_0_WIDTH 8\n+\n+#define\tEFX_BYTE_1_LBN 8\n+#define\tEFX_BYTE_1_WIDTH 8\n+\n+#define\tEFX_BYTE_2_LBN 16\n+#define\tEFX_BYTE_2_WIDTH 8\n+\n+#define\tEFX_BYTE_3_LBN 24\n+#define\tEFX_BYTE_3_WIDTH 8\n+\n+#define\tEFX_BYTE_4_LBN 32\n+#define\tEFX_BYTE_4_WIDTH 8\n+\n+#define\tEFX_BYTE_5_LBN 40\n+#define\tEFX_BYTE_5_WIDTH 8\n+\n+#define\tEFX_BYTE_6_LBN 48\n+#define\tEFX_BYTE_6_WIDTH 8\n+\n+#define\tEFX_BYTE_7_LBN 56\n+#define\tEFX_BYTE_7_WIDTH 8\n+\n+#define\tEFX_WORD_0_LBN 0\n+#define\tEFX_WORD_0_WIDTH 16\n+\n+#define\tEFX_WORD_1_LBN 16\n+#define\tEFX_WORD_1_WIDTH 16\n+\n+#define\tEFX_WORD_2_LBN 32\n+#define\tEFX_WORD_2_WIDTH 16\n+\n+#define\tEFX_WORD_3_LBN 48\n+#define\tEFX_WORD_3_WIDTH 16\n+\n+#define\tEFX_DWORD_0_LBN 0\n+#define\tEFX_DWORD_0_WIDTH 32\n+\n+#define\tEFX_DWORD_1_LBN 32\n+#define\tEFX_DWORD_1_WIDTH 32\n+\n+#define\tEFX_DWORD_2_LBN 64\n+#define\tEFX_DWORD_2_WIDTH 32\n+\n+#define\tEFX_DWORD_3_LBN 96\n+#define\tEFX_DWORD_3_WIDTH 32\n+\n+/* There are intentionally no EFX_QWORD_0 or EFX_QWORD_1 field definitions\n+ * here as the implementaion of EFX_QWORD_FIELD and EFX_OWORD_FIELD do not\n+ * support field widths larger than 32 bits.\n+ */\n+\n+/* Specified attribute (i.e. LBN ow WIDTH) of the specified field */\n+#define\tEFX_VAL(_field, _attribute)\t\t\t\t\t\\\n+\t_field ## _ ## _attribute\n+\n+/* Lowest bit number of the specified field */\n+#define\tEFX_LOW_BIT(_field)\t\t\t\t\t\t\\\n+\tEFX_VAL(_field, LBN)\n+\n+/* Width of the specified field */\n+#define\tEFX_WIDTH(_field)\t\t\t\t\t\t\\\n+\tEFX_VAL(_field, WIDTH)\n+\n+/* Highest bit number of the specified field */\n+#define\tEFX_HIGH_BIT(_field)\t\t\t\t\t\t\\\n+\t(EFX_LOW_BIT(_field) + EFX_WIDTH(_field) - 1)\n+\n+/*\n+ * 64-bit mask equal in width to the specified field.\n+ *\n+ * For example, a field with width 5 would have a mask of 0x000000000000001f.\n+ */\n+#define\tEFX_MASK64(_field)\t\t\t\t\t\t\\\n+\t((EFX_WIDTH(_field) == 64) ? ~((uint64_t)0) :\t\t\t\\\n+\t    (((((uint64_t)1) << EFX_WIDTH(_field))) - 1))\n+/*\n+ * 32-bit mask equal in width to the specified field.\n+ *\n+ * For example, a field with width 5 would have a mask of 0x0000001f.\n+ */\n+#define\tEFX_MASK32(_field)\t\t\t\t\t\t\\\n+\t((EFX_WIDTH(_field) == 32) ? ~((uint32_t)0) :\t\t\t\\\n+\t    (((((uint32_t)1) << EFX_WIDTH(_field))) - 1))\n+\n+/*\n+ * 16-bit mask equal in width to the specified field.\n+ *\n+ * For example, a field with width 5 would have a mask of 0x001f.\n+ */\n+#define\tEFX_MASK16(_field)\t\t\t\t\t\t\\\n+\t((EFX_WIDTH(_field) == 16) ? 0xffffu :\t\t\t\t\\\n+\t    (uint16_t)((1 << EFX_WIDTH(_field)) - 1))\n+\n+/*\n+ * 8-bit mask equal in width to the specified field.\n+ *\n+ * For example, a field with width 5 would have a mask of 0x1f.\n+ */\n+#define\tEFX_MASK8(_field)\t\t\t\t\t\t\\\n+\t((uint8_t)((1 << EFX_WIDTH(_field)) - 1))\n+\n+#pragma pack(1)\n+\n+/*\n+ * A byte (i.e. 8-bit) datatype\n+ */\n+typedef union efx_byte_u {\n+\tuint8_t eb_u8[1];\n+} efx_byte_t;\n+\n+/*\n+ * A word (i.e. 16-bit) datatype\n+ *\n+ * This datatype is defined to be little-endian.\n+ */\n+typedef union efx_word_u {\n+\tefx_byte_t ew_byte[2];\n+\tuint16_t ew_u16[1];\n+\tuint8_t ew_u8[2];\n+} efx_word_t;\n+\n+/*\n+ * A doubleword (i.e. 32-bit) datatype\n+ *\n+ * This datatype is defined to be little-endian.\n+ */\n+typedef union efx_dword_u {\n+\tefx_byte_t ed_byte[4];\n+\tefx_word_t ed_word[2];\n+\tuint32_t ed_u32[1];\n+\tuint16_t ed_u16[2];\n+\tuint8_t ed_u8[4];\n+} efx_dword_t;\n+\n+/*\n+ * A quadword (i.e. 64-bit) datatype\n+ *\n+ * This datatype is defined to be little-endian.\n+ */\n+typedef union efx_qword_u {\n+\tefx_byte_t eq_byte[8];\n+\tefx_word_t eq_word[4];\n+\tefx_dword_t eq_dword[2];\n+#if EFSYS_HAS_UINT64\n+\tuint64_t eq_u64[1];\n+#endif\n+\tuint32_t eq_u32[2];\n+\tuint16_t eq_u16[4];\n+\tuint8_t eq_u8[8];\n+} efx_qword_t;\n+\n+/*\n+ * An octword (i.e. 128-bit) datatype\n+ *\n+ * This datatype is defined to be little-endian.\n+ */\n+typedef union efx_oword_u {\n+\tefx_byte_t eo_byte[16];\n+\tefx_word_t eo_word[8];\n+\tefx_dword_t eo_dword[4];\n+\tefx_qword_t eo_qword[2];\n+#if EFSYS_HAS_SSE2_M128\n+\t__m128i eo_u128[1];\n+#endif\n+#if EFSYS_HAS_UINT64\n+\tuint64_t eo_u64[2];\n+#endif\n+\tuint32_t eo_u32[4];\n+\tuint16_t eo_u16[8];\n+\tuint8_t eo_u8[16];\n+} efx_oword_t;\n+\n+#pragma pack()\n+\n+#define\t__SWAP16(_x)\t\t\t\t\\\n+\t((((_x) & 0xff) << 8) |\t\t\t\\\n+\t(((_x) >> 8) & 0xff))\n+\n+#define\t__SWAP32(_x)\t\t\t\t\\\n+\t((__SWAP16((_x) & 0xffff) << 16) |\t\\\n+\t__SWAP16(((_x) >> 16) & 0xffff))\n+\n+#define\t__SWAP64(_x)\t\t\t\t\\\n+\t((__SWAP32((_x) & 0xffffffff) << 32) |\t\\\n+\t__SWAP32(((_x) >> 32) & 0xffffffff))\n+\n+#define\t__NOSWAP16(_x)\t\t(_x)\n+#define\t__NOSWAP32(_x)\t\t(_x)\n+#define\t__NOSWAP64(_x)\t\t(_x)\n+\n+#if EFSYS_IS_BIG_ENDIAN\n+\n+#define\t__CPU_TO_LE_16(_x)\t((uint16_t)__SWAP16(_x))\n+#define\t__LE_TO_CPU_16(_x)\t((uint16_t)__SWAP16(_x))\n+#define\t__CPU_TO_BE_16(_x)\t((uint16_t)__NOSWAP16(_x))\n+#define\t__BE_TO_CPU_16(_x)\t((uint16_t)__NOSWAP16(_x))\n+\n+#define\t__CPU_TO_LE_32(_x)\t((uint32_t)__SWAP32(_x))\n+#define\t__LE_TO_CPU_32(_x)\t((uint32_t)__SWAP32(_x))\n+#define\t__CPU_TO_BE_32(_x)\t((uint32_t)__NOSWAP32(_x))\n+#define\t__BE_TO_CPU_32(_x)\t((uint32_t)__NOSWAP32(_x))\n+\n+#define\t__CPU_TO_LE_64(_x)\t((uint64_t)__SWAP64(_x))\n+#define\t__LE_TO_CPU_64(_x)\t((uint64_t)__SWAP64(_x))\n+#define\t__CPU_TO_BE_64(_x)\t((uint64_t)__NOSWAP64(_x))\n+#define\t__BE_TO_CPU_64(_x)\t((uint64_t)__NOSWAP64(_x))\n+\n+#elif EFSYS_IS_LITTLE_ENDIAN\n+\n+#define\t__CPU_TO_LE_16(_x)\t((uint16_t)__NOSWAP16(_x))\n+#define\t__LE_TO_CPU_16(_x)\t((uint16_t)__NOSWAP16(_x))\n+#define\t__CPU_TO_BE_16(_x)\t((uint16_t)__SWAP16(_x))\n+#define\t__BE_TO_CPU_16(_x)\t((uint16_t)__SWAP16(_x))\n+\n+#define\t__CPU_TO_LE_32(_x)\t((uint32_t)__NOSWAP32(_x))\n+#define\t__LE_TO_CPU_32(_x)\t((uint32_t)__NOSWAP32(_x))\n+#define\t__CPU_TO_BE_32(_x)\t((uint32_t)__SWAP32(_x))\n+#define\t__BE_TO_CPU_32(_x)\t((uint32_t)__SWAP32(_x))\n+\n+#define\t__CPU_TO_LE_64(_x)\t((uint64_t)__NOSWAP64(_x))\n+#define\t__LE_TO_CPU_64(_x)\t((uint64_t)__NOSWAP64(_x))\n+#define\t__CPU_TO_BE_64(_x)\t((uint64_t)__SWAP64(_x))\n+#define\t__BE_TO_CPU_64(_x)\t((uint64_t)__SWAP64(_x))\n+\n+#else\n+\n+#error \"Neither of EFSYS_IS_{BIG,LITTLE}_ENDIAN is set\"\n+\n+#endif\n+\n+#define\t__NATIVE_8(_x)\t(uint8_t)(_x)\n+\n+/* Format string for printing an efx_byte_t */\n+#define\tEFX_BYTE_FMT \"0x%02x\"\n+\n+/* Format string for printing an efx_word_t */\n+#define\tEFX_WORD_FMT \"0x%04x\"\n+\n+/* Format string for printing an efx_dword_t */\n+#define\tEFX_DWORD_FMT \"0x%08x\"\n+\n+/* Format string for printing an efx_qword_t */\n+#define\tEFX_QWORD_FMT \"0x%08x:%08x\"\n+\n+/* Format string for printing an efx_oword_t */\n+#define\tEFX_OWORD_FMT \"0x%08x:%08x:%08x:%08x\"\n+\n+/* Parameters for printing an efx_byte_t */\n+#define\tEFX_BYTE_VAL(_byte)\t\t\t\t\t\\\n+\t((unsigned int)__NATIVE_8((_byte).eb_u8[0]))\n+\n+/* Parameters for printing an efx_word_t */\n+#define\tEFX_WORD_VAL(_word)\t\t\t\t\t\\\n+\t((unsigned int)__LE_TO_CPU_16((_word).ew_u16[0]))\n+\n+/* Parameters for printing an efx_dword_t */\n+#define\tEFX_DWORD_VAL(_dword)\t\t\t\t\t\\\n+\t((unsigned int)__LE_TO_CPU_32((_dword).ed_u32[0]))\n+\n+/* Parameters for printing an efx_qword_t */\n+#define\tEFX_QWORD_VAL(_qword)\t\t\t\t\t\\\n+\t((unsigned int)__LE_TO_CPU_32((_qword).eq_u32[1])),\t\\\n+\t((unsigned int)__LE_TO_CPU_32((_qword).eq_u32[0]))\n+\n+/* Parameters for printing an efx_oword_t */\n+#define\tEFX_OWORD_VAL(_oword)\t\t\t\t\t\\\n+\t((unsigned int)__LE_TO_CPU_32((_oword).eo_u32[3])),\t\\\n+\t((unsigned int)__LE_TO_CPU_32((_oword).eo_u32[2])),\t\\\n+\t((unsigned int)__LE_TO_CPU_32((_oword).eo_u32[1])),\t\\\n+\t((unsigned int)__LE_TO_CPU_32((_oword).eo_u32[0]))\n+\n+/*\n+ * Stop lint complaining about some shifts.\n+ */\n+#ifdef\t__lint\n+extern int fix_lint;\n+#define\tFIX_LINT(_x)\t(_x + fix_lint)\n+#else\n+#define\tFIX_LINT(_x)\t(_x)\n+#endif\n+\n+/*\n+ * Extract bit field portion [low,high) from the native-endian element\n+ * which contains bits [min,max).\n+ *\n+ * For example, suppose \"element\" represents the high 32 bits of a\n+ * 64-bit value, and we wish to extract the bits belonging to the bit\n+ * field occupying bits 28-45 of this 64-bit value.\n+ *\n+ * Then EFX_EXTRACT(_element, 32, 63, 28, 45) would give\n+ *\n+ *   (_element) << 4\n+ *\n+ * The result will contain the relevant bits filled in in the range\n+ * [0,high-low), with garbage in bits [high-low+1,...).\n+ */\n+#define\tEFX_EXTRACT_NATIVE(_element, _min, _max, _low, _high)\t\t\\\n+\t((FIX_LINT(_low > _max) || FIX_LINT(_high < _min)) ?\t\t\\\n+\t\t0U :\t\t\t\t\t\t\t\\\n+\t\t((_low > _min) ?\t\t\t\t\t\\\n+\t\t\t((_element) >> (_low - _min)) :\t\t\t\\\n+\t\t\t((_element) << (_min - _low))))\n+\n+/*\n+ * Extract bit field portion [low,high) from the 64-bit little-endian\n+ * element which contains bits [min,max)\n+ */\n+#define\tEFX_EXTRACT64(_element, _min, _max, _low, _high)\t\t\\\n+\tEFX_EXTRACT_NATIVE(__LE_TO_CPU_64(_element), _min, _max, _low, _high)\n+\n+/*\n+ * Extract bit field portion [low,high) from the 32-bit little-endian\n+ * element which contains bits [min,max)\n+ */\n+#define\tEFX_EXTRACT32(_element, _min, _max, _low, _high)\t\t\\\n+\tEFX_EXTRACT_NATIVE(__LE_TO_CPU_32(_element), _min, _max, _low, _high)\n+\n+/*\n+ * Extract bit field portion [low,high) from the 16-bit little-endian\n+ * element which contains bits [min,max)\n+ */\n+#define\tEFX_EXTRACT16(_element, _min, _max, _low, _high)\t\t\\\n+\tEFX_EXTRACT_NATIVE(__LE_TO_CPU_16(_element), _min, _max, _low, _high)\n+\n+/*\n+ * Extract bit field portion [low,high) from the 8-bit\n+ * element which contains bits [min,max)\n+ */\n+#define\tEFX_EXTRACT8(_element, _min, _max, _low, _high)\t\t\t\\\n+\tEFX_EXTRACT_NATIVE(__NATIVE_8(_element), _min, _max, _low, _high)\n+\n+#define\tEFX_EXTRACT_OWORD64(_oword, _low, _high)\t\t\t\\\n+\t(EFX_EXTRACT64((_oword).eo_u64[0], FIX_LINT(0), FIX_LINT(63),\t\\\n+\t    _low, _high) |\t\t\t\t\t\t\\\n+\tEFX_EXTRACT64((_oword).eo_u64[1], FIX_LINT(64), FIX_LINT(127),\t\\\n+\t    _low, _high))\n+\n+#define\tEFX_EXTRACT_OWORD32(_oword, _low, _high)\t\t\t\\\n+\t(EFX_EXTRACT32((_oword).eo_u32[0], FIX_LINT(0), FIX_LINT(31),\t\\\n+\t    _low, _high) |\t\t\t\t\t\t\\\n+\tEFX_EXTRACT32((_oword).eo_u32[1], FIX_LINT(32), FIX_LINT(63),\t\\\n+\t    _low, _high) |\t\t\t\t\t\t\\\n+\tEFX_EXTRACT32((_oword).eo_u32[2], FIX_LINT(64), FIX_LINT(95),\t\\\n+\t    _low, _high) |\t\t\t\t\t\t\\\n+\tEFX_EXTRACT32((_oword).eo_u32[3], FIX_LINT(96), FIX_LINT(127),\t\\\n+\t    _low, _high))\n+\n+#define\tEFX_EXTRACT_QWORD64(_qword, _low, _high)\t\t\t\\\n+\t(EFX_EXTRACT64((_qword).eq_u64[0], FIX_LINT(0), FIX_LINT(63),\t\\\n+\t    _low, _high))\n+\n+#define\tEFX_EXTRACT_QWORD32(_qword, _low, _high)\t\t\t\\\n+\t(EFX_EXTRACT32((_qword).eq_u32[0], FIX_LINT(0), FIX_LINT(31),\t\\\n+\t    _low, _high) |\t\t\t\t\t\t\\\n+\tEFX_EXTRACT32((_qword).eq_u32[1], FIX_LINT(32), FIX_LINT(63),\t\\\n+\t    _low, _high))\n+\n+#define\tEFX_EXTRACT_DWORD(_dword, _low, _high)\t\t\t\t\\\n+\t(EFX_EXTRACT32((_dword).ed_u32[0], FIX_LINT(0), FIX_LINT(31),\t\\\n+\t    _low, _high))\n+\n+#define\tEFX_EXTRACT_WORD(_word, _low, _high)\t\t\t\t\\\n+\t(EFX_EXTRACT16((_word).ew_u16[0], FIX_LINT(0), FIX_LINT(15),\t\\\n+\t    _low, _high))\n+\n+#define\tEFX_EXTRACT_BYTE(_byte, _low, _high)\t\t\t\t\\\n+\t(EFX_EXTRACT8((_byte).eb_u8[0], FIX_LINT(0), FIX_LINT(7),\t\\\n+\t    _low, _high))\n+\n+\n+#define\tEFX_OWORD_FIELD64(_oword, _field)\t\t\t\t\\\n+\t((uint32_t)EFX_EXTRACT_OWORD64(_oword, EFX_LOW_BIT(_field),\t\\\n+\t    EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))\n+\n+#define\tEFX_OWORD_FIELD32(_oword, _field)\t\t\t\t\\\n+\t(EFX_EXTRACT_OWORD32(_oword, EFX_LOW_BIT(_field),\t\t\\\n+\t    EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))\n+\n+#define\tEFX_QWORD_FIELD64(_qword, _field)\t\t\t\t\\\n+\t((uint32_t)EFX_EXTRACT_QWORD64(_qword, EFX_LOW_BIT(_field),\t\\\n+\t    EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))\n+\n+#define\tEFX_QWORD_FIELD32(_qword, _field)\t\t\t\t\\\n+\t(EFX_EXTRACT_QWORD32(_qword, EFX_LOW_BIT(_field),\t\t\\\n+\t    EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))\n+\n+#define\tEFX_DWORD_FIELD(_dword, _field)\t\t\t\t\t\\\n+\t(EFX_EXTRACT_DWORD(_dword, EFX_LOW_BIT(_field),\t\t\t\\\n+\t    EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))\n+\n+#define\tEFX_WORD_FIELD(_word, _field)\t\t\t\t\t\\\n+\t(EFX_EXTRACT_WORD(_word, EFX_LOW_BIT(_field),\t\t\t\\\n+\t    EFX_HIGH_BIT(_field)) & EFX_MASK16(_field))\n+\n+#define\tEFX_BYTE_FIELD(_byte, _field)\t\t\t\t\t\\\n+\t(EFX_EXTRACT_BYTE(_byte, EFX_LOW_BIT(_field),\t\t\t\\\n+\t    EFX_HIGH_BIT(_field)) & EFX_MASK8(_field))\n+\n+\n+#define\tEFX_OWORD_IS_EQUAL64(_oword_a, _oword_b)\t\t\t\\\n+\t((_oword_a).eo_u64[0] == (_oword_b).eo_u64[0] &&\t\t\\\n+\t    (_oword_a).eo_u64[1] == (_oword_b).eo_u64[1])\n+\n+#define\tEFX_OWORD_IS_EQUAL32(_oword_a, _oword_b)\t\t\t\\\n+\t((_oword_a).eo_u32[0] == (_oword_b).eo_u32[0] &&\t\t\\\n+\t    (_oword_a).eo_u32[1] == (_oword_b).eo_u32[1] &&\t\t\\\n+\t    (_oword_a).eo_u32[2] == (_oword_b).eo_u32[2] &&\t\t\\\n+\t    (_oword_a).eo_u32[3] == (_oword_b).eo_u32[3])\n+\n+#define\tEFX_QWORD_IS_EQUAL64(_qword_a, _qword_b)\t\t\t\\\n+\t((_qword_a).eq_u64[0] == (_qword_b).eq_u64[0])\n+\n+#define\tEFX_QWORD_IS_EQUAL32(_qword_a, _qword_b)\t\t\t\\\n+\t((_qword_a).eq_u32[0] == (_qword_b).eq_u32[0] &&\t\t\\\n+\t    (_qword_a).eq_u32[1] == (_qword_b).eq_u32[1])\n+\n+#define\tEFX_DWORD_IS_EQUAL(_dword_a, _dword_b)\t\t\t\t\\\n+\t((_dword_a).ed_u32[0] == (_dword_b).ed_u32[0])\n+\n+#define\tEFX_WORD_IS_EQUAL(_word_a, _word_b)\t\t\t\t\\\n+\t((_word_a).ew_u16[0] == (_word_b).ew_u16[0])\n+\n+#define\tEFX_BYTE_IS_EQUAL(_byte_a, _byte_b)\t\t\t\t\\\n+\t((_byte_a).eb_u8[0] == (_byte_b).eb_u8[0])\n+\n+\n+#define\tEFX_OWORD_IS_ZERO64(_oword)\t\t\t\t\t\\\n+\t(((_oword).eo_u64[0] |\t\t\t\t\t\t\\\n+\t    (_oword).eo_u64[1]) == 0)\n+\n+#define\tEFX_OWORD_IS_ZERO32(_oword)\t\t\t\t\t\\\n+\t(((_oword).eo_u32[0] |\t\t\t\t\t\t\\\n+\t    (_oword).eo_u32[1] |\t\t\t\t\t\\\n+\t    (_oword).eo_u32[2] |\t\t\t\t\t\\\n+\t    (_oword).eo_u32[3]) == 0)\n+\n+#define\tEFX_QWORD_IS_ZERO64(_qword)\t\t\t\t\t\\\n+\t(((_qword).eq_u64[0]) == 0)\n+\n+#define\tEFX_QWORD_IS_ZERO32(_qword)\t\t\t\t\t\\\n+\t(((_qword).eq_u32[0] |\t\t\t\t\t\t\\\n+\t    (_qword).eq_u32[1]) == 0)\n+\n+#define\tEFX_DWORD_IS_ZERO(_dword)\t\t\t\t\t\\\n+\t(((_dword).ed_u32[0]) == 0)\n+\n+#define\tEFX_WORD_IS_ZERO(_word)\t\t\t\t\t\t\\\n+\t(((_word).ew_u16[0]) == 0)\n+\n+#define\tEFX_BYTE_IS_ZERO(_byte)\t\t\t\t\t\t\\\n+\t(((_byte).eb_u8[0]) == 0)\n+\n+\n+#define\tEFX_OWORD_IS_SET64(_oword)\t\t\t\t\t\\\n+\t(((_oword).eo_u64[0] &\t\t\t\t\t\t\\\n+\t    (_oword).eo_u64[1]) == ~((uint64_t)0))\n+\n+#define\tEFX_OWORD_IS_SET32(_oword)\t\t\t\t\t\\\n+\t(((_oword).eo_u32[0] &\t\t\t\t\t\t\\\n+\t    (_oword).eo_u32[1] &\t\t\t\t\t\\\n+\t    (_oword).eo_u32[2] &\t\t\t\t\t\\\n+\t    (_oword).eo_u32[3]) == ~((uint32_t)0))\n+\n+#define\tEFX_QWORD_IS_SET64(_qword)\t\t\t\t\t\\\n+\t(((_qword).eq_u64[0]) == ~((uint64_t)0))\n+\n+#define\tEFX_QWORD_IS_SET32(_qword)\t\t\t\t\t\\\n+\t(((_qword).eq_u32[0] &\t\t\t\t\t\t\\\n+\t    (_qword).eq_u32[1]) == ~((uint32_t)0))\n+\n+#define\tEFX_DWORD_IS_SET(_dword)\t\t\t\t\t\\\n+\t((_dword).ed_u32[0] == ~((uint32_t)0))\n+\n+#define\tEFX_WORD_IS_SET(_word)\t\t\t\t\t\t\\\n+\t((_word).ew_u16[0] == ~((uint16_t)0))\n+\n+#define\tEFX_BYTE_IS_SET(_byte)\t\t\t\t\t\t\\\n+\t((_byte).eb_u8[0] == ~((uint8_t)0))\n+\n+/*\n+ * Construct bit field portion\n+ *\n+ * Creates the portion of the bit field [low,high) that lies within\n+ * the range [min,max).\n+ */\n+\n+#define\tEFX_INSERT_NATIVE64(_min, _max, _low, _high, _value)\t\t\\\n+\t(((_low > _max) || (_high < _min)) ?\t\t\t\t\\\n+\t\t0U :\t\t\t\t\t\t\t\\\n+\t\t((_low > _min) ?\t\t\t\t\t\\\n+\t\t\t(((uint64_t)(_value)) << (_low - _min)) :\t\\\n+\t\t\t(((uint64_t)(_value)) >> (_min - _low))))\n+\n+#define\tEFX_INSERT_NATIVE32(_min, _max, _low, _high, _value)\t\t\\\n+\t(((_low > _max) || (_high < _min)) ?\t\t\t\t\\\n+\t\t0U :\t\t\t\t\t\t\t\\\n+\t\t((_low > _min) ?\t\t\t\t\t\\\n+\t\t\t(((uint32_t)(_value)) << (_low - _min)) :\t\\\n+\t\t\t(((uint32_t)(_value)) >> (_min - _low))))\n+\n+#define\tEFX_INSERT_NATIVE16(_min, _max, _low, _high, _value)\t\t\\\n+\t(((_low > _max) || (_high < _min)) ?\t\t\t\t\\\n+\t\t0U :\t\t\t\t\t\t\t\\\n+\t\t(uint16_t)((_low > _min) ?\t\t\t\t\\\n+\t\t\t\t((_value) << (_low - _min)) :\t\t\\\n+\t\t\t\t((_value) >> (_min - _low))))\n+\n+#define\tEFX_INSERT_NATIVE8(_min, _max, _low, _high, _value)\t\t\\\n+\t(((_low > _max) || (_high < _min)) ?\t\t\t\t\\\n+\t\t0U :\t\t\t\t\t\t\t\\\n+\t\t(uint8_t)((_low > _min) ?\t\t\t\t\\\n+\t\t\t\t((_value) << (_low - _min)) :\t\\\n+\t\t\t\t((_value) >> (_min - _low))))\n+\n+/*\n+ * Construct bit field portion\n+ *\n+ * Creates the portion of the named bit field that lies within the\n+ * range [min,max).\n+ */\n+#define\tEFX_INSERT_FIELD_NATIVE64(_min, _max, _field, _value)\t\t\\\n+\tEFX_INSERT_NATIVE64(_min, _max, EFX_LOW_BIT(_field),\t\t\\\n+\t    EFX_HIGH_BIT(_field), _value)\n+\n+#define\tEFX_INSERT_FIELD_NATIVE32(_min, _max, _field, _value)\t\t\\\n+\tEFX_INSERT_NATIVE32(_min, _max, EFX_LOW_BIT(_field),\t\t\\\n+\t    EFX_HIGH_BIT(_field), _value)\n+\n+#define\tEFX_INSERT_FIELD_NATIVE16(_min, _max, _field, _value)\t\t\\\n+\tEFX_INSERT_NATIVE16(_min, _max, EFX_LOW_BIT(_field),\t\t\\\n+\t    EFX_HIGH_BIT(_field), _value)\n+\n+#define\tEFX_INSERT_FIELD_NATIVE8(_min, _max, _field, _value)\t\t\\\n+\tEFX_INSERT_NATIVE8(_min, _max, EFX_LOW_BIT(_field),\t\t\\\n+\t    EFX_HIGH_BIT(_field), _value)\n+\n+/*\n+ * Construct bit field\n+ *\n+ * Creates the portion of the named bit fields that lie within the\n+ * range [min,max).\n+ */\n+#define\tEFX_INSERT_FIELDS64(_min, _max,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\t__CPU_TO_LE_64(\t\t\t\t\t\t\t\\\n+\t    EFX_INSERT_FIELD_NATIVE64(_min, _max, _field1, _value1) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE64(_min, _max, _field2, _value2) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE64(_min, _max, _field3, _value3) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE64(_min, _max, _field4, _value4) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE64(_min, _max, _field5, _value5) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE64(_min, _max, _field6, _value6) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE64(_min, _max, _field7, _value7) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE64(_min, _max, _field8, _value8) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE64(_min, _max, _field9, _value9) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE64(_min, _max, _field10, _value10))\n+\n+#define\tEFX_INSERT_FIELDS32(_min, _max,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\t__CPU_TO_LE_32(\t\t\t\t\t\t\t\\\n+\t    EFX_INSERT_FIELD_NATIVE32(_min, _max, _field1, _value1) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE32(_min, _max, _field2, _value2) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE32(_min, _max, _field3, _value3) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE32(_min, _max, _field4, _value4) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE32(_min, _max, _field5, _value5) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE32(_min, _max, _field6, _value6) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE32(_min, _max, _field7, _value7) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE32(_min, _max, _field8, _value8) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE32(_min, _max, _field9, _value9) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE32(_min, _max, _field10, _value10))\n+\n+#define\tEFX_INSERT_FIELDS16(_min, _max,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\t__CPU_TO_LE_16(\t\t\t\t\t\t\t\\\n+\t    EFX_INSERT_FIELD_NATIVE16(_min, _max, _field1, _value1) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE16(_min, _max, _field2, _value2) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE16(_min, _max, _field3, _value3) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE16(_min, _max, _field4, _value4) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE16(_min, _max, _field5, _value5) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE16(_min, _max, _field6, _value6) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE16(_min, _max, _field7, _value7) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE16(_min, _max, _field8, _value8) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE16(_min, _max, _field9, _value9) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE16(_min, _max, _field10, _value10))\n+\n+#define\tEFX_INSERT_FIELDS8(_min, _max,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\t__NATIVE_8(\t\t\t\t\t\t\t\\\n+\t    EFX_INSERT_FIELD_NATIVE8(_min, _max, _field1, _value1) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE8(_min, _max, _field2, _value2) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE8(_min, _max, _field3, _value3) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE8(_min, _max, _field4, _value4) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE8(_min, _max, _field5, _value5) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE8(_min, _max, _field6, _value6) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE8(_min, _max, _field7, _value7) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE8(_min, _max, _field8, _value8) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE8(_min, _max, _field9, _value9) |\t\\\n+\t    EFX_INSERT_FIELD_NATIVE8(_min, _max, _field10, _value10))\n+\n+#define\tEFX_POPULATE_OWORD64(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u64[0] = EFX_INSERT_FIELDS64(0, 63,\t\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u64[1] = EFX_INSERT_FIELDS64(64, 127,\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_POPULATE_OWORD32(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u32[0] = EFX_INSERT_FIELDS32(0, 31,\t\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u32[1] = EFX_INSERT_FIELDS32(32, 63,\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u32[2] = EFX_INSERT_FIELDS32(64, 95,\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u32[3] = EFX_INSERT_FIELDS32(96, 127,\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_POPULATE_QWORD64(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_qword).eq_u64[0] = EFX_INSERT_FIELDS64(0, 63,\t\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_POPULATE_QWORD32(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_qword).eq_u32[0] = EFX_INSERT_FIELDS32(0, 31,\t\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_qword).eq_u32[1] = EFX_INSERT_FIELDS32(32, 63,\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_POPULATE_DWORD(_dword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_dword).ed_u32[0] = EFX_INSERT_FIELDS32(0, 31,\t\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_POPULATE_WORD(_word,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_word).ew_u16[0] = EFX_INSERT_FIELDS16(0, 15,\t\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_POPULATE_BYTE(_byte,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9,\t\\\n+\t    _field10, _value10)\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_byte).eb_u8[0] = EFX_INSERT_FIELDS8(0, 7,\t\t\\\n+\t\t    _field1, _value1, _field2, _value2,\t\t\t\\\n+\t\t    _field3, _value3, _field4, _value4,\t\t\t\\\n+\t\t    _field5, _value5, _field6, _value6,\t\t\t\\\n+\t\t    _field7, _value7, _field8, _value8,\t\t\t\\\n+\t\t    _field9, _value9, _field10, _value10);\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/* Populate an octword field with various numbers of arguments */\n+#define\tEFX_POPULATE_OWORD_10 EFX_POPULATE_OWORD\n+\n+#define\tEFX_POPULATE_OWORD_9(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9)\t\\\n+\tEFX_POPULATE_OWORD_10(_oword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9)\n+\n+#define\tEFX_POPULATE_OWORD_8(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8)\t\t\t\t\\\n+\tEFX_POPULATE_OWORD_9(_oword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8)\n+\n+#define\tEFX_POPULATE_OWORD_7(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_OWORD_8(_oword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7)\n+\n+#define\tEFX_POPULATE_OWORD_6(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6)\t\\\n+\tEFX_POPULATE_OWORD_7(_oword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6)\n+\n+#define\tEFX_POPULATE_OWORD_5(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5)\t\t\t\t\\\n+\tEFX_POPULATE_OWORD_6(_oword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5)\n+\n+#define\tEFX_POPULATE_OWORD_4(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_OWORD_5(_oword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4)\n+\n+#define\tEFX_POPULATE_OWORD_3(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3)\t\\\n+\tEFX_POPULATE_OWORD_4(_oword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3)\n+\n+#define\tEFX_POPULATE_OWORD_2(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2)\t\t\t\t\\\n+\tEFX_POPULATE_OWORD_3(_oword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2)\n+\n+#define\tEFX_POPULATE_OWORD_1(_oword,\t\t\t\t\t\\\n+\t    _field1, _value1)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_OWORD_2(_oword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1)\n+\n+#define\tEFX_ZERO_OWORD(_oword)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_OWORD_1(_oword, EFX_DUMMY_FIELD, 0)\n+\n+#define\tEFX_SET_OWORD(_oword)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_OWORD_4(_oword,\t\t\t\t\t\\\n+\t    EFX_DWORD_0, 0xffffffff, EFX_DWORD_1, 0xffffffff,\t\t\\\n+\t    EFX_DWORD_2, 0xffffffff, EFX_DWORD_3, 0xffffffff)\n+\n+/* Populate a quadword field with various numbers of arguments */\n+#define\tEFX_POPULATE_QWORD_10 EFX_POPULATE_QWORD\n+\n+#define\tEFX_POPULATE_QWORD_9(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9)\t\\\n+\tEFX_POPULATE_QWORD_10(_qword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9)\n+\n+#define\tEFX_POPULATE_QWORD_8(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8)\t\t\t\t\\\n+\tEFX_POPULATE_QWORD_9(_qword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8)\n+\n+#define\tEFX_POPULATE_QWORD_7(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_QWORD_8(_qword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7)\n+\n+#define\tEFX_POPULATE_QWORD_6(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6)\t\\\n+\tEFX_POPULATE_QWORD_7(_qword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6)\n+\n+#define\tEFX_POPULATE_QWORD_5(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5)\t\t\t\t\\\n+\tEFX_POPULATE_QWORD_6(_qword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5)\n+\n+#define\tEFX_POPULATE_QWORD_4(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_QWORD_5(_qword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4)\n+\n+#define\tEFX_POPULATE_QWORD_3(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3)\t\\\n+\tEFX_POPULATE_QWORD_4(_qword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3)\n+\n+#define\tEFX_POPULATE_QWORD_2(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2)\t\t\t\t\\\n+\tEFX_POPULATE_QWORD_3(_qword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2)\n+\n+#define\tEFX_POPULATE_QWORD_1(_qword,\t\t\t\t\t\\\n+\t    _field1, _value1)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_QWORD_2(_qword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1)\n+\n+#define\tEFX_ZERO_QWORD(_qword)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_QWORD_1(_qword, EFX_DUMMY_FIELD, 0)\n+\n+#define\tEFX_SET_QWORD(_qword)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_QWORD_2(_qword,\t\t\t\t\t\\\n+\t    EFX_DWORD_0, 0xffffffff, EFX_DWORD_1, 0xffffffff)\n+\n+/* Populate a dword field with various numbers of arguments */\n+#define\tEFX_POPULATE_DWORD_10 EFX_POPULATE_DWORD\n+\n+#define\tEFX_POPULATE_DWORD_9(_dword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9)\t\\\n+\tEFX_POPULATE_DWORD_10(_dword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9)\n+\n+#define\tEFX_POPULATE_DWORD_8(_dword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8)\t\t\t\t\\\n+\tEFX_POPULATE_DWORD_9(_dword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8)\n+\n+#define\tEFX_POPULATE_DWORD_7(_dword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_DWORD_8(_dword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7)\n+\n+#define\tEFX_POPULATE_DWORD_6(_dword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6)\t\\\n+\tEFX_POPULATE_DWORD_7(_dword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6)\n+\n+#define\tEFX_POPULATE_DWORD_5(_dword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5)\t\t\t\t\\\n+\tEFX_POPULATE_DWORD_6(_dword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5)\n+\n+#define\tEFX_POPULATE_DWORD_4(_dword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_DWORD_5(_dword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4)\n+\n+#define\tEFX_POPULATE_DWORD_3(_dword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3)\t\\\n+\tEFX_POPULATE_DWORD_4(_dword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3)\n+\n+#define\tEFX_POPULATE_DWORD_2(_dword,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2)\t\t\t\t\\\n+\tEFX_POPULATE_DWORD_3(_dword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1, _field2, _value2)\n+\n+#define\tEFX_POPULATE_DWORD_1(_dword,\t\t\t\t\t\\\n+\t    _field1, _value1)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_DWORD_2(_dword, EFX_DUMMY_FIELD, 0,\t\t\\\n+\t    _field1, _value1)\n+\n+#define\tEFX_ZERO_DWORD(_dword)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_DWORD_1(_dword, EFX_DUMMY_FIELD, 0)\n+\n+#define\tEFX_SET_DWORD(_dword)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_DWORD_1(_dword,\t\t\t\t\t\\\n+\t    EFX_DWORD_0, 0xffffffff)\n+\n+/* Populate a word field with various numbers of arguments */\n+#define\tEFX_POPULATE_WORD_10 EFX_POPULATE_WORD\n+\n+#define\tEFX_POPULATE_WORD_9(_word,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9)\t\\\n+\tEFX_POPULATE_WORD_10(_word, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9)\n+\n+#define\tEFX_POPULATE_WORD_8(_word,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8)\t\t\t\t\\\n+\tEFX_POPULATE_WORD_9(_word, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8)\n+\n+#define\tEFX_POPULATE_WORD_7(_word,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_WORD_8(_word, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7)\n+\n+#define\tEFX_POPULATE_WORD_6(_word,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6)\t\\\n+\tEFX_POPULATE_WORD_7(_word, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6)\n+\n+#define\tEFX_POPULATE_WORD_5(_word,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5)\t\t\t\t\\\n+\tEFX_POPULATE_WORD_6(_word, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5)\n+\n+#define\tEFX_POPULATE_WORD_4(_word,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_WORD_5(_word, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4)\n+\n+#define\tEFX_POPULATE_WORD_3(_word,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3)\t\\\n+\tEFX_POPULATE_WORD_4(_word, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3)\n+\n+#define\tEFX_POPULATE_WORD_2(_word,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2)\t\t\t\t\\\n+\tEFX_POPULATE_WORD_3(_word, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2)\n+\n+#define\tEFX_POPULATE_WORD_1(_word,\t\t\t\t\t\\\n+\t    _field1, _value1)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_WORD_2(_word, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1)\n+\n+#define\tEFX_ZERO_WORD(_word)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_WORD_1(_word, EFX_DUMMY_FIELD, 0)\n+\n+#define\tEFX_SET_WORD(_word)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_WORD_1(_word,\t\t\t\t\t\\\n+\t    EFX_WORD_0, 0xffff)\n+\n+/* Populate a byte field with various numbers of arguments */\n+#define\tEFX_POPULATE_BYTE_10 EFX_POPULATE_BYTE\n+\n+#define\tEFX_POPULATE_BYTE_9(_byte,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9)\t\\\n+\tEFX_POPULATE_BYTE_10(_byte, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8,\t_field9, _value9)\n+\n+#define\tEFX_POPULATE_BYTE_8(_byte,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8)\t\t\t\t\\\n+\tEFX_POPULATE_BYTE_9(_byte, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7, _field8, _value8)\n+\n+#define\tEFX_POPULATE_BYTE_7(_byte,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_BYTE_8(_byte, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6,\t\\\n+\t    _field7, _value7)\n+\n+#define\tEFX_POPULATE_BYTE_6(_byte,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6)\t\\\n+\tEFX_POPULATE_BYTE_7(_byte, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5,\t_field6, _value6)\n+\n+#define\tEFX_POPULATE_BYTE_5(_byte,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5)\t\t\t\t\\\n+\tEFX_POPULATE_BYTE_6(_byte, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4, _field5, _value5)\n+\n+#define\tEFX_POPULATE_BYTE_4(_byte,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_BYTE_5(_byte, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3,\t\\\n+\t    _field4, _value4)\n+\n+#define\tEFX_POPULATE_BYTE_3(_byte,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3)\t\\\n+\tEFX_POPULATE_BYTE_4(_byte, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2, _field3, _value3)\n+\n+#define\tEFX_POPULATE_BYTE_2(_byte,\t\t\t\t\t\\\n+\t    _field1, _value1, _field2, _value2)\t\t\t\t\\\n+\tEFX_POPULATE_BYTE_3(_byte, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1, _field2, _value2)\n+\n+#define\tEFX_POPULATE_BYTE_1(_byte,\t\t\t\t\t\\\n+\t    _field1, _value1)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_BYTE_2(_byte, EFX_DUMMY_FIELD, 0,\t\t\t\\\n+\t    _field1, _value1)\n+\n+#define\tEFX_ZERO_BYTE(_byte)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_BYTE_1(_byte, EFX_DUMMY_FIELD, 0)\n+\n+#define\tEFX_SET_BYTE(_byte)\t\t\t\t\t\t\\\n+\tEFX_POPULATE_BYTE_1(_byte,\t\t\t\t\t\\\n+\t    EFX_BYTE_0, 0xff)\n+\n+/*\n+ * Modify a named field within an already-populated structure.  Used\n+ * for read-modify-write operations.\n+ */\n+\n+#define\tEFX_INSERT_FIELD64(_min, _max, _field, _value)\t\t\t\\\n+\t__CPU_TO_LE_64(EFX_INSERT_FIELD_NATIVE64(_min, _max, _field, _value))\n+\n+#define\tEFX_INSERT_FIELD32(_min, _max, _field, _value)\t\t\t\\\n+\t__CPU_TO_LE_32(EFX_INSERT_FIELD_NATIVE32(_min, _max, _field, _value))\n+\n+#define\tEFX_INSERT_FIELD16(_min, _max, _field, _value)\t\t\t\\\n+\t__CPU_TO_LE_16(EFX_INSERT_FIELD_NATIVE16(_min, _max, _field, _value))\n+\n+#define\tEFX_INSERT_FIELD8(_min, _max, _field, _value)\t\t\t\\\n+\t__NATIVE_8(EFX_INSERT_FIELD_NATIVE8(_min, _max, _field, _value))\n+\n+#define\tEFX_INPLACE_MASK64(_min, _max, _field)\t\t\t\t\\\n+\tEFX_INSERT_FIELD64(_min, _max, _field, EFX_MASK64(_field))\n+\n+#define\tEFX_INPLACE_MASK32(_min, _max, _field)\t\t\t\t\\\n+\tEFX_INSERT_FIELD32(_min, _max, _field, EFX_MASK32(_field))\n+\n+#define\tEFX_INPLACE_MASK16(_min, _max, _field)\t\t\t\t\\\n+\tEFX_INSERT_FIELD16(_min, _max, _field, EFX_MASK16(_field))\n+\n+#define\tEFX_INPLACE_MASK8(_min, _max, _field)\t\t\t\t\\\n+\tEFX_INSERT_FIELD8(_min, _max, _field, EFX_MASK8(_field))\n+\n+#define\tEFX_SET_OWORD_FIELD64(_oword, _field, _value)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u64[0] = (((_oword).eo_u64[0] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK64(0, 63, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD64(0, 63, _field, _value));\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u64[1] = (((_oword).eo_u64[1] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK64(64, 127, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD64(64, 127, _field, _value));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_SET_OWORD_FIELD32(_oword, _field, _value)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u32[0] = (((_oword).eo_u32[0] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK32(0, 31, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD32(0, 31, _field, _value));\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u32[1] = (((_oword).eo_u32[1] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK32(32, 63, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD32(32, 63, _field, _value));\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u32[2] = (((_oword).eo_u32[2] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK32(64, 95, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD32(64, 95, _field, _value));\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u32[3] = (((_oword).eo_u32[3] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK32(96, 127, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD32(96, 127, _field, _value));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_SET_QWORD_FIELD64(_qword, _field, _value)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_qword).eq_u64[0] = (((_qword).eq_u64[0] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK64(0, 63, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD64(0, 63, _field, _value));\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_SET_QWORD_FIELD32(_qword, _field, _value)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_qword).eq_u32[0] = (((_qword).eq_u32[0] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK32(0, 31, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD32(0, 31, _field, _value));\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_qword).eq_u32[1] = (((_qword).eq_u32[1] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK32(32, 63, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD32(32, 63, _field, _value));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_SET_DWORD_FIELD(_dword, _field, _value)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_dword).ed_u32[0] = (((_dword).ed_u32[0] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK32(0, 31, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD32(0, 31, _field, _value));\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_SET_WORD_FIELD(_word, _field, _value)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_word).ew_u16[0] = (((_word).ew_u16[0] &\t\t\\\n+\t\t    ~EFX_INPLACE_MASK16(0, 15, _field)) |\t\t\\\n+\t\t    EFX_INSERT_FIELD16(0, 15, _field, _value));\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_SET_BYTE_FIELD(_byte, _field, _value)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_byte).eb_u8[0] = (((_byte).eb_u8[0] &\t\t\t\\\n+\t\t    ~EFX_INPLACE_MASK8(0, 7, _field)) |\t\t\t\\\n+\t\t    EFX_INSERT_FIELD8(0, 7, _field, _value));\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+/*\n+ * Set or clear a numbered bit within an octword.\n+ */\n+\n+#define\tEFX_SHIFT64(_bit, _base)\t\t\t\t\t\\\n+\t(((_bit) >= (_base) && (_bit) < (_base) + 64) ?\t\t\t\\\n+\t\t((uint64_t)1 << ((_bit) - (_base))) :\t\t\t\\\n+\t\t0U)\n+\n+#define\tEFX_SHIFT32(_bit, _base)\t\t\t\t\t\\\n+\t(((_bit) >= (_base) && (_bit) < (_base) + 32) ?\t\t\t\\\n+\t\t((uint32_t)1 << ((_bit) - (_base))) :\t\t\t\\\n+\t\t0U)\n+\n+#define\tEFX_SHIFT16(_bit, _base)\t\t\t\t\t\\\n+\t(((_bit) >= (_base) && (_bit) < (_base) + 16) ?\t\t\t\\\n+\t\t(uint16_t)(1 << ((_bit) - (_base))) :\t\t\t\\\n+\t\t0U)\n+\n+#define\tEFX_SHIFT8(_bit, _base)\t\t\t\t\t\t\\\n+\t(((_bit) >= (_base) && (_bit) < (_base) + 8) ?\t\t\t\\\n+\t\t(uint8_t)(1 << ((_bit) - (_base))) :\t\t\t\\\n+\t\t0U)\n+\n+#define\tEFX_SET_OWORD_BIT64(_oword, _bit)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u64[0] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(0)));\t\\\n+\t\t(_oword).eo_u64[1] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(64)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_SET_OWORD_BIT32(_oword, _bit)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u32[0] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)));\t\\\n+\t\t(_oword).eo_u32[1] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(32)));\t\\\n+\t\t(_oword).eo_u32[2] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(64)));\t\\\n+\t\t(_oword).eo_u32[3] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(96)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_CLEAR_OWORD_BIT64(_oword, _bit)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u64[0] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_64(~EFX_SHIFT64(_bit, FIX_LINT(0)));\t\\\n+\t\t(_oword).eo_u64[1] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_64(~EFX_SHIFT64(_bit, FIX_LINT(64)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_CLEAR_OWORD_BIT32(_oword, _bit)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_oword).eo_u32[0] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(0)));\t\\\n+\t\t(_oword).eo_u32[1] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(32)));\t\\\n+\t\t(_oword).eo_u32[2] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(64)));\t\\\n+\t\t(_oword).eo_u32[3] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(96)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_TEST_OWORD_BIT64(_oword, _bit)\t\t\t\t\\\n+\t(((_oword).eo_u64[0] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(0)))) ||\t\\\n+\t((_oword).eo_u64[1] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(64)))))\n+\n+#define\tEFX_TEST_OWORD_BIT32(_oword, _bit)\t\t\t\t\\\n+\t(((_oword).eo_u32[0] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)))) ||\t\\\n+\t((_oword).eo_u32[1] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(32)))) ||\t\\\n+\t((_oword).eo_u32[2] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(64)))) ||\t\\\n+\t((_oword).eo_u32[3] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(96)))))\n+\n+\n+#define\tEFX_SET_QWORD_BIT64(_qword, _bit)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_qword).eq_u64[0] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(0)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_SET_QWORD_BIT32(_qword, _bit)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_qword).eq_u32[0] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)));\t\\\n+\t\t(_qword).eq_u32[1] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(32)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_CLEAR_QWORD_BIT64(_qword, _bit)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_qword).eq_u64[0] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_64(~EFX_SHIFT64(_bit, FIX_LINT(0)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_CLEAR_QWORD_BIT32(_qword, _bit)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t_NOTE(CONSTANTCONDITION)\t\t\t\t\\\n+\t\t(_qword).eq_u32[0] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(0)));\t\\\n+\t\t(_qword).eq_u32[1] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(32)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_TEST_QWORD_BIT64(_qword, _bit)\t\t\t\t\\\n+\t(((_qword).eq_u64[0] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_64(EFX_SHIFT64(_bit, FIX_LINT(0)))) != 0)\n+\n+#define\tEFX_TEST_QWORD_BIT32(_qword, _bit)\t\t\t\t\\\n+\t(((_qword).eq_u32[0] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)))) ||\t\\\n+\t((_qword).eq_u32[1] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(32)))))\n+\n+\n+#define\tEFX_SET_DWORD_BIT(_dword, _bit)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_dword).ed_u32[0] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_CLEAR_DWORD_BIT(_dword, _bit)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_dword).ed_u32[0] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(~EFX_SHIFT32(_bit, FIX_LINT(0)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_TEST_DWORD_BIT(_dword, _bit)\t\t\t\t\\\n+\t(((_dword).ed_u32[0] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)))) != 0)\n+\n+\n+#define\tEFX_SET_WORD_BIT(_word, _bit)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_word).ew_u16[0] |=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_16(EFX_SHIFT16(_bit, FIX_LINT(0)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_CLEAR_WORD_BIT(_word, _bit)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_word).ew_u32[0] &=\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_16(~EFX_SHIFT16(_bit, FIX_LINT(0)));\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_TEST_WORD_BIT(_word, _bit)\t\t\t\t\t\\\n+\t(((_word).ew_u16[0] &\t\t\t\t\t\t\\\n+\t\t    __CPU_TO_LE_16(EFX_SHIFT16(_bit, FIX_LINT(0)))) != 0)\n+\n+\n+#define\tEFX_SET_BYTE_BIT(_byte, _bit)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_byte).eb_u8[0] |=\t\t\t\t\t\\\n+\t\t    __NATIVE_8(EFX_SHIFT8(_bit, FIX_LINT(0)));\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_CLEAR_BYTE_BIT(_byte, _bit)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_byte).eb_u8[0] &=\t\t\t\t\t\\\n+\t\t    __NATIVE_8(~EFX_SHIFT8(_bit, FIX_LINT(0)));\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_TEST_BYTE_BIT(_byte, _bit)\t\t\t\t\t\\\n+\t(((_byte).eb_u8[0] &\t\t\t\t\t\t\\\n+\t\t    __NATIVE_8(EFX_SHIFT8(_bit, FIX_LINT(0)))) != 0)\n+\n+\n+#define\tEFX_OR_OWORD64(_oword1, _oword2)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_oword1).eo_u64[0] |= (_oword2).eo_u64[0];\t\t\\\n+\t\t(_oword1).eo_u64[1] |= (_oword2).eo_u64[1];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_OR_OWORD32(_oword1, _oword2)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_oword1).eo_u32[0] |= (_oword2).eo_u32[0];\t\t\\\n+\t\t(_oword1).eo_u32[1] |= (_oword2).eo_u32[1];\t\t\\\n+\t\t(_oword1).eo_u32[2] |= (_oword2).eo_u32[2];\t\t\\\n+\t\t(_oword1).eo_u32[3] |= (_oword2).eo_u32[3];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_AND_OWORD64(_oword1, _oword2)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_oword1).eo_u64[0] &= (_oword2).eo_u64[0];\t\t\\\n+\t\t(_oword1).eo_u64[1] &= (_oword2).eo_u64[1];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_AND_OWORD32(_oword1, _oword2)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_oword1).eo_u32[0] &= (_oword2).eo_u32[0];\t\t\\\n+\t\t(_oword1).eo_u32[1] &= (_oword2).eo_u32[1];\t\t\\\n+\t\t(_oword1).eo_u32[2] &= (_oword2).eo_u32[2];\t\t\\\n+\t\t(_oword1).eo_u32[3] &= (_oword2).eo_u32[3];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_OR_QWORD64(_qword1, _qword2)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_qword1).eq_u64[0] |= (_qword2).eq_u64[0];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_OR_QWORD32(_qword1, _qword2)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_qword1).eq_u32[0] |= (_qword2).eq_u32[0];\t\t\\\n+\t\t(_qword1).eq_u32[1] |= (_qword2).eq_u32[1];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_AND_QWORD64(_qword1, _qword2)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_qword1).eq_u64[0] &= (_qword2).eq_u64[0];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_AND_QWORD32(_qword1, _qword2)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_qword1).eq_u32[0] &= (_qword2).eq_u32[0];\t\t\\\n+\t\t(_qword1).eq_u32[1] &= (_qword2).eq_u32[1];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_OR_DWORD(_dword1, _dword2)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_dword1).ed_u32[0] |= (_dword2).ed_u32[0];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_AND_DWORD(_dword1, _dword2)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_dword1).ed_u32[0] &= (_dword2).ed_u32[0];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_OR_WORD(_word1, _word2)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_word1).ew_u16[0] |= (_word2).ew_u16[0];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_AND_WORD(_word1, _word2)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_word1).ew_u16[0] &= (_word2).ew_u16[0];\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_OR_BYTE(_byte1, _byte2)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_byte1).eb_u8[0] |= (_byte2).eb_u8[0];\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#define\tEFX_AND_BYTE(_byte1, _byte2)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\t(_byte1).eb_u8[0] &= (_byte2).eb_u8[0];\t\t\t\\\n+\t_NOTE(CONSTANTCONDITION)\t\t\t\t\t\\\n+\t} while (B_FALSE)\n+\n+#if EFSYS_USE_UINT64\n+#define\tEFX_OWORD_FIELD\t\tEFX_OWORD_FIELD64\n+#define\tEFX_QWORD_FIELD\t\tEFX_QWORD_FIELD64\n+#define\tEFX_OWORD_IS_EQUAL\tEFX_OWORD_IS_EQUAL64\n+#define\tEFX_QWORD_IS_EQUAL\tEFX_QWORD_IS_EQUAL64\n+#define\tEFX_OWORD_IS_ZERO\tEFX_OWORD_IS_ZERO64\n+#define\tEFX_QWORD_IS_ZERO\tEFX_QWORD_IS_ZERO64\n+#define\tEFX_OWORD_IS_SET\tEFX_OWORD_IS_SET64\n+#define\tEFX_QWORD_IS_SET\tEFX_QWORD_IS_SET64\n+#define\tEFX_POPULATE_OWORD\tEFX_POPULATE_OWORD64\n+#define\tEFX_POPULATE_QWORD\tEFX_POPULATE_QWORD64\n+#define\tEFX_SET_OWORD_FIELD\tEFX_SET_OWORD_FIELD64\n+#define\tEFX_SET_QWORD_FIELD\tEFX_SET_QWORD_FIELD64\n+#define\tEFX_SET_OWORD_BIT\tEFX_SET_OWORD_BIT64\n+#define\tEFX_CLEAR_OWORD_BIT\tEFX_CLEAR_OWORD_BIT64\n+#define\tEFX_TEST_OWORD_BIT\tEFX_TEST_OWORD_BIT64\n+#define\tEFX_SET_QWORD_BIT\tEFX_SET_QWORD_BIT64\n+#define\tEFX_CLEAR_QWORD_BIT\tEFX_CLEAR_QWORD_BIT64\n+#define\tEFX_TEST_QWORD_BIT\tEFX_TEST_QWORD_BIT64\n+#define\tEFX_OR_OWORD\t\tEFX_OR_OWORD64\n+#define\tEFX_AND_OWORD\t\tEFX_AND_OWORD64\n+#define\tEFX_OR_QWORD\t\tEFX_OR_QWORD64\n+#define\tEFX_AND_QWORD\t\tEFX_AND_QWORD64\n+#else\n+#define\tEFX_OWORD_FIELD\t\tEFX_OWORD_FIELD32\n+#define\tEFX_QWORD_FIELD\t\tEFX_QWORD_FIELD32\n+#define\tEFX_OWORD_IS_EQUAL\tEFX_OWORD_IS_EQUAL32\n+#define\tEFX_QWORD_IS_EQUAL\tEFX_QWORD_IS_EQUAL32\n+#define\tEFX_OWORD_IS_ZERO\tEFX_OWORD_IS_ZERO32\n+#define\tEFX_QWORD_IS_ZERO\tEFX_QWORD_IS_ZERO32\n+#define\tEFX_OWORD_IS_SET\tEFX_OWORD_IS_SET32\n+#define\tEFX_QWORD_IS_SET\tEFX_QWORD_IS_SET32\n+#define\tEFX_POPULATE_OWORD\tEFX_POPULATE_OWORD32\n+#define\tEFX_POPULATE_QWORD\tEFX_POPULATE_QWORD32\n+#define\tEFX_SET_OWORD_FIELD\tEFX_SET_OWORD_FIELD32\n+#define\tEFX_SET_QWORD_FIELD\tEFX_SET_QWORD_FIELD32\n+#define\tEFX_SET_OWORD_BIT\tEFX_SET_OWORD_BIT32\n+#define\tEFX_CLEAR_OWORD_BIT\tEFX_CLEAR_OWORD_BIT32\n+#define\tEFX_TEST_OWORD_BIT\tEFX_TEST_OWORD_BIT32\n+#define\tEFX_SET_QWORD_BIT\tEFX_SET_QWORD_BIT32\n+#define\tEFX_CLEAR_QWORD_BIT\tEFX_CLEAR_QWORD_BIT32\n+#define\tEFX_TEST_QWORD_BIT\tEFX_TEST_QWORD_BIT32\n+#define\tEFX_OR_OWORD\t\tEFX_OR_OWORD32\n+#define\tEFX_AND_OWORD\t\tEFX_AND_OWORD32\n+#define\tEFX_OR_QWORD\t\tEFX_OR_QWORD32\n+#define\tEFX_AND_QWORD\t\tEFX_AND_QWORD32\n+#endif\n+\n+#ifdef\t__cplusplus\n+}\n+#endif\n+\n+#endif\t/* _SYS_EFX_TYPES_H */\n",
    "prefixes": [
        "dpdk-dev",
        "02/56"
    ]
}