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{
    "id": 17130,
    "url": "https://patches.dpdk.org/api/patches/17130/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1479740470-6723-19-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1479740470-6723-19-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1479740470-6723-19-git-send-email-arybchenko@solarflare.com",
    "date": "2016-11-21T15:00:32",
    "name": "[dpdk-dev,18/56] net/sfc: import libefx MAC statistics support",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "156da5417023f9797ee8e35ae689cbefb051a320",
    "submitter": {
        "id": 607,
        "url": "https://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1479740470-6723-19-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/17130/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/17130/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 7FB7BD546;\n\tMon, 21 Nov 2016 16:03:17 +0100 (CET)",
            "from nbfkord-smmo02.seg.att.com (nbfkord-smmo02.seg.att.com\n\t[209.65.160.78]) by dpdk.org (Postfix) with ESMTP id 3EB0C2A5D\n\tfor <dev@dpdk.org>; Mon, 21 Nov 2016 16:01:36 +0100 (CET)",
            "from unknown [12.187.104.26]\n\tby nbfkord-smmo02.seg.att.com(mxl_mta-7.2.4-7) with SMTP id\n\tf4c03385.0.1541294.00-2341.3424221.nbfkord-smmo02.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tMon, 21 Nov 2016 15:01:36 +0000 (UTC)",
            "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 21 Nov 2016 07:01:21 -0800",
            "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 21 Nov 2016 07:01:21 -0800",
            "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1KvJ007150 for <dev@dpdk.org>; Mon, 21 Nov 2016 15:01:20 GMT",
            "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1J39006765 for <dev@dpdk.org>; Mon, 21 Nov 2016 15:01:20 GMT"
        ],
        "X-MXL-Hash": "58330c505b1e8274-90493c1eff7c7d5b6cd80bc71d69079b6d3da12c",
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<dev@dpdk.org>",
        "Date": "Mon, 21 Nov 2016 15:00:32 +0000",
        "Message-ID": "<1479740470-6723-19-git-send-email-arybchenko@solarflare.com>",
        "X-Mailer": "git-send-email 1.8.2.3",
        "In-Reply-To": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>",
        "References": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-AnalysisOut": [
            "[v=2.1 cv=UI/baXry c=1 sm=1 tr=0 a=8BlWFWvVlq5taO8ncb8nKg==]",
            "[:17 a=L24OOQBejmoA:10 a=zRKbQ67AAAAA:8 a=6NTPsIJp9QXYow5L1]",
            "[iwA:9 a=O2Z7V4drA1lkGnfx:21 a=BrwsYzqvlwZVq3dQ:21 a=9xFqiD]",
            "[Ze9yZbLnpf:21 a=PA03WX8tBzeizutn5_OT:22]"
        ],
        "X-Spam": "[F=0.4927616373; CM=0.500; S=0.492(2015072901)]",
        "X-MAIL-FROM": "<arybchenko@solarflare.com>",
        "X-SOURCE-IP": "[12.187.104.26]",
        "Subject": "[dpdk-dev] [PATCH 18/56] net/sfc: import libefx MAC statistics\n\tsupport",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "MAC statistics are either periodically (if supported/requested)\nor on-demand written to provided DMA-mapped memory.\nIf periodic update is not supported (e.g. for EF10 virtual\nfunctions), it is the driver responsiblity to handle it.\n\nEFSYS_OPT_MAC_STATS should be enabled to use it.\n\nFrom Solarflare Communications Inc.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/efx/base/ef10_ev.c    |   6 +\n drivers/net/sfc/efx/base/ef10_impl.h  |  17 ++\n drivers/net/sfc/efx/base/ef10_mac.c   | 415 ++++++++++++++++++++++++++++++++++\n drivers/net/sfc/efx/base/ef10_nic.c   |  10 +\n drivers/net/sfc/efx/base/efx.h        | 175 ++++++++++++++\n drivers/net/sfc/efx/base/efx_check.h  |   7 +\n drivers/net/sfc/efx/base/efx_ev.c     |   6 +\n drivers/net/sfc/efx/base/efx_impl.h   |  29 +++\n drivers/net/sfc/efx/base/efx_mac.c    | 305 +++++++++++++++++++++++++\n drivers/net/sfc/efx/base/efx_mcdi.c   | 158 +++++++++++++\n drivers/net/sfc/efx/base/siena_impl.h |  17 ++\n drivers/net/sfc/efx/base/siena_mac.c  | 235 +++++++++++++++++++\n drivers/net/sfc/efx/base/siena_nic.c  |  10 +\n 13 files changed, 1390 insertions(+)",
    "diff": "diff --git a/drivers/net/sfc/efx/base/ef10_ev.c b/drivers/net/sfc/efx/base/ef10_ev.c\nindex b4fe9a7..f58ccc6 100644\n--- a/drivers/net/sfc/efx/base/ef10_ev.c\n+++ b/drivers/net/sfc/efx/base/ef10_ev.c\n@@ -1103,6 +1103,12 @@ ef10_ev_mcdi(\n \t\tbreak;\n \n \tcase MCDI_EVENT_CODE_MAC_STATS_DMA:\n+#if EFSYS_OPT_MAC_STATS\n+\t\tif (eecp->eec_mac_stats != NULL) {\n+\t\t\teecp->eec_mac_stats(arg,\n+\t\t\t    MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));\n+\t\t}\n+#endif\n \t\tbreak;\n \n \tcase MCDI_EVENT_CODE_FWALERT: {\ndiff --git a/drivers/net/sfc/efx/base/ef10_impl.h b/drivers/net/sfc/efx/base/ef10_impl.h\nindex e847c22..c778cce 100644\n--- a/drivers/net/sfc/efx/base/ef10_impl.h\n+++ b/drivers/net/sfc/efx/base/ef10_impl.h\n@@ -259,6 +259,23 @@ extern\t\t\tvoid\n ef10_mac_filter_default_rxq_clear(\n \t__in\t\tefx_nic_t *enp);\n \n+#if EFSYS_OPT_MAC_STATS\n+\n+extern\t__checkReturn\t\t\tefx_rc_t\n+ef10_mac_stats_get_mask(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__inout_bcount(mask_size)\tuint32_t *maskp,\n+\t__in\t\t\t\tsize_t mask_size);\n+\n+extern\t__checkReturn\t\t\tefx_rc_t\n+ef10_mac_stats_update(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_MAC_NSTATS)\tefsys_stat_t *stat,\n+\t__inout_opt\t\t\tuint32_t *generationp);\n+\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n+\n \n /* MCDI */\n \ndiff --git a/drivers/net/sfc/efx/base/ef10_mac.c b/drivers/net/sfc/efx/base/ef10_mac.c\nindex 7960067..477d0e7 100644\n--- a/drivers/net/sfc/efx/base/ef10_mac.c\n+++ b/drivers/net/sfc/efx/base/ef10_mac.c\n@@ -443,4 +443,419 @@ ef10_mac_filter_default_rxq_clear(\n }\n \n \n+#if EFSYS_OPT_MAC_STATS\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+ef10_mac_stats_get_mask(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__inout_bcount(mask_size)\tuint32_t *maskp,\n+\t__in\t\t\t\tsize_t mask_size)\n+{\n+\tconst struct efx_mac_stats_range ef10_common[] = {\n+\t\t{ EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS },\n+\t\t{ EFX_MAC_RX_FCS_ERRORS, EFX_MAC_RX_DROP_EVENTS },\n+\t\t{ EFX_MAC_RX_JABBER_PKTS, EFX_MAC_RX_JABBER_PKTS },\n+\t\t{ EFX_MAC_RX_NODESC_DROP_CNT, EFX_MAC_TX_PAUSE_PKTS },\n+\t};\n+\tconst struct efx_mac_stats_range ef10_tx_size_bins[] = {\n+\t\t{ EFX_MAC_TX_LE_64_PKTS, EFX_MAC_TX_GE_15XX_PKTS },\n+\t};\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tefx_port_t *epp = &(enp->en_port);\n+\tefx_rc_t rc;\n+\n+\tif ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,\n+\t    ef10_common, EFX_ARRAY_SIZE(ef10_common))) != 0)\n+\t\tgoto fail1;\n+\n+\tif (epp->ep_phy_cap_mask & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {\n+\t\tconst struct efx_mac_stats_range ef10_40g_extra[] = {\n+\t\t\t{ EFX_MAC_RX_ALIGN_ERRORS, EFX_MAC_RX_ALIGN_ERRORS },\n+\t\t};\n+\n+\t\tif ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,\n+\t\t    ef10_40g_extra, EFX_ARRAY_SIZE(ef10_40g_extra))) != 0)\n+\t\t\tgoto fail2;\n+\n+\t\tif (encp->enc_mac_stats_40g_tx_size_bins) {\n+\t\t\tif ((rc = efx_mac_stats_mask_add_ranges(maskp,\n+\t\t\t    mask_size, ef10_tx_size_bins,\n+\t\t\t    EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0)\n+\t\t\t\tgoto fail3;\n+\t\t}\n+\t} else {\n+\t\tif ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,\n+\t\t    ef10_tx_size_bins, EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0)\n+\t\t\tgoto fail4;\n+\t}\n+\n+\tif (encp->enc_pm_and_rxdp_counters) {\n+\t\tconst struct efx_mac_stats_range ef10_pm_and_rxdp[] = {\n+\t\t\t{ EFX_MAC_PM_TRUNC_BB_OVERFLOW, EFX_MAC_RXDP_HLB_WAIT },\n+\t\t};\n+\n+\t\tif ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,\n+\t\t    ef10_pm_and_rxdp, EFX_ARRAY_SIZE(ef10_pm_and_rxdp))) != 0)\n+\t\t\tgoto fail5;\n+\t}\n+\n+\tif (encp->enc_datapath_cap_evb) {\n+\t\tconst struct efx_mac_stats_range ef10_vadaptor[] = {\n+\t\t\t{ EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,\n+\t\t\t    EFX_MAC_VADAPTER_TX_OVERFLOW },\n+\t\t};\n+\n+\t\tif ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,\n+\t\t    ef10_vadaptor, EFX_ARRAY_SIZE(ef10_vadaptor))) != 0)\n+\t\t\tgoto fail6;\n+\t}\n+\n+\treturn (0);\n+\n+fail6:\n+\tEFSYS_PROBE(fail6);\n+fail5:\n+\tEFSYS_PROBE(fail5);\n+fail4:\n+\tEFSYS_PROBE(fail4);\n+fail3:\n+\tEFSYS_PROBE(fail3);\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+#define\tEF10_MAC_STAT_READ(_esmp, _field, _eqp)\t\t\t\\\n+\tEFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)\n+\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+ef10_mac_stats_update(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_MAC_NSTATS)\tefsys_stat_t *stat,\n+\t__inout_opt\t\t\tuint32_t *generationp)\n+{\n+\tefx_qword_t value;\n+\tefx_qword_t generation_start;\n+\tefx_qword_t generation_end;\n+\n+\t_NOTE(ARGUNUSED(enp))\n+\n+\t/* Read END first so we don't race with the MC */\n+\tEFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE);\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_END,\n+\t\t\t    &generation_end);\n+\tEFSYS_MEM_READ_BARRIER();\n+\n+\t/* TX */\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value);\n+\tEFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value);\n+\tEFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS,\n+\t\t\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS,\n+\t\t\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value);\n+\n+\t/* RX */\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value);\n+\tEFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value);\n+\tEFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value);\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]),\n+\t\t\t    &(value.eq_dword[0]));\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]),\n+\t\t\t    &(value.eq_dword[1]));\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value);\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]),\n+\t\t\t    &(value.eq_dword[0]));\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]),\n+\t\t\t    &(value.eq_dword[1]));\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value);\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]),\n+\t\t\t    &(value.eq_dword[0]));\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]),\n+\t\t\t    &(value.eq_dword[1]));\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value);\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]),\n+\t\t\t    &(value.eq_dword[0]));\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]),\n+\t\t\t    &(value.eq_dword[1]));\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value);\n+\n+\t/* Packet memory (EF10 only) */\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_BB_OVERFLOW]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_BB_OVERFLOW]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_VFIFO_FULL, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_VFIFO_FULL]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_VFIFO_FULL, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_VFIFO_FULL]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_QBB, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_QBB]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_QBB, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_QBB]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_MAPPING, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_MAPPING]), &value);\n+\n+\t/* RX datapath */\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_Q_DISABLED_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_Q_DISABLED_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_DI_DROPPED_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_DI_DROPPED_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_STREAMING_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_STREAMING_PKTS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_FETCH]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_WAIT]), &value);\n+\n+\n+\t/* VADAPTER RX */\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_PACKETS]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_BYTES]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_BYTES]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_BYTES]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_PACKETS]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_BYTES, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_BYTES]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_OVERFLOW, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_OVERFLOW]), &value);\n+\n+\t/* VADAPTER TX */\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_PACKETS]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_BYTES]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_BYTES]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES]),\n+\t    &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_PACKETS]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_BYTES, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_BYTES]), &value);\n+\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_OVERFLOW, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_OVERFLOW]), &value);\n+\n+\n+\tEFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE);\n+\tEFSYS_MEM_READ_BARRIER();\n+\tEF10_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START,\n+\t\t\t    &generation_start);\n+\n+\t/* Check that we didn't read the stats in the middle of a DMA */\n+\t/* Not a good enough check ? */\n+\tif (memcmp(&generation_start, &generation_end,\n+\t    sizeof (generation_start)))\n+\t\treturn (EAGAIN);\n+\n+\tif (generationp)\n+\t\t*generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);\n+\n+\treturn (0);\n+}\n+\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n+\n #endif\t/* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */\ndiff --git a/drivers/net/sfc/efx/base/ef10_nic.c b/drivers/net/sfc/efx/base/ef10_nic.c\nindex 0eb72a7..f28edd2 100644\n--- a/drivers/net/sfc/efx/base/ef10_nic.c\n+++ b/drivers/net/sfc/efx/base/ef10_nic.c\n@@ -1371,10 +1371,20 @@ ef10_nic_probe(\n \tedcp->edc_max_piobuf_count = 0;\n \tedcp->edc_pio_alloc_size = 0;\n \n+#if EFSYS_OPT_MAC_STATS\n+\t/* Wipe the MAC statistics */\n+\tif ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)\n+\t\tgoto fail5;\n+#endif\n+\n \tencp->enc_features = enp->en_features;\n \n \treturn (0);\n \n+#if EFSYS_OPT_MAC_STATS\n+fail5:\n+\tEFSYS_PROBE(fail5);\n+#endif\n fail4:\n \tEFSYS_PROBE(fail4);\n fail3:\ndiff --git a/drivers/net/sfc/efx/base/efx.h b/drivers/net/sfc/efx/base/efx.h\nindex 649c1a3..c06c9b6 100644\n--- a/drivers/net/sfc/efx/base/efx.h\n+++ b/drivers/net/sfc/efx/base/efx.h\n@@ -326,6 +326,98 @@ efx_intr_fini(\n \n /* MAC */\n \n+#if EFSYS_OPT_MAC_STATS\n+\n+/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */\n+typedef enum efx_mac_stat_e {\n+\tEFX_MAC_RX_OCTETS,\n+\tEFX_MAC_RX_PKTS,\n+\tEFX_MAC_RX_UNICST_PKTS,\n+\tEFX_MAC_RX_MULTICST_PKTS,\n+\tEFX_MAC_RX_BRDCST_PKTS,\n+\tEFX_MAC_RX_PAUSE_PKTS,\n+\tEFX_MAC_RX_LE_64_PKTS,\n+\tEFX_MAC_RX_65_TO_127_PKTS,\n+\tEFX_MAC_RX_128_TO_255_PKTS,\n+\tEFX_MAC_RX_256_TO_511_PKTS,\n+\tEFX_MAC_RX_512_TO_1023_PKTS,\n+\tEFX_MAC_RX_1024_TO_15XX_PKTS,\n+\tEFX_MAC_RX_GE_15XX_PKTS,\n+\tEFX_MAC_RX_ERRORS,\n+\tEFX_MAC_RX_FCS_ERRORS,\n+\tEFX_MAC_RX_DROP_EVENTS,\n+\tEFX_MAC_RX_FALSE_CARRIER_ERRORS,\n+\tEFX_MAC_RX_SYMBOL_ERRORS,\n+\tEFX_MAC_RX_ALIGN_ERRORS,\n+\tEFX_MAC_RX_INTERNAL_ERRORS,\n+\tEFX_MAC_RX_JABBER_PKTS,\n+\tEFX_MAC_RX_LANE0_CHAR_ERR,\n+\tEFX_MAC_RX_LANE1_CHAR_ERR,\n+\tEFX_MAC_RX_LANE2_CHAR_ERR,\n+\tEFX_MAC_RX_LANE3_CHAR_ERR,\n+\tEFX_MAC_RX_LANE0_DISP_ERR,\n+\tEFX_MAC_RX_LANE1_DISP_ERR,\n+\tEFX_MAC_RX_LANE2_DISP_ERR,\n+\tEFX_MAC_RX_LANE3_DISP_ERR,\n+\tEFX_MAC_RX_MATCH_FAULT,\n+\tEFX_MAC_RX_NODESC_DROP_CNT,\n+\tEFX_MAC_TX_OCTETS,\n+\tEFX_MAC_TX_PKTS,\n+\tEFX_MAC_TX_UNICST_PKTS,\n+\tEFX_MAC_TX_MULTICST_PKTS,\n+\tEFX_MAC_TX_BRDCST_PKTS,\n+\tEFX_MAC_TX_PAUSE_PKTS,\n+\tEFX_MAC_TX_LE_64_PKTS,\n+\tEFX_MAC_TX_65_TO_127_PKTS,\n+\tEFX_MAC_TX_128_TO_255_PKTS,\n+\tEFX_MAC_TX_256_TO_511_PKTS,\n+\tEFX_MAC_TX_512_TO_1023_PKTS,\n+\tEFX_MAC_TX_1024_TO_15XX_PKTS,\n+\tEFX_MAC_TX_GE_15XX_PKTS,\n+\tEFX_MAC_TX_ERRORS,\n+\tEFX_MAC_TX_SGL_COL_PKTS,\n+\tEFX_MAC_TX_MULT_COL_PKTS,\n+\tEFX_MAC_TX_EX_COL_PKTS,\n+\tEFX_MAC_TX_LATE_COL_PKTS,\n+\tEFX_MAC_TX_DEF_PKTS,\n+\tEFX_MAC_TX_EX_DEF_PKTS,\n+\tEFX_MAC_PM_TRUNC_BB_OVERFLOW,\n+\tEFX_MAC_PM_DISCARD_BB_OVERFLOW,\n+\tEFX_MAC_PM_TRUNC_VFIFO_FULL,\n+\tEFX_MAC_PM_DISCARD_VFIFO_FULL,\n+\tEFX_MAC_PM_TRUNC_QBB,\n+\tEFX_MAC_PM_DISCARD_QBB,\n+\tEFX_MAC_PM_DISCARD_MAPPING,\n+\tEFX_MAC_RXDP_Q_DISABLED_PKTS,\n+\tEFX_MAC_RXDP_DI_DROPPED_PKTS,\n+\tEFX_MAC_RXDP_STREAMING_PKTS,\n+\tEFX_MAC_RXDP_HLB_FETCH,\n+\tEFX_MAC_RXDP_HLB_WAIT,\n+\tEFX_MAC_VADAPTER_RX_UNICAST_PACKETS,\n+\tEFX_MAC_VADAPTER_RX_UNICAST_BYTES,\n+\tEFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,\n+\tEFX_MAC_VADAPTER_RX_MULTICAST_BYTES,\n+\tEFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,\n+\tEFX_MAC_VADAPTER_RX_BROADCAST_BYTES,\n+\tEFX_MAC_VADAPTER_RX_BAD_PACKETS,\n+\tEFX_MAC_VADAPTER_RX_BAD_BYTES,\n+\tEFX_MAC_VADAPTER_RX_OVERFLOW,\n+\tEFX_MAC_VADAPTER_TX_UNICAST_PACKETS,\n+\tEFX_MAC_VADAPTER_TX_UNICAST_BYTES,\n+\tEFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,\n+\tEFX_MAC_VADAPTER_TX_MULTICAST_BYTES,\n+\tEFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,\n+\tEFX_MAC_VADAPTER_TX_BROADCAST_BYTES,\n+\tEFX_MAC_VADAPTER_TX_BAD_PACKETS,\n+\tEFX_MAC_VADAPTER_TX_BAD_BYTES,\n+\tEFX_MAC_VADAPTER_TX_OVERFLOW,\n+\tEFX_MAC_NSTATS\n+} efx_mac_stat_t;\n+\n+/* END MKCONFIG GENERATED EfxHeaderMacBlock */\n+\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n+\n typedef enum efx_link_mode_e {\n \tEFX_LINK_UNKNOWN = 0,\n \tEFX_LINK_DOWN,\n@@ -431,6 +523,76 @@ efx_mac_fcntl_get(\n \t__out\t\tunsigned int *fcntl_linkp);\n \n \n+#if EFSYS_OPT_MAC_STATS\n+\n+#if EFSYS_OPT_NAMES\n+\n+extern\t__checkReturn\t\t\tconst char *\n+efx_mac_stat_name(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tunsigned int id);\n+\n+#endif\t/* EFSYS_OPT_NAMES */\n+\n+#define\tEFX_MAC_STATS_MASK_BITS_PER_PAGE\t(8 * sizeof (uint32_t))\n+\n+#define\tEFX_MAC_STATS_MASK_NPAGES\t\\\n+\t(P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \\\n+\t    EFX_MAC_STATS_MASK_BITS_PER_PAGE)\n+\n+/*\n+ * Get mask of MAC statistics supported by the hardware.\n+ *\n+ * If mask_size is insufficient to return the mask, EINVAL error is\n+ * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page\n+ * (which is sizeof (uint32_t)) is sufficient.\n+ */\n+extern\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_stats_get_mask(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__out_bcount(mask_size)\t\tuint32_t *maskp,\n+\t__in\t\t\t\tsize_t mask_size);\n+\n+#define\tEFX_MAC_STAT_SUPPORTED(_mask, _stat)\t\\\n+\t((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] &\t\\\n+\t (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))\n+\n+#define\tEFX_MAC_STATS_SIZE 0x400\n+\n+/*\n+ * Upload mac statistics supported by the hardware into the given buffer.\n+ *\n+ * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,\n+ * and page aligned.\n+ *\n+ * The hardware will only DMA statistics that it understands (of course).\n+ * Drivers should not make any assumptions about which statistics are\n+ * supported, especially when the statistics are generated by firmware.\n+ *\n+ * Thus, drivers should zero this buffer before use, so that not-understood\n+ * statistics read back as zero.\n+ */\n+extern\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_stats_upload(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp);\n+\n+extern\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_stats_periodic(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__in\t\t\t\tuint16_t period_ms,\n+\t__in\t\t\t\tboolean_t events);\n+\n+extern\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_stats_update(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_MAC_NSTATS)\tefsys_stat_t *stat,\n+\t__inout_opt\t\t\tuint32_t *generationp);\n+\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n+\n /* MON */\n \n typedef enum efx_mon_type_e {\n@@ -1122,6 +1284,16 @@ typedef __checkReturn\tboolean_t\n \t__in_opt\tvoid *arg,\n \t__in\t\tefx_link_mode_t\tlink_mode);\n \n+#if EFSYS_OPT_MAC_STATS\n+\n+typedef __checkReturn\tboolean_t\n+(*efx_mac_stats_ev_t)(\n+\t__in_opt\tvoid *arg,\n+\t__in\t\tuint32_t generation\n+\t);\n+\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n+\n typedef struct efx_ev_callbacks_s {\n \tefx_initialized_ev_t\t\teec_initialized;\n \tefx_rx_ev_t\t\t\teec_rx;\n@@ -1135,6 +1307,9 @@ typedef struct efx_ev_callbacks_s {\n \tefx_wake_up_ev_t\t\teec_wake_up;\n \tefx_timer_ev_t\t\t\teec_timer;\n \tefx_link_change_ev_t\t\teec_link_change;\n+#if EFSYS_OPT_MAC_STATS\n+\tefx_mac_stats_ev_t\t\teec_mac_stats;\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n } efx_ev_callbacks_t;\n \n extern\t__checkReturn\tboolean_t\ndiff --git a/drivers/net/sfc/efx/base/efx_check.h b/drivers/net/sfc/efx/base/efx_check.h\nindex 4e76dc1..5956052 100644\n--- a/drivers/net/sfc/efx/base/efx_check.h\n+++ b/drivers/net/sfc/efx/base/efx_check.h\n@@ -91,6 +91,13 @@\n # error \"MAC_FALCON_XMAC is obsolete and is not supported.\"\n #endif\n \n+#if EFSYS_OPT_MAC_STATS\n+/* Support MAC statistics */\n+# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)\n+#  error \"MAC_STATS requires SIENA or HUNTINGTON or MEDFORD\"\n+# endif\n+#endif /* EFSYS_OPT_MAC_STATS */\n+\n #if EFSYS_OPT_MCDI\n /* Support management controller messages */\n # if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)\ndiff --git a/drivers/net/sfc/efx/base/efx_ev.c b/drivers/net/sfc/efx/base/efx_ev.c\nindex c7c5fa8..74d146e 100644\n--- a/drivers/net/sfc/efx/base/efx_ev.c\n+++ b/drivers/net/sfc/efx/base/efx_ev.c\n@@ -1065,6 +1065,12 @@ siena_ev_mcdi(\n \t\tbreak;\n \n \tcase MCDI_EVENT_CODE_MAC_STATS_DMA:\n+#if EFSYS_OPT_MAC_STATS\n+\t\tif (eecp->eec_mac_stats != NULL) {\n+\t\t\teecp->eec_mac_stats(arg,\n+\t\t\t    MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));\n+\t\t}\n+#endif\n \t\tbreak;\n \n \tcase MCDI_EVENT_CODE_FWALERT: {\ndiff --git a/drivers/net/sfc/efx/base/efx_impl.h b/drivers/net/sfc/efx/base/efx_impl.h\nindex 6077114..a1eabcd 100644\n--- a/drivers/net/sfc/efx/base/efx_impl.h\n+++ b/drivers/net/sfc/efx/base/efx_impl.h\n@@ -174,6 +174,14 @@ typedef struct efx_mac_ops_s {\n \tefx_rc_t\t(*emo_filter_default_rxq_set)(efx_nic_t *,\n \t\t\t\t\t\t      efx_rxq_t *, boolean_t);\n \tvoid\t\t(*emo_filter_default_rxq_clear)(efx_nic_t *);\n+#if EFSYS_OPT_MAC_STATS\n+\tefx_rc_t\t(*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);\n+\tefx_rc_t\t(*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);\n+\tefx_rc_t\t(*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,\n+\t\t\t\t\t      uint16_t, boolean_t);\n+\tefx_rc_t\t(*emo_stats_update)(efx_nic_t *, efsys_mem_t *,\n+\t\t\t\t\t    efsys_stat_t *, uint32_t *);\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n } efx_mac_ops_t;\n \n typedef struct efx_phy_ops_s {\n@@ -909,6 +917,27 @@ efx_mcdi_get_workarounds(\n \n #endif /* EFSYS_OPT_MCDI */\n \n+#if EFSYS_OPT_MAC_STATS\n+\n+/*\n+ * Closed range of stats (i.e. the first and the last are included).\n+ * The last must be greater or equal (if the range is one item only) to\n+ * the first.\n+ */\n+struct efx_mac_stats_range {\n+\tefx_mac_stat_t\t\tfirst;\n+\tefx_mac_stat_t\t\tlast;\n+};\n+\n+extern\t\t\t\t\tefx_rc_t\n+efx_mac_stats_mask_add_ranges(\n+\t__inout_bcount(mask_size)\tuint32_t *maskp,\n+\t__in\t\t\t\tsize_t mask_size,\n+\t__in_ecount(rng_count)\t\tconst struct efx_mac_stats_range *rngp,\n+\t__in\t\t\t\tunsigned int rng_count);\n+\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n+\n #ifdef\t__cplusplus\n }\n #endif\ndiff --git a/drivers/net/sfc/efx/base/efx_mac.c b/drivers/net/sfc/efx/base/efx_mac.c\nindex c10c79a..840b7db 100644\n--- a/drivers/net/sfc/efx/base/efx_mac.c\n+++ b/drivers/net/sfc/efx/base/efx_mac.c\n@@ -50,6 +50,12 @@ static const efx_mac_ops_t\t__efx_siena_mac_ops = {\n \tsiena_mac_multicast_list_set,\t\t/* emo_multicast_list_set */\n \tNULL,\t\t\t\t\t/* emo_filter_set_default_rxq */\n \tNULL,\t\t\t\t/* emo_filter_default_rxq_clear */\n+#if EFSYS_OPT_MAC_STATS\n+\tsiena_mac_stats_get_mask,\t\t/* emo_stats_get_mask */\n+\tefx_mcdi_mac_stats_upload,\t\t/* emo_stats_upload */\n+\tefx_mcdi_mac_stats_periodic,\t\t/* emo_stats_periodic */\n+\tsiena_mac_stats_update\t\t\t/* emo_stats_update */\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n };\n #endif\t/* EFSYS_OPT_SIENA */\n \n@@ -65,6 +71,12 @@ static const efx_mac_ops_t\t__efx_ef10_mac_ops = {\n \tef10_mac_filter_default_rxq_set,\t/* emo_filter_default_rxq_set */\n \tef10_mac_filter_default_rxq_clear,\n \t\t\t\t\t/* emo_filter_default_rxq_clear */\n+#if EFSYS_OPT_MAC_STATS\n+\tef10_mac_stats_get_mask,\t\t/* emo_stats_get_mask */\n+\tefx_mcdi_mac_stats_upload,\t\t/* emo_stats_upload */\n+\tefx_mcdi_mac_stats_periodic,\t\t/* emo_stats_periodic */\n+\tef10_mac_stats_update\t\t\t/* emo_stats_update */\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n };\n #endif\t/* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */\n \n@@ -492,6 +504,299 @@ efx_mac_filter_default_rxq_clear(\n }\n \n \n+#if EFSYS_OPT_MAC_STATS\n+\n+#if EFSYS_OPT_NAMES\n+\n+/* START MKCONFIG GENERATED EfxMacStatNamesBlock c11b91b42f922516 */\n+static const char * const __efx_mac_stat_name[] = {\n+\t\"rx_octets\",\n+\t\"rx_pkts\",\n+\t\"rx_unicst_pkts\",\n+\t\"rx_multicst_pkts\",\n+\t\"rx_brdcst_pkts\",\n+\t\"rx_pause_pkts\",\n+\t\"rx_le_64_pkts\",\n+\t\"rx_65_to_127_pkts\",\n+\t\"rx_128_to_255_pkts\",\n+\t\"rx_256_to_511_pkts\",\n+\t\"rx_512_to_1023_pkts\",\n+\t\"rx_1024_to_15xx_pkts\",\n+\t\"rx_ge_15xx_pkts\",\n+\t\"rx_errors\",\n+\t\"rx_fcs_errors\",\n+\t\"rx_drop_events\",\n+\t\"rx_false_carrier_errors\",\n+\t\"rx_symbol_errors\",\n+\t\"rx_align_errors\",\n+\t\"rx_internal_errors\",\n+\t\"rx_jabber_pkts\",\n+\t\"rx_lane0_char_err\",\n+\t\"rx_lane1_char_err\",\n+\t\"rx_lane2_char_err\",\n+\t\"rx_lane3_char_err\",\n+\t\"rx_lane0_disp_err\",\n+\t\"rx_lane1_disp_err\",\n+\t\"rx_lane2_disp_err\",\n+\t\"rx_lane3_disp_err\",\n+\t\"rx_match_fault\",\n+\t\"rx_nodesc_drop_cnt\",\n+\t\"tx_octets\",\n+\t\"tx_pkts\",\n+\t\"tx_unicst_pkts\",\n+\t\"tx_multicst_pkts\",\n+\t\"tx_brdcst_pkts\",\n+\t\"tx_pause_pkts\",\n+\t\"tx_le_64_pkts\",\n+\t\"tx_65_to_127_pkts\",\n+\t\"tx_128_to_255_pkts\",\n+\t\"tx_256_to_511_pkts\",\n+\t\"tx_512_to_1023_pkts\",\n+\t\"tx_1024_to_15xx_pkts\",\n+\t\"tx_ge_15xx_pkts\",\n+\t\"tx_errors\",\n+\t\"tx_sgl_col_pkts\",\n+\t\"tx_mult_col_pkts\",\n+\t\"tx_ex_col_pkts\",\n+\t\"tx_late_col_pkts\",\n+\t\"tx_def_pkts\",\n+\t\"tx_ex_def_pkts\",\n+\t\"pm_trunc_bb_overflow\",\n+\t\"pm_discard_bb_overflow\",\n+\t\"pm_trunc_vfifo_full\",\n+\t\"pm_discard_vfifo_full\",\n+\t\"pm_trunc_qbb\",\n+\t\"pm_discard_qbb\",\n+\t\"pm_discard_mapping\",\n+\t\"rxdp_q_disabled_pkts\",\n+\t\"rxdp_di_dropped_pkts\",\n+\t\"rxdp_streaming_pkts\",\n+\t\"rxdp_hlb_fetch\",\n+\t\"rxdp_hlb_wait\",\n+\t\"vadapter_rx_unicast_packets\",\n+\t\"vadapter_rx_unicast_bytes\",\n+\t\"vadapter_rx_multicast_packets\",\n+\t\"vadapter_rx_multicast_bytes\",\n+\t\"vadapter_rx_broadcast_packets\",\n+\t\"vadapter_rx_broadcast_bytes\",\n+\t\"vadapter_rx_bad_packets\",\n+\t\"vadapter_rx_bad_bytes\",\n+\t\"vadapter_rx_overflow\",\n+\t\"vadapter_tx_unicast_packets\",\n+\t\"vadapter_tx_unicast_bytes\",\n+\t\"vadapter_tx_multicast_packets\",\n+\t\"vadapter_tx_multicast_bytes\",\n+\t\"vadapter_tx_broadcast_packets\",\n+\t\"vadapter_tx_broadcast_bytes\",\n+\t\"vadapter_tx_bad_packets\",\n+\t\"vadapter_tx_bad_bytes\",\n+\t\"vadapter_tx_overflow\",\n+};\n+/* END MKCONFIG GENERATED EfxMacStatNamesBlock */\n+\n+\t__checkReturn\t\t\tconst char *\n+efx_mac_stat_name(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tunsigned int id)\n+{\n+\t_NOTE(ARGUNUSED(enp))\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\n+\tEFSYS_ASSERT3U(id, <, EFX_MAC_NSTATS);\n+\treturn (__efx_mac_stat_name[id]);\n+}\n+\n+#endif\t/* EFSYS_OPT_NAMES */\n+\n+static\t\t\t\t\tefx_rc_t\n+efx_mac_stats_mask_add_range(\n+\t__inout_bcount(mask_size)\tuint32_t *maskp,\n+\t__in\t\t\t\tsize_t mask_size,\n+\t__in\t\t\t\tconst struct efx_mac_stats_range *rngp)\n+{\n+\tunsigned int mask_npages = mask_size / sizeof (*maskp);\n+\tunsigned int el;\n+\tunsigned int el_min;\n+\tunsigned int el_max;\n+\tunsigned int low;\n+\tunsigned int high;\n+\tunsigned int width;\n+\tefx_rc_t rc;\n+\n+\tif ((mask_npages * EFX_MAC_STATS_MASK_BITS_PER_PAGE) <=\n+\t    (unsigned int)rngp->last) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tEFSYS_ASSERT3U(rngp->first, <=, rngp->last);\n+\tEFSYS_ASSERT3U(rngp->last, <, EFX_MAC_NSTATS);\n+\n+\tfor (el = 0; el < mask_npages; ++el) {\n+\t\tel_min = el * EFX_MAC_STATS_MASK_BITS_PER_PAGE;\n+\t\tel_max =\n+\t\t    el_min + (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1);\n+\t\tif ((unsigned int)rngp->first > el_max ||\n+\t\t    (unsigned int)rngp->last < el_min)\n+\t\t\tcontinue;\n+\t\tlow = MAX((unsigned int)rngp->first, el_min);\n+\t\thigh = MIN((unsigned int)rngp->last, el_max);\n+\t\twidth = high - low + 1;\n+\t\tmaskp[el] |=\n+\t\t    (width == EFX_MAC_STATS_MASK_BITS_PER_PAGE) ?\n+\t\t    (~0ULL) : (((1ULL << width) - 1) << (low - el_min));\n+\t}\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t\t\t\t\tefx_rc_t\n+efx_mac_stats_mask_add_ranges(\n+\t__inout_bcount(mask_size)\tuint32_t *maskp,\n+\t__in\t\t\t\tsize_t mask_size,\n+\t__in_ecount(rng_count)\t\tconst struct efx_mac_stats_range *rngp,\n+\t__in\t\t\t\tunsigned int rng_count)\n+{\n+\tunsigned int i;\n+\tefx_rc_t rc;\n+\n+\tfor (i = 0; i < rng_count; ++i) {\n+\t\tif ((rc = efx_mac_stats_mask_add_range(maskp, mask_size,\n+\t\t    &rngp[i])) != 0)\n+\t\t\tgoto fail1;\n+\t}\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_stats_get_mask(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__out_bcount(mask_size)\t\tuint32_t *maskp,\n+\t__in\t\t\t\tsize_t mask_size)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);\n+\tEFSYS_ASSERT(maskp != NULL);\n+\tEFSYS_ASSERT(mask_size % sizeof (maskp[0]) == 0);\n+\n+\t(void) memset(maskp, 0, mask_size);\n+\n+\tif ((rc = emop->emo_stats_get_mask(enp, maskp, mask_size)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_stats_upload(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\tEFSYS_ASSERT(emop != NULL);\n+\n+\t/*\n+\t * Don't assert !ep_mac_stats_pending, because the client might\n+\t * have failed to finalise statistics when previously stopping\n+\t * the port.\n+\t */\n+\tif ((rc = emop->emo_stats_upload(enp, esmp)) != 0)\n+\t\tgoto fail1;\n+\n+\tepp->ep_mac_stats_pending = B_TRUE;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_stats_periodic(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__in\t\t\t\tuint16_t period_ms,\n+\t__in\t\t\t\tboolean_t events)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\tEFSYS_ASSERT(emop != NULL);\n+\n+\tif (emop->emo_stats_periodic == NULL) {\n+\t\trc = EINVAL;\n+\t\tgoto fail1;\n+\t}\n+\n+\tif ((rc = emop->emo_stats_periodic(enp, esmp, period_ms, events)) != 0)\n+\t\tgoto fail2;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_mac_stats_update(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_MAC_NSTATS)\tefsys_stat_t *essp,\n+\t__inout_opt\t\t\tuint32_t *generationp)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_mac_ops_t *emop = epp->ep_emop;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\tEFSYS_ASSERT(emop != NULL);\n+\n+\trc = emop->emo_stats_update(enp, esmp, essp, generationp);\n+\tif (rc == 0)\n+\t\tepp->ep_mac_stats_pending = B_FALSE;\n+\n+\treturn (rc);\n+}\n+\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n+\n \t__checkReturn\t\t\tefx_rc_t\n efx_mac_select(\n \t__in\t\t\t\tefx_nic_t *enp)\ndiff --git a/drivers/net/sfc/efx/base/efx_mcdi.c b/drivers/net/sfc/efx/base/efx_mcdi.c\nindex 15ec999..dc34e48 100644\n--- a/drivers/net/sfc/efx/base/efx_mcdi.c\n+++ b/drivers/net/sfc/efx/base/efx_mcdi.c\n@@ -1708,6 +1708,164 @@ efx_mcdi_log_ctrl(\n }\n \n \n+#if EFSYS_OPT_MAC_STATS\n+\n+typedef enum efx_stats_action_e {\n+\tEFX_STATS_CLEAR,\n+\tEFX_STATS_UPLOAD,\n+\tEFX_STATS_ENABLE_NOEVENTS,\n+\tEFX_STATS_ENABLE_EVENTS,\n+\tEFX_STATS_DISABLE,\n+} efx_stats_action_t;\n+\n+static\t__checkReturn\tefx_rc_t\n+efx_mcdi_mac_stats(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in_opt\tefsys_mem_t *esmp,\n+\t__in\t\tefx_stats_action_t action)\n+{\n+\tefx_mcdi_req_t req;\n+\tuint8_t payload[MAX(MC_CMD_MAC_STATS_IN_LEN,\n+\t\t\t    MC_CMD_MAC_STATS_OUT_DMA_LEN)];\n+\tint clear = (action == EFX_STATS_CLEAR);\n+\tint upload = (action == EFX_STATS_UPLOAD);\n+\tint enable = (action == EFX_STATS_ENABLE_NOEVENTS);\n+\tint events = (action == EFX_STATS_ENABLE_EVENTS);\n+\tint disable = (action == EFX_STATS_DISABLE);\n+\tefx_rc_t rc;\n+\n+\t(void) memset(payload, 0, sizeof (payload));\n+\treq.emr_cmd = MC_CMD_MAC_STATS;\n+\treq.emr_in_buf = payload;\n+\treq.emr_in_length = MC_CMD_MAC_STATS_IN_LEN;\n+\treq.emr_out_buf = payload;\n+\treq.emr_out_length = MC_CMD_MAC_STATS_OUT_DMA_LEN;\n+\n+\tMCDI_IN_POPULATE_DWORD_6(req, MAC_STATS_IN_CMD,\n+\t    MAC_STATS_IN_DMA, upload,\n+\t    MAC_STATS_IN_CLEAR, clear,\n+\t    MAC_STATS_IN_PERIODIC_CHANGE, enable | events | disable,\n+\t    MAC_STATS_IN_PERIODIC_ENABLE, enable | events,\n+\t    MAC_STATS_IN_PERIODIC_NOEVENT, !events,\n+\t    MAC_STATS_IN_PERIOD_MS, (enable | events) ? 1000 : 0);\n+\n+\tif (esmp != NULL) {\n+\t\tint bytes = MC_CMD_MAC_NSTATS * sizeof (uint64_t);\n+\n+\t\tEFX_STATIC_ASSERT(MC_CMD_MAC_NSTATS * sizeof (uint64_t) <=\n+\t\t    EFX_MAC_STATS_SIZE);\n+\n+\t\tMCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_LO,\n+\t\t\t    EFSYS_MEM_ADDR(esmp) & 0xffffffff);\n+\t\tMCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_HI,\n+\t\t\t    EFSYS_MEM_ADDR(esmp) >> 32);\n+\t\tMCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_LEN, bytes);\n+\t} else {\n+\t\tEFSYS_ASSERT(!upload && !enable && !events);\n+\t}\n+\n+\t/*\n+\t * NOTE: Do not use EVB_PORT_ID_ASSIGNED when disabling periodic stats,\n+\t *\t as this may fail (and leave periodic DMA enabled) if the\n+\t *\t vadapter has already been deleted.\n+\t */\n+\tMCDI_IN_SET_DWORD(req, MAC_STATS_IN_PORT_ID,\n+\t    (disable ? EVB_PORT_ID_NULL : enp->en_vport_id));\n+\n+\tefx_mcdi_execute(enp, &req);\n+\n+\tif (req.emr_rc != 0) {\n+\t\t/* EF10: Expect ENOENT if no DMA queues are initialised */\n+\t\tif ((req.emr_rc != ENOENT) ||\n+\t\t    (enp->en_rx_qcount + enp->en_tx_qcount != 0)) {\n+\t\t\trc = req.emr_rc;\n+\t\t\tgoto fail1;\n+\t\t}\n+\t}\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_mcdi_mac_stats_clear(\n+\t__in\t\tefx_nic_t *enp)\n+{\n+\tefx_rc_t rc;\n+\n+\tif ((rc = efx_mcdi_mac_stats(enp, NULL, EFX_STATS_CLEAR)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_mcdi_mac_stats_upload(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefsys_mem_t *esmp)\n+{\n+\tefx_rc_t rc;\n+\n+\t/*\n+\t * The MC DMAs aggregate statistics for our convenience, so we can\n+\t * avoid having to pull the statistics buffer into the cache to\n+\t * maintain cumulative statistics.\n+\t */\n+\tif ((rc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_UPLOAD)) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\t__checkReturn\tefx_rc_t\n+efx_mcdi_mac_stats_periodic(\n+\t__in\t\tefx_nic_t *enp,\n+\t__in\t\tefsys_mem_t *esmp,\n+\t__in\t\tuint16_t period,\n+\t__in\t\tboolean_t events)\n+{\n+\tefx_rc_t rc;\n+\n+\t/*\n+\t * The MC DMAs aggregate statistics for our convenience, so we can\n+\t * avoid having to pull the statistics buffer into the cache to\n+\t * maintain cumulative statistics.\n+\t * Huntington uses a fixed 1sec period, so use that on Siena too.\n+\t */\n+\tif (period == 0)\n+\t\trc = efx_mcdi_mac_stats(enp, NULL, EFX_STATS_DISABLE);\n+\telse if (events)\n+\t\trc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_ENABLE_EVENTS);\n+\telse\n+\t\trc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_ENABLE_NOEVENTS);\n+\n+\tif (rc != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n+\n #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD\n \n /*\ndiff --git a/drivers/net/sfc/efx/base/siena_impl.h b/drivers/net/sfc/efx/base/siena_impl.h\nindex fc01205..98fd2c5 100644\n--- a/drivers/net/sfc/efx/base/siena_impl.h\n+++ b/drivers/net/sfc/efx/base/siena_impl.h\n@@ -232,6 +232,23 @@ siena_mac_pdu_get(\n \t__in\tefx_nic_t *enp,\n \t__out\tsize_t *pdu);\n \n+#if EFSYS_OPT_MAC_STATS\n+\n+extern\t__checkReturn\t\t\tefx_rc_t\n+siena_mac_stats_get_mask(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__inout_bcount(mask_size)\tuint32_t *maskp,\n+\t__in\t\t\t\tsize_t mask_size);\n+\n+extern\t__checkReturn\t\t\tefx_rc_t\n+siena_mac_stats_update(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_MAC_NSTATS)\tefsys_stat_t *stat,\n+\t__inout_opt\t\t\tuint32_t *generationp);\n+\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n+\n #ifdef\t__cplusplus\n }\n #endif\ndiff --git a/drivers/net/sfc/efx/base/siena_mac.c b/drivers/net/sfc/efx/base/siena_mac.c\nindex 71b0a9a..dbe9c6f 100644\n--- a/drivers/net/sfc/efx/base/siena_mac.c\n+++ b/drivers/net/sfc/efx/base/siena_mac.c\n@@ -194,6 +194,241 @@ siena_mac_reconfigure(\n \treturn (rc);\n }\n \n+#if EFSYS_OPT_MAC_STATS\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+siena_mac_stats_get_mask(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__inout_bcount(mask_size)\tuint32_t *maskp,\n+\t__in\t\t\t\tsize_t mask_size)\n+{\n+\tconst struct efx_mac_stats_range siena_stats[] = {\n+\t\t{ EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS },\n+\t\t/* EFX_MAC_RX_ERRORS is not supported */\n+\t\t{ EFX_MAC_RX_FCS_ERRORS, EFX_MAC_TX_EX_DEF_PKTS },\n+\t};\n+\tefx_rc_t rc;\n+\n+\t_NOTE(ARGUNUSED(enp))\n+\n+\tif ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,\n+\t    siena_stats, EFX_ARRAY_SIZE(siena_stats))) != 0)\n+\t\tgoto fail1;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+#define\tSIENA_MAC_STAT_READ(_esmp, _field, _eqp)\t\t\t\\\n+\tEFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+siena_mac_stats_update(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_MAC_NSTATS)\tefsys_stat_t *stat,\n+\t__inout_opt\t\t\tuint32_t *generationp)\n+{\n+\tefx_qword_t value;\n+\tefx_qword_t generation_start;\n+\tefx_qword_t generation_end;\n+\n+\t_NOTE(ARGUNUSED(enp))\n+\n+\t/* Read END first so we don't race with the MC */\n+\tEFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE);\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_END,\n+\t\t\t    &generation_end);\n+\tEFSYS_MEM_READ_BARRIER();\n+\n+\t/* TX */\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value);\n+\tEFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value);\n+\tEFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value);\n+\tEFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS,\n+\t\t\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS,\n+\t\t\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS,\n+\t    &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value);\n+\n+\t/* RX */\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value);\n+\tEFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value);\n+\tEFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value);\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]),\n+\t\t\t    &(value.eq_dword[0]));\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]),\n+\t\t\t    &(value.eq_dword[1]));\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value);\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]),\n+\t\t\t    &(value.eq_dword[0]));\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]),\n+\t\t\t    &(value.eq_dword[1]));\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value);\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]),\n+\t\t\t    &(value.eq_dword[0]));\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]),\n+\t\t\t    &(value.eq_dword[1]));\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value);\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]),\n+\t\t\t    &(value.eq_dword[0]));\n+\tEFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]),\n+\t\t\t    &(value.eq_dword[1]));\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value);\n+\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value);\n+\tEFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value);\n+\n+\tEFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE);\n+\tEFSYS_MEM_READ_BARRIER();\n+\tSIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START,\n+\t\t\t    &generation_start);\n+\n+\t/* Check that we didn't read the stats in the middle of a DMA */\n+\t/* Not a good enough check ? */\n+\tif (memcmp(&generation_start, &generation_end,\n+\t    sizeof (generation_start)))\n+\t\treturn (EAGAIN);\n+\n+\tif (generationp)\n+\t\t*generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);\n+\n+\treturn (0);\n+}\n+\n+#endif\t/* EFSYS_OPT_MAC_STATS */\n+\n \t__checkReturn\t\tefx_rc_t\n siena_mac_pdu_get(\n \t__in\t\tefx_nic_t *enp,\ndiff --git a/drivers/net/sfc/efx/base/siena_nic.c b/drivers/net/sfc/efx/base/siena_nic.c\nindex 135f705..c77393a 100644\n--- a/drivers/net/sfc/efx/base/siena_nic.c\n+++ b/drivers/net/sfc/efx/base/siena_nic.c\n@@ -210,10 +210,20 @@ siena_nic_probe(\n \tepp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;\n \tepp->ep_adv_cap_mask = sls.sls_adv_cap_mask;\n \n+#if EFSYS_OPT_MAC_STATS\n+\t/* Wipe the MAC statistics */\n+\tif ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)\n+\t\tgoto fail10;\n+#endif\n+\n \tencp->enc_features = enp->en_features;\n \n \treturn (0);\n \n+#if EFSYS_OPT_MAC_STATS\n+fail10:\n+\tEFSYS_PROBE(fail10);\n+#endif\n fail8:\n \tEFSYS_PROBE(fail8);\n fail7:\n",
    "prefixes": [
        "dpdk-dev",
        "18/56"
    ]
}