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{
    "id": 16262,
    "url": "https://patches.dpdk.org/api/patches/16262/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1475219169-8774-2-git-send-email-rasesh.mody@qlogic.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1475219169-8774-2-git-send-email-rasesh.mody@qlogic.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1475219169-8774-2-git-send-email-rasesh.mody@qlogic.com",
    "date": "2016-09-30T07:05:48",
    "name": "[dpdk-dev,v2,01/22] qede/base: add new files and shuffle the code",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "bc7b29009bf87f5fcc937b269d9d27f958b86dee",
    "submitter": {
        "id": 325,
        "url": "https://patches.dpdk.org/api/people/325/?format=api",
        "name": "Rasesh Mody",
        "email": "rasesh.mody@qlogic.com"
    },
    "delegate": {
        "id": 10,
        "url": "https://patches.dpdk.org/api/users/10/?format=api",
        "username": "bruce",
        "first_name": "Bruce",
        "last_name": "Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1475219169-8774-2-git-send-email-rasesh.mody@qlogic.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/16262/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/16262/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 9F67E56A8;\n\tFri, 30 Sep 2016 09:06:19 +0200 (CEST)",
            "from mx0b-0016ce01.pphosted.com (mx0b-0016ce01.pphosted.com\n\t[67.231.156.153]) by dpdk.org (Postfix) with ESMTP id E08205699\n\tfor <dev@dpdk.org>; Fri, 30 Sep 2016 09:06:17 +0200 (CEST)",
            "from pps.filterd (m0085408.ppops.net [127.0.0.1])\n\tby mx0b-0016ce01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id\n\tu8U76HNG021380 for <dev@dpdk.org>; Fri, 30 Sep 2016 00:06:17 -0700",
            "from avcashub1.qlogic.com ([198.186.0.116])\n\tby mx0b-0016ce01.pphosted.com with ESMTP id 25s5nvu6bd-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 30 Sep 2016 00:06:16 -0700",
            "from avluser05.qlc.com (10.1.113.115) by qlc.com (10.1.4.191) with\n\tMicrosoft SMTP Server id 14.3.235.1;\n\tFri, 30 Sep 2016 00:06:14 -0700",
            "(from rmody@localhost)\tby avluser05.qlc.com (8.14.4/8.14.4/Submit)\n\tid u8U76FCk008834;\tFri, 30 Sep 2016 00:06:15 -0700"
        ],
        "X-Authentication-Warning": "avluser05.qlc.com: rmody set sender to\n\trasesh.mody@qlogic.com using -f",
        "From": "Rasesh Mody <rasesh.mody@qlogic.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<Dept-EngDPDKDev@qlogic.com>, Rasesh Mody <rasesh.mody@qlogic.com>",
        "Date": "Fri, 30 Sep 2016 00:05:48 -0700",
        "Message-ID": "<1475219169-8774-2-git-send-email-rasesh.mody@qlogic.com>",
        "X-Mailer": "git-send-email 1.7.10.3",
        "In-Reply-To": "<1475219169-8774-1-git-send-email-rasesh.mody@qlogic.com>",
        "References": "<1475219169-8774-1-git-send-email-rasesh.mody@qlogic.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "disclaimer": "bypass",
        "X-Proofpoint-Virus-Version": "vendor=nai engine=5800 definitions=8303\n\tsignatures=670713",
        "X-Proofpoint-Spam-Details": "rule=notspam policy=default score=0\n\tpriorityscore=1501 malwarescore=0\n\tsuspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011\n\tlowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam\n\tadjust=0\n\treason=mlx scancount=1 engine=8.0.1-1609280000\n\tdefinitions=main-1609300128",
        "Subject": "[dpdk-dev] [PATCH v2 01/22] qede/base: add new files and shuffle\n\tthe code",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Added ecore_hsi_debug_tools.h, ecore_hsi_init_func.h,\necore_hsi_init_tool.h files. Shuffled code from ecore_hsi_common.h and\necore_hsi_tools.h to the new files. Removed unused code.\n\nSigned-off-by: Rasesh Mody <rasesh.mody@qlogic.com>\n---\n drivers/net/qede/base/ecore.h                 |   17 +-\n drivers/net/qede/base/ecore_dev.c             |   73 +-\n drivers/net/qede/base/ecore_hsi_common.h      |  226 ------\n drivers/net/qede/base/ecore_hsi_debug_tools.h | 1025 +++++++++++++++++++++++\n drivers/net/qede/base/ecore_hsi_init_func.h   |  132 +++\n drivers/net/qede/base/ecore_hsi_init_tool.h   |  454 +++++++++++\n drivers/net/qede/base/ecore_hsi_tools.h       | 1081 -------------------------\n drivers/net/qede/base/ecore_init_fw_funcs.c   |   67 +-\n drivers/net/qede/base/ecore_init_ops.c        |    2 +-\n drivers/net/qede/base/ecore_int.c             |  141 +---\n 10 files changed, 1678 insertions(+), 1540 deletions(-)\n create mode 100644 drivers/net/qede/base/ecore_hsi_debug_tools.h\n create mode 100644 drivers/net/qede/base/ecore_hsi_init_func.h\n create mode 100644 drivers/net/qede/base/ecore_hsi_init_tool.h\n delete mode 100644 drivers/net/qede/base/ecore_hsi_tools.h",
    "diff": "diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex d682a78..db72f03 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -10,7 +10,9 @@\n #define __ECORE_H\n \n #include \"ecore_hsi_common.h\"\n-#include \"ecore_hsi_tools.h\"\n+#include \"ecore_hsi_debug_tools.h\"\n+#include \"ecore_hsi_init_func.h\"\n+#include \"ecore_hsi_init_tool.h\"\n #include \"ecore_proto_if.h\"\n #include \"mcp_public.h\"\n \n@@ -556,14 +558,15 @@ struct ecore_dev {\n #define ECORE_DEV_TYPE_AH\t(1 << 0)\n /* Translate type/revision combo into the proper conditions */\n #define ECORE_IS_BB(dev)\t((dev)->type == ECORE_DEV_TYPE_BB)\n-#define ECORE_IS_BB_A0(dev)\t(ECORE_IS_BB(dev) && \\\n-\t\t\t\t CHIP_REV_IS_A0(dev))\n-#define ECORE_IS_BB_B0(dev)\t(ECORE_IS_BB(dev) && \\\n-\t\t\t\t CHIP_REV_IS_B0(dev))\n+#define ECORE_IS_BB_A0(dev)\t(ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))\n+#ifndef ASIC_ONLY\n+#define ECORE_IS_BB_B0(dev)\t((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \\\n+\t\t\t\t (CHIP_REV_IS_TEDIBEAR(dev)))\n+#else\n+#define ECORE_IS_BB_B0(dev)\t(ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))\n+#endif\n #define ECORE_IS_AH(dev)\t((dev)->type == ECORE_DEV_TYPE_AH)\n #define ECORE_IS_K2(dev)\tECORE_IS_AH(dev)\n-#define ECORE_GET_TYPE(dev)\t(ECORE_IS_BB_A0(dev) ? CHIP_BB_A0 : \\\n-\t\t\t\t ECORE_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)\n \n \tu16 vendor_id;\n \tu16 device_id;\ndiff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex 0a68969..89faa35 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -281,13 +281,6 @@ static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,\n \tfor (i = 0; i < num_ports; i++) {\n \t\tp_qm_port = &qm_info->qm_port_params[i];\n \t\tp_qm_port->active = 1;\n-\t\t/* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will\n-\t\t * be in place\n-\t\t */\n-\t\tif (num_ports == 4)\n-\t\t\tp_qm_port->num_active_phys_tcs = 2;\n-\t\telse\n-\t\t\tp_qm_port->num_active_phys_tcs = 5;\n \t\tp_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;\n \t\tp_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;\n \t}\n@@ -599,19 +592,15 @@ static void ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)\n {\n \tint hw_mode = 0;\n \n-\tswitch (ECORE_GET_TYPE(p_hwfn->p_dev)) {\n-\tcase CHIP_BB_A0:\n+\tif (ECORE_IS_BB_A0(p_hwfn->p_dev)) {\n \t\thw_mode |= 1 << MODE_BB_A0;\n-\t\tbreak;\n-\tcase CHIP_BB_B0:\n+\t} else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {\n \t\thw_mode |= 1 << MODE_BB_B0;\n-\t\tbreak;\n-\tcase CHIP_K2:\n+\t} else if (ECORE_IS_AH(p_hwfn->p_dev)) {\n \t\thw_mode |= 1 << MODE_K2;\n-\t\tbreak;\n-\tdefault:\n-\t\tDP_NOTICE(p_hwfn, true, \"Can't initialize chip ID %d\\n\",\n-\t\t\t  ECORE_GET_TYPE(p_hwfn->p_dev));\n+\t} else {\n+\t\tDP_NOTICE(p_hwfn, true, \"Unknown chip type %#x\\n\",\n+\t\t\t  p_hwfn->p_dev->type);\n \t\treturn;\n \t}\n \n@@ -690,37 +679,6 @@ static void ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,\n \tif (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))\n \t\tecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);\n \n-\t/* initialize interrupt masks */\n-\tfor (i = 0;\n-\t     i <\n-\t     attn_blocks[BLOCK_MISCS].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].\n-\t     num_of_int_regs; i++)\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t attn_blocks[BLOCK_MISCS].\n-\t\t\t chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[i]->\n-\t\t\t mask_addr, 0);\n-\n-\tif (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t attn_blocks[BLOCK_CNIG].\n-\t\t\t chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->\n-\t\t\t mask_addr, 0);\n-\tecore_wr(p_hwfn, p_ptt,\n-\t\t attn_blocks[BLOCK_PGLCS].\n-\t\t chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->\n-\t\t mask_addr, 0);\n-\tecore_wr(p_hwfn, p_ptt,\n-\t\t attn_blocks[BLOCK_CPMU].\n-\t\t chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->\n-\t\t mask_addr, 0);\n-\t/* Currently A0 and B0 interrupt bits are the same in pglue_b;\n-\t * If this changes, need to set this according to chip type. <14/09/23>\n-\t */\n-\tecore_wr(p_hwfn, p_ptt,\n-\t\t attn_blocks[BLOCK_PGLUE_B].\n-\t\t chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->\n-\t\t mask_addr, 0x80000);\n-\n \t/* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */\n \t/* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */\n \tif (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))\n@@ -1227,25 +1185,6 @@ ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,\n \t *                           &ctrl);\n \t */\n \n-#ifndef ASIC_ONLY\n-\t/*@@TMP - On B0 build 1, need to mask the datapath_registers parity */\n-\tif (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev) &&\n-\t    (p_hwfn->p_dev->chip_metal == 1)) {\n-\t\tu32 reg_addr, tmp;\n-\n-\t\treg_addr =\n-\t\t    attn_blocks[BLOCK_PGLUE_B].\n-\t\t    chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].prty_regs[0]->\n-\t\t    mask_addr;\n-\t\tDP_NOTICE(p_hwfn, false,\n-\t\t\t  \"Masking datapath registers parity on\"\n-\t\t\t  \" B0 emulation [build 1]\\n\");\n-\t\ttmp = ecore_rd(p_hwfn, p_ptt, reg_addr);\n-\t\ttmp |= (1 << 0);\t/* Was PRTY_MASK_DATAPATH_REGISTERS */\n-\t\tecore_wr(p_hwfn, p_ptt, reg_addr, tmp);\n-\t}\n-#endif\n-\n \trc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);\n \tif (rc)\n \t\treturn rc;\ndiff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h\nindex e341b95..9cd55c4 100644\n--- a/drivers/net/qede/base/ecore_hsi_common.h\n+++ b/drivers/net/qede/base/ecore_hsi_common.h\n@@ -1319,172 +1319,6 @@ struct atten_status_block {\n \t__le32 reserved1;\n };\n \n-enum block_addr {\n-\tGRCBASE_GRC = 0x50000,\n-\tGRCBASE_MISCS = 0x9000,\n-\tGRCBASE_MISC = 0x8000,\n-\tGRCBASE_DBU = 0xa000,\n-\tGRCBASE_PGLUE_B = 0x2a8000,\n-\tGRCBASE_CNIG = 0x218000,\n-\tGRCBASE_CPMU = 0x30000,\n-\tGRCBASE_NCSI = 0x40000,\n-\tGRCBASE_OPTE = 0x53000,\n-\tGRCBASE_BMB = 0x540000,\n-\tGRCBASE_PCIE = 0x54000,\n-\tGRCBASE_MCP = 0xe00000,\n-\tGRCBASE_MCP2 = 0x52000,\n-\tGRCBASE_PSWHST = 0x2a0000,\n-\tGRCBASE_PSWHST2 = 0x29e000,\n-\tGRCBASE_PSWRD = 0x29c000,\n-\tGRCBASE_PSWRD2 = 0x29d000,\n-\tGRCBASE_PSWWR = 0x29a000,\n-\tGRCBASE_PSWWR2 = 0x29b000,\n-\tGRCBASE_PSWRQ = 0x280000,\n-\tGRCBASE_PSWRQ2 = 0x240000,\n-\tGRCBASE_PGLCS = 0x0,\n-\tGRCBASE_DMAE = 0xc000,\n-\tGRCBASE_PTU = 0x560000,\n-\tGRCBASE_TCM = 0x1180000,\n-\tGRCBASE_MCM = 0x1200000,\n-\tGRCBASE_UCM = 0x1280000,\n-\tGRCBASE_XCM = 0x1000000,\n-\tGRCBASE_YCM = 0x1080000,\n-\tGRCBASE_PCM = 0x1100000,\n-\tGRCBASE_QM = 0x2f0000,\n-\tGRCBASE_TM = 0x2c0000,\n-\tGRCBASE_DORQ = 0x100000,\n-\tGRCBASE_BRB = 0x340000,\n-\tGRCBASE_SRC = 0x238000,\n-\tGRCBASE_PRS = 0x1f0000,\n-\tGRCBASE_TSDM = 0xfb0000,\n-\tGRCBASE_MSDM = 0xfc0000,\n-\tGRCBASE_USDM = 0xfd0000,\n-\tGRCBASE_XSDM = 0xf80000,\n-\tGRCBASE_YSDM = 0xf90000,\n-\tGRCBASE_PSDM = 0xfa0000,\n-\tGRCBASE_TSEM = 0x1700000,\n-\tGRCBASE_MSEM = 0x1800000,\n-\tGRCBASE_USEM = 0x1900000,\n-\tGRCBASE_XSEM = 0x1400000,\n-\tGRCBASE_YSEM = 0x1500000,\n-\tGRCBASE_PSEM = 0x1600000,\n-\tGRCBASE_RSS = 0x238800,\n-\tGRCBASE_TMLD = 0x4d0000,\n-\tGRCBASE_MULD = 0x4e0000,\n-\tGRCBASE_YULD = 0x4c8000,\n-\tGRCBASE_XYLD = 0x4c0000,\n-\tGRCBASE_PRM = 0x230000,\n-\tGRCBASE_PBF_PB1 = 0xda0000,\n-\tGRCBASE_PBF_PB2 = 0xda4000,\n-\tGRCBASE_RPB = 0x23c000,\n-\tGRCBASE_BTB = 0xdb0000,\n-\tGRCBASE_PBF = 0xd80000,\n-\tGRCBASE_RDIF = 0x300000,\n-\tGRCBASE_TDIF = 0x310000,\n-\tGRCBASE_CDU = 0x580000,\n-\tGRCBASE_CCFC = 0x2e0000,\n-\tGRCBASE_TCFC = 0x2d0000,\n-\tGRCBASE_IGU = 0x180000,\n-\tGRCBASE_CAU = 0x1c0000,\n-\tGRCBASE_UMAC = 0x51000,\n-\tGRCBASE_XMAC = 0x210000,\n-\tGRCBASE_DBG = 0x10000,\n-\tGRCBASE_NIG = 0x500000,\n-\tGRCBASE_WOL = 0x600000,\n-\tGRCBASE_BMBN = 0x610000,\n-\tGRCBASE_IPC = 0x20000,\n-\tGRCBASE_NWM = 0x800000,\n-\tGRCBASE_NWS = 0x700000,\n-\tGRCBASE_MS = 0x6a0000,\n-\tGRCBASE_PHY_PCIE = 0x620000,\n-\tGRCBASE_MISC_AEU = 0x8000,\n-\tGRCBASE_BAR0_MAP = 0x1c00000,\n-\tMAX_BLOCK_ADDR\n-};\n-\n-enum block_id {\n-\tBLOCK_GRC,\n-\tBLOCK_MISCS,\n-\tBLOCK_MISC,\n-\tBLOCK_DBU,\n-\tBLOCK_PGLUE_B,\n-\tBLOCK_CNIG,\n-\tBLOCK_CPMU,\n-\tBLOCK_NCSI,\n-\tBLOCK_OPTE,\n-\tBLOCK_BMB,\n-\tBLOCK_PCIE,\n-\tBLOCK_MCP,\n-\tBLOCK_MCP2,\n-\tBLOCK_PSWHST,\n-\tBLOCK_PSWHST2,\n-\tBLOCK_PSWRD,\n-\tBLOCK_PSWRD2,\n-\tBLOCK_PSWWR,\n-\tBLOCK_PSWWR2,\n-\tBLOCK_PSWRQ,\n-\tBLOCK_PSWRQ2,\n-\tBLOCK_PGLCS,\n-\tBLOCK_DMAE,\n-\tBLOCK_PTU,\n-\tBLOCK_TCM,\n-\tBLOCK_MCM,\n-\tBLOCK_UCM,\n-\tBLOCK_XCM,\n-\tBLOCK_YCM,\n-\tBLOCK_PCM,\n-\tBLOCK_QM,\n-\tBLOCK_TM,\n-\tBLOCK_DORQ,\n-\tBLOCK_BRB,\n-\tBLOCK_SRC,\n-\tBLOCK_PRS,\n-\tBLOCK_TSDM,\n-\tBLOCK_MSDM,\n-\tBLOCK_USDM,\n-\tBLOCK_XSDM,\n-\tBLOCK_YSDM,\n-\tBLOCK_PSDM,\n-\tBLOCK_TSEM,\n-\tBLOCK_MSEM,\n-\tBLOCK_USEM,\n-\tBLOCK_XSEM,\n-\tBLOCK_YSEM,\n-\tBLOCK_PSEM,\n-\tBLOCK_RSS,\n-\tBLOCK_TMLD,\n-\tBLOCK_MULD,\n-\tBLOCK_YULD,\n-\tBLOCK_XYLD,\n-\tBLOCK_PRM,\n-\tBLOCK_PBF_PB1,\n-\tBLOCK_PBF_PB2,\n-\tBLOCK_RPB,\n-\tBLOCK_BTB,\n-\tBLOCK_PBF,\n-\tBLOCK_RDIF,\n-\tBLOCK_TDIF,\n-\tBLOCK_CDU,\n-\tBLOCK_CCFC,\n-\tBLOCK_TCFC,\n-\tBLOCK_IGU,\n-\tBLOCK_CAU,\n-\tBLOCK_UMAC,\n-\tBLOCK_XMAC,\n-\tBLOCK_DBG,\n-\tBLOCK_NIG,\n-\tBLOCK_WOL,\n-\tBLOCK_BMBN,\n-\tBLOCK_IPC,\n-\tBLOCK_NWM,\n-\tBLOCK_NWS,\n-\tBLOCK_MS,\n-\tBLOCK_PHY_PCIE,\n-\tBLOCK_MISC_AEU,\n-\tBLOCK_BAR0_MAP,\n-\tMAX_BLOCK_ID\n-};\n-\n /*\n  * Igu cleanup bit values to distinguish between clean or producer consumer\n  */\n@@ -1561,43 +1395,12 @@ struct dmae_cmd {\n \t__le16 xsum8 /* checksum8 result  */;\n };\n \n-struct fw_ver_num {\n-\tu8 major /* Firmware major version number */;\n-\tu8 minor /* Firmware minor version number */;\n-\tu8 rev /* Firmware revision version number */;\n-\tu8 eng /* Firmware engineering version number (for bootleg versions) */\n-\t  ;\n-};\n-\n-struct fw_ver_info {\n-\t__le16 tools_ver /* Tools version number */;\n-\tu8 image_id /* FW image ID (e.g. main, l2b, kuku) */;\n-\tu8 reserved1;\n-\tstruct fw_ver_num num /* FW version number */;\n-\t__le32 timestamp /* FW Timestamp in unix time  (sec. since 1970) */;\n-\t__le32 reserved2;\n-};\n-\n struct storm_ram_section {\n \t__le16 offset\n \t    /* The offset of the section in the RAM (in 64 bit units) */;\n \t__le16 size /* The size of the section (in 64 bit units) */;\n };\n \n-struct fw_info {\n-\tstruct fw_ver_info ver /* FW version information */;\n-\tstruct storm_ram_section fw_asserts_section\n-\t    /* The FW Asserts offset/size in Storm RAM */;\n-\t__le32 reserved;\n-};\n-\n-struct fw_info_location {\n-\t__le32 grc_addr /* GRC address where the fw_info struct is located. */;\n-\t__le32 size\n-\t    /* Size of the fw_info structure (thats located at the grc_addr). */\n-\t  ;\n-};\n-\n /*\n  * IGU cleanup command\n  */\n@@ -1672,35 +1475,6 @@ struct igu_msix_vector {\n #define IGU_MSIX_VECTOR_RESERVED1_SHIFT    24\n };\n \n-enum init_modes {\n-\tMODE_BB_A0,\n-\tMODE_BB_B0,\n-\tMODE_K2,\n-\tMODE_ASIC,\n-\tMODE_EMUL_REDUCED,\n-\tMODE_EMUL_FULL,\n-\tMODE_FPGA,\n-\tMODE_CHIPSIM,\n-\tMODE_SF,\n-\tMODE_MF_SD,\n-\tMODE_MF_SI,\n-\tMODE_PORTS_PER_ENG_1,\n-\tMODE_PORTS_PER_ENG_2,\n-\tMODE_PORTS_PER_ENG_4,\n-\tMODE_100G,\n-\tMODE_EAGLE_ENG1_WORKAROUND,\n-\tMAX_INIT_MODES\n-};\n-\n-enum init_phases {\n-\tPHASE_ENGINE,\n-\tPHASE_PORT,\n-\tPHASE_PF,\n-\tPHASE_VF,\n-\tPHASE_QM_PF,\n-\tMAX_INIT_PHASES\n-};\n-\n struct mstorm_core_conn_ag_ctx {\n \tu8 byte0 /* cdu_validation */;\n \tu8 byte1 /* state */;\ndiff --git a/drivers/net/qede/base/ecore_hsi_debug_tools.h b/drivers/net/qede/base/ecore_hsi_debug_tools.h\nnew file mode 100644\nindex 0000000..e82b0d4\n--- /dev/null\n+++ b/drivers/net/qede/base/ecore_hsi_debug_tools.h\n@@ -0,0 +1,1025 @@\n+/*\n+ * Copyright (c) 2016 QLogic Corporation.\n+ * All rights reserved.\n+ * www.qlogic.com\n+ *\n+ * See LICENSE.qede_pmd for copyright and licensing details.\n+ */\n+\n+#ifndef __ECORE_HSI_DEBUG_TOOLS__\n+#define __ECORE_HSI_DEBUG_TOOLS__\n+/****************************************/\n+/* Debug Tools HSI constants and macros */\n+/****************************************/\n+\n+\n+enum block_addr {\n+\tGRCBASE_GRC = 0x50000,\n+\tGRCBASE_MISCS = 0x9000,\n+\tGRCBASE_MISC = 0x8000,\n+\tGRCBASE_DBU = 0xa000,\n+\tGRCBASE_PGLUE_B = 0x2a8000,\n+\tGRCBASE_CNIG = 0x218000,\n+\tGRCBASE_CPMU = 0x30000,\n+\tGRCBASE_NCSI = 0x40000,\n+\tGRCBASE_OPTE = 0x53000,\n+\tGRCBASE_BMB = 0x540000,\n+\tGRCBASE_PCIE = 0x54000,\n+\tGRCBASE_MCP = 0xe00000,\n+\tGRCBASE_MCP2 = 0x52000,\n+\tGRCBASE_PSWHST = 0x2a0000,\n+\tGRCBASE_PSWHST2 = 0x29e000,\n+\tGRCBASE_PSWRD = 0x29c000,\n+\tGRCBASE_PSWRD2 = 0x29d000,\n+\tGRCBASE_PSWWR = 0x29a000,\n+\tGRCBASE_PSWWR2 = 0x29b000,\n+\tGRCBASE_PSWRQ = 0x280000,\n+\tGRCBASE_PSWRQ2 = 0x240000,\n+\tGRCBASE_PGLCS = 0x0,\n+\tGRCBASE_DMAE = 0xc000,\n+\tGRCBASE_PTU = 0x560000,\n+\tGRCBASE_TCM = 0x1180000,\n+\tGRCBASE_MCM = 0x1200000,\n+\tGRCBASE_UCM = 0x1280000,\n+\tGRCBASE_XCM = 0x1000000,\n+\tGRCBASE_YCM = 0x1080000,\n+\tGRCBASE_PCM = 0x1100000,\n+\tGRCBASE_QM = 0x2f0000,\n+\tGRCBASE_TM = 0x2c0000,\n+\tGRCBASE_DORQ = 0x100000,\n+\tGRCBASE_BRB = 0x340000,\n+\tGRCBASE_SRC = 0x238000,\n+\tGRCBASE_PRS = 0x1f0000,\n+\tGRCBASE_TSDM = 0xfb0000,\n+\tGRCBASE_MSDM = 0xfc0000,\n+\tGRCBASE_USDM = 0xfd0000,\n+\tGRCBASE_XSDM = 0xf80000,\n+\tGRCBASE_YSDM = 0xf90000,\n+\tGRCBASE_PSDM = 0xfa0000,\n+\tGRCBASE_TSEM = 0x1700000,\n+\tGRCBASE_MSEM = 0x1800000,\n+\tGRCBASE_USEM = 0x1900000,\n+\tGRCBASE_XSEM = 0x1400000,\n+\tGRCBASE_YSEM = 0x1500000,\n+\tGRCBASE_PSEM = 0x1600000,\n+\tGRCBASE_RSS = 0x238800,\n+\tGRCBASE_TMLD = 0x4d0000,\n+\tGRCBASE_MULD = 0x4e0000,\n+\tGRCBASE_YULD = 0x4c8000,\n+\tGRCBASE_XYLD = 0x4c0000,\n+\tGRCBASE_PRM = 0x230000,\n+\tGRCBASE_PBF_PB1 = 0xda0000,\n+\tGRCBASE_PBF_PB2 = 0xda4000,\n+\tGRCBASE_RPB = 0x23c000,\n+\tGRCBASE_BTB = 0xdb0000,\n+\tGRCBASE_PBF = 0xd80000,\n+\tGRCBASE_RDIF = 0x300000,\n+\tGRCBASE_TDIF = 0x310000,\n+\tGRCBASE_CDU = 0x580000,\n+\tGRCBASE_CCFC = 0x2e0000,\n+\tGRCBASE_TCFC = 0x2d0000,\n+\tGRCBASE_IGU = 0x180000,\n+\tGRCBASE_CAU = 0x1c0000,\n+\tGRCBASE_UMAC = 0x51000,\n+\tGRCBASE_XMAC = 0x210000,\n+\tGRCBASE_DBG = 0x10000,\n+\tGRCBASE_NIG = 0x500000,\n+\tGRCBASE_WOL = 0x600000,\n+\tGRCBASE_BMBN = 0x610000,\n+\tGRCBASE_IPC = 0x20000,\n+\tGRCBASE_NWM = 0x800000,\n+\tGRCBASE_NWS = 0x700000,\n+\tGRCBASE_MS = 0x6a0000,\n+\tGRCBASE_PHY_PCIE = 0x620000,\n+\tGRCBASE_LED = 0x6b8000,\n+\tGRCBASE_MISC_AEU = 0x8000,\n+\tGRCBASE_BAR0_MAP = 0x1c00000,\n+\tMAX_BLOCK_ADDR\n+};\n+\n+\n+enum block_id {\n+\tBLOCK_GRC,\n+\tBLOCK_MISCS,\n+\tBLOCK_MISC,\n+\tBLOCK_DBU,\n+\tBLOCK_PGLUE_B,\n+\tBLOCK_CNIG,\n+\tBLOCK_CPMU,\n+\tBLOCK_NCSI,\n+\tBLOCK_OPTE,\n+\tBLOCK_BMB,\n+\tBLOCK_PCIE,\n+\tBLOCK_MCP,\n+\tBLOCK_MCP2,\n+\tBLOCK_PSWHST,\n+\tBLOCK_PSWHST2,\n+\tBLOCK_PSWRD,\n+\tBLOCK_PSWRD2,\n+\tBLOCK_PSWWR,\n+\tBLOCK_PSWWR2,\n+\tBLOCK_PSWRQ,\n+\tBLOCK_PSWRQ2,\n+\tBLOCK_PGLCS,\n+\tBLOCK_DMAE,\n+\tBLOCK_PTU,\n+\tBLOCK_TCM,\n+\tBLOCK_MCM,\n+\tBLOCK_UCM,\n+\tBLOCK_XCM,\n+\tBLOCK_YCM,\n+\tBLOCK_PCM,\n+\tBLOCK_QM,\n+\tBLOCK_TM,\n+\tBLOCK_DORQ,\n+\tBLOCK_BRB,\n+\tBLOCK_SRC,\n+\tBLOCK_PRS,\n+\tBLOCK_TSDM,\n+\tBLOCK_MSDM,\n+\tBLOCK_USDM,\n+\tBLOCK_XSDM,\n+\tBLOCK_YSDM,\n+\tBLOCK_PSDM,\n+\tBLOCK_TSEM,\n+\tBLOCK_MSEM,\n+\tBLOCK_USEM,\n+\tBLOCK_XSEM,\n+\tBLOCK_YSEM,\n+\tBLOCK_PSEM,\n+\tBLOCK_RSS,\n+\tBLOCK_TMLD,\n+\tBLOCK_MULD,\n+\tBLOCK_YULD,\n+\tBLOCK_XYLD,\n+\tBLOCK_PRM,\n+\tBLOCK_PBF_PB1,\n+\tBLOCK_PBF_PB2,\n+\tBLOCK_RPB,\n+\tBLOCK_BTB,\n+\tBLOCK_PBF,\n+\tBLOCK_RDIF,\n+\tBLOCK_TDIF,\n+\tBLOCK_CDU,\n+\tBLOCK_CCFC,\n+\tBLOCK_TCFC,\n+\tBLOCK_IGU,\n+\tBLOCK_CAU,\n+\tBLOCK_UMAC,\n+\tBLOCK_XMAC,\n+\tBLOCK_DBG,\n+\tBLOCK_NIG,\n+\tBLOCK_WOL,\n+\tBLOCK_BMBN,\n+\tBLOCK_IPC,\n+\tBLOCK_NWM,\n+\tBLOCK_NWS,\n+\tBLOCK_MS,\n+\tBLOCK_PHY_PCIE,\n+\tBLOCK_LED,\n+\tBLOCK_MISC_AEU,\n+\tBLOCK_BAR0_MAP,\n+\tMAX_BLOCK_ID\n+};\n+\n+\n+/*\n+ * binary debug buffer types\n+ */\n+enum bin_dbg_buffer_type {\n+\tBIN_BUF_DBG_MODE_TREE /* init modes tree */,\n+\tBIN_BUF_DBG_DUMP_REG /* GRC Dump registers */,\n+\tBIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */,\n+\tBIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */,\n+\tBIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */,\n+\tBIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */,\n+\tBIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */,\n+\tBIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */,\n+\tBIN_BUF_DBG_ATTN_REGS /* Attention registers */,\n+\tBIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */,\n+\tBIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */,\n+\tBIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */,\n+\tMAX_BIN_DBG_BUFFER_TYPE\n+};\n+\n+\n+/*\n+ * Attention bit mapping\n+ */\n+struct dbg_attn_bit_mapping {\n+\t__le16 data;\n+/* The index of an attention in the blocks attentions list\n+ * (if is_unused_idx_cnt=0), or a number of consecutive unused attention bits\n+ * (if is_unused_idx_cnt=1)\n+ */\n+#define DBG_ATTN_BIT_MAPPING_VAL_MASK                0x7FFF\n+#define DBG_ATTN_BIT_MAPPING_VAL_SHIFT               0\n+/* if set, the val field indicates the number of consecutive unused attention\n+ * bits\n+ */\n+#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK  0x1\n+#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15\n+};\n+\n+\n+/*\n+ * Attention block per-type data\n+ */\n+struct dbg_attn_block_type_data {\n+/* Offset of this block attention names in the debug attention name offsets\n+ * array\n+ */\n+\t__le16 names_offset;\n+\t__le16 reserved1;\n+\tu8 num_regs /* Number of attention registers in this block */;\n+\tu8 reserved2;\n+/* Offset of this blocks attention registers in the attention registers array\n+ * (in dbg_attn_reg units)\n+ */\n+\t__le16 regs_offset;\n+};\n+\n+/*\n+ * Block attentions\n+ */\n+struct dbg_attn_block {\n+/* attention block per-type data. Count must match the number of elements in\n+ * dbg_attn_type.\n+ */\n+\tstruct dbg_attn_block_type_data per_type_data[2];\n+};\n+\n+\n+/*\n+ * Attention register result\n+ */\n+struct dbg_attn_reg_result {\n+\t__le32 data;\n+/* STS attention register GRC address (in dwords) */\n+#define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK   0xFFFFFF\n+#define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT  0\n+/* Number of attention indexes in this register */\n+#define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_MASK  0xFF\n+#define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_SHIFT 24\n+/* Offset of this registers block attention indexes (values in the range\n+ * 0..number of block attentions)\n+ */\n+\t__le16 attn_idx_offset;\n+\t__le16 reserved;\n+\t__le32 sts_val /* Value read from the STS attention register */;\n+\t__le32 mask_val /* Value read from the MASK attention register */;\n+};\n+\n+/*\n+ * Attention block result\n+ */\n+struct dbg_attn_block_result {\n+\tu8 block_id /* Registers block ID */;\n+\tu8 data;\n+/* Value from dbg_attn_type enum */\n+#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK  0x3\n+#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0\n+/* Number of registers in the blok in which at least one attention bit is set */\n+#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK   0x3F\n+#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT  2\n+/* Offset of this registers block attention names in the attention name offsets\n+ * array\n+ */\n+\t__le16 names_offset;\n+/* result data for each register in the block in which at least one attention\n+ * bit is set\n+ */\n+\tstruct dbg_attn_reg_result reg_results[15];\n+};\n+\n+\n+\n+/*\n+ * mode header\n+ */\n+struct dbg_mode_hdr {\n+\t__le16 data;\n+/* indicates if a mode expression should be evaluated (0/1) */\n+#define DBG_MODE_HDR_EVAL_MODE_MASK         0x1\n+#define DBG_MODE_HDR_EVAL_MODE_SHIFT        0\n+/* offset (in bytes) in modes expression buffer. valid only if eval_mode is\n+ * set.\n+ */\n+#define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK  0x7FFF\n+#define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1\n+};\n+\n+/*\n+ * Attention register\n+ */\n+struct dbg_attn_reg {\n+\tstruct dbg_mode_hdr mode /* Mode header */;\n+/* Offset of this registers block attention indexes (values in the range\n+ * 0..number of block attentions)\n+ */\n+\t__le16 attn_idx_offset;\n+\t__le32 data;\n+/* STS attention register GRC address (in dwords) */\n+#define DBG_ATTN_REG_STS_ADDRESS_MASK   0xFFFFFF\n+#define DBG_ATTN_REG_STS_ADDRESS_SHIFT  0\n+/* Number of attention indexes in this register */\n+#define DBG_ATTN_REG_NUM_ATTN_IDX_MASK  0xFF\n+#define DBG_ATTN_REG_NUM_ATTN_IDX_SHIFT 24\n+/* STS_CLR attention register GRC address (in dwords) */\n+\t__le32 sts_clr_address;\n+/* MASK attention register GRC address (in dwords) */\n+\t__le32 mask_address;\n+};\n+\n+\n+\n+/*\n+ * attention types\n+ */\n+enum dbg_attn_type {\n+\tATTN_TYPE_INTERRUPT,\n+\tATTN_TYPE_PARITY,\n+\tMAX_DBG_ATTN_TYPE\n+};\n+\n+\n+/*\n+ * condition header for registers dump\n+ */\n+struct dbg_dump_cond_hdr {\n+\tstruct dbg_mode_hdr mode /* Mode header */;\n+\tu8 block_id /* block ID */;\n+\tu8 data_size /* size in dwords of the data following this header */;\n+};\n+\n+\n+/*\n+ * memory data for registers dump\n+ */\n+struct dbg_dump_mem {\n+\t__le32 dword0;\n+/* register address (in dwords) */\n+#define DBG_DUMP_MEM_ADDRESS_MASK       0xFFFFFF\n+#define DBG_DUMP_MEM_ADDRESS_SHIFT      0\n+#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK  0xFF /* memory group ID */\n+#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24\n+\t__le32 dword1;\n+/* register size (in dwords) */\n+#define DBG_DUMP_MEM_LENGTH_MASK        0xFFFFFF\n+#define DBG_DUMP_MEM_LENGTH_SHIFT       0\n+#define DBG_DUMP_MEM_RESERVED_MASK      0xFF\n+#define DBG_DUMP_MEM_RESERVED_SHIFT     24\n+};\n+\n+\n+/*\n+ * register data for registers dump\n+ */\n+struct dbg_dump_reg {\n+\t__le32 data;\n+/* register address (in dwords) */\n+#define DBG_DUMP_REG_ADDRESS_MASK  0xFFFFFF\n+#define DBG_DUMP_REG_ADDRESS_SHIFT 0\n+#define DBG_DUMP_REG_LENGTH_MASK   0xFF /* register size (in dwords) */\n+#define DBG_DUMP_REG_LENGTH_SHIFT  24\n+};\n+\n+\n+/*\n+ * split header for registers dump\n+ */\n+struct dbg_dump_split_hdr {\n+\t__le32 hdr;\n+/* size in dwords of the data following this header */\n+#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK      0xFFFFFF\n+#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT     0\n+#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK  0xFF /* split type ID */\n+#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24\n+};\n+\n+\n+/*\n+ * condition header for idle check\n+ */\n+struct dbg_idle_chk_cond_hdr {\n+\tstruct dbg_mode_hdr mode /* Mode header */;\n+/* size in dwords of the data following this header */\n+\t__le16 data_size;\n+};\n+\n+\n+/*\n+ * Idle Check condition register\n+ */\n+struct dbg_idle_chk_cond_reg {\n+\t__le32 data;\n+/* Register GRC address (in dwords) */\n+#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK   0xFFFFFF\n+#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT  0\n+/* value from block_id enum */\n+#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK  0xFF\n+#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24\n+\t__le16 num_entries /* number of registers entries to check */;\n+\tu8 entry_size /* size of registers entry (in dwords) */;\n+\tu8 start_entry /* index of the first entry to check */;\n+};\n+\n+\n+/*\n+ * Idle Check info register\n+ */\n+struct dbg_idle_chk_info_reg {\n+\t__le32 data;\n+/* Register GRC address (in dwords) */\n+#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK   0xFFFFFF\n+#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT  0\n+/* value from block_id enum */\n+#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK  0xFF\n+#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24\n+\t__le16 size /* register size in dwords */;\n+\tstruct dbg_mode_hdr mode /* Mode header */;\n+};\n+\n+\n+/*\n+ * Idle Check register\n+ */\n+union dbg_idle_chk_reg {\n+\tstruct dbg_idle_chk_cond_reg cond_reg /* condition register */;\n+\tstruct dbg_idle_chk_info_reg info_reg /* info register */;\n+};\n+\n+\n+/*\n+ * Idle Check result header\n+ */\n+struct dbg_idle_chk_result_hdr {\n+\t__le16 rule_id /* Failing rule index */;\n+\t__le16 mem_entry_id /* Failing memory entry index */;\n+\tu8 num_dumped_cond_regs /* number of dumped condition registers */;\n+\tu8 num_dumped_info_regs /* number of dumped condition registers */;\n+\tu8 severity /* from dbg_idle_chk_severity_types enum */;\n+\tu8 reserved;\n+};\n+\n+\n+/*\n+ * Idle Check result register header\n+ */\n+struct dbg_idle_chk_result_reg_hdr {\n+\tu8 data;\n+/* indicates if this register is a memory */\n+#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK  0x1\n+#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0\n+/* register index within the failing rule */\n+#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK  0x7F\n+#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1\n+\tu8 start_entry /* index of the first checked entry */;\n+\t__le16 size /* register size in dwords */;\n+};\n+\n+\n+/*\n+ * Idle Check rule\n+ */\n+struct dbg_idle_chk_rule {\n+\t__le16 rule_id /* Idle Check rule ID */;\n+\tu8 severity /* value from dbg_idle_chk_severity_types enum */;\n+\tu8 cond_id /* Condition ID */;\n+\tu8 num_cond_regs /* number of condition registers */;\n+\tu8 num_info_regs /* number of info registers */;\n+\tu8 num_imms /* number of immediates in the condition */;\n+\tu8 reserved1;\n+/* offset of this rules registers in the idle check register array\n+ * (in dbg_idle_chk_reg units)\n+ */\n+\t__le16 reg_offset;\n+/* offset of this rules immediate values in the immediate values array\n+ * (in dwords)\n+ */\n+\t__le16 imm_offset;\n+};\n+\n+\n+/*\n+ * Idle Check rule parsing data\n+ */\n+struct dbg_idle_chk_rule_parsing_data {\n+\t__le32 data;\n+/* indicates if this register has a FW message */\n+#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK  0x1\n+#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0\n+/* Offset of this rules strings in the debug strings array (in bytes) */\n+#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK  0x7FFFFFFF\n+#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1\n+};\n+\n+\n+/*\n+ * idle check severity types\n+ */\n+enum dbg_idle_chk_severity_types {\n+/* idle check failure should cause an error */\n+\tIDLE_CHK_SEVERITY_ERROR,\n+/* idle check failure should cause an error only if theres no traffic */\n+\tIDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,\n+/* idle check failure should cause a warning */\n+\tIDLE_CHK_SEVERITY_WARNING,\n+\tMAX_DBG_IDLE_CHK_SEVERITY_TYPES\n+};\n+\n+\n+\n+/*\n+ * Debug Bus block data\n+ */\n+struct dbg_bus_block_data {\n+/* Indicates if the block is enabled for recording (0/1) */\n+\tu8 enabled;\n+\tu8 hw_id /* HW ID associated with the block */;\n+\tu8 line_num /* Debug line number to select */;\n+\tu8 right_shift /* Number of units to  right the debug data (0-3) */;\n+\tu8 cycle_en /* 4-bit value: bit i set -> unit i is enabled. */;\n+/* 4-bit value: bit i set -> unit i is forced valid. */\n+\tu8 force_valid;\n+/* 4-bit value: bit i set -> unit i frame bit is forced. */\n+\tu8 force_frame;\n+\tu8 reserved;\n+};\n+\n+\n+/*\n+ * Debug Bus Clients\n+ */\n+enum dbg_bus_clients {\n+\tDBG_BUS_CLIENT_RBCN,\n+\tDBG_BUS_CLIENT_RBCP,\n+\tDBG_BUS_CLIENT_RBCR,\n+\tDBG_BUS_CLIENT_RBCT,\n+\tDBG_BUS_CLIENT_RBCU,\n+\tDBG_BUS_CLIENT_RBCF,\n+\tDBG_BUS_CLIENT_RBCX,\n+\tDBG_BUS_CLIENT_RBCS,\n+\tDBG_BUS_CLIENT_RBCH,\n+\tDBG_BUS_CLIENT_RBCZ,\n+\tDBG_BUS_CLIENT_OTHER_ENGINE,\n+\tDBG_BUS_CLIENT_TIMESTAMP,\n+\tDBG_BUS_CLIENT_CPU,\n+\tDBG_BUS_CLIENT_RBCY,\n+\tDBG_BUS_CLIENT_RBCQ,\n+\tDBG_BUS_CLIENT_RBCM,\n+\tDBG_BUS_CLIENT_RBCB,\n+\tDBG_BUS_CLIENT_RBCW,\n+\tDBG_BUS_CLIENT_RBCV,\n+\tMAX_DBG_BUS_CLIENTS\n+};\n+\n+\n+/*\n+ * Debug Bus constraint operation types\n+ */\n+enum dbg_bus_constraint_ops {\n+\tDBG_BUS_CONSTRAINT_OP_EQ /* equal */,\n+\tDBG_BUS_CONSTRAINT_OP_NE /* not equal */,\n+\tDBG_BUS_CONSTRAINT_OP_LT /* less than */,\n+\tDBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */,\n+\tDBG_BUS_CONSTRAINT_OP_LE /* less than or equal */,\n+\tDBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */,\n+\tDBG_BUS_CONSTRAINT_OP_GT /* greater than */,\n+\tDBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */,\n+\tDBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */,\n+\tDBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */,\n+\tMAX_DBG_BUS_CONSTRAINT_OPS\n+};\n+\n+\n+/*\n+ * Debug Bus memory address\n+ */\n+struct dbg_bus_mem_addr {\n+\t__le32 lo;\n+\t__le32 hi;\n+};\n+\n+/*\n+ * Debug Bus PCI buffer data\n+ */\n+struct dbg_bus_pci_buf_data {\n+\tstruct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */;\n+\tstruct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */;\n+\t__le32 size /* PCI buffer size in bytes */;\n+};\n+\n+/*\n+ * Debug Bus Storm EID range filter params\n+ */\n+struct dbg_bus_storm_eid_range_params {\n+\tu8 min /* Minimal event ID to filter on */;\n+\tu8 max /* Maximal event ID to filter on */;\n+};\n+\n+/*\n+ * Debug Bus Storm EID mask filter params\n+ */\n+struct dbg_bus_storm_eid_mask_params {\n+\tu8 val /* Event ID value */;\n+\tu8 mask /* Event ID mask. 1s in the mask = dont care bits. */;\n+};\n+\n+/*\n+ * Debug Bus Storm EID filter params\n+ */\n+union dbg_bus_storm_eid_params {\n+/* EID range filter params */\n+\tstruct dbg_bus_storm_eid_range_params range;\n+/* EID mask filter params */\n+\tstruct dbg_bus_storm_eid_mask_params mask;\n+};\n+\n+/*\n+ * Debug Bus Storm data\n+ */\n+struct dbg_bus_storm_data {\n+/* Indicates if the Storm is enabled for fast debug recording (0/1) */\n+\tu8 fast_enabled;\n+/* Fast debug Storm mode, valid only if fast_enabled is set */\n+\tu8 fast_mode;\n+/* Indicates if the Storm is enabled for slow debug recording (0/1) */\n+\tu8 slow_enabled;\n+/* Slow debug Storm mode, valid only if slow_enabled is set */\n+\tu8 slow_mode;\n+\tu8 hw_id /* HW ID associated with the Storm */;\n+\tu8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */;\n+/* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is\n+ * set,\n+ */\n+\tu8 eid_range_not_mask;\n+\tu8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */;\n+/* EID filter params to filter on. Valid only if eid_filter_en is set. */\n+\tunion dbg_bus_storm_eid_params eid_filter_params;\n+\t__le16 reserved;\n+/* CID to filter on. Valid only if cid_filter_en is set. */\n+\t__le32 cid;\n+};\n+\n+/*\n+ * Debug Bus data\n+ */\n+struct dbg_bus_data {\n+\t__le32 app_version /* The tools version number of the application */;\n+\tu8 state /* The current debug bus state */;\n+\tu8 hw_dwords /* HW dwords per cycle */;\n+\tu8 next_hw_id /* Next HW ID to be associated with an input */;\n+\tu8 num_enabled_blocks /* Number of blocks enabled for recording */;\n+\tu8 num_enabled_storms /* Number of Storms enabled for recording */;\n+\tu8 target /* Output target */;\n+\tu8 next_trigger_state /* ID of next trigger state to be added */;\n+/* ID of next filter/trigger constraint to be added */\n+\tu8 next_constraint_id;\n+\tu8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */;\n+\tu8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */;\n+/* Indicates if timestamp recording is enabled (0/1) */\n+\tu8 timestamp_input_en;\n+\tu8 filter_en /* Indicates if the recording filter is enabled (0/1) */;\n+/* Indicates if the recording trigger is enabled (0/1) */\n+\tu8 trigger_en;\n+/* If true, the next added constraint belong to the filter. Otherwise,\n+ * it belongs to the last added trigger state. Valid only if either filter or\n+ * triggers are enabled.\n+ */\n+\tu8 adding_filter;\n+/* Indicates if the recording filter should be applied before the trigger.\n+ * Valid only if both filter and trigger are enabled (0/1)\n+ */\n+\tu8 filter_pre_trigger;\n+/* Indicates if the recording filter should be applied after the trigger.\n+ * Valid only if both filter and trigger are enabled (0/1)\n+ */\n+\tu8 filter_post_trigger;\n+/* If true, all inputs are associated with HW ID 0. Otherwise, each input is\n+ * assigned a different HW ID (0/1)\n+ */\n+\tu8 unify_inputs;\n+/* Indicates if the other engine sends it NW recording to this engine (0/1) */\n+\tu8 rcv_from_other_engine;\n+/* Debug Bus PCI buffer data. Valid only when the target is\n+ * DBG_BUS_TARGET_ID_PCI.\n+ */\n+\tstruct dbg_bus_pci_buf_data pci_buf;\n+\t__le16 reserved;\n+/* Debug Bus data for each block */\n+\tstruct dbg_bus_block_data blocks[80];\n+/* Debug Bus data for each block */\n+\tstruct dbg_bus_storm_data storms[6];\n+};\n+\n+\n+/*\n+ * Debug bus filter types\n+ */\n+enum dbg_bus_filter_types {\n+\tDBG_BUS_FILTER_TYPE_OFF /* filter always off */,\n+\tDBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */,\n+\tDBG_BUS_FILTER_TYPE_POST /* filter after trigger only */,\n+\tDBG_BUS_FILTER_TYPE_ON /* filter always on */,\n+\tMAX_DBG_BUS_FILTER_TYPES\n+};\n+\n+\n+/*\n+ * Debug bus frame modes\n+ */\n+enum dbg_bus_frame_modes {\n+\tDBG_BUS_FRAME_MODE_0HW_4ST = 0 /* 0 HW dwords, 4 Storm dwords */,\n+\tDBG_BUS_FRAME_MODE_4HW_0ST = 3 /* 4 HW dwords, 0 Storm dwords */,\n+\tDBG_BUS_FRAME_MODE_8HW_0ST = 4 /* 8 HW dwords, 0 Storm dwords */,\n+\tMAX_DBG_BUS_FRAME_MODES\n+};\n+\n+\n+/*\n+ * Debug bus input types\n+ */\n+enum dbg_bus_input_types {\n+\tDBG_BUS_INPUT_TYPE_STORM,\n+\tDBG_BUS_INPUT_TYPE_BLOCK,\n+\tMAX_DBG_BUS_INPUT_TYPES\n+};\n+\n+\n+\n+/*\n+ * Debug bus other engine mode\n+ */\n+enum dbg_bus_other_engine_modes {\n+\tDBG_BUS_OTHER_ENGINE_MODE_NONE,\n+\tDBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,\n+\tDBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,\n+\tDBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,\n+\tDBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,\n+\tMAX_DBG_BUS_OTHER_ENGINE_MODES\n+};\n+\n+\n+\n+/*\n+ * Debug bus post-trigger recording types\n+ */\n+enum dbg_bus_post_trigger_types {\n+\tDBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */,\n+\tDBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */,\n+\tMAX_DBG_BUS_POST_TRIGGER_TYPES\n+};\n+\n+\n+/*\n+ * Debug bus pre-trigger recording types\n+ */\n+enum dbg_bus_pre_trigger_types {\n+\tDBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */,\n+/* start recording some chunks before trigger */\n+\tDBG_BUS_PRE_TRIGGER_NUM_CHUNKS,\n+\tDBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */,\n+\tMAX_DBG_BUS_PRE_TRIGGER_TYPES\n+};\n+\n+\n+/*\n+ * Debug bus SEMI frame modes\n+ */\n+enum dbg_bus_semi_frame_modes {\n+/* 0 slow dwords, 4 fast dwords */\n+\tDBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,\n+/* 4 slow dwords, 0 fast dwords */\n+\tDBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,\n+\tMAX_DBG_BUS_SEMI_FRAME_MODES\n+};\n+\n+\n+/*\n+ * Debug bus states\n+ */\n+enum dbg_bus_states {\n+\tDBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */,\n+/* debug bus is ready for configuration and recording */\n+\tDBG_BUS_STATE_READY,\n+\tDBG_BUS_STATE_RECORDING /* debug bus is currently recording */,\n+\tDBG_BUS_STATE_STOPPED /* debug bus recording has stopped */,\n+\tMAX_DBG_BUS_STATES\n+};\n+\n+\n+\n+\n+\n+\n+/*\n+ * Debug Bus Storm modes\n+ */\n+enum dbg_bus_storm_modes {\n+\tDBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */,\n+\tDBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */,\n+\tDBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */,\n+\tDBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */,\n+\tDBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */,\n+\tDBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */,\n+\tDBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */,\n+\tDBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */,\n+\tDBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */,\n+\tMAX_DBG_BUS_STORM_MODES\n+};\n+\n+\n+/*\n+ * Debug bus target IDs\n+ */\n+enum dbg_bus_targets {\n+/* records debug bus to DBG block internal buffer */\n+\tDBG_BUS_TARGET_ID_INT_BUF,\n+\tDBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */,\n+\tDBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */,\n+\tMAX_DBG_BUS_TARGETS\n+};\n+\n+\n+/*\n+ * GRC Dump data\n+ */\n+struct dbg_grc_data {\n+/* Value of each GRC parameter. Array size must match enum dbg_grc_params. */\n+\t__le32 param_val[40];\n+/* Indicates for each GRC parameter if it was set by the user (0/1).\n+ * Array size must match the enum dbg_grc_params.\n+ */\n+\tu8 param_set_by_user[40];\n+};\n+\n+\n+/*\n+ * Debug GRC params\n+ */\n+enum dbg_grc_params {\n+\tDBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */,\n+\tDBG_GRC_PARAM_RESERVED /* reserved */,\n+\tDBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */,\n+\tDBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */,\n+\tDBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */,\n+\tDBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */,\n+/* preset: exclude all memories from dump (1 only) */\n+\tDBG_GRC_PARAM_EXCLUDE_ALL,\n+/* preset: include memories for crash dump (1 only) */\n+\tDBG_GRC_PARAM_CRASH,\n+/* perform dump only if MFW is responding (0/1) */\n+\tDBG_GRC_PARAM_PARITY_SAFE,\n+\tDBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */,\n+\tDBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */,\n+\tMAX_DBG_GRC_PARAMS\n+};\n+\n+\n+/*\n+ * Debug reset registers\n+ */\n+enum dbg_reset_regs {\n+\tDBG_RESET_REG_MISCS_PL_UA,\n+\tDBG_RESET_REG_MISCS_PL_HV,\n+\tDBG_RESET_REG_MISCS_PL_HV_2,\n+\tDBG_RESET_REG_MISC_PL_UA,\n+\tDBG_RESET_REG_MISC_PL_HV,\n+\tDBG_RESET_REG_MISC_PL_PDA_VMAIN_1,\n+\tDBG_RESET_REG_MISC_PL_PDA_VMAIN_2,\n+\tDBG_RESET_REG_MISC_PL_PDA_VAUX,\n+\tMAX_DBG_RESET_REGS\n+};\n+\n+\n+/*\n+ * Debug status codes\n+ */\n+enum dbg_status {\n+\tDBG_STATUS_OK,\n+\tDBG_STATUS_APP_VERSION_NOT_SET,\n+\tDBG_STATUS_UNSUPPORTED_APP_VERSION,\n+\tDBG_STATUS_DBG_BLOCK_NOT_RESET,\n+\tDBG_STATUS_INVALID_ARGS,\n+\tDBG_STATUS_OUTPUT_ALREADY_SET,\n+\tDBG_STATUS_INVALID_PCI_BUF_SIZE,\n+\tDBG_STATUS_PCI_BUF_ALLOC_FAILED,\n+\tDBG_STATUS_PCI_BUF_NOT_ALLOCATED,\n+\tDBG_STATUS_TOO_MANY_INPUTS,\n+\tDBG_STATUS_INPUT_OVERLAP,\n+\tDBG_STATUS_HW_ONLY_RECORDING,\n+\tDBG_STATUS_STORM_ALREADY_ENABLED,\n+\tDBG_STATUS_STORM_NOT_ENABLED,\n+\tDBG_STATUS_BLOCK_ALREADY_ENABLED,\n+\tDBG_STATUS_BLOCK_NOT_ENABLED,\n+\tDBG_STATUS_NO_INPUT_ENABLED,\n+\tDBG_STATUS_NO_FILTER_TRIGGER_64B,\n+\tDBG_STATUS_FILTER_ALREADY_ENABLED,\n+\tDBG_STATUS_TRIGGER_ALREADY_ENABLED,\n+\tDBG_STATUS_TRIGGER_NOT_ENABLED,\n+\tDBG_STATUS_CANT_ADD_CONSTRAINT,\n+\tDBG_STATUS_TOO_MANY_TRIGGER_STATES,\n+\tDBG_STATUS_TOO_MANY_CONSTRAINTS,\n+\tDBG_STATUS_RECORDING_NOT_STARTED,\n+\tDBG_STATUS_DATA_DIDNT_TRIGGER,\n+\tDBG_STATUS_NO_DATA_RECORDED,\n+\tDBG_STATUS_DUMP_BUF_TOO_SMALL,\n+\tDBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,\n+\tDBG_STATUS_UNKNOWN_CHIP,\n+\tDBG_STATUS_VIRT_MEM_ALLOC_FAILED,\n+\tDBG_STATUS_BLOCK_IN_RESET,\n+\tDBG_STATUS_INVALID_TRACE_SIGNATURE,\n+\tDBG_STATUS_INVALID_NVRAM_BUNDLE,\n+\tDBG_STATUS_NVRAM_GET_IMAGE_FAILED,\n+\tDBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,\n+\tDBG_STATUS_NVRAM_READ_FAILED,\n+\tDBG_STATUS_IDLE_CHK_PARSE_FAILED,\n+\tDBG_STATUS_MCP_TRACE_BAD_DATA,\n+\tDBG_STATUS_MCP_TRACE_NO_META,\n+\tDBG_STATUS_MCP_COULD_NOT_HALT,\n+\tDBG_STATUS_MCP_COULD_NOT_RESUME,\n+\tDBG_STATUS_DMAE_FAILED,\n+\tDBG_STATUS_SEMI_FIFO_NOT_EMPTY,\n+\tDBG_STATUS_IGU_FIFO_BAD_DATA,\n+\tDBG_STATUS_MCP_COULD_NOT_MASK_PRTY,\n+\tDBG_STATUS_FW_ASSERTS_PARSE_FAILED,\n+\tDBG_STATUS_REG_FIFO_BAD_DATA,\n+\tDBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,\n+\tDBG_STATUS_DBG_ARRAY_NOT_SET,\n+\tDBG_STATUS_MULTI_BLOCKS_WITH_FILTER,\n+\tMAX_DBG_STATUS\n+};\n+\n+\n+/*\n+ * Debug Storms IDs\n+ */\n+enum dbg_storms {\n+\tDBG_TSTORM_ID,\n+\tDBG_MSTORM_ID,\n+\tDBG_USTORM_ID,\n+\tDBG_XSTORM_ID,\n+\tDBG_YSTORM_ID,\n+\tDBG_PSTORM_ID,\n+\tMAX_DBG_STORMS\n+};\n+\n+\n+/*\n+ * Idle Check data\n+ */\n+struct idle_chk_data {\n+\t__le32 buf_size /* Idle check buffer size in dwords */;\n+/* Indicates if the idle check buffer size was set (0/1) */\n+\tu8 buf_size_set;\n+\tu8 reserved1;\n+\t__le16 reserved2;\n+};\n+\n+/*\n+ * Debug Tools data (per HW function)\n+ */\n+struct dbg_tools_data {\n+\tstruct dbg_grc_data grc /* GRC Dump data */;\n+\tstruct dbg_bus_data bus /* Debug Bus data */;\n+\tstruct idle_chk_data idle_chk /* Idle Check data */;\n+\tu8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */;\n+/* Indicates if a block is in reset state (0/1) */\n+\tu8 block_in_reset[80];\n+\tu8 chip_id /* Chip ID (from enum chip_ids) */;\n+\tu8 platform_id /* Platform ID (from enum platform_ids) */;\n+\tu8 initialized /* Indicates if the data was initialized */;\n+\tu8 reserved;\n+};\n+\n+\n+#endif /* __ECORE_HSI_DEBUG_TOOLS__ */\ndiff --git a/drivers/net/qede/base/ecore_hsi_init_func.h b/drivers/net/qede/base/ecore_hsi_init_func.h\nnew file mode 100644\nindex 0000000..fca7479\n--- /dev/null\n+++ b/drivers/net/qede/base/ecore_hsi_init_func.h\n@@ -0,0 +1,132 @@\n+/*\n+ * Copyright (c) 2016 QLogic Corporation.\n+ * All rights reserved.\n+ * www.qlogic.com\n+ *\n+ * See LICENSE.qede_pmd for copyright and licensing details.\n+ */\n+\n+#ifndef __ECORE_HSI_INIT_FUNC__\n+#define __ECORE_HSI_INIT_FUNC__\n+/********************************/\n+/* HSI Init Functions constants */\n+/********************************/\n+\n+/* Number of VLAN priorities */\n+#define NUM_OF_VLAN_PRIORITIES\t\t\t8\n+\n+\n+/*\n+ * BRB RAM init requirements\n+ */\n+struct init_brb_ram_req {\n+\t__le32 guranteed_per_tc /* guaranteed size per TC, in bytes */;\n+\t__le32 headroom_per_tc /* headroom size per TC, in bytes */;\n+\t__le32 min_pkt_size /* min packet size, in bytes */;\n+\t__le32 max_ports_per_engine /* min packet size, in bytes */;\n+\tu8 num_active_tcs[MAX_NUM_PORTS] /* number of active TCs per port */;\n+};\n+\n+\n+/*\n+ * ETS per-TC init requirements\n+ */\n+struct init_ets_tc_req {\n+/* if set, this TC participates in the arbitration with a strict priority\n+ * (the priority is equal to the TC ID)\n+ */\n+\tu8 use_sp;\n+/* if set, this TC participates in the arbitration with a WFQ weight\n+ * (indicated by the weight field)\n+ */\n+\tu8 use_wfq;\n+/* An arbitration weight. Valid only if use_wfq is set. */\n+\t__le16 weight;\n+};\n+\n+/*\n+ * ETS init requirements\n+ */\n+struct init_ets_req {\n+\t__le32 mtu /* Max packet size (in bytes) */;\n+/* ETS initialization requirements per TC. */\n+\tstruct init_ets_tc_req tc_req[NUM_OF_TCS];\n+};\n+\n+\n+\n+/*\n+ * NIG LB RL init requirements\n+ */\n+struct init_nig_lb_rl_req {\n+/* Global MAC+LB RL rate (in Mbps). If set to 0, the RL will be disabled. */\n+\t__le16 lb_mac_rate;\n+/* Global LB RL rate (in Mbps). If set to 0, the RL will be disabled. */\n+\t__le16 lb_rate;\n+\t__le32 mtu /* Max packet size (in bytes) */;\n+/* RL rate per physical TC (in Mbps). If set to 0, the RL will be disabled. */\n+\t__le16 tc_rate[NUM_OF_PHYS_TCS];\n+};\n+\n+\n+/*\n+ * NIG TC mapping for each priority\n+ */\n+struct init_nig_pri_tc_map_entry {\n+\tu8 tc_id /* the mapped TC ID */;\n+\tu8 valid /* indicates if the mapping entry is valid */;\n+};\n+\n+\n+/*\n+ * NIG priority to TC map init requirements\n+ */\n+struct init_nig_pri_tc_map_req {\n+\tstruct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];\n+};\n+\n+\n+/*\n+ * QM per-port init parameters\n+ */\n+struct init_qm_port_params {\n+\tu8 active /* Indicates if this port is active */;\n+/* Vector of valid bits for active TCs used by this port */\n+\tu8 active_phys_tcs;\n+/* number of PBF command lines that can be used by this port */\n+\t__le16 num_pbf_cmd_lines;\n+/* number of BTB blocks that can be used by this port */\n+\t__le16 num_btb_blocks;\n+\t__le16 reserved;\n+};\n+\n+\n+/*\n+ * QM per-PQ init parameters\n+ */\n+struct init_qm_pq_params {\n+\tu8 vport_id /* VPORT ID */;\n+\tu8 tc_id /* TC ID */;\n+\tu8 wrr_group /* WRR group */;\n+/* Indicates if a rate limiter should be allocated for the PQ (0/1) */\n+\tu8 rl_valid;\n+};\n+\n+\n+/*\n+ * QM per-vport init parameters\n+ */\n+struct init_qm_vport_params {\n+/* rate limit in Mb/sec units. a value of 0 means dont configure. ignored if\n+ * VPORT RL is globally disabled.\n+ */\n+\t__le32 vport_rl;\n+/* WFQ weight. A value of 0 means dont configure. ignored if VPORT WFQ is\n+ * globally disabled.\n+ */\n+\t__le16 vport_wfq;\n+/* the first Tx PQ ID associated with this VPORT for each TC. */\n+\t__le16 first_tx_pq_id[NUM_OF_TCS];\n+};\n+\n+#endif /* __ECORE_HSI_INIT_FUNC__ */\ndiff --git a/drivers/net/qede/base/ecore_hsi_init_tool.h b/drivers/net/qede/base/ecore_hsi_init_tool.h\nnew file mode 100644\nindex 0000000..410b0bc\n--- /dev/null\n+++ b/drivers/net/qede/base/ecore_hsi_init_tool.h\n@@ -0,0 +1,454 @@\n+/*\n+ * Copyright (c) 2016 QLogic Corporation.\n+ * All rights reserved.\n+ * www.qlogic.com\n+ *\n+ * See LICENSE.qede_pmd for copyright and licensing details.\n+ */\n+\n+#ifndef __ECORE_HSI_INIT_TOOL__\n+#define __ECORE_HSI_INIT_TOOL__\n+/**************************************/\n+/* Init Tool HSI constants and macros */\n+/**************************************/\n+\n+/* Width of GRC address in bits (addresses are specified in dwords) */\n+#define GRC_ADDR_BITS\t\t\t23\n+#define MAX_GRC_ADDR\t\t\t((1 << GRC_ADDR_BITS) - 1)\n+\n+/* indicates an init that should be applied to any phase ID */\n+#define ANY_PHASE_ID\t\t\t0xffff\n+\n+/* Max size in dwords of a zipped array */\n+#define MAX_ZIPPED_SIZE\t\t\t8192\n+\n+\n+struct fw_asserts_ram_section {\n+/* The offset of the section in the RAM in RAM lines (64-bit units) */\n+\t__le16 section_ram_line_offset;\n+/* The size of the section in RAM lines (64-bit units) */\n+\t__le16 section_ram_line_size;\n+/* The offset of the asserts list within the section in dwords */\n+\tu8 list_dword_offset;\n+/* The size of an assert list element in dwords */\n+\tu8 list_element_dword_size;\n+\tu8 list_num_elements /* The number of elements in the asserts list */;\n+/* The offset of the next list index field within the section in dwords */\n+\tu8 list_next_index_dword_offset;\n+};\n+\n+\n+struct fw_ver_num {\n+\tu8 major /* Firmware major version number */;\n+\tu8 minor /* Firmware minor version number */;\n+\tu8 rev /* Firmware revision version number */;\n+/* Firmware engineering version number (for bootleg versions) */\n+\tu8 eng;\n+};\n+\n+struct fw_ver_info {\n+\t__le16 tools_ver /* Tools version number */;\n+\tu8 image_id /* FW image ID (e.g. main, l2b, kuku) */;\n+\tu8 reserved1;\n+\tstruct fw_ver_num num /* FW version number */;\n+\t__le32 timestamp /* FW Timestamp in unix time  (sec. since 1970) */;\n+\t__le32 reserved2;\n+};\n+\n+struct fw_info {\n+\tstruct fw_ver_info ver /* FW version information */;\n+/* Info regarding the FW asserts section in the Storm RAM */\n+\tstruct fw_asserts_ram_section fw_asserts_section;\n+};\n+\n+\n+struct fw_info_location {\n+/* GRC address where the fw_info struct is located. */\n+\t__le32 grc_addr;\n+/* Size of the fw_info structure (thats located at the grc_addr). */\n+\t__le32 size;\n+};\n+\n+\n+\n+\n+enum init_modes {\n+\tMODE_BB_A0,\n+\tMODE_BB_B0,\n+\tMODE_K2,\n+\tMODE_ASIC,\n+\tMODE_EMUL_REDUCED,\n+\tMODE_EMUL_FULL,\n+\tMODE_FPGA,\n+\tMODE_CHIPSIM,\n+\tMODE_SF,\n+\tMODE_MF_SD,\n+\tMODE_MF_SI,\n+\tMODE_PORTS_PER_ENG_1,\n+\tMODE_PORTS_PER_ENG_2,\n+\tMODE_PORTS_PER_ENG_4,\n+\tMODE_100G,\n+\tMODE_40G,\n+\tMODE_EAGLE_ENG1_WORKAROUND,\n+\tMAX_INIT_MODES\n+};\n+\n+\n+enum init_phases {\n+\tPHASE_ENGINE,\n+\tPHASE_PORT,\n+\tPHASE_PF,\n+\tPHASE_VF,\n+\tPHASE_QM_PF,\n+\tMAX_INIT_PHASES\n+};\n+\n+\n+enum init_split_types {\n+\tSPLIT_TYPE_NONE,\n+\tSPLIT_TYPE_PORT,\n+\tSPLIT_TYPE_PF,\n+\tSPLIT_TYPE_PORT_PF,\n+\tSPLIT_TYPE_VF,\n+\tMAX_INIT_SPLIT_TYPES\n+};\n+\n+\n+/*\n+ * Binary buffer header\n+ */\n+struct bin_buffer_hdr {\n+/* buffer offset in bytes from the beginning of the binary file */\n+\t__le32 offset;\n+\t__le32 length /* buffer length in bytes */;\n+};\n+\n+\n+/*\n+ * binary init buffer types\n+ */\n+enum bin_init_buffer_type {\n+\tBIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,\n+\tBIN_BUF_INIT_CMD /* init commands */,\n+\tBIN_BUF_INIT_VAL /* init data */,\n+\tBIN_BUF_INIT_MODE_TREE /* init modes tree */,\n+\tBIN_BUF_INIT_IRO /* internal RAM offsets */,\n+\tMAX_BIN_INIT_BUFFER_TYPE\n+};\n+\n+\n+/*\n+ * init array header: raw\n+ */\n+struct init_array_raw_hdr {\n+\t__le32 data;\n+/* Init array type, from init_array_types enum */\n+#define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF\n+#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0\n+/* init array params */\n+#define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF\n+#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4\n+};\n+\n+/*\n+ * init array header: standard\n+ */\n+struct init_array_standard_hdr {\n+\t__le32 data;\n+/* Init array type, from init_array_types enum */\n+#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK  0xF\n+#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0\n+/* Init array size (in dwords) */\n+#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK  0xFFFFFFF\n+#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4\n+};\n+\n+/*\n+ * init array header: zipped\n+ */\n+struct init_array_zipped_hdr {\n+\t__le32 data;\n+/* Init array type, from init_array_types enum */\n+#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF\n+#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0\n+/* Init array zipped size (in bytes) */\n+#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF\n+#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4\n+};\n+\n+/*\n+ * init array header: pattern\n+ */\n+struct init_array_pattern_hdr {\n+\t__le32 data;\n+/* Init array type, from init_array_types enum */\n+#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK          0xF\n+#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT         0\n+/* pattern size in dword */\n+#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK  0xF\n+#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4\n+/* pattern repetitions */\n+#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK   0xFFFFFF\n+#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT  8\n+};\n+\n+/*\n+ * init array header union\n+ */\n+union init_array_hdr {\n+\tstruct init_array_raw_hdr raw /* raw init array header */;\n+/* standard init array header */\n+\tstruct init_array_standard_hdr standard;\n+\tstruct init_array_zipped_hdr zipped /* zipped init array header */;\n+\tstruct init_array_pattern_hdr pattern /* pattern init array header */;\n+};\n+\n+\n+\n+\n+\n+/*\n+ * init array types\n+ */\n+enum init_array_types {\n+\tINIT_ARR_STANDARD /* standard init array */,\n+\tINIT_ARR_ZIPPED /* zipped init array */,\n+\tINIT_ARR_PATTERN /* a repeated pattern */,\n+\tMAX_INIT_ARRAY_TYPES\n+};\n+\n+\n+\n+/*\n+ * init operation: callback\n+ */\n+struct init_callback_op {\n+\t__le32 op_data;\n+/* Init operation, from init_op_types enum */\n+#define INIT_CALLBACK_OP_OP_MASK        0xF\n+#define INIT_CALLBACK_OP_OP_SHIFT       0\n+#define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF\n+#define INIT_CALLBACK_OP_RESERVED_SHIFT 4\n+\t__le16 callback_id /* Callback ID */;\n+\t__le16 block_id /* Blocks ID */;\n+};\n+\n+\n+/*\n+ * init operation: delay\n+ */\n+struct init_delay_op {\n+\t__le32 op_data;\n+/* Init operation, from init_op_types enum */\n+#define INIT_DELAY_OP_OP_MASK        0xF\n+#define INIT_DELAY_OP_OP_SHIFT       0\n+#define INIT_DELAY_OP_RESERVED_MASK  0xFFFFFFF\n+#define INIT_DELAY_OP_RESERVED_SHIFT 4\n+\t__le32 delay /* delay in us */;\n+};\n+\n+\n+/*\n+ * init operation: if_mode\n+ */\n+struct init_if_mode_op {\n+\t__le32 op_data;\n+/* Init operation, from init_op_types enum */\n+#define INIT_IF_MODE_OP_OP_MASK          0xF\n+#define INIT_IF_MODE_OP_OP_SHIFT         0\n+#define INIT_IF_MODE_OP_RESERVED1_MASK   0xFFF\n+#define INIT_IF_MODE_OP_RESERVED1_SHIFT  4\n+/* Commands to skip if the modes dont match */\n+#define INIT_IF_MODE_OP_CMD_OFFSET_MASK  0xFFFF\n+#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16\n+\t__le16 reserved2;\n+/* offset (in bytes) in modes expression buffer */\n+\t__le16 modes_buf_offset;\n+};\n+\n+\n+/*\n+ * init operation: if_phase\n+ */\n+struct init_if_phase_op {\n+\t__le32 op_data;\n+/* Init operation, from init_op_types enum */\n+#define INIT_IF_PHASE_OP_OP_MASK           0xF\n+#define INIT_IF_PHASE_OP_OP_SHIFT          0\n+/* Indicates if DMAE is enabled in this phase */\n+#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK  0x1\n+#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4\n+#define INIT_IF_PHASE_OP_RESERVED1_MASK    0x7FF\n+#define INIT_IF_PHASE_OP_RESERVED1_SHIFT   5\n+/* Commands to skip if the phases dont match */\n+#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK   0xFFFF\n+#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT  16\n+\t__le32 phase_data;\n+#define INIT_IF_PHASE_OP_PHASE_MASK        0xFF /* Init phase */\n+#define INIT_IF_PHASE_OP_PHASE_SHIFT       0\n+#define INIT_IF_PHASE_OP_RESERVED2_MASK    0xFF\n+#define INIT_IF_PHASE_OP_RESERVED2_SHIFT   8\n+#define INIT_IF_PHASE_OP_PHASE_ID_MASK     0xFFFF /* Init phase ID */\n+#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT    16\n+};\n+\n+\n+/*\n+ * init mode operators\n+ */\n+enum init_mode_ops {\n+\tINIT_MODE_OP_NOT /* init mode not operator */,\n+\tINIT_MODE_OP_OR /* init mode or operator */,\n+\tINIT_MODE_OP_AND /* init mode and operator */,\n+\tMAX_INIT_MODE_OPS\n+};\n+\n+\n+/*\n+ * init operation: raw\n+ */\n+struct init_raw_op {\n+\t__le32 op_data;\n+/* Init operation, from init_op_types enum */\n+#define INIT_RAW_OP_OP_MASK      0xF\n+#define INIT_RAW_OP_OP_SHIFT     0\n+#define INIT_RAW_OP_PARAM1_MASK  0xFFFFFFF /* init param 1 */\n+#define INIT_RAW_OP_PARAM1_SHIFT 4\n+\t__le32 param2 /* Init param 2 */;\n+};\n+\n+/*\n+ * init array params\n+ */\n+struct init_op_array_params {\n+\t__le16 size /* array size in dwords */;\n+\t__le16 offset /* array start offset in dwords */;\n+};\n+\n+/*\n+ * Write init operation arguments\n+ */\n+union init_write_args {\n+/* value to write, used when init source is INIT_SRC_INLINE */\n+\t__le32 inline_val;\n+/* number of zeros to write, used when init source is INIT_SRC_ZEROS */\n+\t__le32 zeros_count;\n+/* array offset to write, used when init source is INIT_SRC_ARRAY */\n+\t__le32 array_offset;\n+/* runtime array params to write, used when init source is INIT_SRC_RUNTIME */\n+\tstruct init_op_array_params runtime;\n+};\n+\n+/*\n+ * init operation: write\n+ */\n+struct init_write_op {\n+\t__le32 data;\n+/* init operation, from init_op_types enum */\n+#define INIT_WRITE_OP_OP_MASK        0xF\n+#define INIT_WRITE_OP_OP_SHIFT       0\n+/* init source type, taken from init_source_types enum */\n+#define INIT_WRITE_OP_SOURCE_MASK    0x7\n+#define INIT_WRITE_OP_SOURCE_SHIFT   4\n+#define INIT_WRITE_OP_RESERVED_MASK  0x1\n+#define INIT_WRITE_OP_RESERVED_SHIFT 7\n+/* indicates if the register is wide-bus */\n+#define INIT_WRITE_OP_WIDE_BUS_MASK  0x1\n+#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8\n+/* internal (absolute) GRC address, in dwords */\n+#define INIT_WRITE_OP_ADDRESS_MASK   0x7FFFFF\n+#define INIT_WRITE_OP_ADDRESS_SHIFT  9\n+\tunion init_write_args args /* Write init operation arguments */;\n+};\n+\n+/*\n+ * init operation: read\n+ */\n+struct init_read_op {\n+\t__le32 op_data;\n+/* init operation, from init_op_types enum */\n+#define INIT_READ_OP_OP_MASK         0xF\n+#define INIT_READ_OP_OP_SHIFT        0\n+/* polling type, from init_poll_types enum */\n+#define INIT_READ_OP_POLL_TYPE_MASK  0xF\n+#define INIT_READ_OP_POLL_TYPE_SHIFT 4\n+#define INIT_READ_OP_RESERVED_MASK   0x1\n+#define INIT_READ_OP_RESERVED_SHIFT  8\n+/* internal (absolute) GRC address, in dwords */\n+#define INIT_READ_OP_ADDRESS_MASK    0x7FFFFF\n+#define INIT_READ_OP_ADDRESS_SHIFT   9\n+/* expected polling value, used only when polling is done */\n+\t__le32 expected_val;\n+};\n+\n+/*\n+ * Init operations union\n+ */\n+union init_op {\n+\tstruct init_raw_op raw /* raw init operation */;\n+\tstruct init_write_op write /* write init operation */;\n+\tstruct init_read_op read /* read init operation */;\n+\tstruct init_if_mode_op if_mode /* if_mode init operation */;\n+\tstruct init_if_phase_op if_phase /* if_phase init operation */;\n+\tstruct init_callback_op callback /* callback init operation */;\n+\tstruct init_delay_op delay /* delay init operation */;\n+};\n+\n+\n+\n+/*\n+ * Init command operation types\n+ */\n+enum init_op_types {\n+\tINIT_OP_READ /* GRC read init command */,\n+\tINIT_OP_WRITE /* GRC write init command */,\n+/* Skip init commands if the init modes expression doesn't match */\n+\tINIT_OP_IF_MODE,\n+/* Skip init commands if the init phase doesn't match */\n+\tINIT_OP_IF_PHASE,\n+\tINIT_OP_DELAY /* delay init command */,\n+\tINIT_OP_CALLBACK /* callback init command */,\n+\tMAX_INIT_OP_TYPES\n+};\n+\n+\n+/*\n+ * init polling types\n+ */\n+enum init_poll_types {\n+\tINIT_POLL_NONE /* No polling */,\n+\tINIT_POLL_EQ /* init value is included in the init command */,\n+\tINIT_POLL_OR /* init value is all zeros */,\n+\tINIT_POLL_AND /* init value is an array of values */,\n+\tMAX_INIT_POLL_TYPES\n+};\n+\n+\n+\n+\n+/*\n+ * init source types\n+ */\n+enum init_source_types {\n+\tINIT_SRC_INLINE /* init value is included in the init command */,\n+\tINIT_SRC_ZEROS /* init value is all zeros */,\n+\tINIT_SRC_ARRAY /* init value is an array of values */,\n+\tINIT_SRC_RUNTIME /* init value is provided during runtime */,\n+\tMAX_INIT_SOURCE_TYPES\n+};\n+\n+\n+\n+\n+/*\n+ * Internal RAM Offsets macro data\n+ */\n+struct iro {\n+\t__le32 base /* RAM field offset */;\n+\t__le16 m1 /* multiplier 1 */;\n+\t__le16 m2 /* multiplier 2 */;\n+\t__le16 m3 /* multiplier 3 */;\n+\t__le16 size /* RAM field size */;\n+};\n+\n+#endif /* __ECORE_HSI_INIT_TOOL__ */\ndiff --git a/drivers/net/qede/base/ecore_hsi_tools.h b/drivers/net/qede/base/ecore_hsi_tools.h\ndeleted file mode 100644\nindex 18eea76..0000000\n--- a/drivers/net/qede/base/ecore_hsi_tools.h\n+++ /dev/null\n@@ -1,1081 +0,0 @@\n-/*\n- * Copyright (c) 2016 QLogic Corporation.\n- * All rights reserved.\n- * www.qlogic.com\n- *\n- * See LICENSE.qede_pmd for copyright and licensing details.\n- */\n-\n-#ifndef __ECORE_HSI_TOOLS__\n-#define __ECORE_HSI_TOOLS__\n-/**********************************/\n-/* Tools HSI constants and macros */\n-/**********************************/\n-\n-/*********************************** Init ************************************/\n-\n-/* Width of GRC address in bits (addresses are specified in dwords) */\n-#define GRC_ADDR_BITS\t\t\t23\n-#define MAX_GRC_ADDR\t\t\t((1 << GRC_ADDR_BITS) - 1)\n-\n-/* indicates an init that should be applied to any phase ID */\n-#define ANY_PHASE_ID\t\t\t0xffff\n-\n-/* init pattern size in bytes */\n-#define INIT_PATTERN_SIZE_BITS\t4\n-#define MAX_INIT_PATTERN_SIZE\t(1 << INIT_PATTERN_SIZE_BITS)\n-\n-/* Max size in dwords of a zipped array */\n-#define MAX_ZIPPED_SIZE\t\t\t8192\n-\n-/* Global PXP window */\n-#define NUM_OF_PXP_WIN\t\t\t19\n-#define PXP_WIN_DWORD_SIZE_BITS\t10\n-#define PXP_WIN_DWORD_SIZE\t\t(1 << PXP_WIN_DWORD_SIZE_BITS)\n-#define PXP_WIN_BYTE_SIZE_BITS\t(PXP_WIN_DWORD_SIZE_BITS + 2)\n-#define PXP_WIN_BYTE_SIZE\t\t(PXP_WIN_DWORD_SIZE * 4)\n-\n-/********************************* GRC Dump **********************************/\n-\n-/* width of GRC dump register sequence length in bits */\n-#define DUMP_SEQ_LEN_BITS\t\t\t8\n-#define DUMP_SEQ_LEN_MAX_VAL\t\t((1 << DUMP_SEQ_LEN_BITS) - 1)\n-\n-/* width of GRC dump memory length in bits */\n-#define DUMP_MEM_LEN_BITS\t\t\t18\n-#define DUMP_MEM_LEN_MAX_VAL\t\t((1 << DUMP_MEM_LEN_BITS) - 1)\n-\n-/* width of register type ID in bits */\n-#define REG_TYPE_ID_BITS\t\t\t6\n-#define REG_TYPE_ID_MAX_VAL\t\t\t((1 << REG_TYPE_ID_BITS) - 1)\n-\n-/* width of block ID in bits */\n-#define BLOCK_ID_BITS\t\t\t\t8\n-#define BLOCK_ID_MAX_VAL\t\t\t((1 << BLOCK_ID_BITS) - 1)\n-\n-/******************************** Idle Check *********************************/\n-\n-/* max number of idle check predicate immediates */\n-#define MAX_IDLE_CHK_PRED_IMM\t\t3\n-\n-/* max number of idle check argument registers */\n-#define MAX_IDLE_CHK_READ_REGS\t\t3\n-\n-/* max number of idle check loops */\n-#define MAX_IDLE_CHK_LOOPS\t\t\t0x10000\n-\n-/* max idle check address increment */\n-#define MAX_IDLE_CHK_INCREMENT\t\t0x10000\n-\n-/* inicates an undefined idle check line index */\n-#define IDLE_CHK_UNDEFINED_LINE_IDX\t0xffffff\n-\n-/* max number of register values following the idle check header for LSI */\n-#define IDLE_CHK_MAX_LSI_DUMP_REGS\t2\n-\n-/* arguments for IDLE_CHK_MACRO_TYPE_QM_RD_WR */\n-#define IDLE_CHK_QM_RD_WR_PTR\t\t0\n-#define IDLE_CHK_QM_RD_WR_BANK\t\t1\n-\n-/**************************************/\n-/* HSI Functions constants and macros */\n-/**************************************/\n-\n-/* Number of VLAN priorities */\n-#define NUM_OF_VLAN_PRIORITIES\t\t\t8\n-\n-/* the MCP Trace meta data signautre is duplicated in the\n- * perl script that generats the NVRAM images\n- */\n-#define MCP_TRACE_META_IMAGE_SIGNATURE\t0x669955aa\n-\n-/* Maximal number of RAM lines occupied by FW Asserts data */\n-#define MAX_FW_ASSERTS_RAM_LINES\t\t800\n-\n-/*\n- * Binary buffer header\n- */\n-struct bin_buffer_hdr {\n-\t__le32 offset\n-\t    /* buffer offset in bytes from the beginning of the binary file */;\n-\t__le32 length /* buffer length in bytes */;\n-};\n-\n-/*\n- * binary buffer types\n- */\n-enum bin_buffer_type {\n-\tBIN_BUF_FW_VER_INFO /* fw_ver_info struct */,\n-\tBIN_BUF_INIT_CMD /* init commands */,\n-\tBIN_BUF_INIT_VAL /* init data */,\n-\tBIN_BUF_INIT_MODE_TREE /* init modes tree */,\n-\tBIN_BUF_IRO /* internal RAM offsets array */,\n-\tMAX_BIN_BUFFER_TYPE\n-};\n-\n-/*\n- * Chip IDs\n- */\n-enum chip_ids {\n-\tCHIP_BB_A0 /* BB A0 chip ID */,\n-\tCHIP_BB_B0 /* BB B0 chip ID */,\n-\tCHIP_K2 /* AH chip ID */,\n-\tMAX_CHIP_IDS\n-};\n-\n-/*\n- * memory dump descriptor\n- */\n-struct dbg_dump_mem_desc {\n-\t__le32 dword0;\n-#define DBG_DUMP_MEM_DESC_ADDRESS_MASK         0xFFFFFF\n-#define DBG_DUMP_MEM_DESC_ADDRESS_SHIFT        0\n-#define DBG_DUMP_MEM_DESC_ASIC_CHIP_MASK_MASK  0xF\n-#define DBG_DUMP_MEM_DESC_ASIC_CHIP_MASK_SHIFT 24\n-#define DBG_DUMP_MEM_DESC_SIM_CHIP_MASK_MASK   0xF\n-#define DBG_DUMP_MEM_DESC_SIM_CHIP_MASK_SHIFT  28\n-\t__le32 dword1;\n-#define DBG_DUMP_MEM_DESC_LENGTH_MASK          0x3FFFF\n-#define DBG_DUMP_MEM_DESC_LENGTH_SHIFT         0\n-#define DBG_DUMP_MEM_DESC_REG_TYPE_ID_MASK     0x3F\n-#define DBG_DUMP_MEM_DESC_REG_TYPE_ID_SHIFT    18\n-#define DBG_DUMP_MEM_DESC_BLOCK_ID_MASK        0xFF\n-#define DBG_DUMP_MEM_DESC_BLOCK_ID_SHIFT       24\n-};\n-\n-/*\n- * registers dump descriptor: chip\n- */\n-struct dbg_dump_regs_chip_desc {\n-\t__le32 data;\n-#define DBG_DUMP_REGS_CHIP_DESC_IS_CHIP_MASK_MASK    0x1\n-#define DBG_DUMP_REGS_CHIP_DESC_IS_CHIP_MASK_SHIFT   0\n-#define DBG_DUMP_REGS_CHIP_DESC_ASIC_CHIP_MASK_MASK  0x7FFFFF\n-#define DBG_DUMP_REGS_CHIP_DESC_ASIC_CHIP_MASK_SHIFT 1\n-#define DBG_DUMP_REGS_CHIP_DESC_SIM_CHIP_MASK_MASK   0xFF\n-#define DBG_DUMP_REGS_CHIP_DESC_SIM_CHIP_MASK_SHIFT  24\n-};\n-\n-/*\n- * registers dump descriptor: raw\n- */\n-struct dbg_dump_regs_raw_desc {\n-\t__le32 data;\n-#define DBG_DUMP_REGS_RAW_DESC_IS_CHIP_MASK_MASK  0x1\n-#define DBG_DUMP_REGS_RAW_DESC_IS_CHIP_MASK_SHIFT 0\n-#define DBG_DUMP_REGS_RAW_DESC_PARAM1_MASK        0x7FFFFF\n-#define DBG_DUMP_REGS_RAW_DESC_PARAM1_SHIFT       1\n-#define DBG_DUMP_REGS_RAW_DESC_PARAM2_MASK        0xFF\n-#define DBG_DUMP_REGS_RAW_DESC_PARAM2_SHIFT       24\n-};\n-\n-/*\n- * registers dump descriptor: sequence\n- */\n-struct dbg_dump_regs_seq_desc {\n-\t__le32 data;\n-#define DBG_DUMP_REGS_SEQ_DESC_IS_CHIP_MASK_MASK  0x1\n-#define DBG_DUMP_REGS_SEQ_DESC_IS_CHIP_MASK_SHIFT 0\n-#define DBG_DUMP_REGS_SEQ_DESC_ADDRESS_MASK       0x7FFFFF\n-#define DBG_DUMP_REGS_SEQ_DESC_ADDRESS_SHIFT      1\n-#define DBG_DUMP_REGS_SEQ_DESC_LENGTH_MASK        0xFF\n-#define DBG_DUMP_REGS_SEQ_DESC_LENGTH_SHIFT       24\n-};\n-\n-/*\n- * registers dump descriptor\n- */\n-union dbg_dump_regs_desc {\n-\tstruct dbg_dump_regs_raw_desc raw /* dumped registers raw descriptor */\n-\t   ;\n-\tstruct dbg_dump_regs_seq_desc seq /* dumped registers seq descriptor */\n-\t   ;\n-\tstruct dbg_dump_regs_chip_desc chip\n-\t    /* dumped registers chip descriptor */;\n-};\n-\n-/*\n- * idle check macro types\n- */\n-enum idle_chk_macro_types {\n-\tIDLE_CHK_MACRO_TYPE_COMPARE /* parametric register comparison */,\n-\tIDLE_CHK_MACRO_TYPE_QM_RD_WR /* compare QM r/w pointers and banks */,\n-\tMAX_IDLE_CHK_MACRO_TYPES\n-};\n-\n-/*\n- * Idle Check result header\n- */\n-struct idle_chk_result_hdr {\n-\t__le16 rule_idx /* Idle check rule index in CSV file */;\n-\t__le16 loop_idx /* the loop index in which the failure occurred */;\n-\t__le16 num_fw_values;\n-\t__le16 data;\n-#define IDLE_CHK_RESULT_HDR_NUM_LSI_VALUES_MASK  0xF\n-#define IDLE_CHK_RESULT_HDR_NUM_LSI_VALUES_SHIFT 0\n-#define IDLE_CHK_RESULT_HDR_LOOP_VALID_MASK      0x1\n-#define IDLE_CHK_RESULT_HDR_LOOP_VALID_SHIFT     4\n-#define IDLE_CHK_RESULT_HDR_SEVERITY_MASK        0x7\n-#define IDLE_CHK_RESULT_HDR_SEVERITY_SHIFT       5\n-#define IDLE_CHK_RESULT_HDR_MACRO_TYPE_MASK      0xF\n-#define IDLE_CHK_RESULT_HDR_MACRO_TYPE_SHIFT     8\n-#define IDLE_CHK_RESULT_HDR_MACRO_TYPE_ARG_MASK  0xF\n-#define IDLE_CHK_RESULT_HDR_MACRO_TYPE_ARG_SHIFT 12\n-};\n-\n-/*\n- * Idle Check rule\n- */\n-struct idle_chk_rule {\n-\t__le32 data;\n-#define IDLE_CHK_RULE_ASIC_CHIP_MASK_MASK  0xF\n-#define IDLE_CHK_RULE_ASIC_CHIP_MASK_SHIFT 0\n-#define IDLE_CHK_RULE_SIM_CHIP_MASK_MASK   0xF\n-#define IDLE_CHK_RULE_SIM_CHIP_MASK_SHIFT  4\n-#define IDLE_CHK_RULE_BLOCK_ID_MASK        0xFF\n-#define IDLE_CHK_RULE_BLOCK_ID_SHIFT       8\n-#define IDLE_CHK_RULE_MACRO_TYPE_MASK      0xF\n-#define IDLE_CHK_RULE_MACRO_TYPE_SHIFT     16\n-#define IDLE_CHK_RULE_SEVERITY_MASK        0x7\n-#define IDLE_CHK_RULE_SEVERITY_SHIFT       20\n-#define IDLE_CHK_RULE_RESERVED_MASK        0x1\n-#define IDLE_CHK_RULE_RESERVED_SHIFT       23\n-#define IDLE_CHK_RULE_PRED_ID_MASK         0xFF\n-#define IDLE_CHK_RULE_PRED_ID_SHIFT        24\n-\t__le16 loop;\n-\t__le16 increment\n-\t    /* address increment of first argument register on each iteration */\n-\t   ;\n-\t__le32 reg_addr[3];\n-\t__le32 pred_imm[3]\n-\t    /* immediate values passed as arguments to the idle check rule */;\n-};\n-\n-/*\n- * idle check severity types\n- */\n-enum idle_chk_severity_types {\n-\tIDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */,\n-\tIDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC\n-\t    ,\n-\tIDLE_CHK_SEVERITY_WARNING\n-\t    /* idle check failure should cause a warning */,\n-\tMAX_IDLE_CHK_SEVERITY_TYPES\n-};\n-\n-/*\n- * init array header: raw\n- */\n-struct init_array_raw_hdr {\n-\t__le32 data;\n-#define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF\n-#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0\n-#define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF\n-#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4\n-};\n-\n-/*\n- * init array header: standard\n- */\n-struct init_array_standard_hdr {\n-\t__le32 data;\n-#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK  0xF\n-#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0\n-#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK  0xFFFFFFF\n-#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4\n-};\n-\n-/*\n- * init array header: zipped\n- */\n-struct init_array_zipped_hdr {\n-\t__le32 data;\n-#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF\n-#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0\n-#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF\n-#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4\n-};\n-\n-/*\n- * init array header: pattern\n- */\n-struct init_array_pattern_hdr {\n-\t__le32 data;\n-#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK          0xF\n-#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT         0\n-#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK  0xF\n-#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4\n-#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK   0xFFFFFF\n-#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT  8\n-};\n-\n-/*\n- * init array header union\n- */\n-union init_array_hdr {\n-\tstruct init_array_raw_hdr raw /* raw init array header */;\n-\tstruct init_array_standard_hdr standard /* standard init array header */\n-\t   ;\n-\tstruct init_array_zipped_hdr zipped /* zipped init array header */;\n-\tstruct init_array_pattern_hdr pattern /* pattern init array header */;\n-};\n-\n-/*\n- * init array types\n- */\n-enum init_array_types {\n-\tINIT_ARR_STANDARD /* standard init array */,\n-\tINIT_ARR_ZIPPED /* zipped init array */,\n-\tINIT_ARR_PATTERN /* a repeated pattern */,\n-\tMAX_INIT_ARRAY_TYPES\n-};\n-\n-/*\n- * init operation: callback\n- */\n-struct init_callback_op {\n-\t__le32 op_data;\n-#define INIT_CALLBACK_OP_OP_MASK        0xF\n-#define INIT_CALLBACK_OP_OP_SHIFT       0\n-#define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF\n-#define INIT_CALLBACK_OP_RESERVED_SHIFT 4\n-\t__le16 callback_id /* Callback ID */;\n-\t__le16 block_id /* Blocks ID */;\n-};\n-\n-/*\n- * init operation: delay\n- */\n-struct init_delay_op {\n-\t__le32 op_data;\n-#define INIT_DELAY_OP_OP_MASK        0xF\n-#define INIT_DELAY_OP_OP_SHIFT       0\n-#define INIT_DELAY_OP_RESERVED_MASK  0xFFFFFFF\n-#define INIT_DELAY_OP_RESERVED_SHIFT 4\n-\t__le32 delay /* delay in us */;\n-};\n-\n-/*\n- * init operation: if_mode\n- */\n-struct init_if_mode_op {\n-\t__le32 op_data;\n-#define INIT_IF_MODE_OP_OP_MASK          0xF\n-#define INIT_IF_MODE_OP_OP_SHIFT         0\n-#define INIT_IF_MODE_OP_RESERVED1_MASK   0xFFF\n-#define INIT_IF_MODE_OP_RESERVED1_SHIFT  4\n-#define INIT_IF_MODE_OP_CMD_OFFSET_MASK  0xFFFF\n-#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16\n-\t__le16 reserved2;\n-\t__le16 modes_buf_offset\n-\t    /* offset (in bytes) in modes expression buffer */;\n-};\n-\n-/*\n- * init operation: if_phase\n- */\n-struct init_if_phase_op {\n-\t__le32 op_data;\n-#define INIT_IF_PHASE_OP_OP_MASK           0xF\n-#define INIT_IF_PHASE_OP_OP_SHIFT          0\n-#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK  0x1\n-#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4\n-#define INIT_IF_PHASE_OP_RESERVED1_MASK    0x7FF\n-#define INIT_IF_PHASE_OP_RESERVED1_SHIFT   5\n-#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK   0xFFFF\n-#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT  16\n-\t__le32 phase_data;\n-#define INIT_IF_PHASE_OP_PHASE_MASK        0xFF\n-#define INIT_IF_PHASE_OP_PHASE_SHIFT       0\n-#define INIT_IF_PHASE_OP_RESERVED2_MASK    0xFF\n-#define INIT_IF_PHASE_OP_RESERVED2_SHIFT   8\n-#define INIT_IF_PHASE_OP_PHASE_ID_MASK     0xFFFF\n-#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT    16\n-};\n-\n-/*\n- * init mode operators\n- */\n-enum init_mode_ops {\n-\tINIT_MODE_OP_NOT /* init mode not operator */,\n-\tINIT_MODE_OP_OR /* init mode or operator */,\n-\tINIT_MODE_OP_AND /* init mode and operator */,\n-\tMAX_INIT_MODE_OPS\n-};\n-\n-/*\n- * init operation: raw\n- */\n-struct init_raw_op {\n-\t__le32 op_data;\n-#define INIT_RAW_OP_OP_MASK      0xF\n-#define INIT_RAW_OP_OP_SHIFT     0\n-#define INIT_RAW_OP_PARAM1_MASK  0xFFFFFFF\n-#define INIT_RAW_OP_PARAM1_SHIFT 4\n-\t__le32 param2 /* Init param 2 */;\n-};\n-\n-/*\n- * init array params\n- */\n-struct init_op_array_params {\n-\t__le16 size /* array size in dwords */;\n-\t__le16 offset /* array start offset in dwords */;\n-};\n-\n-/*\n- * Write init operation arguments\n- */\n-union init_write_args {\n-\t__le32 inline_val\n-\t    /* value to write, used when init source is INIT_SRC_INLINE */;\n-\t__le32 zeros_count;\n-\t__le32 array_offset\n-\t    /* array offset to write, used when init source is INIT_SRC_ARRAY */\n-\t   ;\n-\tstruct init_op_array_params runtime;\n-};\n-\n-/*\n- * init operation: write\n- */\n-struct init_write_op {\n-\t__le32 data;\n-#define INIT_WRITE_OP_OP_MASK        0xF\n-#define INIT_WRITE_OP_OP_SHIFT       0\n-#define INIT_WRITE_OP_SOURCE_MASK    0x7\n-#define INIT_WRITE_OP_SOURCE_SHIFT   4\n-#define INIT_WRITE_OP_RESERVED_MASK  0x1\n-#define INIT_WRITE_OP_RESERVED_SHIFT 7\n-#define INIT_WRITE_OP_WIDE_BUS_MASK  0x1\n-#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8\n-#define INIT_WRITE_OP_ADDRESS_MASK   0x7FFFFF\n-#define INIT_WRITE_OP_ADDRESS_SHIFT  9\n-\tunion init_write_args args /* Write init operation arguments */;\n-};\n-\n-/*\n- * init operation: read\n- */\n-struct init_read_op {\n-\t__le32 op_data;\n-#define INIT_READ_OP_OP_MASK         0xF\n-#define INIT_READ_OP_OP_SHIFT        0\n-#define INIT_READ_OP_POLL_TYPE_MASK  0xF\n-#define INIT_READ_OP_POLL_TYPE_SHIFT 4\n-#define INIT_READ_OP_RESERVED_MASK   0x1\n-#define INIT_READ_OP_RESERVED_SHIFT  8\n-#define INIT_READ_OP_ADDRESS_MASK    0x7FFFFF\n-#define INIT_READ_OP_ADDRESS_SHIFT   9\n-\t__le32 expected_val\n-\t    /* expected polling value, used only when polling is done */;\n-};\n-\n-/*\n- * Init operations union\n- */\n-union init_op {\n-\tstruct init_raw_op raw /* raw init operation */;\n-\tstruct init_write_op write /* write init operation */;\n-\tstruct init_read_op read /* read init operation */;\n-\tstruct init_if_mode_op if_mode /* if_mode init operation */;\n-\tstruct init_if_phase_op if_phase /* if_phase init operation */;\n-\tstruct init_callback_op callback /* callback init operation */;\n-\tstruct init_delay_op delay /* delay init operation */;\n-};\n-\n-/*\n- * Init command operation types\n- */\n-enum init_op_types {\n-\tINIT_OP_READ /* GRC read init command */,\n-\tINIT_OP_WRITE /* GRC write init command */,\n-\tINIT_OP_IF_MODE\n-\t    /* Skip init commands if the init modes expression doesn't match */,\n-\tINIT_OP_IF_PHASE\n-\t    /* Skip init commands if the init phase doesn't match */,\n-\tINIT_OP_DELAY /* delay init command */,\n-\tINIT_OP_CALLBACK /* callback init command */,\n-\tMAX_INIT_OP_TYPES\n-};\n-\n-/*\n- * init polling types\n- */\n-enum init_poll_types {\n-\tINIT_POLL_NONE /* No polling */,\n-\tINIT_POLL_EQ /* init value is included in the init command */,\n-\tINIT_POLL_OR /* init value is all zeros */,\n-\tINIT_POLL_AND /* init value is an array of values */,\n-\tMAX_INIT_POLL_TYPES\n-};\n-\n-/*\n- * init source types\n- */\n-enum init_source_types {\n-\tINIT_SRC_INLINE /* init value is included in the init command */,\n-\tINIT_SRC_ZEROS /* init value is all zeros */,\n-\tINIT_SRC_ARRAY /* init value is an array of values */,\n-\tINIT_SRC_RUNTIME /* init value is provided during runtime */,\n-\tMAX_INIT_SOURCE_TYPES\n-};\n-\n-/*\n- * Internal RAM Offsets macro data\n- */\n-struct iro {\n-\t__le32 base /* RAM field offset */;\n-\t__le16 m1 /* multiplier 1 */;\n-\t__le16 m2 /* multiplier 2 */;\n-\t__le16 m3 /* multiplier 3 */;\n-\t__le16 size /* RAM field size */;\n-};\n-\n-/*\n- * register descriptor\n- */\n-struct reg_desc {\n-\t__le32 data;\n-#define REG_DESC_ADDRESS_MASK  0xFFFFFF\n-#define REG_DESC_ADDRESS_SHIFT 0\n-#define REG_DESC_SIZE_MASK     0xFF\n-#define REG_DESC_SIZE_SHIFT    24\n-};\n-\n-/*\n- * Debug Bus block data\n- */\n-struct dbg_bus_block_data {\n-\tu8 enabled /* Indicates if the block is enabled for recording (0/1) */;\n-\tu8 hw_id /* HW ID associated with the block */;\n-\tu8 line_num /* Debug line number to select */;\n-\tu8 right_shift /* Number of units to  right the debug data (0-3) */;\n-\tu8 cycle_en /* 4-bit value: bit i set -> unit i is enabled. */;\n-\tu8 force_valid /* 4-bit value: bit i set -> unit i is forced valid. */;\n-\tu8 force_frame\n-\t    /* 4-bit value: bit i set -> unit i frame bit is forced. */;\n-\tu8 reserved;\n-};\n-\n-/*\n- * Debug Bus Clients\n- */\n-enum dbg_bus_clients {\n-\tDBG_BUS_CLIENT_RBCN,\n-\tDBG_BUS_CLIENT_RBCP,\n-\tDBG_BUS_CLIENT_RBCR,\n-\tDBG_BUS_CLIENT_RBCT,\n-\tDBG_BUS_CLIENT_RBCU,\n-\tDBG_BUS_CLIENT_RBCF,\n-\tDBG_BUS_CLIENT_RBCX,\n-\tDBG_BUS_CLIENT_RBCS,\n-\tDBG_BUS_CLIENT_RBCH,\n-\tDBG_BUS_CLIENT_RBCZ,\n-\tDBG_BUS_CLIENT_OTHER_ENGINE,\n-\tDBG_BUS_CLIENT_TIMESTAMP,\n-\tDBG_BUS_CLIENT_CPU,\n-\tDBG_BUS_CLIENT_RBCY,\n-\tDBG_BUS_CLIENT_RBCQ,\n-\tDBG_BUS_CLIENT_RBCM,\n-\tDBG_BUS_CLIENT_RBCB,\n-\tDBG_BUS_CLIENT_RBCW,\n-\tDBG_BUS_CLIENT_RBCV,\n-\tMAX_DBG_BUS_CLIENTS\n-};\n-\n-/*\n- * Debug Bus constraint operation types\n- */\n-enum dbg_bus_constraint_ops {\n-\tDBG_BUS_CONSTRAINT_OP_EQ /* equal */,\n-\tDBG_BUS_CONSTRAINT_OP_NE /* not equal */,\n-\tDBG_BUS_CONSTRAINT_OP_LT /* less than */,\n-\tDBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */,\n-\tDBG_BUS_CONSTRAINT_OP_LE /* less than or equal */,\n-\tDBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */,\n-\tDBG_BUS_CONSTRAINT_OP_GT /* greater than */,\n-\tDBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */,\n-\tDBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */,\n-\tDBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */,\n-\tMAX_DBG_BUS_CONSTRAINT_OPS\n-};\n-\n-/*\n- * Debug Bus memory address\n- */\n-struct dbg_bus_mem_addr {\n-\t__le32 lo;\n-\t__le32 hi;\n-};\n-\n-/*\n- * Debug Bus PCI buffer data\n- */\n-struct dbg_bus_pci_buf_data {\n-\tstruct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */;\n-\tstruct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */;\n-\t__le32 size /* PCI buffer size in bytes */;\n-};\n-\n-/*\n- * Debug Bus Storm EID range filter params\n- */\n-struct dbg_bus_storm_eid_range_params {\n-\tu8 min /* Minimal event ID to filter on */;\n-\tu8 max /* Maximal event ID to filter on */;\n-};\n-\n-/*\n- * Debug Bus Storm EID mask filter params\n- */\n-struct dbg_bus_storm_eid_mask_params {\n-\tu8 val /* Event ID value */;\n-\tu8 mask /* Event ID mask. 1s in the mask = dont care bits. */;\n-};\n-\n-/*\n- * Debug Bus Storm EID filter params\n- */\n-union dbg_bus_storm_eid_params {\n-\tstruct dbg_bus_storm_eid_range_params range\n-\t    /* EID range filter params */;\n-\tstruct dbg_bus_storm_eid_mask_params mask /* EID mask filter params */;\n-};\n-\n-/*\n- * Debug Bus Storm data\n- */\n-struct dbg_bus_storm_data {\n-\tu8 fast_enabled;\n-\tu8 fast_mode\n-\t    /* Fast debug Storm mode, valid only if fast_enabled is set */;\n-\tu8 slow_enabled;\n-\tu8 slow_mode\n-\t    /* Slow debug Storm mode, valid only if slow_enabled is set */;\n-\tu8 hw_id /* HW ID associated with the Storm */;\n-\tu8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */;\n-\tu8 eid_range_not_mask;\n-\tu8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */;\n-\tunion dbg_bus_storm_eid_params eid_filter_params;\n-\t__le16 reserved;\n-\t__le32 cid /* CID to filter on. Valid only if cid_filter_en is set. */;\n-};\n-\n-/*\n- * Debug Bus data\n- */\n-struct dbg_bus_data {\n-\t__le32 app_version /* The tools version number of the application */;\n-\tu8 state /* The current debug bus state */;\n-\tu8 hw_dwords /* HW dwords per cycle */;\n-\tu8 next_hw_id /* Next HW ID to be associated with an input */;\n-\tu8 num_enabled_blocks /* Number of blocks enabled for recording */;\n-\tu8 num_enabled_storms /* Number of Storms enabled for recording */;\n-\tu8 target /* Output target */;\n-\tu8 next_trigger_state /* ID of next trigger state to be added */;\n-\tu8 next_constraint_id\n-\t    /* ID of next filter/trigger constraint to be added */;\n-\tu8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */;\n-\tu8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */;\n-\tu8 timestamp_input_en\n-\t    /* Indicates if timestamp recording is enabled (0/1) */;\n-\tu8 filter_en /* Indicates if the recording filter is enabled (0/1) */;\n-\tu8 trigger_en /* Indicates if the recording trigger is enabled (0/1) */\n-\t   ;\n-\tu8 adding_filter;\n-\tu8 filter_pre_trigger;\n-\tu8 filter_post_trigger;\n-\tu8 unify_inputs;\n-\tu8 rcv_from_other_engine;\n-\tstruct dbg_bus_pci_buf_data pci_buf;\n-\t__le16 reserved;\n-\tstruct dbg_bus_block_data blocks[80] /* Debug Bus data for each block */\n-\t   ;\n-\tstruct dbg_bus_storm_data storms[6] /* Debug Bus data for each block */\n-\t   ;\n-};\n-\n-/*\n- * Debug bus filter types\n- */\n-enum dbg_bus_filter_types {\n-\tDBG_BUS_FILTER_TYPE_OFF /* filter always off */,\n-\tDBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */,\n-\tDBG_BUS_FILTER_TYPE_POST /* filter after trigger only */,\n-\tDBG_BUS_FILTER_TYPE_ON /* filter always on */,\n-\tMAX_DBG_BUS_FILTER_TYPES\n-};\n-\n-/*\n- * Debug bus frame modes\n- */\n-enum dbg_bus_frame_modes {\n-\tDBG_BUS_FRAME_MODE_0HW_4ST = 0 /* 0 HW dwords, 4 Storm dwords */,\n-\tDBG_BUS_FRAME_MODE_4HW_0ST = 3 /* 4 HW dwords, 0 Storm dwords */,\n-\tDBG_BUS_FRAME_MODE_8HW_0ST = 4 /* 8 HW dwords, 0 Storm dwords */,\n-\tMAX_DBG_BUS_FRAME_MODES\n-};\n-\n-/*\n- * Debug bus input types\n- */\n-enum dbg_bus_input_types {\n-\tDBG_BUS_INPUT_TYPE_STORM,\n-\tDBG_BUS_INPUT_TYPE_BLOCK,\n-\tMAX_DBG_BUS_INPUT_TYPES\n-};\n-\n-/*\n- * Debug bus other engine mode\n- */\n-enum dbg_bus_other_engine_modes {\n-\tDBG_BUS_OTHER_ENGINE_MODE_NONE,\n-\tDBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,\n-\tDBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,\n-\tDBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,\n-\tDBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,\n-\tMAX_DBG_BUS_OTHER_ENGINE_MODES\n-};\n-\n-/*\n- * Debug bus post-trigger recording types\n- */\n-enum dbg_bus_post_trigger_types {\n-\tDBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */,\n-\tDBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */,\n-\tMAX_DBG_BUS_POST_TRIGGER_TYPES\n-};\n-\n-/*\n- * Debug bus pre-trigger recording types\n- */\n-enum dbg_bus_pre_trigger_types {\n-\tDBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */,\n-\tDBG_BUS_PRE_TRIGGER_NUM_CHUNKS\n-\t    /* start recording some chunks before trigger */,\n-\tDBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */,\n-\tMAX_DBG_BUS_PRE_TRIGGER_TYPES\n-};\n-\n-/*\n- * Debug bus SEMI frame modes\n- */\n-enum dbg_bus_semi_frame_modes {\n-\tDBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST =\n-\t    0 /* 0 slow dwords, 4 fast dwords */,\n-\tDBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST =\n-\t    3 /* 4 slow dwords, 0 fast dwords */,\n-\tMAX_DBG_BUS_SEMI_FRAME_MODES\n-};\n-\n-/*\n- * Debug bus states\n- */\n-enum dbg_bus_states {\n-\tDBG_BUS_STATE_BEFORE_RECORD /* before debug bus the recording starts */\n-\t    ,\n-\tDBG_BUS_STATE_DURING_RECORD /* during debug bus recording */,\n-\tDBG_BUS_STATE_AFTER_RECORD /* after debug bus recording */,\n-\tMAX_DBG_BUS_STATES\n-};\n-\n-/*\n- * Debug Bus Storm modes\n- */\n-enum dbg_bus_storm_modes {\n-\tDBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */,\n-\tDBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */,\n-\tDBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */,\n-\tDBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */,\n-\tDBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */,\n-\tDBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */,\n-\tDBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */,\n-\tDBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */,\n-\tDBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */,\n-\tMAX_DBG_BUS_STORM_MODES\n-};\n-\n-/*\n- * Debug bus target IDs\n- */\n-enum dbg_bus_targets {\n-\tDBG_BUS_TARGET_ID_INT_BUF\n-\t    /* records debug bus to DBG block internal buffer */,\n-\tDBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */,\n-\tDBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */,\n-\tMAX_DBG_BUS_TARGETS\n-};\n-\n-/*\n- * GRC Dump data\n- */\n-struct dbg_grc_data {\n-\tu8 is_updated /* Indicates if the GRC Dump data is updated (0/1) */;\n-\tu8 chip_id /* Chip ID */;\n-\tu8 chip_mask /* Chip mask */;\n-\tu8 reserved;\n-\t__le32 max_dump_dwords /* Max GRC Dump size in dwords */;\n-\t__le32 param_val[40];\n-\tu8 param_set_by_user[40];\n-};\n-\n-/*\n- * Debug GRC params\n- */\n-enum dbg_grc_params {\n-\tDBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */,\n-\tDBG_GRC_PARAM_RESERVED /* reserved */,\n-\tDBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */,\n-\tDBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */,\n-\tDBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */,\n-\tDBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */,\n-\tDBG_GRC_PARAM_EXCLUDE_ALL\n-\t    /* preset: exclude all memories from dump (1 only) */,\n-\tDBG_GRC_PARAM_CRASH\n-\t    /* preset: include memories for crash dump (1 only) */,\n-\tDBG_GRC_PARAM_PARITY_SAFE\n-\t    /* perform dump only if MFW is responding (0/1) */,\n-\tDBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */,\n-\tMAX_DBG_GRC_PARAMS\n-};\n-\n-/*\n- * Debug reset registers\n- */\n-enum dbg_reset_regs {\n-\tDBG_RESET_REG_MISCS_PL_UA,\n-\tDBG_RESET_REG_MISCS_PL_HV,\n-\tDBG_RESET_REG_MISC_PL_UA,\n-\tDBG_RESET_REG_MISC_PL_HV,\n-\tDBG_RESET_REG_MISC_PL_PDA_VMAIN_1,\n-\tDBG_RESET_REG_MISC_PL_PDA_VMAIN_2,\n-\tDBG_RESET_REG_MISC_PL_PDA_VAUX,\n-\tMAX_DBG_RESET_REGS\n-};\n-\n-/*\n- * @DPDK Debug status codes\n- */\n-enum dbg_status {\n-\tDBG_STATUS_OK,\n-\tDBG_STATUS_APP_VERSION_NOT_SET,\n-\tDBG_STATUS_UNSUPPORTED_APP_VERSION,\n-\tDBG_STATUS_DBG_BLOCK_NOT_RESET,\n-\tDBG_STATUS_INVALID_ARGS,\n-\tDBG_STATUS_OUTPUT_ALREADY_SET,\n-\tDBG_STATUS_INVALID_PCI_BUF_SIZE,\n-\tDBG_STATUS_PCI_BUF_ALLOC_FAILED,\n-\tDBG_STATUS_PCI_BUF_NOT_ALLOCATED,\n-\tDBG_STATUS_TOO_MANY_INPUTS,\n-\tDBG_STATUS_INPUT_OVERLAP,\n-\tDBG_STATUS_HW_ONLY_RECORDING,\n-\tDBG_STATUS_STORM_ALREADY_ENABLED,\n-\tDBG_STATUS_STORM_NOT_ENABLED,\n-\tDBG_STATUS_BLOCK_ALREADY_ENABLED,\n-\tDBG_STATUS_BLOCK_NOT_ENABLED,\n-\tDBG_STATUS_NO_INPUT_ENABLED,\n-\tDBG_STATUS_NO_FILTER_TRIGGER_64B,\n-\tDBG_STATUS_FILTER_ALREADY_ENABLED,\n-\tDBG_STATUS_TRIGGER_ALREADY_ENABLED,\n-\tDBG_STATUS_TRIGGER_NOT_ENABLED,\n-\tDBG_STATUS_CANT_ADD_CONSTRAINT,\n-\tDBG_STATUS_TOO_MANY_TRIGGER_STATES,\n-\tDBG_STATUS_TOO_MANY_CONSTRAINTS,\n-\tDBG_STATUS_RECORDING_NOT_STARTED,\n-\tDBG_STATUS_NO_DATA_TRIGGERED,\n-\tDBG_STATUS_NO_DATA_RECORDED,\n-\tDBG_STATUS_DUMP_BUF_TOO_SMALL,\n-\tDBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,\n-\tDBG_STATUS_UNKNOWN_CHIP,\n-\tDBG_STATUS_VIRT_MEM_ALLOC_FAILED,\n-\tDBG_STATUS_BLOCK_IN_RESET,\n-\tDBG_STATUS_INVALID_TRACE_SIGNATURE,\n-\tDBG_STATUS_INVALID_NVRAM_BUNDLE,\n-\tDBG_STATUS_NVRAM_GET_IMAGE_FAILED,\n-\tDBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,\n-\tDBG_STATUS_NVRAM_READ_FAILED,\n-\tDBG_STATUS_IDLE_CHK_PARSE_FAILED,\n-\tDBG_STATUS_MCP_TRACE_BAD_DATA,\n-\tDBG_STATUS_MCP_TRACE_NO_META,\n-\tDBG_STATUS_MCP_COULD_NOT_HALT,\n-\tDBG_STATUS_MCP_COULD_NOT_RESUME,\n-\tDBG_STATUS_DMAE_FAILED,\n-\tDBG_STATUS_SEMI_FIFO_NOT_EMPTY,\n-\tDBG_STATUS_IGU_FIFO_BAD_DATA,\n-\tDBG_STATUS_MCP_COULD_NOT_MASK_PRTY,\n-\tDBG_STATUS_FW_ASSERTS_PARSE_FAILED,\n-\tDBG_STATUS_REG_FIFO_BAD_DATA,\n-\tDBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,\n-\tMAX_DBG_STATUS\n-};\n-\n-/*\n- * Debug Storms IDs\n- */\n-enum dbg_storms {\n-\tDBG_TSTORM_ID,\n-\tDBG_MSTORM_ID,\n-\tDBG_USTORM_ID,\n-\tDBG_XSTORM_ID,\n-\tDBG_YSTORM_ID,\n-\tDBG_PSTORM_ID,\n-\tMAX_DBG_STORMS\n-};\n-\n-/*\n- * Idle Check data\n- */\n-struct idle_chk_data {\n-\t__le32 buf_size /* Idle check buffer size in dwords */;\n-\tu8 buf_size_set\n-\t    /* Indicates if the idle check buffer size was set (0/1) */;\n-\tu8 reserved1;\n-\t__le16 reserved2;\n-};\n-\n-/*\n- * Idle Check data\n- */\n-struct mcp_trace_data {\n-\t__le32 buf_size /* MCP Trace buffer size in dwords */;\n-\tu8 buf_size_set\n-\t    /* Indicates if the MCP Trace buffer size was set (0/1) */;\n-\tu8 reserved1;\n-\t__le16 reserved2;\n-};\n-\n-/*\n- * Debug Tools data (per HW function)\n- */\n-struct dbg_tools_data {\n-\tstruct dbg_grc_data grc /* GRC Dump data */;\n-\tstruct dbg_bus_data bus /* Debug Bus data */;\n-\tstruct idle_chk_data idle_chk /* Idle Check data */;\n-\tstruct mcp_trace_data mcp_trace /* MCP Trace data */;\n-\tu8 block_in_reset[80] /* Indicates if a block is in reset state (0/1) */\n-\t   ;\n-\tu8 chip_id /* Chip ID (from enum chip_ids) */;\n-\tu8 chip_mask\n-\t    /* Chip mask = bit index chip_id is set, the rest are cleared */;\n-\tu8 initialized /* Indicates if the data was initialized */;\n-\tu8 reset_state_updated\n-\t    /* Indicates if blocks reset state is updated (0/1) */;\n-};\n-\n-/*\n- * BRB RAM init requirements\n- */\n-struct init_brb_ram_req {\n-\t__le32 guranteed_per_tc /* guaranteed size per TC, in bytes */;\n-\t__le32 headroom_per_tc /* headroom size per TC, in bytes */;\n-\t__le32 min_pkt_size /* min packet size, in bytes */;\n-\t__le32 max_ports_per_engine /* min packet size, in bytes */;\n-\tu8 num_active_tcs[MAX_NUM_PORTS] /* number of active TCs per port */;\n-};\n-\n-/*\n- * ETS per-TC init requirements\n- */\n-struct init_ets_tc_req {\n-\tu8 use_sp;\n-\tu8 use_wfq;\n-\t__le16 weight /* An arbitration weight. Valid only if use_wfq is set. */\n-\t   ;\n-};\n-\n-/*\n- * ETS init requirements\n- */\n-struct init_ets_req {\n-\t__le32 mtu /* Max packet size (in bytes) */;\n-\tstruct init_ets_tc_req tc_req[NUM_OF_TCS]\n-\t    /* ETS initialization requirements per TC. */;\n-};\n-\n-/*\n- * NIG LB RL init requirements\n- */\n-struct init_nig_lb_rl_req {\n-\t__le16 lb_mac_rate;\n-\t__le16 lb_rate;\n-\t__le32 mtu /* Max packet size (in bytes) */;\n-\t__le16 tc_rate[NUM_OF_PHYS_TCS];\n-};\n-\n-/*\n- * NIG TC mapping for each priority\n- */\n-struct init_nig_pri_tc_map_entry {\n-\tu8 tc_id /* the mapped TC ID */;\n-\tu8 valid /* indicates if the mapping entry is valid */;\n-};\n-\n-/*\n- * NIG priority to TC map init requirements\n- */\n-struct init_nig_pri_tc_map_req {\n-\tstruct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];\n-};\n-\n-/*\n- * QM per-port init parameters\n- */\n-struct init_qm_port_params {\n-\tu8 active /* Indicates if this port is active */;\n-\tu8 num_active_phys_tcs /* number of physical TCs used by this port */;\n-\t__le16 num_pbf_cmd_lines\n-\t    /* number of PBF command lines that can be used by this port */;\n-\t__le16 num_btb_blocks\n-\t    /* number of BTB blocks that can be used by this port */;\n-\t__le16 reserved;\n-};\n-\n-/*\n- * QM per-PQ init parameters\n- */\n-struct init_qm_pq_params {\n-\tu8 vport_id /* VPORT ID */;\n-\tu8 tc_id /* TC ID */;\n-\tu8 wrr_group /* WRR group */;\n-\tu8 reserved;\n-};\n-\n-/*\n- * QM per-vport init parameters\n- */\n-struct init_qm_vport_params {\n-\t__le32 vport_rl;\n-\t__le16 vport_wfq;\n-\t__le16 first_tx_pq_id[NUM_OF_TCS]\n-\t    /* the first Tx PQ ID associated with this VPORT for each TC. */;\n-};\n-\n-#endif /* __ECORE_HSI_TOOLS__ */\ndiff --git a/drivers/net/qede/base/ecore_init_fw_funcs.c b/drivers/net/qede/base/ecore_init_fw_funcs.c\nindex 5324e05..5440731 100644\n--- a/drivers/net/qede/base/ecore_init_fw_funcs.c\n+++ b/drivers/net/qede/base/ecore_init_fw_funcs.c\n@@ -12,7 +12,8 @@\n #include \"reg_addr.h\"\n #include \"ecore_rt_defs.h\"\n #include \"ecore_hsi_common.h\"\n-#include \"ecore_hsi_tools.h\"\n+#include \"ecore_hsi_init_func.h\"\n+#include \"ecore_hsi_init_tool.h\"\n #include \"ecore_init_fw_funcs.h\"\n \n /* @DPDK CmInterfaceEnum */\n@@ -187,7 +188,7 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,\n \t\t\t\t     struct init_qm_port_params\n \t\t\t\t     port_params[MAX_NUM_PORTS])\n {\n-\tu8 tc, voq, port_id;\n+\tu8 tc, voq, port_id, num_tcs_in_port;\n \tbool eagle_workaround = ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn);\n \t/* clear PBF lines for all VOQs */\n \tfor (voq = 0; voq < MAX_NUM_VOQS; voq++)\n@@ -201,18 +202,22 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,\n \t\t\tif (eagle_workaround)\n \t\t\t\tphys_lines -= PBF_CMDQ_EAGLE_WORKAROUND_LINES;\n \t\t\t/* find #lines per active physical TC */\n-\t\t\tphys_lines_per_tc =\n-\t\t\t    phys_lines /\n-\t\t\t    port_params[port_id].num_active_phys_tcs;\n+\t\t\tnum_tcs_in_port = 0;\n+\t\t\tfor (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {\n+\t\t\t\tif (((port_params[port_id].active_phys_tcs >>\n+\t\t\t\t\t\ttc) & 0x1) == 1)\n+\t\t\t\tnum_tcs_in_port++;\n+\t\t\t}\n+\t\t\tphys_lines_per_tc = phys_lines / num_tcs_in_port;\n \t\t\t/* init registers per active TC */\n-\t\t\tfor (tc = 0;\n-\t\t\t     tc < port_params[port_id].num_active_phys_tcs;\n-\t\t\t     tc++) {\n-\t\t\t\tvoq =\n-\t\t\t\t    PHYS_VOQ(port_id, tc,\n-\t\t\t\t\t     max_phys_tcs_per_port);\n-\t\t\t\tecore_cmdq_lines_voq_rt_init(p_hwfn, voq,\n-\t\t\t\t\t\t\t     phys_lines_per_tc);\n+\t\t\tfor (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {\n+\t\t\t\tif (((port_params[port_id].active_phys_tcs >>\n+\t\t\t\t\t\t\ttc) & 0x1) == 1) {\n+\t\t\t\t\tvoq = PHYS_VOQ(port_id, tc,\n+\t\t\t\t\t\t\tmax_phys_tcs_per_port);\n+\t\t\t\t\tecore_cmdq_lines_voq_rt_init(p_hwfn,\n+\t\t\t\t\t\t\tvoq, phys_lines_per_tc);\n+\t\t\t\t}\n \t\t\t}\n \t\t\t/* init registers for pure LB TC */\n \t\t\tecore_cmdq_lines_voq_rt_init(p_hwfn, LB_VOQ(port_id),\n@@ -255,7 +260,7 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,\n \t\t\t\t     struct init_qm_port_params\n \t\t\t\t     port_params[MAX_NUM_PORTS])\n {\n-\tu8 tc, voq, port_id;\n+\tu8 tc, voq, port_id, num_tcs_in_port;\n \tu32 usable_blocks, pure_lb_blocks, phys_blocks;\n \tbool eagle_workaround = ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn);\n \tfor (port_id = 0; port_id < max_ports_per_engine; port_id++) {\n@@ -266,9 +271,15 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,\n \t\t\t    BTB_HEADROOM_BLOCKS;\n \t\t\tif (eagle_workaround)\n \t\t\t\tusable_blocks -= BTB_EAGLE_WORKAROUND_BLOCKS;\n+\n+\t\t\tnum_tcs_in_port = 0;\n+\t\t\tfor (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)\n+\t\t\t\tif (((port_params[port_id].active_phys_tcs >>\n+\t\t\t\t\t\t\t\ttc) & 0x1) == 1)\n+\t\t\t\t\tnum_tcs_in_port++;\n \t\t\tpure_lb_blocks =\n \t\t\t    (usable_blocks * BTB_PURE_LB_FACTOR) /\n-\t\t\t    (port_params[port_id].num_active_phys_tcs *\n+\t\t\t    (num_tcs_in_port *\n \t\t\t     BTB_PURE_LB_FACTOR + BTB_PURE_LB_RATIO);\n \t\t\tpure_lb_blocks =\n \t\t\t    OSAL_MAX_T(u32, BTB_JUMBO_PKT_BLOCKS,\n@@ -276,17 +287,19 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,\n \t\t\tphys_blocks =\n \t\t\t    (usable_blocks -\n \t\t\t     pure_lb_blocks) /\n-\t\t\t    port_params[port_id].num_active_phys_tcs;\n+\t\t\t     num_tcs_in_port;\n \t\t\t/* init physical TCs */\n \t\t\tfor (tc = 0;\n-\t\t\t     tc < port_params[port_id].num_active_phys_tcs;\n+\t\t\t     tc < NUM_OF_PHYS_TCS;\n \t\t\t     tc++) {\n-\t\t\t\tvoq =\n-\t\t\t\t    PHYS_VOQ(port_id, tc,\n-\t\t\t\t\t     max_phys_tcs_per_port);\n-\t\t\t\tSTORE_RT_REG(p_hwfn,\n+\t\t\t\tif (((port_params[port_id].active_phys_tcs >>\n+\t\t\t\t\t\t\t tc) & 0x1) == 1) {\n+\t\t\t\t\tvoq = PHYS_VOQ(port_id, tc,\n+\t\t\t\t\t\t\tmax_phys_tcs_per_port);\n+\t\t\t\t\tSTORE_RT_REG(p_hwfn,\n \t\t\t\t\t     PBF_BTB_GUARANTEED_RT_OFFSET(voq),\n \t\t\t\t\t     phys_blocks);\n+\t\t\t\t}\n \t\t\t}\n \t\t\t/* init pure LB TC */\n \t\t\tSTORE_RT_REG(p_hwfn,\n@@ -610,18 +623,6 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,\n \t    (QM_OPPOR_PQ_EMPTY_DEF <<\n \t     QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT);\n \tSTORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);\n-\t/* check eagle workaround */\n-\tfor (port_id = 0; port_id < max_ports_per_engine; port_id++) {\n-\t\tif (port_params[port_id].active &&\n-\t\t    port_params[port_id].num_active_phys_tcs >\n-\t\t    EAGLE_WORKAROUND_TC &&\n-\t\t    ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {\n-\t\t\tDP_NOTICE(p_hwfn, true,\n-\t\t\t\t  \"Can't config 8 TCs with Eagle\"\n-\t\t\t\t  \" eng1 workaround\");\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n \t/* enable/disable PF RL */\n \tecore_enable_pf_rl(p_hwfn, pf_rl_en);\n \t/* enable/disable PF WFQ */\ndiff --git a/drivers/net/qede/base/ecore_init_ops.c b/drivers/net/qede/base/ecore_init_ops.c\nindex 326eb92..e6e4c36 100644\n--- a/drivers/net/qede/base/ecore_init_ops.c\n+++ b/drivers/net/qede/base/ecore_init_ops.c\n@@ -575,7 +575,7 @@ enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,\n \n \tbuf_hdr = (struct bin_buffer_hdr *)(uintptr_t)data;\n \n-\toffset = buf_hdr[BIN_BUF_FW_VER_INFO].offset;\n+\toffset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;\n \tfw->fw_ver_info = (struct fw_ver_info *)((uintptr_t)(data + offset));\n \n \toffset = buf_hdr[BIN_BUF_INIT_CMD].offset;\ndiff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c\nindex ea0fd7a..bed9ea3 100644\n--- a/drivers/net/qede/base/ecore_int.c\n+++ b/drivers/net/qede/base/ecore_int.c\n@@ -284,16 +284,7 @@ out:\n #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)\n static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)\n {\n-\tu32 tmp, reg_addr;\n-\n-\treg_addr =\n-\t    attn_blocks[BLOCK_PGLUE_B].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].\n-\t    int_regs[0]->mask_addr;\n-\n-\t/* Mask unnecessary attentions -@TBD move to MFW */\n-\ttmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr);\n-\ttmp |= (1 << 19);\t/* Was PGL_PCIE_ATTN */\n-\tecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr, tmp);\n+\tu32 tmp;\n \n \ttmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n \t\t       PGLUE_B_REG_TX_ERR_WR_DETAILS2);\n@@ -407,32 +398,6 @@ static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)\n \treturn ECORE_SUCCESS;\n }\n \n-static enum _ecore_status_t ecore_nig_attn_cb(struct ecore_hwfn *p_hwfn)\n-{\n-\tu32 tmp, reg_addr;\n-\n-\t/* Mask unnecessary attentions -@TBD move to MFW */\n-\treg_addr =\n-\t    attn_blocks[BLOCK_NIG].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].\n-\t    int_regs[3]->mask_addr;\n-\ttmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr);\n-\ttmp |= (1 << 0);\t/* Was 3_P0_TX_PAUSE_TOO_LONG_INT */\n-\ttmp |= NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT;\n-\tecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr, tmp);\n-\n-\treg_addr =\n-\t    attn_blocks[BLOCK_NIG].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].\n-\t    int_regs[5]->mask_addr;\n-\ttmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr);\n-\ttmp |= (1 << 0);\t/* Was 5_P1_TX_PAUSE_TOO_LONG_INT */\n-\tecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr, tmp);\n-\n-\t/* TODO - a bit risky to return success here; But alternative is to\n-\t * actually read the multitdue of interrupt register of the block.\n-\t */\n-\treturn ECORE_SUCCESS;\n-}\n-\n static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)\n {\n \tDP_NOTICE(p_hwfn, false, \"FW assertion!\\n\");\n@@ -559,7 +524,7 @@ static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {\n \t  {\"MSTAT per-path\", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},\n \t  {\"Reserved %d\", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,\n \t   MAX_BLOCK_ID},\n-\t  {\"NIG\", ATTENTION_PAR_INT, ecore_nig_attn_cb, BLOCK_NIG},\n+\t  {\"NIG\", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},\n \t  {\"BMB/OPTE/MCP\", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},\n \t  {\"BTB\", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},\n \t  {\"BRB\", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},\n@@ -839,43 +804,10 @@ ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,\n \t\trc = p_aeu->cb(p_hwfn);\n \t}\n \n-\t/* Handle HW block interrupt registers */\n-\tif (p_aeu->block_index != MAX_BLOCK_ID) {\n-\t\tu16 chip_type = ECORE_GET_TYPE(p_hwfn->p_dev);\n-\t\tstruct attn_hw_block *p_block;\n-\t\tint i;\n-\n-\t\tp_block = &attn_blocks[p_aeu->block_index];\n-\n-\t\t/* Handle each interrupt register */\n-\t\tfor (i = 0;\n-\t\t     i < p_block->chip_regs[chip_type].num_of_int_regs; i++) {\n-\t\t\tstruct attn_hw_reg *p_reg_desc;\n-\t\t\tu32 sts_addr;\n-\n-\t\t\tp_reg_desc = p_block->chip_regs[chip_type].int_regs[i];\n-\n-\t\t\t/* In case of fatal attention, don't clear the status\n-\t\t\t * so it would appear in idle check.\n-\t\t\t */\n-\t\t\tif (rc == ECORE_SUCCESS)\n-\t\t\t\tsts_addr = p_reg_desc->sts_clr_addr;\n-\t\t\telse\n-\t\t\t\tsts_addr = p_reg_desc->sts_addr;\n-\n-\t\t\tval = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, sts_addr);\n-\t\t\tmask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n-\t\t\t\t\tp_reg_desc->mask_addr);\n-\t\t\tecore_int_deassertion_print_bit(p_hwfn, p_reg_desc,\n-\t\t\t\t\t\t\tp_block,\n-\t\t\t\t\t\t\tECORE_ATTN_TYPE_ATTN,\n-\t\t\t\t\t\t\tval, mask);\n-\n-#ifndef REMOVE_DBG\n-\t\t\tinterrupts[i] = val;\n-#endif\n-\t\t}\n-\t}\n+\t/* Print HW block interrupt registers */\n+\tif (p_aeu->block_index != MAX_BLOCK_ID)\n+\t\tDP_NOTICE(p_hwfn->p_dev, false, \"[block_id %d type %d]\\n\",\n+\t\t\t  p_aeu->block_index, ATTN_TYPE_INTERRUPT);\n \n \t/* Reach assertion if attention is fatal */\n \tif (rc != ECORE_SUCCESS) {\n@@ -905,33 +837,6 @@ ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,\n \treturn rc;\n }\n \n-static void ecore_int_parity_print(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t   struct aeu_invert_reg_bit *p_aeu,\n-\t\t\t\t   struct attn_hw_block *p_block, u8 bit_index)\n-{\n-\tu16 chip_type = ECORE_GET_TYPE(p_hwfn->p_dev);\n-\tint i;\n-\n-\tfor (i = 0; i < p_block->chip_regs[chip_type].num_of_prty_regs; i++) {\n-\t\tstruct attn_hw_reg *p_reg_desc;\n-\t\tu32 val, mask;\n-\n-\t\tp_reg_desc = p_block->chip_regs[chip_type].prty_regs[i];\n-\n-\t\tval = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n-\t\t\t       p_reg_desc->sts_clr_addr);\n-\t\tmask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,\n-\t\t\t\tp_reg_desc->mask_addr);\n-\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_INTR,\n-\t\t\t   \"%s[%d] - parity register[%d] is %08x [mask is %08x]\\n\",\n-\t\t\t   p_aeu->bit_name, bit_index, i, val, mask);\n-\t\tecore_int_deassertion_print_bit(p_hwfn, p_reg_desc,\n-\t\t\t\t\t\tp_block,\n-\t\t\t\t\t\tECORE_ATTN_TYPE_PARITY,\n-\t\t\t\t\t\tval, mask);\n-\t}\n-}\n-\n /**\n  * @brief ecore_int_deassertion_parity - handle a single parity AEU source\n  *\n@@ -949,19 +854,15 @@ static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,\n \tDP_INFO(p_hwfn->p_dev, \"%s[%d] parity attention is set\\n\",\n \t\tp_aeu->bit_name, bit_index);\n \n-\tif (block_id != MAX_BLOCK_ID) {\n-\t\tecore_int_parity_print(p_hwfn, p_aeu, &attn_blocks[block_id],\n-\t\t\t\t       bit_index);\n-\n-\t\t/* In A0, there's a single parity bit for several blocks */\n-\t\tif (block_id == BLOCK_BTB) {\n-\t\t\tecore_int_parity_print(p_hwfn, p_aeu,\n-\t\t\t\t\t       &attn_blocks[BLOCK_OPTE],\n-\t\t\t\t\t       bit_index);\n-\t\t\tecore_int_parity_print(p_hwfn, p_aeu,\n-\t\t\t\t\t       &attn_blocks[BLOCK_MCP],\n-\t\t\t\t\t       bit_index);\n-\t\t}\n+\tif (block_id != MAX_BLOCK_ID)\n+\t\treturn;\n+\n+\t/* In A0, there's a single parity bit for several blocks */\n+\tif (block_id == BLOCK_BTB) {\n+\t\tDP_NOTICE(p_hwfn->p_dev, false, \"[block_id %d type %d]\\n\",\n+\t\t\t  BLOCK_OPTE, ATTN_TYPE_PARITY);\n+\t\tDP_NOTICE(p_hwfn->p_dev, false, \"[block_id %d type %d]\\n\",\n+\t\t\t  BLOCK_MCP, ATTN_TYPE_PARITY);\n \t}\n }\n \n@@ -1778,7 +1679,7 @@ ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n \t\t     enum ecore_int_mode int_mode)\n {\n \tenum _ecore_status_t rc = ECORE_SUCCESS;\n-\tu32 tmp, reg_addr;\n+\tu32 tmp;\n \n \t/* @@@tmp - Mask General HW attentions 0-31, Enable 32-36 */\n \ttmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);\n@@ -1794,16 +1695,6 @@ ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n \ttmp &= ~0x800;\n \tecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);\n \n-\t/* @@@tmp - Mask interrupt sources - should move to init tool;\n-\t * Also, correct for A0 [might still change in B0.\n-\t */\n-\treg_addr =\n-\t    attn_blocks[BLOCK_BRB].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].\n-\t    int_regs[0]->mask_addr;\n-\ttmp = ecore_rd(p_hwfn, p_ptt, reg_addr);\n-\ttmp |= (1 << 21);\t/* Was PKT4_LEN_ERROR */\n-\tecore_wr(p_hwfn, p_ptt, reg_addr, tmp);\n-\n \tecore_int_igu_enable_attn(p_hwfn, p_ptt);\n \n \tif ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {\n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "01/22"
    ]
}