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GET /api/patches/1425/?format=api
{ "id": 1425, "url": "https://patches.dpdk.org/api/patches/1425/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1416530816-2159-16-git-send-email-jingjing.wu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1416530816-2159-16-git-send-email-jingjing.wu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1416530816-2159-16-git-send-email-jingjing.wu@intel.com", "date": "2014-11-21T00:46:49", "name": "[dpdk-dev,v6,15/22] i40e: implement operations to get fdir info", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "910fed9378d1002dccd38899805fe0d4308234d0", "submitter": { "id": 47, "url": "https://patches.dpdk.org/api/people/47/?format=api", "name": "Jingjing Wu", "email": "jingjing.wu@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1416530816-2159-16-git-send-email-jingjing.wu@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/1425/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/1425/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id AD2777FCF;\n\tFri, 21 Nov 2014 01:37:27 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 0C8E2800E\n\tfor <dev@dpdk.org>; Fri, 21 Nov 2014 01:37:22 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP; 20 Nov 2014 16:45:22 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga002.jf.intel.com with ESMTP; 20 Nov 2014 16:47:35 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id sAL0lXpf004185;\n\tFri, 21 Nov 2014 08:47:33 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid sAL0lVqA002300; Fri, 21 Nov 2014 08:47:33 +0800", "(from wujingji@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id sAL0lVvR002296; \n\tFri, 21 Nov 2014 08:47:31 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.07,426,1413270000\"; d=\"scan'208\";a=\"640843677\"", "From": "Jingjing Wu <jingjing.wu@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 21 Nov 2014 08:46:49 +0800", "Message-Id": "<1416530816-2159-16-git-send-email-jingjing.wu@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1416530816-2159-1-git-send-email-jingjing.wu@intel.com>", "References": "<1414654006-7472-1-git-send-email-jingjing.wu@intel.com>\n\t<1416530816-2159-1-git-send-email-jingjing.wu@intel.com>", "Subject": "[dpdk-dev] [PATCH v6 15/22] i40e: implement operations to get fdir\n\tinfo", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "implement operation to get flow director information in i40e pmd driver, includes\n - mode\n - supported flow types\n - table space\n - flexible payload size and granularity\n - configured flexible payload and mask information\n\nSigned-off-by: jingjing.wu <jingjing.wu@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.h | 1 +\n lib/librte_pmd_i40e/i40e_fdir.c | 145 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 146 insertions(+)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h\nindex fbce86a..f3ef65f 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.h\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.h\n@@ -67,6 +67,7 @@ enum i40e_flxpld_layer_idx {\n #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */\n #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */\n #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */\n+#define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */\n \n /* i40e flags */\n #define I40E_FLAG_RSS (1ULL << 0)\ndiff --git a/lib/librte_pmd_i40e/i40e_fdir.c b/lib/librte_pmd_i40e/i40e_fdir.c\nindex 93aa8a1..2edb3a6 100644\n--- a/lib/librte_pmd_i40e/i40e_fdir.c\n+++ b/lib/librte_pmd_i40e/i40e_fdir.c\n@@ -80,8 +80,34 @@\n #define I40E_COUNTER_PF 2\n /* Statistic counter index for one pf */\n #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)\n+#define I40E_MAX_FLX_SOURCE_OFF 480\n #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50\n \n+#define NONUSE_FLX_PIT_DEST_OFF 63\n+#define NONUSE_FLX_PIT_FSIZE 1\n+#define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \\\n+\t(((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \\\n+\t\tI40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \\\n+\t(((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \\\n+\t\t\tI40E_PRTQF_FLX_PIT_FSIZE_MASK) | \\\n+\t((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \\\n+\t\t\tI40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \\\n+\t\t\tI40E_PRTQF_FLX_PIT_DEST_OFF_MASK))\n+\n+#define I40E_FDIR_FLOW_TYPES ( \\\n+\t(1 << RTE_ETH_FLOW_TYPE_UDPV4) | \\\n+\t(1 << RTE_ETH_FLOW_TYPE_TCPV4) | \\\n+\t(1 << RTE_ETH_FLOW_TYPE_SCTPV4) | \\\n+\t(1 << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \\\n+\t(1 << RTE_ETH_FLOW_TYPE_FRAG_IPV4) | \\\n+\t(1 << RTE_ETH_FLOW_TYPE_UDPV6) | \\\n+\t(1 << RTE_ETH_FLOW_TYPE_TCPV6) | \\\n+\t(1 << RTE_ETH_FLOW_TYPE_SCTPV6) | \\\n+\t(1 << RTE_ETH_FLOW_TYPE_IPV6_OTHER) | \\\n+\t(1 << RTE_ETH_FLOW_TYPE_FRAG_IPV6))\n+\n+#define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))\n+\n static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);\n static int i40e_fdir_construct_pkt(struct i40e_pf *pf,\n \t\t\t\t const struct rte_eth_fdir_input *fdir_input,\n@@ -94,6 +120,8 @@ static int i40e_fdir_filter_programming(struct i40e_pf *pf,\n \t\t\tconst struct rte_eth_fdir_filter *filter,\n \t\t\tbool add);\n static int i40e_fdir_flush(struct rte_eth_dev *dev);\n+static void i40e_fdir_info_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_fdir_info *fdir);\n \n static int\n i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)\n@@ -861,6 +889,120 @@ i40e_fdir_flush(struct rte_eth_dev *dev)\n \treturn 0;\n }\n \n+static inline void\n+i40e_fdir_info_get_flex_set(struct i40e_pf *pf,\n+\t\t\tstruct rte_eth_flex_payload_cfg *flex_set,\n+\t\t\tuint16_t *num)\n+{\n+\tstruct i40e_fdir_flex_pit *flex_pit;\n+\tstruct rte_eth_flex_payload_cfg *ptr = flex_set;\n+\tuint16_t src, dst, size, j, k;\n+\tuint8_t i, layer_idx;\n+\n+\tfor (layer_idx = I40E_FLXPLD_L2_IDX;\n+\t layer_idx <= I40E_FLXPLD_L4_IDX;\n+\t layer_idx++) {\n+\t\tif (layer_idx == I40E_FLXPLD_L2_IDX)\n+\t\t\tptr->type = RTE_ETH_L2_PAYLOAD;\n+\t\telse if (layer_idx == I40E_FLXPLD_L3_IDX)\n+\t\t\tptr->type = RTE_ETH_L3_PAYLOAD;\n+\t\telse if (layer_idx == I40E_FLXPLD_L4_IDX)\n+\t\t\tptr->type = RTE_ETH_L4_PAYLOAD;\n+\n+\t\tfor (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {\n+\t\t\tflex_pit = &pf->fdir.flex_set[layer_idx *\n+\t\t\t\tI40E_MAX_FLXPLD_FIED + i];\n+\t\t\tif (flex_pit->size == 0)\n+\t\t\t\tcontinue;\n+\t\t\tsrc = flex_pit->src_offset * sizeof(uint16_t);\n+\t\t\tdst = flex_pit->dst_offset * sizeof(uint16_t);\n+\t\t\tsize = flex_pit->size * sizeof(uint16_t);\n+\t\t\tfor (j = src, k = dst; j < src + size; j++, k++)\n+\t\t\t\tptr->src_offset[k] = j;\n+\t\t}\n+\t\t(*num)++;\n+\t\tptr++;\n+\t}\n+}\n+\n+static inline void\n+i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,\n+\t\t\tstruct rte_eth_fdir_flex_mask *flex_mask,\n+\t\t\tuint16_t *num)\n+{\n+\tstruct i40e_fdir_flex_mask *mask;\n+\tstruct rte_eth_fdir_flex_mask *ptr = flex_mask;\n+\tenum rte_eth_flow_type flow_type;\n+\tuint8_t i, j;\n+\tuint16_t off_bytes, mask_tmp;\n+\n+\tfor (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;\n+\t i <= I40E_FILTER_PCTYPE_FRAG_IPV6;\n+\t i++) {\n+\t\tmask = &pf->fdir.flex_mask[i];\n+\t\tif (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))\n+\t\t\tcontinue;\n+\t\tflow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);\n+\t\tfor (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {\n+\t\t\tif (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {\n+\t\t\t\tptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;\n+\t\t\t\tptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;\n+\t\t\t} else {\n+\t\t\t\tptr->mask[j * sizeof(uint16_t)] = 0x0;\n+\t\t\t\tptr->mask[j * sizeof(uint16_t) + 1] = 0x0;\n+\t\t\t}\n+\t\t}\n+\t\tfor (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {\n+\t\t\toff_bytes = mask->bitmask[j].offset * sizeof(uint16_t);\n+\t\t\tmask_tmp = ~mask->bitmask[j].mask;\n+\t\t\tptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);\n+\t\t\tptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);\n+\t\t}\n+\t\tptr->flow_type = flow_type;\n+\t\tptr++;\n+\t\t(*num)++;\n+\t}\n+}\n+\n+/*\n+ * i40e_fdir_info_get - get information of Flow Director\n+ * @pf: ethernet device to get info from\n+ * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with\n+ * the flow director information.\n+ */\n+static void\n+i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tuint16_t num_flex_set = 0;\n+\tuint16_t num_flex_mask = 0;\n+\n+\tfdir->mode = (pf->flags & I40E_FLAG_FDIR) ?\n+\t\t\tRTE_FDIR_MODE_PERFECT : RTE_FDIR_MODE_NONE;\n+\tfdir->guarant_spc =\n+\t\t(uint32_t)hw->func_caps.fd_filters_guaranteed;\n+\tfdir->best_spc =\n+\t\t(uint32_t)hw->func_caps.fd_filters_best_effort;\n+\tfdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;\n+\tfdir->flow_types_mask[0] = I40E_FDIR_FLOW_TYPES;\n+\tfdir->flex_payload_unit = sizeof(uint16_t);\n+\tfdir->flex_bitmask_unit = sizeof(uint16_t);\n+\tfdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;\n+\tfdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;\n+\tfdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;\n+\n+\ti40e_fdir_info_get_flex_set(pf,\n+\t\t\t\tfdir->flex_conf.flex_set,\n+\t\t\t\t&num_flex_set);\n+\ti40e_fdir_info_get_flex_mask(pf,\n+\t\t\t\tfdir->flex_conf.flex_mask,\n+\t\t\t\t&num_flex_mask);\n+\n+\tfdir->flex_conf.nb_payloads = num_flex_set;\n+\tfdir->flex_conf.nb_flexmasks = num_flex_mask;\n+}\n+\n /*\n * i40e_fdir_ctrl_func - deal with all operations on flow director.\n * @pf: board private structure\n@@ -898,6 +1040,9 @@ i40e_fdir_ctrl_func(struct rte_eth_dev *dev,\n \tcase RTE_ETH_FILTER_FLUSH:\n \t\tret = i40e_fdir_flush(dev);\n \t\tbreak;\n+\tcase RTE_ETH_FILTER_INFO:\n+\t\ti40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);\n+\t\tbreak;\n \tdefault:\n \t\tPMD_DRV_LOG(ERR, \"unknown operation %u.\", filter_op);\n \t\tret = -EINVAL;\n", "prefixes": [ "dpdk-dev", "v6", "15/22" ] }