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GET /api/patches/14243/?format=api
{ "id": 14243, "url": "https://patches.dpdk.org/api/patches/14243/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1466666557-14312-10-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1466666557-14312-10-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1466666557-14312-10-git-send-email-beilei.xing@intel.com", "date": "2016-06-23T07:22:17", "name": "[dpdk-dev,v4,09/29] ixgbe/base: add link MAC setup for X550a SFP+", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d673f1809b7d80c54521918263a42fed58a31aa2", "submitter": { "id": 410, "url": "https://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 10, "url": "https://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1466666557-14312-10-git-send-email-beilei.xing@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/14243/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/14243/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id C97F4C46C;\n\tThu, 23 Jun 2016 09:23:09 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id 03886C438\n\tfor <dev@dpdk.org>; Thu, 23 Jun 2016 09:23:05 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga103.fm.intel.com with ESMTP; 23 Jun 2016 00:23:05 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 23 Jun 2016 00:23:05 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id u5N7N25S013780;\n\tThu, 23 Jun 2016 15:23:02 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid u5N7MxWu014410; Thu, 23 Jun 2016 15:23:01 +0800", "(from beileixi@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u5N7MxfJ014406; \n\tThu, 23 Jun 2016 15:22:59 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.26,509,1459839600\"; d=\"scan'208\";a=\"981673698\"", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "wenzhuo.lu@intel.com", "Cc": "dev@dpdk.org, Beilei Xing <beilei.xing@intel.com>", "Date": "Thu, 23 Jun 2016 15:22:17 +0800", "Message-Id": "<1466666557-14312-10-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1466666557-14312-1-git-send-email-beilei.xing@intel.com>", "References": "<1465977220-3970-1-git-send-email-beilei.xing@intel.com>\n\t<1466666557-14312-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 09/29] ixgbe/base: add link MAC setup for\n\tX550a SFP+", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch updates ixgbe_setup_mac_link_sfp_x550a for X550 SFP+.\nixgbe_set_lan_id_multi_port_pcie has been updated to set the MAC\ninstance(0/1) which is needed when configuring the external PHY,\nsince X550a has two instances of MGPK. The MAC instance is read\nfrom the EEPROM.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_common.c | 13 +++++-\n drivers/net/ixgbe/base/ixgbe_phy.h | 3 ++\n drivers/net/ixgbe/base/ixgbe_type.h | 8 ++++\n drivers/net/ixgbe/base/ixgbe_x550.c | 85 ++++++++++++++++++++++++++---------\n 4 files changed, 86 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_common.c b/drivers/net/ixgbe/base/ixgbe_common.c\nindex ec61408..82a8416 100644\n--- a/drivers/net/ixgbe/base/ixgbe_common.c\n+++ b/drivers/net/ixgbe/base/ixgbe_common.c\n@@ -1020,13 +1020,15 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)\n * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices\n * @hw: pointer to the HW structure\n *\n- * Determines the LAN function id by reading memory-mapped registers\n- * and swaps the port value if requested.\n+ * Determines the LAN function id by reading memory-mapped registers and swaps\n+ * the port value if requested, and set MAC instance for devices that share\n+ * CS4227.\n **/\n void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)\n {\n \tstruct ixgbe_bus_info *bus = &hw->bus;\n \tu32 reg;\n+\tu16 ee_ctrl_4;\n \n \tDEBUGFUNC(\"ixgbe_set_lan_id_multi_port_pcie\");\n \n@@ -1038,6 +1040,13 @@ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)\n \treg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));\n \tif (reg & IXGBE_FACTPS_LFS)\n \t\tbus->func ^= 0x1;\n+\n+\t/* Get MAC instance from EEPROM for configuring CS4227 */\n+\tif (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {\n+\t\thw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);\n+\t\tbus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>\n+\t\t\tIXGBE_EE_CTRL_4_INST_ID_SHIFT;\n+\t}\n }\n \n /**\ndiff --git a/drivers/net/ixgbe/base/ixgbe_phy.h b/drivers/net/ixgbe/base/ixgbe_phy.h\nindex 1a5affe..281f9fa 100644\n--- a/drivers/net/ixgbe/base/ixgbe_phy.h\n+++ b/drivers/net/ixgbe/base/ixgbe_phy.h\n@@ -89,8 +89,11 @@ POSSIBILITY OF SUCH DAMAGE.\n \n #define IXGBE_CS4227\t\t\t0xBE\t/* CS4227 address */\n #define IXGBE_CS4227_GLOBAL_ID_LSB\t0\n+#define IXGBE_CS4227_GLOBAL_ID_MSB\t1\n #define IXGBE_CS4227_SCRATCH\t\t2\n #define IXGBE_CS4227_GLOBAL_ID_VALUE\t0x03E5\n+#define IXGBE_CS4223_PHY_ID\t\t0x7003/* Quad port */\n+#define IXGBE_CS4227_PHY_ID\t\t0x3003/* Dual port */\n #define IXGBE_CS4227_RESET_PENDING\t0x1357\n #define IXGBE_CS4227_RESET_COMPLETE\t0x5AA5\n #define IXGBE_CS4227_RETRIES\t\t15\ndiff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h\nindex 7bd6f2c..0a35891 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type.h\n@@ -1472,6 +1472,7 @@ struct ixgbe_dmac_config {\n #define IXGBE_CORECTL_WRITE_CMD\t\t0x00010000\n \n /* Device Type definitions for new protocol MDIO commands */\n+#define IXGBE_MDIO_ZERO_DEV_TYPE\t\t0x0\n #define IXGBE_MDIO_PMA_PMD_DEV_TYPE\t\t0x1\n #define IXGBE_MDIO_PCS_DEV_TYPE\t\t\t0x3\n #define IXGBE_MDIO_PHY_XS_DEV_TYPE\t\t0x4\n@@ -2247,6 +2248,9 @@ enum {\n #define IXGBE_PBANUM_PTR_GUARD\t\t0xFAFA\n #define IXGBE_EEPROM_CHECKSUM\t\t0x3F\n #define IXGBE_EEPROM_SUM\t\t0xBABA\n+#define IXGBE_EEPROM_CTRL_4\t\t0x45\n+#define IXGBE_EE_CTRL_4_INST_ID\t\t0x10\n+#define IXGBE_EE_CTRL_4_INST_ID_SHIFT\t4\n #define IXGBE_PCIE_ANALOG_PTR\t\t0x03\n #define IXGBE_ATLAS0_CONFIG_PTR\t\t0x04\n #define IXGBE_PHY_PTR\t\t\t0x04\n@@ -3630,6 +3634,7 @@ struct ixgbe_bus_info {\n \n \tu16 func;\n \tu16 lan_id;\n+\tu16 instance_id;\n };\n \n /* Flow control parameters */\n@@ -4130,5 +4135,8 @@ struct ixgbe_hw {\n \n #define IXGBE_NW_MNG_IF_SEL\t\t0x00011178\n #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24)\n+#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3\n+#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD\t\\\n+\t\t(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)\n \n #endif /* _IXGBE_TYPE_H_ */\ndiff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c\nindex 1834549..f129e8c 100644\n--- a/drivers/net/ixgbe/base/ixgbe_x550.c\n+++ b/drivers/net/ixgbe/base/ixgbe_x550.c\n@@ -1551,7 +1551,8 @@ void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)\n \t\tmac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;\n \t\tmac->ops.set_rate_select_speed =\n \t\t\t\t\tixgbe_set_soft_rate_select_speed;\n-\t\tif (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)\n+\t\tif ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||\n+\t\t (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))\n \t\t\tmac->ops.setup_mac_link =\n \t\t\t\tixgbe_setup_mac_link_sfp_x550a;\n \t\telse\n@@ -2207,8 +2208,9 @@ s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,\n \t\t\t\t bool autoneg_wait_to_complete)\n {\n \ts32 ret_val;\n-\tu32 reg_val;\n+\tu16 reg_phy_ext;\n \tbool setup_linear = false;\n+\tu32 reg_slice, reg_phy_int, slice_offset;\n \n \tUNREFERENCED_1PARAMETER(autoneg_wait_to_complete);\n \n@@ -2224,32 +2226,73 @@ s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,\n \tif (ret_val != IXGBE_SUCCESS)\n \t\treturn ret_val;\n \n-\t/* Configure internal PHY for native SFI */\n-\tret_val = hw->mac.ops.read_iosf_sb_reg(hw,\n-\t\t IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),\n-\t\t IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n+\tif (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {\n+\t\t/* Configure internal PHY for native SFI */\n+\t\tret_val = hw->mac.ops.read_iosf_sb_reg(hw,\n+\t\t\t IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),\n+\t\t\t IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);\n \n-\tif (ret_val != IXGBE_SUCCESS)\n-\t\treturn ret_val;\n+\t\tif (ret_val != IXGBE_SUCCESS)\n+\t\t\treturn ret_val;\n+\n+\t\tif (setup_linear) {\n+\t\t\treg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;\n+\t\t\treg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;\n+\t\t} else {\n+\t\t\treg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;\n+\t\t\treg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;\n+\t\t}\n+\n+\t\tret_val = hw->mac.ops.write_iosf_sb_reg(hw,\n+\t\t\t\tIXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),\n+\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);\n \n-\tif (setup_linear) {\n-\t\treg_val &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;\n-\t\treg_val |= IXGBE_KRM_AN_CNTL_8_LINEAR;\n+\t\tif (ret_val != IXGBE_SUCCESS)\n+\t\t\treturn ret_val;\n+\n+\t\t/* Setup XFI/SFI internal link. */\n+\t\tret_val = ixgbe_setup_ixfi_x550em(hw, &speed);\n \t} else {\n-\t\treg_val |= IXGBE_KRM_AN_CNTL_8_LIMITING;\n-\t\treg_val &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;\n-\t}\n+\t\t/* Configure internal PHY for KR/KX. */\n+\t\tixgbe_setup_kr_speed_x550em(hw, speed);\n \n-\tret_val = hw->mac.ops.write_iosf_sb_reg(hw,\n-\t\t\tIXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),\n-\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n+\t\t/* Get CS4227 MDIO address */\n+\t\thw->phy.addr =\n+\t\t\t(hw->phy.nw_mng_if_sel &\n+\t\t\t IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD)\n+\t\t\t>> IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;\n \n-\tif (ret_val != IXGBE_SUCCESS)\n-\t\treturn ret_val;\n+\t\tif (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {\n+\t\t\t/* Find Address */\n+\t\t\tDEBUGOUT(\"Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\\n\");\n+\t\t\treturn IXGBE_ERR_PHY_ADDR_INVALID;\n+\t\t}\n+\n+\t\t/* Get external PHY device id */\n+\t\tret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,\n+\t\t\t\t IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);\n \n-\t/* Setup XFI/SFI internal link. */\n-\tret_val = ixgbe_setup_ixfi_x550em(hw, &speed);\n+\t\tif (ret_val != IXGBE_SUCCESS)\n+\t\t\treturn ret_val;\n \n+\t\t/* When configuring quad port CS4223, the MAC instance is part\n+\t\t * of the slice offset.\n+\t\t */\n+\t\tif (reg_phy_ext == IXGBE_CS4223_PHY_ID)\n+\t\t\tslice_offset = (hw->bus.lan_id +\n+\t\t\t\t\t(hw->bus.instance_id << 1)) << 12;\n+\t\telse\n+\t\t\tslice_offset = hw->bus.lan_id << 12;\n+\n+\t\t/* Configure CS4227/CS4223 LINE side to proper mode. */\n+\t\treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;\n+\t\tif (setup_linear)\n+\t\t\treg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;\n+\t\telse\n+\t\t\treg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;\n+\t\tret_val = hw->phy.ops.write_reg(hw, reg_slice,\n+\t\t\t\t\tIXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);\n+\t}\n \treturn ret_val;\n }\n \n", "prefixes": [ "dpdk-dev", "v4", "09/29" ] }