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GET /api/patches/14190/?format=api
{ "id": 14190, "url": "https://patches.dpdk.org/api/patches/14190/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1466586355-30777-10-git-send-email-nelio.laranjeiro@6wind.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1466586355-30777-10-git-send-email-nelio.laranjeiro@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1466586355-30777-10-git-send-email-nelio.laranjeiro@6wind.com", "date": "2016-06-22T09:05:39", "name": "[dpdk-dev,v4,09/25] mlx5: update prerequisites for upcoming enhancements", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8084f596ed6ae3e308413020d47e44413b4b1bdb", "submitter": { "id": 243, "url": "https://patches.dpdk.org/api/people/243/?format=api", "name": "Nélio Laranjeiro", "email": "nelio.laranjeiro@6wind.com" }, "delegate": { "id": 10, "url": "https://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1466586355-30777-10-git-send-email-nelio.laranjeiro@6wind.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/14190/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/14190/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id C0429C3F4;\n\tWed, 22 Jun 2016 11:06:35 +0200 (CEST)", "from mail-lb0-f178.google.com (mail-lb0-f178.google.com\n\t[209.85.217.178]) by dpdk.org (Postfix) with ESMTP id 03C49C3A2\n\tfor <dev@dpdk.org>; Wed, 22 Jun 2016 11:06:19 +0200 (CEST)", "by mail-lb0-f178.google.com with SMTP id oe3so18516795lbb.1\n\tfor <dev@dpdk.org>; Wed, 22 Jun 2016 02:06:18 -0700 (PDT)", "from ping.vm.6wind.com (guy78-3-82-239-227-177.fbx.proxad.net.\n\t[82.239.227.177]) by smtp.gmail.com with ESMTPSA id\n\tz5sm7019178wme.5.2016.06.22.02.06.17\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tWed, 22 Jun 2016 02:06:17 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=6wind-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=zMIsH8xHO9rAPXVOLhOHzmcpqnaBn3fRNcVoclmPhNg=;\n\tb=FxHHLlNU3wuN5AaOr0GUU1SfLVnX8Njir8PZCbWs+ejCFP9TYnZTVLuGGllovIAzAM\n\tCzzK7lbPxIufgtTe1hmGvtSJrX+dKsfvMydCsK41Nbh9P2iT+JRb8cXPQ2y2cP3C6ap4\n\tez9GixtmvgiLSIH42u5EIq3SNSa0t2ooNcgCfUbYos/twu0yb+ki/5gNmkgIiE3yHbRE\n\tQXuV0FxiY9EZs95miMmwZGlI7MBqx/UqXgleCnhcwOcFoEoDdKqx2I6ZyKPYWqtrg6Dg\n\tWdO58XCKHCP69cOdWQyf0upfsJ9NmzM5pZW2ZnxEHf3bXeRZsXR1b7EQzCufLnpvaoI3\n\ttAgA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=zMIsH8xHO9rAPXVOLhOHzmcpqnaBn3fRNcVoclmPhNg=;\n\tb=SSdXKYr4l+wsYq56MA2m2B3BvnejnI2j2mmEpO//wzBeOrvmgWjfMRTTtDtKXTdCXO\n\tVzl9v4CHVW3CKZzx78brmwbvu3DH8VPVkFBoBdX1Pjt+6YBu4hex0iy9y+Ey6u7AdafG\n\t1NEISVL3NGtpXqOMg1IQHTyyoz5wujVCq14tiDO+osqi2dvPtNrOaMcR/K9gC5lAvi4x\n\tbtCcnM7IF7745uPk3axQIwsjD2iNEDxGb+JHJcoW3OPa+vGCmmVmtBhIe5rB62IMd2c3\n\tt07vF77Ts70zhKZ2ozkJFhX8r1vTMWrzd2PSDqiePRqS7NqU47dTnq1iXREWZZ5/Kbl1\n\tpysQ==", "X-Gm-Message-State": "ALyK8tLmyA5VpMbONyXh5Uuj957Ki7hRaPD60h7jv2ylpArsRJtIJ1jHYT7BIEL4fjFq/bMS", "X-Received": "by 10.194.242.163 with SMTP id wr3mr23629946wjc.1.1466586378345; \n\tWed, 22 Jun 2016 02:06:18 -0700 (PDT)", "From": "Nelio Laranjeiro <nelio.laranjeiro@6wind.com>", "To": "dev@dpdk.org", "Cc": "Ferruh Yigit <ferruh.yigit@intel.com>,\n\tAdrien Mazarguil <adrien.mazarguil@6wind.com>", "Date": "Wed, 22 Jun 2016 11:05:39 +0200", "Message-Id": "<1466586355-30777-10-git-send-email-nelio.laranjeiro@6wind.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1466586355-30777-1-git-send-email-nelio.laranjeiro@6wind.com>", "References": "<1466493818-1877-1-git-send-email-nelio.laranjeiro@6wind.com>\n\t<1466586355-30777-1-git-send-email-nelio.laranjeiro@6wind.com>", "Subject": "[dpdk-dev] [PATCH v4 09/25] mlx5: update prerequisites for upcoming\n\tenhancements", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The latest version of Mellanox OFED exposes hardware definitions necessary\nto implement data path operation bypassing Verbs. Update the minimum\nversion requirement to MLNX_OFED >= 3.3 and clean up compatibility checks\nfor previous releases.\n\nSigned-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>\nSigned-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>\n---\n doc/guides/nics/mlx5.rst | 44 +++---------------------------------------\n drivers/net/mlx5/Makefile | 39 ++++++++-----------------------------\n drivers/net/mlx5/mlx5.c | 23 ----------------------\n drivers/net/mlx5/mlx5.h | 5 +++++\n drivers/net/mlx5/mlx5_defs.h | 9 ---------\n drivers/net/mlx5/mlx5_fdir.c | 10 ----------\n drivers/net/mlx5/mlx5_rxmode.c | 8 --------\n drivers/net/mlx5/mlx5_rxq.c | 30 ----------------------------\n drivers/net/mlx5/mlx5_rxtx.c | 4 ----\n drivers/net/mlx5/mlx5_rxtx.h | 8 --------\n drivers/net/mlx5/mlx5_txq.c | 2 --\n drivers/net/mlx5/mlx5_vlan.c | 3 ---\n 12 files changed, 16 insertions(+), 169 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 77fa957..3a07928 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -125,16 +125,6 @@ These options can be modified in the ``.config`` file.\n Environment variables\n ~~~~~~~~~~~~~~~~~~~~~\n \n-- ``MLX5_ENABLE_CQE_COMPRESSION``\n-\n- A nonzero value lets ConnectX-4 return smaller completion entries to\n- improve performance when PCI backpressure is detected. It is most useful\n- for scenarios involving heavy traffic on many queues.\n-\n- Since the additional software logic necessary to handle this mode can\n- lower performance when there is no backpressure, it is not enabled by\n- default.\n-\n - ``MLX5_PMD_ENABLE_PADDING``\n \n Enables HW packet padding in PCI bus transactions.\n@@ -211,40 +201,12 @@ DPDK and must be installed separately:\n \n Currently supported by DPDK:\n \n-- Mellanox OFED **3.1-1.0.3**, **3.1-1.5.7.1** or **3.2-2.0.0.0** depending\n- on usage.\n-\n- The following features are supported with version **3.1-1.5.7.1** and\n- above only:\n-\n- - IPv6, UPDv6, TCPv6 RSS.\n- - RX checksum offloads.\n- - IBM POWER8.\n-\n- The following features are supported with version **3.2-2.0.0.0** and\n- above only:\n-\n- - Flow director.\n- - RX VLAN stripping.\n- - TX VLAN insertion.\n- - RX CRC stripping configuration.\n+- Mellanox OFED **3.3-1.0.0.0**.\n \n - Minimum firmware version:\n \n- With MLNX_OFED **3.1-1.0.3**:\n-\n- - ConnectX-4: **12.12.1240**\n- - ConnectX-4 Lx: **14.12.1100**\n-\n- With MLNX_OFED **3.1-1.5.7.1**:\n-\n- - ConnectX-4: **12.13.0144**\n- - ConnectX-4 Lx: **14.13.0144**\n-\n- With MLNX_OFED **3.2-2.0.0.0**:\n-\n- - ConnectX-4: **12.14.2036**\n- - ConnectX-4 Lx: **14.14.2036**\n+ - ConnectX-4: **12.16.1006**\n+ - ConnectX-4 Lx: **14.16.1006**\n \n Getting Mellanox OFED\n ~~~~~~~~~~~~~~~~~~~~~\ndiff --git a/drivers/net/mlx5/Makefile b/drivers/net/mlx5/Makefile\nindex 289c85e..dc99797 100644\n--- a/drivers/net/mlx5/Makefile\n+++ b/drivers/net/mlx5/Makefile\n@@ -106,42 +106,19 @@ mlx5_autoconf.h.new: FORCE\n mlx5_autoconf.h.new: $(RTE_SDK)/scripts/auto-config-h.sh\n \t$Q $(RM) -f -- '$@'\n \t$Q sh -- '$<' '$@' \\\n-\t\tHAVE_EXP_QUERY_DEVICE \\\n-\t\tinfiniband/verbs.h \\\n-\t\ttype 'struct ibv_exp_device_attr' $(AUTOCONF_OUTPUT)\n-\t$Q sh -- '$<' '$@' \\\n-\t\tHAVE_FLOW_SPEC_IPV6 \\\n-\t\tinfiniband/verbs.h \\\n-\t\ttype 'struct ibv_exp_flow_spec_ipv6' $(AUTOCONF_OUTPUT)\n-\t$Q sh -- '$<' '$@' \\\n-\t\tHAVE_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR \\\n-\t\tinfiniband/verbs.h \\\n-\t\tenum IBV_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR \\\n-\t\t$(AUTOCONF_OUTPUT)\n-\t$Q sh -- '$<' '$@' \\\n-\t\tHAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS \\\n-\t\tinfiniband/verbs.h \\\n-\t\tenum IBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS \\\n-\t\t$(AUTOCONF_OUTPUT)\n-\t$Q sh -- '$<' '$@' \\\n-\t\tHAVE_EXP_CQ_RX_TCP_PACKET \\\n+\t\tHAVE_VERBS_VLAN_INSERTION \\\n \t\tinfiniband/verbs.h \\\n-\t\tenum IBV_EXP_CQ_RX_TCP_PACKET \\\n+\t\tenum IBV_EXP_RECEIVE_WQ_CVLAN_INSERTION \\\n \t\t$(AUTOCONF_OUTPUT)\n \t$Q sh -- '$<' '$@' \\\n-\t\tHAVE_VERBS_FCS \\\n-\t\tinfiniband/verbs.h \\\n-\t\tenum IBV_EXP_CREATE_WQ_FLAG_SCATTER_FCS \\\n+\t\tHAVE_VERBS_IBV_EXP_CQ_COMPRESSED_CQE \\\n+\t\tinfiniband/verbs_exp.h \\\n+\t\tenum IBV_EXP_CQ_COMPRESSED_CQE \\\n \t\t$(AUTOCONF_OUTPUT)\n \t$Q sh -- '$<' '$@' \\\n-\t\tHAVE_VERBS_RX_END_PADDING \\\n-\t\tinfiniband/verbs.h \\\n-\t\tenum IBV_EXP_CREATE_WQ_FLAG_RX_END_PADDING \\\n-\t\t$(AUTOCONF_OUTPUT)\n-\t$Q sh -- '$<' '$@' \\\n-\t\tHAVE_VERBS_VLAN_INSERTION \\\n-\t\tinfiniband/verbs.h \\\n-\t\tenum IBV_EXP_RECEIVE_WQ_CVLAN_INSERTION \\\n+\t\tHAVE_VERBS_MLX5_ETH_VLAN_INLINE_HEADER_SIZE \\\n+\t\tinfiniband/mlx5_hw.h \\\n+\t\tenum MLX5_ETH_VLAN_INLINE_HEADER_SIZE \\\n \t\t$(AUTOCONF_OUTPUT)\n \n # Create mlx5_autoconf.h or update it in case it differs from the new one.\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 27a7a30..3f45d84 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -195,17 +195,13 @@ static const struct eth_dev_ops mlx5_dev_ops = {\n \t.mac_addr_add = mlx5_mac_addr_add,\n \t.mac_addr_set = mlx5_mac_addr_set,\n \t.mtu_set = mlx5_dev_set_mtu,\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n \t.vlan_strip_queue_set = mlx5_vlan_strip_queue_set,\n \t.vlan_offload_set = mlx5_vlan_offload_set,\n-#endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n \t.reta_update = mlx5_dev_rss_reta_update,\n \t.reta_query = mlx5_dev_rss_reta_query,\n \t.rss_hash_update = mlx5_rss_hash_update,\n \t.rss_hash_conf_get = mlx5_rss_hash_conf_get,\n-#ifdef MLX5_FDIR_SUPPORT\n \t.filter_ctrl = mlx5_dev_filter_ctrl,\n-#endif /* MLX5_FDIR_SUPPORT */\n };\n \n static struct {\n@@ -352,24 +348,16 @@ mlx5_pci_devinit(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\tstruct ibv_pd *pd = NULL;\n \t\tstruct priv *priv = NULL;\n \t\tstruct rte_eth_dev *eth_dev;\n-#ifdef HAVE_EXP_QUERY_DEVICE\n \t\tstruct ibv_exp_device_attr exp_device_attr;\n-#endif /* HAVE_EXP_QUERY_DEVICE */\n \t\tstruct ether_addr mac;\n \t\tuint16_t num_vfs = 0;\n \n-#ifdef HAVE_EXP_QUERY_DEVICE\n \t\texp_device_attr.comp_mask =\n \t\t\tIBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS |\n \t\t\tIBV_EXP_DEVICE_ATTR_RX_HASH |\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n \t\t\tIBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS |\n-#endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n-#ifdef HAVE_VERBS_RX_END_PADDING\n \t\t\tIBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN |\n-#endif /* HAVE_VERBS_RX_END_PADDING */\n \t\t\t0;\n-#endif /* HAVE_EXP_QUERY_DEVICE */\n \n \t\tDEBUG(\"using port %u (%08\" PRIx32 \")\", port, test);\n \n@@ -420,7 +408,6 @@ mlx5_pci_devinit(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\tpriv->port = port;\n \t\tpriv->pd = pd;\n \t\tpriv->mtu = ETHER_MTU;\n-#ifdef HAVE_EXP_QUERY_DEVICE\n \t\tif (ibv_exp_query_device(ctx, &exp_device_attr)) {\n \t\t\tERROR(\"ibv_exp_query_device() failed\");\n \t\t\tgoto port_error;\n@@ -446,30 +433,20 @@ mlx5_pci_devinit(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\t\tpriv->ind_table_max_size = RSS_INDIRECTION_TABLE_SIZE;\n \t\tDEBUG(\"maximum RX indirection table size is %u\",\n \t\t priv->ind_table_max_size);\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n \t\tpriv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap &\n \t\t\t\t\t IBV_EXP_RECEIVE_WQ_CVLAN_STRIP);\n-#endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n \t\tDEBUG(\"VLAN stripping is %ssupported\",\n \t\t (priv->hw_vlan_strip ? \"\" : \"not \"));\n \n-#ifdef HAVE_VERBS_FCS\n \t\tpriv->hw_fcs_strip = !!(exp_device_attr.exp_device_cap_flags &\n \t\t\t\t\tIBV_EXP_DEVICE_SCATTER_FCS);\n-#endif /* HAVE_VERBS_FCS */\n \t\tDEBUG(\"FCS stripping configuration is %ssupported\",\n \t\t (priv->hw_fcs_strip ? \"\" : \"not \"));\n \n-#ifdef HAVE_VERBS_RX_END_PADDING\n \t\tpriv->hw_padding = !!exp_device_attr.rx_pad_end_addr_align;\n-#endif /* HAVE_VERBS_RX_END_PADDING */\n \t\tDEBUG(\"hardware RX end alignment padding is %ssupported\",\n \t\t (priv->hw_padding ? \"\" : \"not \"));\n \n-#else /* HAVE_EXP_QUERY_DEVICE */\n-\t\tpriv->ind_table_max_size = RSS_INDIRECTION_TABLE_SIZE;\n-#endif /* HAVE_EXP_QUERY_DEVICE */\n-\n \t\tpriv_get_num_vfs(priv, &num_vfs);\n \t\tpriv->sriov = (num_vfs || sriov);\n \t\tpriv->mps = mps;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex cbcb8b9..935e1b0 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -68,6 +68,11 @@\n #include \"mlx5_autoconf.h\"\n #include \"mlx5_defs.h\"\n \n+#if !defined(HAVE_VERBS_IBV_EXP_CQ_COMPRESSED_CQE) || \\\n+\t!defined(HAVE_VERBS_MLX5_ETH_VLAN_INLINE_HEADER_SIZE)\n+#error Mellanox OFED >= 3.3 is required, please refer to the documentation.\n+#endif\n+\n enum {\n \tPCI_VENDOR_ID_MELLANOX = 0x15b3,\n };\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 9a19835..8d2ec7a 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -76,13 +76,4 @@\n /* Alarm timeout. */\n #define MLX5_ALARM_TIMEOUT_US 100000\n \n-/*\n- * Extended flow priorities necessary to support flow director are available\n- * since MLNX_OFED 3.2. Considering this version adds support for VLAN\n- * offloads as well, their availability means flow director can be used.\n- */\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n-#define MLX5_FDIR_SUPPORT 1\n-#endif\n-\n #endif /* RTE_PMD_MLX5_DEFS_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_fdir.c b/drivers/net/mlx5/mlx5_fdir.c\nindex e3b97ba..1850218 100644\n--- a/drivers/net/mlx5/mlx5_fdir.c\n+++ b/drivers/net/mlx5/mlx5_fdir.c\n@@ -122,7 +122,6 @@ fdir_filter_to_flow_desc(const struct rte_eth_fdir_filter *fdir_filter,\n \tcase RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:\n \t\tdesc->type = HASH_RXQ_IPV4;\n \t\tbreak;\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \tcase RTE_ETH_FLOW_NONFRAG_IPV6_UDP:\n \t\tdesc->type = HASH_RXQ_UDPV6;\n \t\tbreak;\n@@ -132,7 +131,6 @@ fdir_filter_to_flow_desc(const struct rte_eth_fdir_filter *fdir_filter,\n \tcase RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:\n \t\tdesc->type = HASH_RXQ_IPV6;\n \t\tbreak;\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \tdefault:\n \t\tbreak;\n \t}\n@@ -147,7 +145,6 @@ fdir_filter_to_flow_desc(const struct rte_eth_fdir_filter *fdir_filter,\n \t\tdesc->src_ip[0] = fdir_filter->input.flow.ip4_flow.src_ip;\n \t\tdesc->dst_ip[0] = fdir_filter->input.flow.ip4_flow.dst_ip;\n \t\tbreak;\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \tcase RTE_ETH_FLOW_NONFRAG_IPV6_UDP:\n \tcase RTE_ETH_FLOW_NONFRAG_IPV6_TCP:\n \t\tdesc->src_port = fdir_filter->input.flow.udp6_flow.src_port;\n@@ -161,7 +158,6 @@ fdir_filter_to_flow_desc(const struct rte_eth_fdir_filter *fdir_filter,\n \t\t\t fdir_filter->input.flow.ipv6_flow.dst_ip,\n \t\t\t sizeof(desc->dst_ip));\n \t\tbreak;\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \tdefault:\n \t\tbreak;\n \t}\n@@ -211,7 +207,6 @@ priv_fdir_overlap(const struct priv *priv,\n \t\t (desc2->dst_ip[0] & mask->ipv4_mask.dst_ip)))\n \t\t\treturn 0;\n \t\tbreak;\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \tcase HASH_RXQ_IPV6:\n \tcase HASH_RXQ_UDPV6:\n \tcase HASH_RXQ_TCPV6:\n@@ -222,7 +217,6 @@ priv_fdir_overlap(const struct priv *priv,\n \t\t\t (desc2->dst_ip[i] & mask->ipv6_mask.dst_ip[i])))\n \t\t\t\treturn 0;\n \t\tbreak;\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \tdefault:\n \t\tbreak;\n \t}\n@@ -258,9 +252,7 @@ priv_fdir_flow_add(struct priv *priv,\n \tuintptr_t spec_offset = (uintptr_t)&data->spec;\n \tstruct ibv_exp_flow_spec_eth *spec_eth;\n \tstruct ibv_exp_flow_spec_ipv4 *spec_ipv4;\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \tstruct ibv_exp_flow_spec_ipv6 *spec_ipv6;\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \tstruct ibv_exp_flow_spec_tcp_udp *spec_tcp_udp;\n \tstruct mlx5_fdir_filter *iter_fdir_filter;\n \tunsigned int i;\n@@ -334,7 +326,6 @@ priv_fdir_flow_add(struct priv *priv,\n \n \t\tspec_offset += spec_ipv4->size;\n \t\tbreak;\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \tcase HASH_RXQ_IPV6:\n \tcase HASH_RXQ_UDPV6:\n \tcase HASH_RXQ_TCPV6:\n@@ -368,7 +359,6 @@ priv_fdir_flow_add(struct priv *priv,\n \n \t\tspec_offset += spec_ipv6->size;\n \t\tbreak;\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \tdefault:\n \t\tERROR(\"invalid flow attribute type\");\n \t\treturn EINVAL;\ndiff --git a/drivers/net/mlx5/mlx5_rxmode.c b/drivers/net/mlx5/mlx5_rxmode.c\nindex 3a55f63..51e2aca 100644\n--- a/drivers/net/mlx5/mlx5_rxmode.c\n+++ b/drivers/net/mlx5/mlx5_rxmode.c\n@@ -67,11 +67,9 @@ static const struct special_flow_init special_flow_init[] = {\n \t\t\t1 << HASH_RXQ_TCPV4 |\n \t\t\t1 << HASH_RXQ_UDPV4 |\n \t\t\t1 << HASH_RXQ_IPV4 |\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \t\t\t1 << HASH_RXQ_TCPV6 |\n \t\t\t1 << HASH_RXQ_UDPV6 |\n \t\t\t1 << HASH_RXQ_IPV6 |\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \t\t\t1 << HASH_RXQ_ETH |\n \t\t\t0,\n \t\t.per_vlan = 0,\n@@ -82,10 +80,8 @@ static const struct special_flow_init special_flow_init[] = {\n \t\t.hash_types =\n \t\t\t1 << HASH_RXQ_UDPV4 |\n \t\t\t1 << HASH_RXQ_IPV4 |\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \t\t\t1 << HASH_RXQ_UDPV6 |\n \t\t\t1 << HASH_RXQ_IPV6 |\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \t\t\t1 << HASH_RXQ_ETH |\n \t\t\t0,\n \t\t.per_vlan = 0,\n@@ -96,15 +92,12 @@ static const struct special_flow_init special_flow_init[] = {\n \t\t.hash_types =\n \t\t\t1 << HASH_RXQ_UDPV4 |\n \t\t\t1 << HASH_RXQ_IPV4 |\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \t\t\t1 << HASH_RXQ_UDPV6 |\n \t\t\t1 << HASH_RXQ_IPV6 |\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \t\t\t1 << HASH_RXQ_ETH |\n \t\t\t0,\n \t\t.per_vlan = 1,\n \t},\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \t[HASH_RXQ_FLOW_TYPE_IPV6MULTI] = {\n \t\t.dst_mac_val = \"\\x33\\x33\\x00\\x00\\x00\\x00\",\n \t\t.dst_mac_mask = \"\\xff\\xff\\x00\\x00\\x00\\x00\",\n@@ -115,7 +108,6 @@ static const struct special_flow_init special_flow_init[] = {\n \t\t\t0,\n \t\t.per_vlan = 1,\n \t},\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n };\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 8d32e74..7db4ce7 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -105,7 +105,6 @@ const struct hash_rxq_init hash_rxq_init[] = {\n \t\t},\n \t\t.underlayer = &hash_rxq_init[HASH_RXQ_ETH],\n \t},\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \t[HASH_RXQ_TCPV6] = {\n \t\t.hash_fields = (IBV_EXP_RX_HASH_SRC_IPV6 |\n \t\t\t\tIBV_EXP_RX_HASH_DST_IPV6 |\n@@ -144,7 +143,6 @@ const struct hash_rxq_init hash_rxq_init[] = {\n \t\t},\n \t\t.underlayer = &hash_rxq_init[HASH_RXQ_ETH],\n \t},\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \t[HASH_RXQ_ETH] = {\n \t\t.hash_fields = 0,\n \t\t.dpdk_rss_hf = 0,\n@@ -168,17 +166,11 @@ static const struct ind_table_init ind_table_init[] = {\n \t\t\t1 << HASH_RXQ_TCPV4 |\n \t\t\t1 << HASH_RXQ_UDPV4 |\n \t\t\t1 << HASH_RXQ_IPV4 |\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \t\t\t1 << HASH_RXQ_TCPV6 |\n \t\t\t1 << HASH_RXQ_UDPV6 |\n \t\t\t1 << HASH_RXQ_IPV6 |\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \t\t\t0,\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \t\t.hash_types_n = 6,\n-#else /* HAVE_FLOW_SPEC_IPV6 */\n-\t\t.hash_types_n = 3,\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \t},\n \t{\n \t\t.max_size = 1,\n@@ -243,12 +235,8 @@ priv_flow_attr(struct priv *priv, struct ibv_exp_flow_attr *flow_attr,\n \tinit = &hash_rxq_init[type];\n \t*flow_attr = (struct ibv_exp_flow_attr){\n \t\t.type = IBV_EXP_FLOW_ATTR_NORMAL,\n-#ifdef MLX5_FDIR_SUPPORT\n \t\t/* Priorities < 3 are reserved for flow director. */\n \t\t.priority = init->flow_priority + 3,\n-#else /* MLX5_FDIR_SUPPORT */\n-\t\t.priority = init->flow_priority,\n-#endif /* MLX5_FDIR_SUPPORT */\n \t\t.num_of_specs = 0,\n \t\t.port = priv->port,\n \t\t.flags = 0,\n@@ -589,9 +577,7 @@ priv_allow_flow_type(struct priv *priv, enum hash_rxq_flow_type type)\n \tcase HASH_RXQ_FLOW_TYPE_ALLMULTI:\n \t\treturn !!priv->allmulti_req;\n \tcase HASH_RXQ_FLOW_TYPE_BROADCAST:\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \tcase HASH_RXQ_FLOW_TYPE_IPV6MULTI:\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \t\t/* If allmulti is enabled, broadcast and ipv6multi\n \t\t * are unnecessary. */\n \t\treturn !priv->allmulti_req;\n@@ -1038,19 +1024,13 @@ rxq_setup(struct rte_eth_dev *dev, struct rxq_ctrl *rxq_ctrl, uint16_t desc,\n \t\t.cq = tmpl.rxq.cq,\n \t\t.comp_mask =\n \t\t\tIBV_EXP_CREATE_WQ_RES_DOMAIN |\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n \t\t\tIBV_EXP_CREATE_WQ_VLAN_OFFLOADS |\n-#endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n \t\t\t0,\n \t\t.res_domain = tmpl.rd,\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n \t\t.vlan_offloads = (tmpl.rxq.vlan_strip ?\n \t\t\t\t IBV_EXP_RECEIVE_WQ_CVLAN_STRIP :\n \t\t\t\t 0),\n-#endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n \t};\n-\n-#ifdef HAVE_VERBS_FCS\n \t/* By default, FCS (CRC) is stripped by hardware. */\n \tif (dev->data->dev_conf.rxmode.hw_strip_crc) {\n \t\ttmpl.rxq.crc_present = 0;\n@@ -1071,9 +1051,6 @@ rxq_setup(struct rte_eth_dev *dev, struct rxq_ctrl *rxq_ctrl, uint16_t desc,\n \t (void *)dev,\n \t tmpl.rxq.crc_present ? \"disabled\" : \"enabled\",\n \t tmpl.rxq.crc_present << 2);\n-#endif /* HAVE_VERBS_FCS */\n-\n-#ifdef HAVE_VERBS_RX_END_PADDING\n \tif (!mlx5_getenv_int(\"MLX5_PMD_ENABLE_PADDING\"))\n \t\t; /* Nothing else to do. */\n \telse if (priv->hw_padding) {\n@@ -1086,7 +1063,6 @@ rxq_setup(struct rte_eth_dev *dev, struct rxq_ctrl *rxq_ctrl, uint16_t desc,\n \t\t \" supported, make sure MLNX_OFED and firmware are\"\n \t\t \" up to date\",\n \t\t (void *)dev);\n-#endif /* HAVE_VERBS_RX_END_PADDING */\n \n \ttmpl.rxq.wq = ibv_exp_create_wq(priv->ctx, &attr.wq);\n \tif (tmpl.rxq.wq == NULL) {\n@@ -1106,9 +1082,7 @@ rxq_setup(struct rte_eth_dev *dev, struct rxq_ctrl *rxq_ctrl, uint16_t desc,\n \tDEBUG(\"%p: RTE port ID: %u\", (void *)rxq_ctrl, tmpl.rxq.port_id);\n \tattr.params = (struct ibv_exp_query_intf_params){\n \t\t.intf_scope = IBV_EXP_INTF_GLOBAL,\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n \t\t.intf_version = 1,\n-#endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n \t\t.intf = IBV_EXP_INTF_CQ,\n \t\t.obj = tmpl.rxq.cq,\n \t};\n@@ -1164,11 +1138,7 @@ rxq_setup(struct rte_eth_dev *dev, struct rxq_ctrl *rxq_ctrl, uint16_t desc,\n \tDEBUG(\"%p: rxq updated with %p\", (void *)rxq_ctrl, (void *)&tmpl);\n \tassert(ret == 0);\n \t/* Assign function in queue. */\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n \trxq_ctrl->rxq.poll = rxq_ctrl->if_cq->poll_length_flags_cvlan;\n-#else /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n-\trxq_ctrl->rxq.poll = rxq_ctrl->if_cq->poll_length_flags;\n-#endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n \trxq_ctrl->rxq.recv = rxq_ctrl->if_wq->recv_burst;\n \treturn 0;\n error:\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex f0b42e9..6a0d707 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -452,11 +452,9 @@ rxq_cq_to_ol_flags(const struct rxq *rxq, uint32_t flags)\n \t\t\t\tTRANSPOSE(~flags,\n \t\t\t\t\tIBV_EXP_CQ_RX_IP_CSUM_OK,\n \t\t\t\t\tPKT_RX_IP_CKSUM_BAD);\n-#ifdef HAVE_EXP_CQ_RX_TCP_PACKET\n \t\t/* Set L4 checksum flag only for TCP/UDP packets. */\n \t\tif (flags &\n \t\t (IBV_EXP_CQ_RX_TCP_PACKET | IBV_EXP_CQ_RX_UDP_PACKET))\n-#endif /* HAVE_EXP_CQ_RX_TCP_PACKET */\n \t\t\tol_flags |=\n \t\t\t\tTRANSPOSE(~flags,\n \t\t\t\t\tIBV_EXP_CQ_RX_TCP_UDP_CSUM_OK,\n@@ -589,12 +587,10 @@ mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\tif (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip) {\n \t\t\tseg->packet_type = rxq_cq_to_pkt_type(flags);\n \t\t\tseg->ol_flags = rxq_cq_to_ol_flags(rxq, flags);\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n \t\t\tif (flags & IBV_EXP_CQ_RX_CVLAN_STRIPPED_V1) {\n \t\t\t\tseg->ol_flags |= PKT_RX_VLAN_PKT;\n \t\t\t\tseg->vlan_tci = vlan_tci;\n \t\t\t}\n-#endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n \t\t}\n \t\t/* Return packet. */\n \t\t*(pkts++) = seg;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 2c5e447..570345b 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -120,11 +120,7 @@ struct rxq_ctrl {\n \tstruct fdir_queue fdir_queue; /* Flow director queue. */\n \tstruct ibv_mr *mr; /* Memory Region (for mp). */\n \tstruct ibv_exp_wq_family *if_wq; /* WQ burst interface. */\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n \tstruct ibv_exp_cq_family_v1 *if_cq; /* CQ interface. */\n-#else /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n-\tstruct ibv_exp_cq_family *if_cq; /* CQ interface. */\n-#endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n \tunsigned int socket; /* CPU socket ID for allocations. */\n \tstruct rxq rxq; /* Data path structure. */\n };\n@@ -134,11 +130,9 @@ enum hash_rxq_type {\n \tHASH_RXQ_TCPV4,\n \tHASH_RXQ_UDPV4,\n \tHASH_RXQ_IPV4,\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \tHASH_RXQ_TCPV6,\n \tHASH_RXQ_UDPV6,\n \tHASH_RXQ_IPV6,\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \tHASH_RXQ_ETH,\n };\n \n@@ -169,9 +163,7 @@ struct hash_rxq_init {\n \t\t} hdr;\n \t\tstruct ibv_exp_flow_spec_tcp_udp tcp_udp;\n \t\tstruct ibv_exp_flow_spec_ipv4 ipv4;\n-#ifdef HAVE_FLOW_SPEC_IPV6\n \t\tstruct ibv_exp_flow_spec_ipv6 ipv6;\n-#endif /* HAVE_FLOW_SPEC_IPV6 */\n \t\tstruct ibv_exp_flow_spec_eth eth;\n \t} flow_spec; /* Flow specification template. */\n \tconst struct hash_rxq_init *underlayer; /* Pointer to underlayer. */\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 4683775..9f3a33b 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -375,13 +375,11 @@ txq_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl, uint16_t desc,\n #ifdef HAVE_VERBS_VLAN_INSERTION\n \t\t.intf_version = 1,\n #endif\n-#ifdef HAVE_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR\n \t\t/* Enable multi-packet send if supported. */\n \t\t.family_flags =\n \t\t\t(priv->mps ?\n \t\t\t IBV_EXP_QP_BURST_CREATE_ENABLE_MULTI_PACKET_SEND_WR :\n \t\t\t 0),\n-#endif\n \t};\n \ttmpl.if_qp = ibv_exp_query_intf(priv->ctx, &attr.params, &status);\n \tif (tmpl.if_qp == NULL) {\ndiff --git a/drivers/net/mlx5/mlx5_vlan.c b/drivers/net/mlx5/mlx5_vlan.c\nindex ff40538..3b9b771 100644\n--- a/drivers/net/mlx5/mlx5_vlan.c\n+++ b/drivers/net/mlx5/mlx5_vlan.c\n@@ -144,7 +144,6 @@ static void\n priv_vlan_strip_queue_set(struct priv *priv, uint16_t idx, int on)\n {\n \tstruct rxq *rxq = (*priv->rxqs)[idx];\n-#ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS\n \tstruct ibv_exp_wq_attr mod;\n \tuint16_t vlan_offloads =\n \t\t(on ? IBV_EXP_RECEIVE_WQ_CVLAN_STRIP : 0) |\n@@ -165,8 +164,6 @@ priv_vlan_strip_queue_set(struct priv *priv, uint16_t idx, int on)\n \t\treturn;\n \t}\n \n-#endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */\n-\n \t/* Update related bits in RX queue. */\n \trxq->vlan_strip = !!on;\n }\n", "prefixes": [ "dpdk-dev", "v4", "09/25" ] }