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GET /api/patches/14100/?format=api
{ "id": 14100, "url": "https://patches.dpdk.org/api/patches/14100/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1466439037-14095-17-git-send-email-nelio.laranjeiro@6wind.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1466439037-14095-17-git-send-email-nelio.laranjeiro@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1466439037-14095-17-git-send-email-nelio.laranjeiro@6wind.com", "date": "2016-06-20T16:10:28", "name": "[dpdk-dev,v2,16/25] mlx5: replace countdown with threshold for Tx completions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "aec544e3c24d42aa5d18b6392600e61e92c3c3c9", "submitter": { "id": 243, "url": "https://patches.dpdk.org/api/people/243/?format=api", "name": "Nélio Laranjeiro", "email": "nelio.laranjeiro@6wind.com" }, "delegate": { "id": 10, "url": "https://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1466439037-14095-17-git-send-email-nelio.laranjeiro@6wind.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/14100/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/14100/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 55E84ADCD;\n\tMon, 20 Jun 2016 18:11:49 +0200 (CEST)", "from mail-wm0-f42.google.com (mail-wm0-f42.google.com\n\t[74.125.82.42]) by dpdk.org (Postfix) with ESMTP id 2226AAA3B\n\tfor <dev@dpdk.org>; Mon, 20 Jun 2016 18:11:37 +0200 (CEST)", "by mail-wm0-f42.google.com with SMTP id r201so68851269wme.1\n\tfor <dev@dpdk.org>; Mon, 20 Jun 2016 09:11:37 -0700 (PDT)", "from ping.vm.6wind.com (guy78-3-82-239-227-177.fbx.proxad.net.\n\t[82.239.227.177]) by smtp.gmail.com with ESMTPSA id\n\tf189sm4543977wmf.19.2016.06.20.09.11.35\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tMon, 20 Jun 2016 09:11:36 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=6wind-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:in-reply-to:references;\n\tbh=Uv6s2FZYnwAKmvYRNBqmNiW6YQ9XVDnLH8MUVl7Ho90=;\n\tb=W2IyHHzv/gndBOBnNArMs7G0BERqyjwWjXMhtSQezKYUfDyyMiVpmOZ1tuyRTBItMM\n\tRs0w2B8xq5TwzaDuIR6duKpmqMYu6yPTs/EQFdgDoAf19QPlndTqsNrHlE9DY+KGS13a\n\tYpQTVj3hKy05CrfGo6Yb9M0YacqWy5mzwjaaeChqltWmfqZuv/Crui8gIGf3yXhnzNxT\n\tZacvhqZhCinLVzPo0hk88HIbxAC3c89cQcHqIgM+zw7a1iKt0zzz12TeaPjzgfsIS52V\n\tW+5DOGc/zn0JxaJJnZHjViPZNGt0VvzXr3+UPtkqqJ+dSmRJiWfy95k026vu64N8iQ0X\n\t9nWA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:in-reply-to:references;\n\tbh=Uv6s2FZYnwAKmvYRNBqmNiW6YQ9XVDnLH8MUVl7Ho90=;\n\tb=ATif8WS3Ex2r0LkOaQBiWwzH7EGnFEvKSzRjPhbUXvoDNZiHHtlrmTOB/rkB70vo7k\n\tQp1e6tXdYsV7Q56gPHyK5YnzLKmzwR3/cKe1eWIRu0IpxOSPsOnTHIGvQzVLt0FHcYqs\n\ty7iKulx7H/kh8PJQvcHcx+rAn4gr5WpuxWZEUsePyiZxpuDVhF56jrHLim7uX9EQV5u6\n\tOs9rRiswDJRu7r/o/hmFEQsxdAuPVupgnVR1mv4bBpacsb0CJ7Exd/Slh32+tyR2ZI0c\n\tCzTF37FuW3AZehHffKynN3RcLzcavwz3si+89TVBU1Dn3tzzZVkCr1X/cRiK8JlL8iRT\n\tjyUg==", "X-Gm-Message-State": "ALyK8tKNM1XeezD4VhTZbJulxllBVvb6CtlnaaBvUgEcuIlefIFUiZpxHfxp95NbUaecGSuO", "X-Received": "by 10.28.47.16 with SMTP id v16mr104015wmv.6.1466439096722;\n\tMon, 20 Jun 2016 09:11:36 -0700 (PDT)", "From": "Nelio Laranjeiro <nelio.laranjeiro@6wind.com>", "To": "dev@dpdk.org", "Cc": "Ferruh Yigit <ferruh.yigit@intel.com>,\n\tAdrien Mazarguil <adrien.mazarguil@6wind.com>,\n\tVasily Philipov <vasilyf@mellanox.com>", "Date": "Mon, 20 Jun 2016 18:10:28 +0200", "Message-Id": "<1466439037-14095-17-git-send-email-nelio.laranjeiro@6wind.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": [ "<1466439037-14095-1-git-send-email-nelio.laranjeiro@6wind.com>", "<1465379291-25310-1-git-send-email-nelio.laranjeiro@6wind.com>" ], "References": [ "<1465379291-25310-1-git-send-email-nelio.laranjeiro@6wind.com>\n\t<1466439037-14095-1-git-send-email-nelio.laranjeiro@6wind.com>", "<1465379291-25310-1-git-send-email-nelio.laranjeiro@6wind.com>" ], "Subject": "[dpdk-dev] [PATCH v2 16/25] mlx5: replace countdown with threshold\n\tfor Tx completions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Adrien Mazarguil <adrien.mazarguil@6wind.com>\n\nReplacing the variable countdown (which depends on the number of\ndescriptors) with a fixed relative threshold known at compile time improves\nperformance by reducing the TX queue structure footprint and the amount of\ncode to manage completions during a burst.\n\nCompletions are now requested at most once per burst after threshold is\nreached.\n\nSigned-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>\nSigned-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>\nSigned-off-by: Vasily Philipov <vasilyf@mellanox.com>\n---\n drivers/net/mlx5/mlx5_defs.h | 7 +++++--\n drivers/net/mlx5/mlx5_rxtx.c | 42 ++++++++++++++++++++++++------------------\n drivers/net/mlx5/mlx5_rxtx.h | 5 ++---\n drivers/net/mlx5/mlx5_txq.c | 19 ++++++++++++-------\n 4 files changed, 43 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 8d2ec7a..cc2a6f3 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -48,8 +48,11 @@\n /* Maximum number of special flows. */\n #define MLX5_MAX_SPECIAL_FLOWS 4\n \n-/* Request send completion once in every 64 sends, might be less. */\n-#define MLX5_PMD_TX_PER_COMP_REQ 64\n+/*\n+ * Request TX completion every time descriptors reach this threshold since\n+ * the previous request. Must be a power of two for performance reasons.\n+ */\n+#define MLX5_TX_COMP_THRESH 32\n \n /* RSS Indirection table size. */\n #define RSS_INDIRECTION_TABLE_SIZE 256\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 30d413c..d56c9e9 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -154,9 +154,6 @@ check_cqe64(volatile struct mlx5_cqe64 *cqe,\n * Manage TX completions.\n *\n * When sending a burst, mlx5_tx_burst() posts several WRs.\n- * To improve performance, a completion event is only required once every\n- * MLX5_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information\n- * for other WRs, but this information would not be used anyway.\n *\n * @param txq\n * Pointer to TX queue structure.\n@@ -170,14 +167,16 @@ txq_complete(struct txq *txq)\n \tuint16_t elts_free = txq->elts_tail;\n \tuint16_t elts_tail;\n \tuint16_t cq_ci = txq->cq_ci;\n-\tunsigned int wqe_ci = (unsigned int)-1;\n+\tvolatile struct mlx5_cqe64 *cqe = NULL;\n+\tvolatile union mlx5_wqe *wqe;\n \n \tdo {\n-\t\tunsigned int idx = cq_ci & cqe_cnt;\n-\t\tvolatile struct mlx5_cqe64 *cqe = &(*txq->cqes)[idx].cqe64;\n+\t\tvolatile struct mlx5_cqe64 *tmp;\n \n-\t\tif (check_cqe64(cqe, cqe_n, cq_ci) == 1)\n+\t\ttmp = &(*txq->cqes)[cq_ci & cqe_cnt].cqe64;\n+\t\tif (check_cqe64(tmp, cqe_n, cq_ci))\n \t\t\tbreak;\n+\t\tcqe = tmp;\n #ifndef NDEBUG\n \t\tif (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {\n \t\t\tif (!check_cqe64_seen(cqe))\n@@ -191,14 +190,15 @@ txq_complete(struct txq *txq)\n \t\t\treturn;\n \t\t}\n #endif /* NDEBUG */\n-\t\twqe_ci = ntohs(cqe->wqe_counter);\n \t\t++cq_ci;\n \t} while (1);\n-\tif (unlikely(wqe_ci == (unsigned int)-1))\n+\tif (unlikely(cqe == NULL))\n \t\treturn;\n+\twqe = &(*txq->wqes)[htons(cqe->wqe_counter) & (txq->wqe_n - 1)];\n+\telts_tail = wqe->wqe.ctrl.data[3];\n+\tassert(elts_tail < txq->wqe_n);\n \t/* Free buffers. */\n-\telts_tail = (wqe_ci + 1) & (elts_n - 1);\n-\tdo {\n+\twhile (elts_free != elts_tail) {\n \t\tstruct rte_mbuf *elt = (*txq->elts)[elts_free];\n \t\tunsigned int elts_free_next =\n \t\t\t(elts_free + 1) & (elts_n - 1);\n@@ -214,7 +214,7 @@ txq_complete(struct txq *txq)\n \t\t/* Only one segment needs to be freed. */\n \t\trte_pktmbuf_free_seg(elt);\n \t\telts_free = elts_free_next;\n-\t} while (elts_free != elts_tail);\n+\t}\n \ttxq->cq_ci = cq_ci;\n \ttxq->elts_tail = elts_tail;\n \t/* Update the consumer index. */\n@@ -435,6 +435,7 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \tconst unsigned int elts_n = txq->elts_n;\n \tunsigned int i;\n \tunsigned int max;\n+\tunsigned int comp;\n \tvolatile union mlx5_wqe *wqe;\n \tstruct rte_mbuf *buf;\n \n@@ -484,12 +485,7 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\t\t\t buf->vlan_tci);\n \t\telse\n \t\t\tmlx5_wqe_write(txq, wqe, addr, length, lkey);\n-\t\t/* Request completion if needed. */\n-\t\tif (unlikely(--txq->elts_comp == 0)) {\n-\t\t\twqe->wqe.ctrl.data[2] = htonl(8);\n-\t\t\ttxq->elts_comp = txq->elts_comp_cd_init;\n-\t\t} else\n-\t\t\twqe->wqe.ctrl.data[2] = 0;\n+\t\twqe->wqe.ctrl.data[2] = 0;\n \t\t/* Should we enable HW CKSUM offload */\n \t\tif (buf->ol_flags &\n \t\t (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {\n@@ -508,6 +504,16 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t/* Take a shortcut if nothing must be sent. */\n \tif (unlikely(i == 0))\n \t\treturn 0;\n+\t/* Check whether completion threshold has been reached. */\n+\tcomp = txq->elts_comp + i;\n+\tif (comp >= MLX5_TX_COMP_THRESH) {\n+\t\t/* Request completion on last WQE. */\n+\t\twqe->wqe.ctrl.data[2] = htonl(8);\n+\t\t/* Save elts_head in unused \"immediate\" field of WQE. */\n+\t\twqe->wqe.ctrl.data[3] = elts_head;\n+\t\ttxq->elts_comp = 0;\n+\t} else\n+\t\ttxq->elts_comp = comp;\n #ifdef MLX5_PMD_SOFT_COUNTERS\n \t/* Increment sent packets counter. */\n \ttxq->stats.opackets += i;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 77b0fde..f900e65 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -238,8 +238,7 @@ struct hash_rxq {\n struct txq {\n \tuint16_t elts_head; /* Current index in (*elts)[]. */\n \tuint16_t elts_tail; /* First element awaiting completion. */\n-\tuint16_t elts_comp_cd_init; /* Initial value for countdown. */\n-\tuint16_t elts_comp; /* Elements before asking a completion. */\n+\tuint16_t elts_comp; /* Counter since last completion request. */\n \tuint16_t elts_n; /* (*elts)[] length. */\n \tuint16_t cq_ci; /* Consumer index for completion queue. */\n \tuint16_t cqe_n; /* Number of CQ elements. */\n@@ -247,6 +246,7 @@ struct txq {\n \tuint16_t wqe_n; /* Number of WQ elements. */\n \tuint16_t bf_offset; /* Blueflame offset. */\n \tuint16_t bf_buf_size; /* Blueflame size. */\n+\tuint32_t qp_num_8s; /* QP number shifted by 8. */\n \tvolatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */\n \tvolatile union mlx5_wqe (*wqes)[]; /* Work queue. */\n \tvolatile uint32_t *qp_db; /* Work queue doorbell. */\n@@ -259,7 +259,6 @@ struct txq {\n \t} mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */\n \tstruct rte_mbuf *(*elts)[]; /* TX elements. */\n \tstruct mlx5_txq_stats stats; /* TX queue counters. */\n-\tuint32_t qp_num_8s; /* QP number shifted by 8. */\n } __rte_cache_aligned;\n \n /* TX queue control descriptor. */\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex ddcd6b6..7b2dc7c 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -89,6 +89,7 @@ txq_alloc_elts(struct txq_ctrl *txq_ctrl, unsigned int elts_n)\n \tDEBUG(\"%p: allocated and configured %u WRs\", (void *)txq_ctrl, elts_n);\n \ttxq_ctrl->txq.elts_head = 0;\n \ttxq_ctrl->txq.elts_tail = 0;\n+\ttxq_ctrl->txq.elts_comp = 0;\n }\n \n /**\n@@ -108,6 +109,7 @@ txq_free_elts(struct txq_ctrl *txq_ctrl)\n \tDEBUG(\"%p: freeing WRs\", (void *)txq_ctrl);\n \ttxq_ctrl->txq.elts_head = 0;\n \ttxq_ctrl->txq.elts_tail = 0;\n+\ttxq_ctrl->txq.elts_comp = 0;\n \n \twhile (elts_tail != elts_head) {\n \t\tstruct rte_mbuf *elt = (*elts)[elts_tail];\n@@ -274,13 +276,8 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,\n \t\tgoto error;\n \t}\n \t(void)conf; /* Thresholds configuration (ignored). */\n+\tassert(desc > MLX5_TX_COMP_THRESH);\n \ttmpl.txq.elts_n = desc;\n-\t/* Request send completion every MLX5_PMD_TX_PER_COMP_REQ packets or\n-\t * at least 4 times per ring. */\n-\ttmpl.txq.elts_comp_cd_init =\n-\t\t((MLX5_PMD_TX_PER_COMP_REQ < (desc / 4)) ?\n-\t\t MLX5_PMD_TX_PER_COMP_REQ : (desc / 4));\n-\ttmpl.txq.elts_comp = tmpl.txq.elts_comp_cd_init;\n \t/* MRs will be registered in mp2mr[] later. */\n \tattr.rd = (struct ibv_exp_res_domain_init_attr){\n \t\t.comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |\n@@ -300,7 +297,8 @@ txq_ctrl_setup(struct rte_eth_dev *dev, struct txq_ctrl *txq_ctrl,\n \t\t.res_domain = tmpl.rd,\n \t};\n \ttmpl.cq = ibv_exp_create_cq(priv->ctx,\n-\t\t\t\t (desc / tmpl.txq.elts_comp_cd_init) - 1,\n+\t\t\t\t (((desc / MLX5_TX_COMP_THRESH) - 1) ?\n+\t\t\t\t ((desc / MLX5_TX_COMP_THRESH) - 1) : 1),\n \t\t\t\t NULL, NULL, 0, &attr.cq);\n \tif (tmpl.cq == NULL) {\n \t\tret = ENOMEM;\n@@ -452,6 +450,13 @@ mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\treturn -E_RTE_SECONDARY;\n \n \tpriv_lock(priv);\n+\tif (desc <= MLX5_TX_COMP_THRESH) {\n+\t\tWARN(\"%p: number of descriptors requested for TX queue %u\"\n+\t\t \" must be higher than MLX5_TX_COMP_THRESH, using\"\n+\t\t \" %u instead of %u\",\n+\t\t (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);\n+\t\tdesc = MLX5_TX_COMP_THRESH + 1;\n+\t}\n \tif (!rte_is_power_of_2(desc)) {\n \t\tdesc = 1 << log2above(desc);\n \t\tWARN(\"%p: increased number of descriptors in TX queue %u\"\n", "prefixes": [ "dpdk-dev", "v2", "16/25" ] }